ryanlewis · June 9, 2026 21:16
diff --git a/README.md b/README.md
diff --git a/patch_lg_edid.py b/patch_lg_edid.py
 #!/usr/bin/env python3
 """
 patch_lg_edid.py — give an LG UltraGear (DP 1.4 + DSC) a real 4K@120 mode.

 THE SCENARIO
 ------------
 When these monitors run in DisplayPort 1.4 *DSC* mode, their DisplayID block
 advertises 4K @ 240 / 144 / 95 Hz — but NOT 120 Hz. 120 is the only one of
 those that divides 24/30/60 fps cleanly (144 judders on 30 and 60), so it's
 the rate you actually want for mixed video. 4K@120's pixel clock (~1.1 GHz)
 is too high for a legacy 18-byte detailed-timing descriptor (capped ~655 MHz),
 so it can only live in the DisplayID block.

 This script finds the largely-useless 4K@95 timing in the DisplayID Type-I
 timing block and rewrites it as 4K@120 (keeping the same blanking, just a new
 pixel clock), then fixes both checksums.

 USAGE
 -----
  python3 patch_lg_edid.py input.bin  output.bin
  python3 patch_lg_edid.py --b64 'AP///...'        # prints new base64

 AT YOUR OWN RISK. A malformed EDID can give a black/green screen. It's
 recoverable (remove the override / reboot), but back up your original first.
 """
 import sys, base64

 def load(argv):
    if argv[0] == "--b64":
        return bytearray(base64.b64decode(argv[1])), None
    with open(argv[0], "rb") as f:
        return bytearray(f.read()), (argv[1] if len(argv) > 1 else None)

 def find_displayid(data):
    # EDID = 128-byte base block + N extension blocks. DisplayID ext starts 0x70.
    for off in range(128, len(data), 128):
        if data[off] == 0x70:
            return off
    raise SystemExit("No DisplayID extension block (0x70) found.")

 def timings(block):
    """Yield (abs_offset_in_block, refresh, hact, vact) for each Type-I timing."""
    sec_size = block[2]
    i = 5
    while i < 5 + sec_size:
        tag = block[i]
        if tag == 0:
            break
        blen = block[i + 2]
        if tag == 0x03:  # Type I Detailed Timing block; 20 bytes per timing
            for k in range(i + 3, i + 3 + blen, 20):
                t = block[k:k + 20]
                if len(t) < 20:
                    break
                pclk_khz = ((t[0] | (t[1] << 8) | (t[2] << 16)) + 1) * 10
                hact = (t[4] | (t[5] << 8)) + 1
                hbl  = (t[6] | (t[7] << 8)) + 1
                vact = (t[12] | (t[13] << 8)) + 1
                vbl  = (t[14] | (t[15] << 8)) + 1
                htot, vtot = hact + hbl, vact + vbl
                refresh = pclk_khz * 1000 / (htot * vtot)
                yield k, refresh, hact, vact, htot, vtot
        i += 3 + blen

 def main():
    if not sys.argv[1:] or sys.argv[1] in ("-h", "--help"):
        print(__doc__); return
    data, outpath = load(sys.argv[1:])
    did = find_displayid(data)
    block = data[did:did + 128]

    # locate the ~95 Hz 4K timing
    target = None
    print("DisplayID Type-I timings found:")
    for k, refresh, hact, vact, htot, vtot in timings(block):
        flag = ""
        if hact == 3840 and 90 <= refresh <= 100:
            target = (k, htot, vtot); flag = "  <- replacing with 120 Hz"
        print(f"  {hact}x{vact} @ {refresh:6.2f} Hz{flag}")
    if not target:
        raise SystemExit("\nNo ~95 Hz 4K timing found - nothing to replace.")

    k, htot, vtot = target
    abs_k = did + k
    # new pixel clock so refresh == 120, keeping this timing's own blanking
    new_pclk_khz = round(htot * vtot * 120 / 1000)
    raw = new_pclk_khz // 10 - 1
    data[abs_k + 0] = raw & 0xFF
    data[abs_k + 1] = (raw >> 8) & 0xFF
    data[abs_k + 2] = (raw >> 16) & 0xFF
    print(f"\nWrote 4K@120 (pclk {new_pclk_khz/1000:.2f} MHz) over the 95 Hz slot.")

    # fix DisplayID section checksum, then EDID extension-block checksum
    sec_cks_off = did + 5 + data[did + 2]
    data[sec_cks_off] = (-sum(data[did + 1:sec_cks_off])) & 0xFF
    blk_cks_off = did + 127
    data[blk_cks_off] = (-sum(data[did:blk_cks_off])) & 0xFF

    # sanity: re-read
    block = data[did:did + 128]
    print("After patch:")
    for _, refresh, hact, vact, *_ in timings(block):
        print(f"  {hact}x{vact} @ {refresh:6.2f} Hz")
    assert sum(data[did:did + 128]) % 256 == 0, "ext checksum bad"

    if outpath:
        with open(outpath, "wb") as f:
            f.write(bytes(data))
        print(f"\nWrote {outpath}")
    else:
        print("\nNew base64 EDID:\n" + base64.b64encode(bytes(data)).decode())

 if __name__ == "__main__":
    main()
	#!/usr/bin/env python3
	"""
	patch_lg_edid.py — give an LG UltraGear (DP 1.4 + DSC) a real 4K@120 mode.

	THE SCENARIO
	------------
	When these monitors run in DisplayPort 1.4 DSC mode, their DisplayID block
	advertises 4K @ 240 / 144 / 95 Hz — but NOT 120 Hz. 120 is the only one of
	those that divides 24/30/60 fps cleanly (144 judders on 30 and 60), so it's
	the rate you actually want for mixed video. 4K@120's pixel clock (~1.1 GHz)
	is too high for a legacy 18-byte detailed-timing descriptor (capped ~655 MHz),
	so it can only live in the DisplayID block.

	This script finds the largely-useless 4K@95 timing in the DisplayID Type-I
	timing block and rewrites it as 4K@120 (keeping the same blanking, just a new
	pixel clock), then fixes both checksums.

	USAGE
	-----
	python3 patch_lg_edid.py input.bin output.bin
	python3 patch_lg_edid.py --b64 'AP///...' # prints new base64

	AT YOUR OWN RISK. A malformed EDID can give a black/green screen. It's
	recoverable (remove the override / reboot), but back up your original first.
	"""
	import sys, base64

	def load(argv):
	if argv[0] == "--b64":
	return bytearray(base64.b64decode(argv[1])), None
	with open(argv[0], "rb") as f:
	return bytearray(f.read()), (argv[1] if len(argv) > 1 else None)

	def find_displayid(data):
	# EDID = 128-byte base block + N extension blocks. DisplayID ext starts 0x70.
	for off in range(128, len(data), 128):
	if data[off] == 0x70:
	return off
	raise SystemExit("No DisplayID extension block (0x70) found.")

	def timings(block):
	"""Yield (abs_offset_in_block, refresh, hact, vact) for each Type-I timing."""
	sec_size = block[2]
	i = 5
	while i < 5 + sec_size:
	tag = block[i]
	if tag == 0:
	break
	blen = block[i + 2]
	if tag == 0x03: # Type I Detailed Timing block; 20 bytes per timing
	for k in range(i + 3, i + 3 + blen, 20):
	t = block[k:k + 20]
	if len(t) < 20:
	break
	pclk_khz = ((t[0] \| (t[1] << 8) \| (t[2] << 16)) + 1) * 10
	hact = (t[4] \| (t[5] << 8)) + 1
	hbl = (t[6] \| (t[7] << 8)) + 1
	vact = (t[12] \| (t[13] << 8)) + 1
	vbl = (t[14] \| (t[15] << 8)) + 1
	htot, vtot = hact + hbl, vact + vbl
	refresh = pclk_khz * 1000 / (htot * vtot)
	yield k, refresh, hact, vact, htot, vtot
	i += 3 + blen

	def main():
	if not sys.argv[1:] or sys.argv[1] in ("-h", "--help"):
	print(__doc__); return
	data, outpath = load(sys.argv[1:])
	did = find_displayid(data)
	block = data[did:did + 128]

	# locate the ~95 Hz 4K timing
	target = None
	print("DisplayID Type-I timings found:")
	for k, refresh, hact, vact, htot, vtot in timings(block):
	flag = ""
	if hact == 3840 and 90 <= refresh <= 100:
	target = (k, htot, vtot); flag = " <- replacing with 120 Hz"
	print(f" {hact}x{vact} @ {refresh:6.2f} Hz{flag}")
	if not target:
	raise SystemExit("\nNo ~95 Hz 4K timing found - nothing to replace.")

	k, htot, vtot = target
	abs_k = did + k
	# new pixel clock so refresh == 120, keeping this timing's own blanking
	new_pclk_khz = round(htot * vtot * 120 / 1000)
	raw = new_pclk_khz // 10 - 1
	data[abs_k + 0] = raw & 0xFF
	data[abs_k + 1] = (raw >> 8) & 0xFF
	data[abs_k + 2] = (raw >> 16) & 0xFF
	print(f"\nWrote 4K@120 (pclk {new_pclk_khz/1000:.2f} MHz) over the 95 Hz slot.")

	# fix DisplayID section checksum, then EDID extension-block checksum
	sec_cks_off = did + 5 + data[did + 2]
	data[sec_cks_off] = (-sum(data[did + 1:sec_cks_off])) & 0xFF
	blk_cks_off = did + 127
	data[blk_cks_off] = (-sum(data[did:blk_cks_off])) & 0xFF

	# sanity: re-read
	block = data[did:did + 128]
	print("After patch:")
	for _, refresh, hact, vact, *_ in timings(block):
	print(f" {hact}x{vact} @ {refresh:6.2f} Hz")
	assert sum(data[did:did + 128]) % 256 == 0, "ext checksum bad"

	if outpath:
	with open(outpath, "wb") as f:
	f.write(bytes(data))
	print(f"\nWrote {outpath}")
	else:
	print("\nNew base64 EDID:\n" + base64.b64encode(bytes(data)).decode())

	if __name__ == "__main__":
	main()
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