plutil -p /usr/share/kpep/a14.plist

a14.plist.txt

{
  "internal" => 0
  "name" => "a14"
  "system" => {
    "cpu" => {
      "aliases" => {
        "Cycles" => "FIXED_CYCLES"
        "Instructions" => "FIXED_INSTRUCTIONS"
      }
      "architecture" => "arm64"
      "config_counters" => 1020
      "events" => {
        "ATOMIC_OR_EXCLUSIVE_FAIL" => {
          "description" => "Atomic or exclusive instruction failed (due to contention)"
          "number" => 180
        }
        "ATOMIC_OR_EXCLUSIVE_SUCC" => {
          "description" => "Atomic or exclusive instruction successfully completed"
          "number" => 179
        }
        "BRANCH_CALL_INDIR_MISPRED_NONSPEC" => {
          "counters_mask" => 224
          "description" => "Retired indirect call instructions mispredicted"
          "number" => 202
        }
        "BRANCH_COND_MISPRED_NONSPEC" => {
          "counters_mask" => 224
          "description" => "Retired conditional branch instructions that mispredicted"
          "number" => 197
        }
        "BRANCH_INDIR_MISPRED_NONSPEC" => {
          "counters_mask" => 224
          "description" => "Retired indirect branch instructions including calls and returns that mispredicted"
          "number" => 198
        }
        "BRANCH_MISPRED_NONSPEC" => {
          "counters_mask" => 224
          "description" => "Retired branch instructions including calls and returns that mispredicted"
          "number" => 203
        }
        "BRANCH_RET_INDIR_MISPRED_NONSPEC" => {
          "counters_mask" => 224
          "description" => "Retired return instructions that mispredicted"
          "number" => 200
        }
        "CORE_ACTIVE_CYCLE" => {
          "description" => "Cycles while the core was active"
          "number" => 2
        }
        "FETCH_RESTART" => {
          "description" => "Fetch Unit internal restarts for any reason. Does not include branch mispredicts"
          "number" => 222
        }
        "FIXED_CYCLES" => {
          "counters_mask" => 1
          "fixed_counter" => 0
        }
        "FIXED_INSTRUCTIONS" => {
          "counters_mask" => 2
          "fallback" => "INST_ALL"
          "fixed_counter" => 1
        }
        "FLUSH_RESTART_OTHER_NONSPEC" => {
          "description" => "Pipeline flush and restarts that were not due to branch mispredictions or memory order violations"
          "number" => 132
        }
        "INST_ALL" => {
          "counters_mask" => 128
          "description" => "All retired instructions"
          "number" => 140
        }
        "INST_BARRIER" => {
          "counters_mask" => 224
          "description" => "Retired data barrier instructions"
          "number" => 156
        }
        "INST_BRANCH" => {
          "counters_mask" => 224
          "description" => "Retired branch instructions including calls and returns"
          "number" => 141
        }
        "INST_BRANCH_CALL" => {
          "counters_mask" => 224
          "description" => "Retired subroutine call instructions"
          "number" => 142
        }
        "INST_BRANCH_COND" => {
          "counters_mask" => 224
          "description" => "Retired conditional branch instructions (counts only B.cond)"
          "number" => 148
        }
        "INST_BRANCH_INDIR" => {
          "counters_mask" => 224
          "description" => "Retired indirect branch instructions including indirect calls"
          "number" => 147
        }
        "INST_BRANCH_RET" => {
          "counters_mask" => 224
          "description" => "Retired subroutine return instructions"
          "number" => 143
        }
        "INST_BRANCH_TAKEN" => {
          "counters_mask" => 224
          "description" => "Retired taken branch instructions"
          "number" => 144
        }
        "INST_INT_ALU" => {
          "counters_mask" => 128
          "description" => "Retired non-branch and non-load/store Integer Unit instructions"
          "number" => 151
        }
        "INST_INT_LD" => {
          "counters_mask" => 224
          "description" => "Retired load Integer Unit instructions"
          "number" => 149
        }
        "INST_INT_ST" => {
          "counters_mask" => 128
          "description" => "Retired store Integer Unit instructions"
          "number" => 150
        }
        "INST_LDST" => {
          "counters_mask" => 128
          "description" => "Retired load and store instructions"
          "number" => 155
        }
        "INST_SIMD_ALU" => {
          "counters_mask" => 128
          "description" => "Retired non-load/store Advanced SIMD and FP Unit instructions"
          "number" => 154
        }
        "INST_SIMD_LD" => {
          "counters_mask" => 224
          "description" => "Retired load Advanced SIMD and FP Unit instructions"
          "number" => 152
        }
        "INST_SIMD_ST" => {
          "counters_mask" => 224
          "description" => "Retired store Advanced SIMD and FP Unit instructions"
          "number" => 153
        }
        "INTERRUPT_PENDING" => {
          "description" => "Cycles while an interrupt was pending because it was masked"
          "number" => 108
        }
        "L1D_CACHE_MISS_LD" => {
          "description" => "Loads that missed the L1 Data Cache"
          "number" => 163
        }
        "L1D_CACHE_MISS_LD_NONSPEC" => {
          "counters_mask" => 224
          "description" => "Retired loads that missed in the L1 Data Cache"
          "number" => 191
        }
        "L1D_CACHE_MISS_ST" => {
          "description" => "Stores that missed the L1 Data Cache"
          "number" => 162
        }
        "L1D_CACHE_MISS_ST_NONSPEC" => {
          "counters_mask" => 224
          "description" => "Retired stores that missed in the L1 Data Cache"
          "number" => 192
        }
        "L1D_CACHE_WRITEBACK" => {
          "description" => "Dirty cache lines written back from the L1D Cache toward the Shared L2 Cache"
          "number" => 168
        }
        "L1D_TLB_ACCESS" => {
          "description" => "Load and store accesses to the L1 Data TLB"
          "number" => 160
        }
        "L1D_TLB_FILL" => {
          "description" => "Translations filled into the L1 Data TLB"
          "number" => 5
        }
        "L1D_TLB_MISS" => {
          "description" => "Load and store accesses that missed the L1 Data TLB"
          "number" => 161
        }
        "L1D_TLB_MISS_NONSPEC" => {
          "counters_mask" => 224
          "description" => "Retired loads and stores that missed in the L1 Data TLB"
          "number" => 193
        }
        "L1I_CACHE_MISS_DEMAND" => {
          "description" => "Demand fetch misses that require a new cache line fill of the L1 Instruction Cache"
          "number" => 219
        }
        "L1I_TLB_FILL" => {
          "description" => "Translations filled into the L1 Instruction TLB"
          "number" => 4
        }
        "L1I_TLB_MISS_DEMAND" => {
          "description" => "Demand instruction fetches that missed in the L1 Instruction TLB"
          "number" => 212
        }
        "L2_TLB_MISS_DATA" => {
          "description" => "Loads and stores that missed in the L2 TLB"
          "number" => 11
        }
        "L2_TLB_MISS_INSTRUCTION" => {
          "description" => "Instruction fetches that missed in the L2 TLB"
          "number" => 10
        }
        "LD_NT_UOP" => {
          "description" => "Load uops that executed with non-temporal hint"
          "number" => 230
        }
        "LD_UNIT_UOP" => {
          "description" => "Uops that flowed through the Load Unit"
          "number" => 166
        }
        "LDST_X64_UOP" => {
          "description" => "Load and store uops that crossed a 64B boundary"
          "number" => 177
        }
        "LDST_XPG_UOP" => {
          "description" => "Load and store uops that crossed a 16KiB page boundary"
          "number" => 178
        }
        "MAP_DISPATCH_BUBBLE" => {
          "description" => "Bubble detected in dispatch stage"
          "number" => 214
        }
        "MAP_INT_UOP" => {
          "description" => "Mapped Integer Unit uops"
          "number" => 124
        }
        "MAP_LDST_UOP" => {
          "description" => "Mapped Load and Store Unit uops, including GPR to vector register converts"
          "number" => 125
        }
        "MAP_REWIND" => {
          "description" => "Cycles while the Map Unit was blocked while rewinding due to flush and restart"
          "number" => 117
        }
        "MAP_SIMD_UOP" => {
          "description" => "Mapped Advanced SIMD and FP Unit uops"
          "number" => 126
        }
        "MAP_STALL" => {
          "description" => "Cycles while the Map Unit was stalled for any reason"
          "number" => 118
        }
        "MAP_STALL_DISPATCH" => {
          "description" => "Cycles while the Map Unit was stalled because of Dispatch back pressure"
          "number" => 112
        }
        "MMU_TABLE_WALK_DATA" => {
          "description" => "Table walk memory requests on behalf of data accesses"
          "number" => 8
        }
        "MMU_TABLE_WALK_INSTRUCTION" => {
          "description" => "Table walk memory requests on behalf of instruction fetches"
          "number" => 7
        }
        "MMU_VIRTUAL_MEMORY_FAULT_NONSPEC" => {
          "description" => "Memory accesses that reached retirement that triggered any of the MMU virtual memory faults"
          "number" => 13
        }
        "RETIRE_UOP" => {
          "counters_mask" => 128
          "description" => "All retired uops"
          "number" => 1
        }
        "SCHEDULE_UOP" => {
          "description" => "Uops issued by the scheduler to any execution unit"
          "number" => 82
        }
        "ST_MEMORY_ORDER_VIOLATION_NONSPEC" => {
          "counters_mask" => 224
          "description" => "Retired stores that triggered memory order violations"
          "number" => 196
        }
        "ST_NT_UOP" => {
          "description" => "Store uops that executed with non-temporal hint"
          "number" => 229
        }
        "ST_UNIT_UOP" => {
          "description" => "Uops that flowed through the Store Unit"
          "number" => 167
        }
      }
      "fixed_counters" => 3
      "marketing_name" => "Apple A14/M1"
      "power_counters" => 224
    }
  }
  "version" => [
    0 => 1
    1 => 0
  ]
}