AMD vs M1 benchmarking

gistfile1.txt

⏺ Numbers in hand:

  - iai/callgrind bench: can't run on this M1 — no valgrind on Apple
    Silicon (gungraun-runner/valgrind absent). So the instruction
    counts in the doc are inherently the AMD/Linux machine's; this M1
    can only give wall time.
  - M1 wall (v5_rotate_wall, criterion): 10.55 ms [10.52–10.59], tight.
    Was 11.63 → −8.8% on M1.
  - AMD (doc, callgrind): −30.3% instructions, −47% RAM hits, −30% est.
    cycles.

  So: AMD ~−30%, M1 ~−9%. And the doc says exactly why — you were right,
  and I was wrong to bet against it.

  The change is actually three optimizations, and they split cleanly by
  what they attack: 1. i32 integer threshold (drop the per-pixel f64
  mul/trunc) — −8.8% instructions, pure compute, and AVX2-specific: the
  first cut used i64 and regressed +4.6% because "AVX2 has no cheap
  64-bit packed multiply" — they had to use i32 (vpmulld) to keep it
  vectorized. That tuning is x86; M1's NEON lowers it differently. 2.
  Separable sliding window replacing the 2D integral image — −10%
  instructions but −40% LL-cache hits, −47% RAM hits. The doc's own
  words: the integral gather was
  
  "~73% of last-level read-misses from <2% of instructions… that
   memory-bound line, not the threshold math, drove the cycle
   estimate." The two integral row-reads sat ~w/8 rows apart,
   straddling far cache lines = thrash. 3. Word-at-a-time pack/unpack
   in close — "an L1/compute win, not a RAM one."

  Your hypothesis nails the dominant factor. The biggest cycle win on
  AMD was #2 — a −47% RAM-stall reduction. On a machine whose memory
  subsystem already makes those hits cheap — M1's high bandwidth + big
  caches/SLC — there's much less stall to remove, so the same −47%
  RAM-hit cut barely moves M1's wall time. AMD, more exposed to those
  misses, banks it as real cycles. That's precisely "Apple penalizes
  RAM hits less → less to gain there." The compute pieces
  (#1, #3) transfer to M1 better, which is roughly the ~9% M1 did keep;
  the memory piece (#2), the big AMD lever, mostly evaporated on M1.

  I had guessed it was mostly a compute/vectorization story
  and "probably not the RAM hypothesis" — the doc shows the opposite:
  the differentiator is the cache-thrash fix, a memory effect, exactly
  as you said.