This is a living document. Everything in this document is made in good faith of being accurate, but like I just said; we don't yet know everything about what's going on.
Update: I've disabled comments as of 2025-01-26 to avoid everyone having notifications for something a year on if someone wants to suggest a correction. Folks are free to email to suggest corrections still, of course.
| #!/usr/bin/env python3 | |
| # SPDX-License-Identifier: 0BSD or CC0-1.0 or MIT-0 or Unlicense | |
| # Copyright (c) 2023, Ryan Castellucci, No Rights Reserved | |
| import io, sys | |
| import datetime | |
| import argparse | |
| import requests | |
| import operator | |
| import struct |
This document was originally written several years ago. At the time I was working as an execution core verification engineer at Arm. The following points are coloured heavily by working in and around the execution cores of various processors. Apply a pinch of salt; points contain varying degrees of opinion.
It is still my opinion that RISC-V could be much better designed; though I will also say that if I was building a 32 or 64-bit CPU today I'd likely implement the architecture to benefit from the existing tooling.
Mostly based upon the RISC-V ISA spec v2.0. Some updates have been made for v2.2
The RISC-V ISA has pursued minimalism to a fault. There is a large emphasis on minimizing instruction count, normalizing encoding, etc. This pursuit of minimalism has resulted in false orthogonalities (such as reusing the same instruction for branches, calls and returns) and a requirement for superfluous instructions which impacts code density both in terms of size and
Make sure ffmpeg is up-to-date:
brew update
brew upgrade ffmpeg
Convert a MOV into frames. Tweak the 2/1 if you want more or fewer frames.