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NuttX Stm32f429i-disco/fb
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# | |
# Automatically generated file; DO NOT EDIT. | |
# Nuttx/ Configuration | |
# | |
# | |
# Build Setup | |
# | |
# CONFIG_EXPERIMENTAL is not set | |
# CONFIG_DEFAULT_SMALL is not set | |
CONFIG_HOST_LINUX=y | |
# CONFIG_HOST_OSX is not set | |
# CONFIG_HOST_WINDOWS is not set | |
# CONFIG_HOST_OTHER is not set | |
# | |
# Build Configuration | |
# | |
CONFIG_APPS_DIR="../apps" | |
CONFIG_BUILD_FLAT=y | |
# CONFIG_BUILD_2PASS is not set | |
# | |
# Binary Output Formats | |
# | |
# CONFIG_RRLOAD_BINARY is not set | |
CONFIG_INTELHEX_BINARY=y | |
# CONFIG_MOTOROLA_SREC is not set | |
CONFIG_RAW_BINARY=y | |
# CONFIG_UBOOT_UIMAGE is not set | |
# CONFIG_DFU_BINARY is not set | |
# | |
# Customize Header Files | |
# | |
# CONFIG_ARCH_STDINT_H is not set | |
# CONFIG_ARCH_STDBOOL_H is not set | |
# CONFIG_ARCH_MATH_H is not set | |
# CONFIG_ARCH_FLOAT_H is not set | |
# CONFIG_ARCH_STDARG_H is not set | |
# CONFIG_ARCH_DEBUG_H is not set | |
# | |
# Debug Options | |
# | |
CONFIG_DEBUG_ALERT=y | |
# CONFIG_DEBUG_FEATURES is not set | |
CONFIG_ARCH_HAVE_STACKCHECK=y | |
# CONFIG_STACK_COLORATION is not set | |
CONFIG_ARCH_HAVE_HEAPCHECK=y | |
# CONFIG_HEAP_COLORATION is not set | |
CONFIG_DEBUG_SYMBOLS=y | |
CONFIG_ARCH_HAVE_CUSTOMOPT=y | |
# CONFIG_DEBUG_NOOPT is not set | |
CONFIG_DEBUG_CUSTOMOPT=y | |
# CONFIG_DEBUG_FULLOPT is not set | |
CONFIG_DEBUG_OPTLEVEL="-O2" | |
# | |
# System Type | |
# | |
CONFIG_ARCH_ARM=y | |
# CONFIG_ARCH_AVR is not set | |
# CONFIG_ARCH_HC is not set | |
# CONFIG_ARCH_MIPS is not set | |
# CONFIG_ARCH_MISOC is not set | |
# CONFIG_ARCH_RENESAS is not set | |
# CONFIG_ARCH_RISCV is not set | |
# CONFIG_ARCH_SIM is not set | |
# CONFIG_ARCH_X86 is not set | |
# CONFIG_ARCH_XTENSA is not set | |
# CONFIG_ARCH_Z16 is not set | |
# CONFIG_ARCH_Z80 is not set | |
# CONFIG_ARCH_OR1K is not set | |
CONFIG_ARCH="arm" | |
# | |
# ARM Options | |
# | |
# CONFIG_ARCH_CHIP_A1X is not set | |
# CONFIG_ARCH_CHIP_BCM2708 is not set | |
# CONFIG_ARCH_CHIP_C5471 is not set | |
# CONFIG_ARCH_CHIP_DM320 is not set | |
# CONFIG_ARCH_CHIP_EFM32 is not set | |
# CONFIG_ARCH_CHIP_IMX1 is not set | |
# CONFIG_ARCH_CHIP_IMX6 is not set | |
# CONFIG_ARCH_CHIP_IMXRT is not set | |
# CONFIG_ARCH_CHIP_KINETIS is not set | |
# CONFIG_ARCH_CHIP_KL is not set | |
# CONFIG_ARCH_CHIP_LC823450 is not set | |
# CONFIG_ARCH_CHIP_LM is not set | |
# CONFIG_ARCH_CHIP_LPC11XX is not set | |
# CONFIG_ARCH_CHIP_LPC17XX is not set | |
# CONFIG_ARCH_CHIP_LPC214X is not set | |
# CONFIG_ARCH_CHIP_LPC2378 is not set | |
# CONFIG_ARCH_CHIP_LPC31XX is not set | |
# CONFIG_ARCH_CHIP_LPC43XX is not set | |
# CONFIG_ARCH_CHIP_LPC54XX is not set | |
# CONFIG_ARCH_CHIP_MOXART is not set | |
# CONFIG_ARCH_CHIP_NRF52 is not set | |
# CONFIG_ARCH_CHIP_NUC1XX is not set | |
# CONFIG_ARCH_CHIP_SAMA5 is not set | |
# CONFIG_ARCH_CHIP_SAMD is not set | |
# CONFIG_ARCH_CHIP_SAML is not set | |
# CONFIG_ARCH_CHIP_SAM34 is not set | |
# CONFIG_ARCH_CHIP_SAMV7 is not set | |
CONFIG_ARCH_CHIP_STM32=y | |
# CONFIG_ARCH_CHIP_STM32F0 is not set | |
# CONFIG_ARCH_CHIP_STM32F7 is not set | |
# CONFIG_ARCH_CHIP_STM32L4 is not set | |
# CONFIG_ARCH_CHIP_STR71X is not set | |
# CONFIG_ARCH_CHIP_TMS570 is not set | |
# CONFIG_ARCH_CHIP_TIVA is not set | |
# CONFIG_ARCH_CHIP_XMC4 is not set | |
# CONFIG_ARCH_ARM7TDMI is not set | |
# CONFIG_ARCH_ARM920T is not set | |
# CONFIG_ARCH_ARM926EJS is not set | |
# CONFIG_ARCH_ARM1136J is not set | |
# CONFIG_ARCH_ARM1156T2 is not set | |
# CONFIG_ARCH_ARM1176JZ is not set | |
# CONFIG_ARCH_CORTEXM0 is not set | |
# CONFIG_ARCH_CORTEXM23 is not set | |
# CONFIG_ARCH_CORTEXM3 is not set | |
# CONFIG_ARCH_CORTEXM33 is not set | |
CONFIG_ARCH_CORTEXM4=y | |
# CONFIG_ARCH_CORTEXM7 is not set | |
# CONFIG_ARCH_CORTEXA5 is not set | |
# CONFIG_ARCH_CORTEXA8 is not set | |
# CONFIG_ARCH_CORTEXA9 is not set | |
# CONFIG_ARCH_CORTEXR4 is not set | |
# CONFIG_ARCH_CORTEXR4F is not set | |
# CONFIG_ARCH_CORTEXR5 is not set | |
# CONFIG_ARCH_CORTEXR5F is not set | |
# CONFIG_ARCH_CORTEXR7 is not set | |
# CONFIG_ARCH_CORTEXR7F is not set | |
CONFIG_ARCH_FAMILY="armv7-m" | |
CONFIG_ARCH_CHIP="stm32" | |
# CONFIG_ARMV7M_USEBASEPRI is not set | |
CONFIG_ARCH_HAVE_CMNVECTOR=y | |
# CONFIG_ARMV7M_CMNVECTOR is not set | |
# CONFIG_ARMV7M_LAZYFPU is not set | |
CONFIG_ARCH_HAVE_FPU=y | |
# CONFIG_ARCH_HAVE_DPFPU is not set | |
# CONFIG_ARCH_FPU is not set | |
# CONFIG_ARCH_HAVE_TRUSTZONE is not set | |
CONFIG_ARM_HAVE_MPU_UNIFIED=y | |
# CONFIG_ARM_MPU is not set | |
# | |
# ARMV7M Configuration Options | |
# | |
# CONFIG_ARMV7M_HAVE_ICACHE is not set | |
# CONFIG_ARMV7M_HAVE_DCACHE is not set | |
# CONFIG_ARMV7M_HAVE_ITCM is not set | |
# CONFIG_ARMV7M_HAVE_DTCM is not set | |
# CONFIG_ARMV7M_TOOLCHAIN_IARL is not set | |
# CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT is not set | |
# CONFIG_ARMV7M_TOOLCHAIN_CODEREDL is not set | |
CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL=y | |
# CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL is not set | |
# CONFIG_ARMV7M_TOOLCHAIN_CLANGL is not set | |
CONFIG_ARMV7M_HAVE_STACKCHECK=y | |
# CONFIG_ARMV7M_STACKCHECK is not set | |
# CONFIG_ARMV7M_ITMSYSLOG is not set | |
# | |
# STM32 Configuration Options | |
# | |
# CONFIG_ARCH_CHIP_STM32L151C6 is not set | |
# CONFIG_ARCH_CHIP_STM32L151C8 is not set | |
# CONFIG_ARCH_CHIP_STM32L151CB is not set | |
# CONFIG_ARCH_CHIP_STM32L151R6 is not set | |
# CONFIG_ARCH_CHIP_STM32L151R8 is not set | |
# CONFIG_ARCH_CHIP_STM32L151RB is not set | |
# CONFIG_ARCH_CHIP_STM32L151V6 is not set | |
# CONFIG_ARCH_CHIP_STM32L151V8 is not set | |
# CONFIG_ARCH_CHIP_STM32L151VB is not set | |
# CONFIG_ARCH_CHIP_STM32L152C6 is not set | |
# CONFIG_ARCH_CHIP_STM32L152C8 is not set | |
# CONFIG_ARCH_CHIP_STM32L152CB is not set | |
# CONFIG_ARCH_CHIP_STM32L152R6 is not set | |
# CONFIG_ARCH_CHIP_STM32L152R8 is not set | |
# CONFIG_ARCH_CHIP_STM32L152RB is not set | |
# CONFIG_ARCH_CHIP_STM32L152V6 is not set | |
# CONFIG_ARCH_CHIP_STM32L152V8 is not set | |
# CONFIG_ARCH_CHIP_STM32L152VB is not set | |
# CONFIG_ARCH_CHIP_STM32L152CC is not set | |
# CONFIG_ARCH_CHIP_STM32L152RC is not set | |
# CONFIG_ARCH_CHIP_STM32L152VC is not set | |
# CONFIG_ARCH_CHIP_STM32L162ZD is not set | |
# CONFIG_ARCH_CHIP_STM32L162VE is not set | |
# CONFIG_ARCH_CHIP_STM32F100C8 is not set | |
# CONFIG_ARCH_CHIP_STM32F100CB is not set | |
# CONFIG_ARCH_CHIP_STM32F100R8 is not set | |
# CONFIG_ARCH_CHIP_STM32F100RB is not set | |
# CONFIG_ARCH_CHIP_STM32F100RC is not set | |
# CONFIG_ARCH_CHIP_STM32F100RD is not set | |
# CONFIG_ARCH_CHIP_STM32F100RE is not set | |
# CONFIG_ARCH_CHIP_STM32F100V8 is not set | |
# CONFIG_ARCH_CHIP_STM32F100VB is not set | |
# CONFIG_ARCH_CHIP_STM32F100VC is not set | |
# CONFIG_ARCH_CHIP_STM32F100VD is not set | |
# CONFIG_ARCH_CHIP_STM32F100VE is not set | |
# CONFIG_ARCH_CHIP_STM32F102CB is not set | |
# CONFIG_ARCH_CHIP_STM32F103T8 is not set | |
# CONFIG_ARCH_CHIP_STM32F103TB is not set | |
# CONFIG_ARCH_CHIP_STM32F103C4 is not set | |
# CONFIG_ARCH_CHIP_STM32F103C8 is not set | |
# CONFIG_ARCH_CHIP_STM32F103CB is not set | |
# CONFIG_ARCH_CHIP_STM32F103R8 is not set | |
# CONFIG_ARCH_CHIP_STM32F103RB is not set | |
# CONFIG_ARCH_CHIP_STM32F103RC is not set | |
# CONFIG_ARCH_CHIP_STM32F103RD is not set | |
# CONFIG_ARCH_CHIP_STM32F103RE is not set | |
# CONFIG_ARCH_CHIP_STM32F103RG is not set | |
# CONFIG_ARCH_CHIP_STM32F103V8 is not set | |
# CONFIG_ARCH_CHIP_STM32F103VB is not set | |
# CONFIG_ARCH_CHIP_STM32F103VC is not set | |
# CONFIG_ARCH_CHIP_STM32F103VE is not set | |
# CONFIG_ARCH_CHIP_STM32F103ZE is not set | |
# CONFIG_ARCH_CHIP_STM32F105VB is not set | |
# CONFIG_ARCH_CHIP_STM32F105RB is not set | |
# CONFIG_ARCH_CHIP_STM32F107VC is not set | |
# CONFIG_ARCH_CHIP_STM32F205RG is not set | |
# CONFIG_ARCH_CHIP_STM32F207IG is not set | |
# CONFIG_ARCH_CHIP_STM32F207ZE is not set | |
# CONFIG_ARCH_CHIP_STM32F302K6 is not set | |
# CONFIG_ARCH_CHIP_STM32F302K8 is not set | |
# CONFIG_ARCH_CHIP_STM32F302CB is not set | |
# CONFIG_ARCH_CHIP_STM32F302CC is not set | |
# CONFIG_ARCH_CHIP_STM32F302RB is not set | |
# CONFIG_ARCH_CHIP_STM32F302RC is not set | |
# CONFIG_ARCH_CHIP_STM32F302VB is not set | |
# CONFIG_ARCH_CHIP_STM32F302VC is not set | |
# CONFIG_ARCH_CHIP_STM32F303K6 is not set | |
# CONFIG_ARCH_CHIP_STM32F303K8 is not set | |
# CONFIG_ARCH_CHIP_STM32F303C6 is not set | |
# CONFIG_ARCH_CHIP_STM32F303C8 is not set | |
# CONFIG_ARCH_CHIP_STM32F303CB is not set | |
# CONFIG_ARCH_CHIP_STM32F303CC is not set | |
# CONFIG_ARCH_CHIP_STM32F303RB is not set | |
# CONFIG_ARCH_CHIP_STM32F303RC is not set | |
# CONFIG_ARCH_CHIP_STM32F303RD is not set | |
# CONFIG_ARCH_CHIP_STM32F303RE is not set | |
# CONFIG_ARCH_CHIP_STM32F303VB is not set | |
# CONFIG_ARCH_CHIP_STM32F303VC is not set | |
# CONFIG_ARCH_CHIP_STM32F334K4 is not set | |
# CONFIG_ARCH_CHIP_STM32F334K6 is not set | |
# CONFIG_ARCH_CHIP_STM32F334K8 is not set | |
# CONFIG_ARCH_CHIP_STM32F334C4 is not set | |
# CONFIG_ARCH_CHIP_STM32F334C6 is not set | |
# CONFIG_ARCH_CHIP_STM32F334C8 is not set | |
# CONFIG_ARCH_CHIP_STM32F334R4 is not set | |
# CONFIG_ARCH_CHIP_STM32F334R6 is not set | |
# CONFIG_ARCH_CHIP_STM32F334R8 is not set | |
# CONFIG_ARCH_CHIP_STM32F372C8 is not set | |
# CONFIG_ARCH_CHIP_STM32F372R8 is not set | |
# CONFIG_ARCH_CHIP_STM32F372V8 is not set | |
# CONFIG_ARCH_CHIP_STM32F372CB is not set | |
# CONFIG_ARCH_CHIP_STM32F372RB is not set | |
# CONFIG_ARCH_CHIP_STM32F372VB is not set | |
# CONFIG_ARCH_CHIP_STM32F372CC is not set | |
# CONFIG_ARCH_CHIP_STM32F372RC is not set | |
# CONFIG_ARCH_CHIP_STM32F372VC is not set | |
# CONFIG_ARCH_CHIP_STM32F373C8 is not set | |
# CONFIG_ARCH_CHIP_STM32F373R8 is not set | |
# CONFIG_ARCH_CHIP_STM32F373V8 is not set | |
# CONFIG_ARCH_CHIP_STM32F373CB is not set | |
# CONFIG_ARCH_CHIP_STM32F373RB is not set | |
# CONFIG_ARCH_CHIP_STM32F373VB is not set | |
# CONFIG_ARCH_CHIP_STM32F373CC is not set | |
# CONFIG_ARCH_CHIP_STM32F373RC is not set | |
# CONFIG_ARCH_CHIP_STM32F373VC is not set | |
# CONFIG_ARCH_CHIP_STM32F401CB is not set | |
# CONFIG_ARCH_CHIP_STM32F401RB is not set | |
# CONFIG_ARCH_CHIP_STM32F401VB is not set | |
# CONFIG_ARCH_CHIP_STM32F401CC is not set | |
# CONFIG_ARCH_CHIP_STM32F401RC is not set | |
# CONFIG_ARCH_CHIP_STM32F401VC is not set | |
# CONFIG_ARCH_CHIP_STM32F401CD is not set | |
# CONFIG_ARCH_CHIP_STM32F401RD is not set | |
# CONFIG_ARCH_CHIP_STM32F401VD is not set | |
# CONFIG_ARCH_CHIP_STM32F401CE is not set | |
# CONFIG_ARCH_CHIP_STM32F401RE is not set | |
# CONFIG_ARCH_CHIP_STM32F401VE is not set | |
# CONFIG_ARCH_CHIP_STM32F410RB is not set | |
# CONFIG_ARCH_CHIP_STM32F411RE is not set | |
# CONFIG_ARCH_CHIP_STM32F411VE is not set | |
# CONFIG_ARCH_CHIP_STM32F405RG is not set | |
# CONFIG_ARCH_CHIP_STM32F405VG is not set | |
# CONFIG_ARCH_CHIP_STM32F405ZG is not set | |
# CONFIG_ARCH_CHIP_STM32F407VE is not set | |
# CONFIG_ARCH_CHIP_STM32F407VG is not set | |
# CONFIG_ARCH_CHIP_STM32F407ZE is not set | |
# CONFIG_ARCH_CHIP_STM32F407ZG is not set | |
# CONFIG_ARCH_CHIP_STM32F407IE is not set | |
# CONFIG_ARCH_CHIP_STM32F407IG is not set | |
# CONFIG_ARCH_CHIP_STM32F427V is not set | |
# CONFIG_ARCH_CHIP_STM32F427Z is not set | |
# CONFIG_ARCH_CHIP_STM32F427I is not set | |
# CONFIG_ARCH_CHIP_STM32F429V is not set | |
CONFIG_ARCH_CHIP_STM32F429Z=y | |
# CONFIG_ARCH_CHIP_STM32F429I is not set | |
# CONFIG_ARCH_CHIP_STM32F429B is not set | |
# CONFIG_ARCH_CHIP_STM32F429N is not set | |
# CONFIG_ARCH_CHIP_STM32F446M is not set | |
# CONFIG_ARCH_CHIP_STM32F446R is not set | |
# CONFIG_ARCH_CHIP_STM32F446V is not set | |
# CONFIG_ARCH_CHIP_STM32F446Z is not set | |
# CONFIG_ARCH_CHIP_STM32F469A is not set | |
# CONFIG_ARCH_CHIP_STM32F469I is not set | |
# CONFIG_ARCH_CHIP_STM32F469B is not set | |
# CONFIG_ARCH_CHIP_STM32F469N is not set | |
CONFIG_STM32_FLASH_CONFIG_DEFAULT=y | |
# CONFIG_STM32_FLASH_CONFIG_4 is not set | |
# CONFIG_STM32_FLASH_CONFIG_6 is not set | |
# CONFIG_STM32_FLASH_CONFIG_8 is not set | |
# CONFIG_STM32_FLASH_CONFIG_B is not set | |
# CONFIG_STM32_FLASH_CONFIG_C is not set | |
# CONFIG_STM32_FLASH_CONFIG_D is not set | |
# CONFIG_STM32_FLASH_CONFIG_E is not set | |
# CONFIG_STM32_FLASH_CONFIG_F is not set | |
# CONFIG_STM32_FLASH_CONFIG_G is not set | |
# CONFIG_STM32_FLASH_CONFIG_I is not set | |
# CONFIG_STM32_STM32L15XX is not set | |
# CONFIG_STM32_ENERGYLITE is not set | |
# CONFIG_STM32_STM32F10XX is not set | |
# CONFIG_STM32_VALUELINE is not set | |
# CONFIG_STM32_CONNECTIVITYLINE is not set | |
# CONFIG_STM32_PERFORMANCELINE is not set | |
# CONFIG_STM32_USBACCESSLINE is not set | |
# CONFIG_STM32_HIGHDENSITY is not set | |
# CONFIG_STM32_MEDIUMDENSITY is not set | |
# CONFIG_STM32_LOWDENSITY is not set | |
# CONFIG_STM32_STM32F20XX is not set | |
# CONFIG_STM32_STM32F205 is not set | |
# CONFIG_STM32_STM32F207 is not set | |
# CONFIG_STM32_STM32F30XX is not set | |
# CONFIG_STM32_STM32F302 is not set | |
# CONFIG_STM32_STM32F303 is not set | |
# CONFIG_STM32_STM32F33XX is not set | |
# CONFIG_STM32_STM32F37XX is not set | |
CONFIG_STM32_STM32F4XXX=y | |
# CONFIG_STM32_STM32F401xBC is not set | |
# CONFIG_STM32_STM32F401xDE is not set | |
# CONFIG_STM32_STM32F401 is not set | |
# CONFIG_STM32_STM32F410 is not set | |
# CONFIG_STM32_STM32F411 is not set | |
# CONFIG_STM32_STM32F405 is not set | |
# CONFIG_STM32_STM32F407 is not set | |
# CONFIG_STM32_STM32F427 is not set | |
CONFIG_STM32_STM32F429=y | |
# CONFIG_STM32_STM32F446 is not set | |
# CONFIG_STM32_STM32F469 is not set | |
# CONFIG_STM32_DFU is not set | |
# | |
# STM32 Peripheral Support | |
# | |
CONFIG_STM32_HAVE_CCM=y | |
# CONFIG_STM32_HAVE_USBDEV is not set | |
CONFIG_STM32_HAVE_OTGFS=y | |
CONFIG_STM32_HAVE_FSMC=y | |
# CONFIG_STM32_HAVE_HRTIM1 is not set | |
CONFIG_STM32_HAVE_LTDC=y | |
CONFIG_STM32_HAVE_USART3=y | |
CONFIG_STM32_HAVE_UART4=y | |
CONFIG_STM32_HAVE_UART5=y | |
CONFIG_STM32_HAVE_USART6=y | |
CONFIG_STM32_HAVE_UART7=y | |
CONFIG_STM32_HAVE_UART8=y | |
CONFIG_STM32_HAVE_TIM1=y | |
# CONFIG_STM32_HAVE_TIM2 is not set | |
CONFIG_STM32_HAVE_TIM3=y | |
CONFIG_STM32_HAVE_TIM4=y | |
CONFIG_STM32_HAVE_TIM5=y | |
CONFIG_STM32_HAVE_TIM6=y | |
CONFIG_STM32_HAVE_TIM7=y | |
CONFIG_STM32_HAVE_TIM8=y | |
CONFIG_STM32_HAVE_TIM9=y | |
CONFIG_STM32_HAVE_TIM10=y | |
CONFIG_STM32_HAVE_TIM11=y | |
CONFIG_STM32_HAVE_TIM12=y | |
CONFIG_STM32_HAVE_TIM13=y | |
CONFIG_STM32_HAVE_TIM14=y | |
# CONFIG_STM32_HAVE_TIM15 is not set | |
# CONFIG_STM32_HAVE_TIM16 is not set | |
# CONFIG_STM32_HAVE_TIM17 is not set | |
CONFIG_STM32_HAVE_ADC2=y | |
CONFIG_STM32_HAVE_ADC3=y | |
# CONFIG_STM32_HAVE_ADC4 is not set | |
# CONFIG_STM32_HAVE_ADC1_DMA is not set | |
# CONFIG_STM32_HAVE_ADC2_DMA is not set | |
# CONFIG_STM32_HAVE_ADC3_DMA is not set | |
# CONFIG_STM32_HAVE_ADC4_DMA is not set | |
# CONFIG_STM32_HAVE_SDADC1 is not set | |
# CONFIG_STM32_HAVE_SDADC2 is not set | |
# CONFIG_STM32_HAVE_SDADC3 is not set | |
# CONFIG_STM32_HAVE_SDADC1_DMA is not set | |
# CONFIG_STM32_HAVE_SDADC2_DMA is not set | |
# CONFIG_STM32_HAVE_SDADC3_DMA is not set | |
CONFIG_STM32_HAVE_CAN1=y | |
CONFIG_STM32_HAVE_CAN2=y | |
# CONFIG_STM32_HAVE_COMP1 is not set | |
# CONFIG_STM32_HAVE_COMP2 is not set | |
# CONFIG_STM32_HAVE_COMP3 is not set | |
# CONFIG_STM32_HAVE_COMP4 is not set | |
# CONFIG_STM32_HAVE_COMP5 is not set | |
# CONFIG_STM32_HAVE_COMP6 is not set | |
# CONFIG_STM32_HAVE_COMP7 is not set | |
CONFIG_STM32_HAVE_DAC1=y | |
CONFIG_STM32_HAVE_DAC2=y | |
CONFIG_STM32_HAVE_RNG=y | |
CONFIG_STM32_HAVE_ETHMAC=y | |
CONFIG_STM32_HAVE_I2C2=y | |
CONFIG_STM32_HAVE_I2C3=y | |
CONFIG_STM32_HAVE_SPI2=y | |
CONFIG_STM32_HAVE_SPI3=y | |
CONFIG_STM32_HAVE_I2S3=y | |
CONFIG_STM32_HAVE_SPI4=y | |
CONFIG_STM32_HAVE_SPI5=y | |
CONFIG_STM32_HAVE_SPI6=y | |
# CONFIG_STM32_HAVE_SAIPLL is not set | |
# CONFIG_STM32_HAVE_I2SPLL is not set | |
# CONFIG_STM32_HAVE_OPAMP1 is not set | |
# CONFIG_STM32_HAVE_OPAMP2 is not set | |
# CONFIG_STM32_HAVE_OPAMP3 is not set | |
# CONFIG_STM32_HAVE_OPAMP4 is not set | |
# CONFIG_STM32_ADC1 is not set | |
# CONFIG_STM32_ADC2 is not set | |
# CONFIG_STM32_ADC3 is not set | |
# CONFIG_STM32_BKPSRAM is not set | |
# CONFIG_STM32_CAN1 is not set | |
# CONFIG_STM32_CAN2 is not set | |
# CONFIG_STM32_CCMDATARAM is not set | |
# CONFIG_STM32_CRC is not set | |
# CONFIG_STM32_CRYP is not set | |
# CONFIG_STM32_DMA1 is not set | |
# CONFIG_STM32_DMA2 is not set | |
# CONFIG_STM32_DAC1 is not set | |
# CONFIG_STM32_DAC2 is not set | |
# CONFIG_STM32_DCMI is not set | |
# CONFIG_STM32_ETHMAC is not set | |
CONFIG_STM32_FSMC=y | |
# CONFIG_STM32_HASH is not set | |
# CONFIG_HRTIM is not set | |
# CONFIG_STM32_I2C1 is not set | |
# CONFIG_STM32_I2C2 is not set | |
CONFIG_STM32_I2C3=y | |
CONFIG_STM32_LTDC=y | |
CONFIG_STM32_DMA2D=y | |
# CONFIG_STM32_OPAMP is not set | |
# CONFIG_STM32_OTGFS is not set | |
# CONFIG_STM32_OTGHS is not set | |
CONFIG_STM32_PWR=y | |
# CONFIG_STM32_RNG is not set | |
# CONFIG_STM32_SDIO is not set | |
# CONFIG_STM32_SPI1 is not set | |
# CONFIG_STM32_SPI2 is not set | |
# CONFIG_STM32_SPI3 is not set | |
# CONFIG_STM32_I2S3 is not set | |
# CONFIG_STM32_SPI4 is not set | |
CONFIG_STM32_SPI5=y | |
# CONFIG_STM32_SPI6 is not set | |
CONFIG_STM32_SYSCFG=y | |
# CONFIG_STM32_TIM1 is not set | |
# CONFIG_STM32_TIM2 is not set | |
# CONFIG_STM32_TIM3 is not set | |
# CONFIG_STM32_TIM4 is not set | |
# CONFIG_STM32_TIM5 is not set | |
# CONFIG_STM32_TIM6 is not set | |
# CONFIG_STM32_TIM7 is not set | |
# CONFIG_STM32_TIM8 is not set | |
# CONFIG_STM32_TIM9 is not set | |
# CONFIG_STM32_TIM10 is not set | |
# CONFIG_STM32_TIM11 is not set | |
# CONFIG_STM32_TIM12 is not set | |
# CONFIG_STM32_TIM13 is not set | |
# CONFIG_STM32_TIM14 is not set | |
CONFIG_STM32_USART1=y | |
# CONFIG_STM32_USART2 is not set | |
# CONFIG_STM32_USART3 is not set | |
# CONFIG_STM32_UART4 is not set | |
# CONFIG_STM32_UART5 is not set | |
# CONFIG_STM32_USART6 is not set | |
# CONFIG_STM32_UART7 is not set | |
# CONFIG_STM32_UART8 is not set | |
# CONFIG_STM32_IWDG is not set | |
# CONFIG_STM32_WWDG is not set | |
CONFIG_STM32_SPI=y | |
CONFIG_STM32_I2C=y | |
# CONFIG_STM32_NOEXT_VECTORS is not set | |
# | |
# Alternate Pin Mapping | |
# | |
# CONFIG_STM32_FLASH_PREFETCH is not set | |
# CONFIG_STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW is not set | |
# CONFIG_STM32_JTAG_DISABLE is not set | |
# CONFIG_STM32_JTAG_FULL_ENABLE is not set | |
# CONFIG_STM32_JTAG_NOJNTRST_ENABLE is not set | |
CONFIG_STM32_JTAG_SW_ENABLE=y | |
CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y | |
# CONFIG_STM32_FORCEPOWER is not set | |
# CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is not set | |
CONFIG_STM32_CCMEXCLUDE=y | |
CONFIG_STM32_FSMC_SRAM=y | |
# | |
# Timer Configuration | |
# | |
# CONFIG_STM32_ONESHOT is not set | |
# CONFIG_STM32_FREERUN is not set | |
# CONFIG_STM32_TIM1_CAP is not set | |
# CONFIG_STM32_TIM3_CAP is not set | |
# CONFIG_STM32_TIM4_CAP is not set | |
# CONFIG_STM32_TIM5_CAP is not set | |
# CONFIG_STM32_TIM8_CAP is not set | |
# CONFIG_STM32_TIM9_CAP is not set | |
# CONFIG_STM32_TIM10_CAP is not set | |
# CONFIG_STM32_TIM11_CAP is not set | |
# CONFIG_STM32_TIM12_CAP is not set | |
# CONFIG_STM32_TIM13_CAP is not set | |
# CONFIG_STM32_TIM14_CAP is not set | |
# | |
# HRTIM Configuration | |
# | |
CONFIG_STM32_USART=y | |
# CONFIG_STM32_USART_RXDMA is not set | |
CONFIG_STM32_SERIALDRIVER=y | |
# CONFIG_STM32_1WIREDRIVER is not set | |
# CONFIG_STM32_HCIUART is not set | |
# CONFIG_STM32_HCIUART_RXDMA is not set | |
# | |
# U[S]ART Configuration | |
# | |
# | |
# U[S]ART Device Configuration | |
# | |
CONFIG_STM32_USART1_SERIALDRIVER=y | |
# CONFIG_STM32_USART1_1WIREDRIVER is not set | |
# CONFIG_USART1_RS485 is not set | |
# | |
# Serial Driver Configuration | |
# | |
# CONFIG_SERIAL_DISABLE_REORDERING is not set | |
# CONFIG_STM32_FLOWCONTROL_BROKEN is not set | |
# CONFIG_STM32_USART_BREAKS is not set | |
# | |
# HCI UART Driver Configuration | |
# | |
# CONFIG_STM32_HCIUART_SW_RXFLOW is not set | |
# | |
# SPI Configuration | |
# | |
# CONFIG_STM32_SPI_INTERRUPTS is not set | |
# CONFIG_STM32_SPI_DMA is not set | |
# | |
# I2C Configuration | |
# | |
# CONFIG_STM32_I2C_ALT is not set | |
# CONFIG_STM32_I2C_DYNTIMEO is not set | |
CONFIG_STM32_I2CTIMEOSEC=0 | |
CONFIG_STM32_I2CTIMEOMS=500 | |
CONFIG_STM32_I2CTIMEOTICKS=500 | |
# CONFIG_STM32_I2C_DUTY16_9 is not set | |
# CONFIG_STM32_HAVE_RTC_COUNTER is not set | |
# CONFIG_STM32_HAVE_RTC_SUBSECONDS is not set | |
# | |
# USB FS Host Configuration | |
# | |
# | |
# USB HS Host Configuration | |
# | |
# | |
# USB Host Debug Configuration | |
# | |
# | |
# USB Device Configuration | |
# | |
# | |
# LTDC Configuration | |
# | |
CONFIG_STM32_LTDC_INTERFACE=y | |
CONFIG_STM32_LTDC_BACKLIGHT=y | |
CONFIG_STM32_LTDC_DEFBACKLIGHT=0xf0 | |
CONFIG_STM32_LTDC_BACKCOLOR=0x0 | |
# CONFIG_STM32_LTDC_DITHER is not set | |
CONFIG_STM32_LTDC_FB_BASE=0xD07B5000 | |
CONFIG_STM32_LTDC_FB_SIZE=307200 | |
# CONFIG_STM32_LTDC_L1_L8 is not set | |
# CONFIG_STM32_LTDC_L1_AL44 is not set | |
# CONFIG_STM32_LTDC_L1_AL88 is not set | |
CONFIG_STM32_LTDC_L1_RGB565=y | |
# CONFIG_STM32_LTDC_L1_ARGB4444 is not set | |
# CONFIG_STM32_LTDC_L1_ARGB1555 is not set | |
# CONFIG_STM32_LTDC_L1_RGB888 is not set | |
# CONFIG_STM32_LTDC_L1_ARGB8888 is not set | |
CONFIG_STM32_LTDC_L2=y | |
# CONFIG_STM32_LTDC_L2_L8 is not set | |
# CONFIG_STM32_LTDC_L2_AL44 is not set | |
# CONFIG_STM32_LTDC_L2_AL88 is not set | |
CONFIG_STM32_LTDC_L2_RGB565=y | |
# CONFIG_STM32_LTDC_L2_ARGB4444 is not set | |
# CONFIG_STM32_LTDC_L2_ARGB1555 is not set | |
# CONFIG_STM32_LTDC_L2_RGB888 is not set | |
# CONFIG_STM32_LTDC_L2_ARGB8888 is not set | |
# | |
# DMA2D Configuration | |
# | |
CONFIG_STM32_DMA2D_NLAYERS=1 | |
# | |
# Supported pixel format | |
# | |
CONFIG_STM32_DMA2D_RGB565=y | |
# CONFIG_STM32_DMA2D_ARGB4444 is not set | |
# CONFIG_STM32_DMA2D_ARGB1555 is not set | |
# CONFIG_STM32_DMA2D_RGB888 is not set | |
# CONFIG_STM32_DMA2D_ARGB8888 is not set | |
# CONFIG_ARCH_TOOLCHAIN_IAR is not set | |
CONFIG_ARCH_TOOLCHAIN_GNU=y | |
# | |
# Architecture Options | |
# | |
# CONFIG_ARCH_NOINTC is not set | |
# CONFIG_ARCH_VECNOTIRQ is not set | |
# CONFIG_ARCH_DMA is not set | |
CONFIG_ARCH_HAVE_IRQPRIO=y | |
# CONFIG_ARCH_L2CACHE is not set | |
# CONFIG_ARCH_HAVE_COHERENT_DCACHE is not set | |
# CONFIG_ARCH_HAVE_ADDRENV is not set | |
# CONFIG_ARCH_NEED_ADDRENV_MAPPING is not set | |
# CONFIG_ARCH_HAVE_MULTICPU is not set | |
CONFIG_ARCH_HAVE_VFORK=y | |
# CONFIG_ARCH_HAVE_MMU is not set | |
CONFIG_ARCH_HAVE_MPU=y | |
# CONFIG_ARCH_NAND_HWECC is not set | |
# CONFIG_ARCH_HAVE_EXTCLK is not set | |
# CONFIG_ARCH_HAVE_POWEROFF is not set | |
CONFIG_ARCH_HAVE_PROGMEM=y | |
CONFIG_ARCH_HAVE_RESET=y | |
CONFIG_ARCH_HAVE_FETCHADD=y | |
# CONFIG_ARCH_HAVE_RTC_SUBSECONDS is not set | |
# CONFIG_ARCH_GLOBAL_IRQDISABLE is not set | |
# CONFIG_ARCH_USE_MPU is not set | |
# CONFIG_ARCH_IRQPRIO is not set | |
CONFIG_ARCH_STACKDUMP=y | |
# CONFIG_ENDIAN_BIG is not set | |
# CONFIG_ARCH_IDLE_CUSTOM is not set | |
# CONFIG_ARCH_HAVE_RAMFUNCS is not set | |
CONFIG_ARCH_HAVE_RAMVECTORS=y | |
# CONFIG_ARCH_RAMVECTORS is not set | |
# CONFIG_ARCH_MINIMAL_VECTORTABLE is not set | |
# | |
# Board Settings | |
# | |
CONFIG_BOARD_LOOPSPERMSEC=16717 | |
# CONFIG_ARCH_CALIBRATION is not set | |
# | |
# Interrupt options | |
# | |
CONFIG_ARCH_HAVE_INTERRUPTSTACK=y | |
CONFIG_ARCH_INTERRUPTSTACK=0 | |
CONFIG_ARCH_HAVE_HIPRI_INTERRUPT=y | |
# CONFIG_ARCH_HIPRI_INTERRUPT is not set | |
# | |
# Boot options | |
# | |
# CONFIG_BOOT_RUNFROMEXTSRAM is not set | |
CONFIG_BOOT_RUNFROMFLASH=y | |
# CONFIG_BOOT_RUNFROMISRAM is not set | |
# CONFIG_BOOT_RUNFROMSDRAM is not set | |
# CONFIG_BOOT_COPYTORAM is not set | |
# | |
# Boot Memory Configuration | |
# | |
CONFIG_RAM_START=0x20000000 | |
CONFIG_RAM_SIZE=114688 | |
# CONFIG_ARCH_HAVE_SDRAM is not set | |
# | |
# Board Selection | |
# | |
CONFIG_ARCH_BOARD_STM32F429I_DISCO=y | |
# CONFIG_ARCH_BOARD_CUSTOM is not set | |
CONFIG_ARCH_BOARD="stm32f429i-disco" | |
# | |
# Common Board Options | |
# | |
CONFIG_ARCH_HAVE_LEDS=y | |
CONFIG_ARCH_LEDS=y | |
CONFIG_ARCH_HAVE_BUTTONS=y | |
CONFIG_ARCH_BUTTONS=y | |
CONFIG_ARCH_HAVE_IRQBUTTONS=y | |
# CONFIG_ARCH_IRQBUTTONS is not set | |
# | |
# Board-Specific Options | |
# | |
# CONFIG_STM32F429I_DISCO_FLASH is not set | |
# CONFIG_STM32F429I_DISCO_RAMMTD is not set | |
# CONFIG_STM32F429I_DISCO_ILI9341 is not set | |
# CONFIG_BOARD_CRASHDUMP is not set | |
CONFIG_LIB_BOARDCTL=y | |
# CONFIG_BOARDCTL_RESET is not set | |
# CONFIG_BOARDCTL_UNIQUEID is not set | |
# CONFIG_BOARDCTL_APP_SYMTAB is not set | |
# CONFIG_BOARDCTL_IOCTL is not set | |
# | |
# RTOS Features | |
# | |
CONFIG_DISABLE_OS_API=y | |
# CONFIG_DISABLE_POSIX_TIMERS is not set | |
# CONFIG_DISABLE_PTHREAD is not set | |
# CONFIG_DISABLE_SIGNALS is not set | |
# CONFIG_DISABLE_MQUEUE is not set | |
# CONFIG_DISABLE_ENVIRON is not set | |
# | |
# Clocks and Timers | |
# | |
CONFIG_ARCH_HAVE_TICKLESS=y | |
# CONFIG_SCHED_TICKLESS is not set | |
CONFIG_USEC_PER_TICK=10000 | |
# CONFIG_SYSTEM_TIME64 is not set | |
# CONFIG_CLOCK_MONOTONIC is not set | |
CONFIG_ARCH_HAVE_TIMEKEEPING=y | |
# CONFIG_JULIAN_TIME is not set | |
CONFIG_START_YEAR=2017 | |
CONFIG_START_MONTH=11 | |
CONFIG_START_DAY=15 | |
CONFIG_MAX_WDOGPARMS=2 | |
CONFIG_PREALLOC_WDOGS=4 | |
CONFIG_WDOG_INTRESERVE=0 | |
CONFIG_PREALLOC_TIMERS=4 | |
# | |
# Tasks and Scheduling | |
# | |
# CONFIG_SPINLOCK is not set | |
# CONFIG_INIT_NONE is not set | |
CONFIG_INIT_ENTRYPOINT=y | |
# CONFIG_INIT_FILEPATH is not set | |
CONFIG_USER_ENTRYPOINT="nsh_main" | |
CONFIG_RR_INTERVAL=200 | |
# CONFIG_SCHED_SPORADIC is not set | |
CONFIG_TASK_NAME_SIZE=0 | |
CONFIG_MAX_TASKS=16 | |
# CONFIG_SCHED_HAVE_PARENT is not set | |
CONFIG_SCHED_WAITPID=y | |
# | |
# Pthread Options | |
# | |
CONFIG_NPTHREAD_KEYS=4 | |
# CONFIG_PTHREAD_MUTEX_TYPES is not set | |
CONFIG_PTHREAD_MUTEX_ROBUST=y | |
# CONFIG_PTHREAD_MUTEX_UNSAFE is not set | |
# CONFIG_PTHREAD_MUTEX_BOTH is not set | |
# CONFIG_PTHREAD_CLEANUP is not set | |
# CONFIG_CANCELLATION_POINTS is not set | |
# | |
# Performance Monitoring | |
# | |
# CONFIG_SCHED_IRQMONITOR is not set | |
# CONFIG_SCHED_CPULOAD is not set | |
# CONFIG_SCHED_INSTRUMENTATION is not set | |
# | |
# Files and I/O | |
# | |
CONFIG_DEV_CONSOLE=y | |
# CONFIG_FDCLONE_DISABLE is not set | |
# CONFIG_FDCLONE_STDIO is not set | |
CONFIG_SDCLONE_DISABLE=y | |
CONFIG_NFILE_DESCRIPTORS=8 | |
CONFIG_NFILE_STREAMS=8 | |
CONFIG_NAME_MAX=32 | |
# CONFIG_PRIORITY_INHERITANCE is not set | |
# | |
# RTOS hooks | |
# | |
# CONFIG_BOARD_INITIALIZE is not set | |
# CONFIG_SCHED_STARTHOOK is not set | |
# CONFIG_SCHED_ATEXIT is not set | |
# CONFIG_SCHED_ONEXIT is not set | |
# CONFIG_SIG_EVTHREAD is not set | |
# | |
# Signal Numbers | |
# | |
CONFIG_SIG_SIGUSR1=1 | |
CONFIG_SIG_SIGUSR2=2 | |
CONFIG_SIG_SIGALARM=3 | |
CONFIG_SIG_SIGCONDTIMEDOUT=16 | |
CONFIG_SIG_SIGWORK=17 | |
# | |
# POSIX Message Queue Options | |
# | |
CONFIG_PREALLOC_MQ_MSGS=4 | |
CONFIG_MQ_MAXMSGSIZE=64 | |
# CONFIG_MODULE is not set | |
# | |
# Work queue support | |
# | |
CONFIG_SCHED_WORKQUEUE=y | |
CONFIG_SCHED_HPWORK=y | |
CONFIG_SCHED_HPWORKPRIORITY=224 | |
CONFIG_SCHED_HPWORKPERIOD=50000 | |
CONFIG_SCHED_HPWORKSTACKSIZE=2048 | |
# CONFIG_SCHED_LPWORK is not set | |
# | |
# Stack and heap information | |
# | |
CONFIG_IDLETHREAD_STACKSIZE=1024 | |
CONFIG_USERMAIN_STACKSIZE=2048 | |
CONFIG_PTHREAD_STACK_MIN=256 | |
CONFIG_PTHREAD_STACK_DEFAULT=2048 | |
# CONFIG_LIB_SYSCALL is not set | |
# | |
# Device Drivers | |
# | |
CONFIG_DISABLE_POLL=y | |
CONFIG_DEV_NULL=y | |
# CONFIG_DEV_ZERO is not set | |
# CONFIG_DEV_URANDOM is not set | |
# CONFIG_DEV_LOOP is not set | |
# | |
# Buffering | |
# | |
# CONFIG_DRVR_WRITEBUFFER is not set | |
# CONFIG_DRVR_READAHEAD is not set | |
# CONFIG_RAMDISK is not set | |
# CONFIG_CAN is not set | |
# CONFIG_ARCH_HAVE_PWM_PULSECOUNT is not set | |
# CONFIG_ARCH_HAVE_PWM_MULTICHAN is not set | |
# CONFIG_PWM is not set | |
CONFIG_ARCH_HAVE_I2CRESET=y | |
CONFIG_I2C=y | |
# CONFIG_I2C_SLAVE is not set | |
# CONFIG_I2C_POLLED is not set | |
# CONFIG_I2C_RESET is not set | |
# CONFIG_I2C_TRACE is not set | |
# CONFIG_I2C_DRIVER is not set | |
# | |
# I2C Multiplexer Support | |
# | |
# CONFIG_I2CMULTIPLEXER_PCA9540BDP is not set | |
# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set | |
# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set | |
CONFIG_ARCH_HAVE_SPI_BITORDER=y | |
CONFIG_SPI=y | |
# CONFIG_SPI_SLAVE is not set | |
CONFIG_SPI_EXCHANGE=y | |
CONFIG_SPI_CMDDATA=y | |
# CONFIG_SPI_CALLBACK is not set | |
# CONFIG_SPI_HWFEATURES is not set | |
# CONFIG_SPI_BITORDER is not set | |
# CONFIG_SPI_CS_DELAY_CONTROL is not set | |
# CONFIG_SPI_DRIVER is not set | |
# CONFIG_SPI_BITBANG is not set | |
# CONFIG_I2S is not set | |
# | |
# Timer Driver Support | |
# | |
# CONFIG_TIMER is not set | |
# CONFIG_ONESHOT is not set | |
# CONFIG_RTC is not set | |
# CONFIG_WATCHDOG is not set | |
# CONFIG_TIMERS_CS2100CP is not set | |
# CONFIG_ANALOG is not set | |
# CONFIG_DRIVERS_AUDIO is not set | |
CONFIG_DRIVERS_VIDEO=y | |
CONFIG_VIDEO_FB=y | |
# CONFIG_VIDEO_OV2640 is not set | |
# CONFIG_BCH is not set | |
CONFIG_INPUT=y | |
# CONFIG_MOUSE is not set | |
# CONFIG_INPUT_MAX11802 is not set | |
# CONFIG_INPUT_TSC2007 is not set | |
# CONFIG_INPUT_FT5X06 is not set | |
# CONFIG_INPUT_ADS7843E is not set | |
# CONFIG_INPUT_MXT is not set | |
CONFIG_INPUT_STMPE811=y | |
# CONFIG_STMPE811_SPI is not set | |
CONFIG_STMPE811_I2C=y | |
CONFIG_STMPE811_ACTIVELOW=y | |
CONFIG_STMPE811_EDGE=y | |
# CONFIG_STMPE811_MULTIPLE is not set | |
# CONFIG_STMPE811_TSC_DISABLE is not set | |
# CONFIG_STMPE811_SWAPXY is not set | |
CONFIG_STMPE811_THRESHX=39 | |
CONFIG_STMPE811_THRESHY=51 | |
CONFIG_STMPE811_ADC_DISABLE=y | |
CONFIG_STMPE811_GPIO_DISABLE=y | |
CONFIG_STMPE811_TEMP_DISABLE=y | |
# CONFIG_INPUT_CYPRESS_MBR3108 is not set | |
# CONFIG_BUTTONS is not set | |
# CONFIG_DJOYSTICK is not set | |
# CONFIG_AJOYSTICK is not set | |
# CONFIG_INPUT_NUNCHUCK is not set | |
# | |
# IO Expander/GPIO Support | |
# | |
# CONFIG_IOEXPANDER is not set | |
# CONFIG_DEV_GPIO is not set | |
# | |
# LCD Driver Support | |
# | |
# CONFIG_LCD is not set | |
# CONFIG_SLCD is not set | |
# | |
# LED Support | |
# | |
# CONFIG_USERLED is not set | |
# CONFIG_LEDS_APA102 is not set | |
# CONFIG_RGBLED is not set | |
# CONFIG_PCA9635PW is not set | |
# CONFIG_NCP5623C is not set | |
# CONFIG_MMCSD is not set | |
# CONFIG_MODEM is not set | |
# CONFIG_MTD is not set | |
# CONFIG_EEPROM is not set | |
# CONFIG_PIPES is not set | |
# CONFIG_PM is not set | |
# CONFIG_DRIVERS_POWERLED is not set | |
# CONFIG_DRIVERS_SMPS is not set | |
# CONFIG_DRIVERS_MOTOR is not set | |
# CONFIG_POWER is not set | |
# CONFIG_SENSORS is not set | |
CONFIG_SERIAL=y | |
# CONFIG_DEV_LOWCONSOLE is not set | |
# CONFIG_SERIAL_REMOVABLE is not set | |
CONFIG_SERIAL_CONSOLE=y | |
# CONFIG_16550_UART is not set | |
# CONFIG_OTHER_UART_SERIALDRIVER is not set | |
CONFIG_MCU_SERIAL=y | |
CONFIG_STANDARD_SERIAL=y | |
# CONFIG_SERIAL_IFLOWCONTROL is not set | |
# CONFIG_SERIAL_OFLOWCONTROL is not set | |
# CONFIG_SERIAL_DMA is not set | |
CONFIG_ARCH_HAVE_SERIAL_TERMIOS=y | |
# CONFIG_SERIAL_TERMIOS is not set | |
CONFIG_USART1_SERIAL_CONSOLE=y | |
# CONFIG_OTHER_SERIAL_CONSOLE is not set | |
# CONFIG_NO_SERIAL_CONSOLE is not set | |
# CONFIG_UART_SERIALDRIVER is not set | |
# CONFIG_UART0_SERIALDRIVER is not set | |
# CONFIG_UART1_SERIALDRIVER is not set | |
# CONFIG_UART2_SERIALDRIVER is not set | |
# CONFIG_UART3_SERIALDRIVER is not set | |
# CONFIG_UART4_SERIALDRIVER is not set | |
# CONFIG_UART5_SERIALDRIVER is not set | |
# CONFIG_UART6_SERIALDRIVER is not set | |
# CONFIG_UART7_SERIALDRIVER is not set | |
# CONFIG_UART8_SERIALDRIVER is not set | |
# CONFIG_LPUART_SERIALDRIVER is not set | |
# CONFIG_LPUART0_SERIALDRIVER is not set | |
# CONFIG_LPUART1_SERIALDRIVER is not set | |
# CONFIG_LPUART2_SERIALDRIVER is not set | |
# CONFIG_LPUART3_SERIALDRIVER is not set | |
# CONFIG_LPUART4_SERIALDRIVER is not set | |
# CONFIG_LPUART5_SERIALDRIVER is not set | |
# CONFIG_LPUART6_SERIALDRIVER is not set | |
# CONFIG_LPUART7_SERIALDRIVER is not set | |
# CONFIG_LPUART8_SERIALDRIVER is not set | |
# CONFIG_USART0_SERIALDRIVER is not set | |
CONFIG_USART1_SERIALDRIVER=y | |
# CONFIG_USART2_SERIALDRIVER is not set | |
# CONFIG_USART3_SERIALDRIVER is not set | |
# CONFIG_USART4_SERIALDRIVER is not set | |
# CONFIG_USART5_SERIALDRIVER is not set | |
# CONFIG_USART6_SERIALDRIVER is not set | |
# CONFIG_USART7_SERIALDRIVER is not set | |
# CONFIG_USART8_SERIALDRIVER is not set | |
# CONFIG_USART9_SERIALDRIVER is not set | |
# | |
# USART1 Configuration | |
# | |
CONFIG_USART1_RXBUFSIZE=256 | |
CONFIG_USART1_TXBUFSIZE=256 | |
CONFIG_USART1_BAUD=115200 | |
CONFIG_USART1_BITS=8 | |
CONFIG_USART1_PARITY=0 | |
CONFIG_USART1_2STOP=0 | |
# CONFIG_USART1_IFLOWCONTROL is not set | |
# CONFIG_USART1_OFLOWCONTROL is not set | |
# CONFIG_USART1_DMA is not set | |
# CONFIG_SCI0_SERIALDRIVER is not set | |
# CONFIG_SCI1_SERIALDRIVER is not set | |
# CONFIG_PSEUDOTERM is not set | |
# CONFIG_USBDEV is not set | |
# CONFIG_USBHOST is not set | |
# CONFIG_USBMISC is not set | |
# CONFIG_HAVE_USBTRACE is not set | |
# CONFIG_DRIVERS_WIRELESS is not set | |
# CONFIG_DRIVERS_CONTACTLESS is not set | |
# CONFIG_1WIRE is not set | |
# | |
# System Logging | |
# | |
# CONFIG_ARCH_SYSLOG is not set | |
CONFIG_SYSLOG_WRITE=y | |
# CONFIG_RAMLOG is not set | |
# CONFIG_SYSLOG_BUFFER is not set | |
# CONFIG_SYSLOG_INTBUFFER is not set | |
# CONFIG_SYSLOG_TIMESTAMP is not set | |
CONFIG_SYSLOG_SERIAL_CONSOLE=y | |
# CONFIG_SYSLOG_CHAR is not set | |
CONFIG_SYSLOG_CONSOLE=y | |
# CONFIG_SYSLOG_NONE is not set | |
# CONFIG_SYSLOG_FILE is not set | |
# CONFIG_SYSLOG_CHARDEV is not set | |
# | |
# Networking Support | |
# | |
# CONFIG_ARCH_HAVE_NET is not set | |
# CONFIG_ARCH_HAVE_PHY is not set | |
# CONFIG_NET_WRITE_BUFFERS is not set | |
# CONFIG_NET_READAHEAD is not set | |
# CONFIG_NET is not set | |
# | |
# Crypto API | |
# | |
# CONFIG_CRYPTO is not set | |
# | |
# File Systems | |
# | |
# | |
# File system configuration | |
# | |
# CONFIG_DISABLE_MOUNTPOINT is not set | |
# CONFIG_FS_AUTOMOUNTER is not set | |
# CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set | |
# CONFIG_PSEUDOFS_SOFTLINKS is not set | |
CONFIG_FS_READABLE=y | |
# CONFIG_FS_WRITABLE is not set | |
# CONFIG_FS_NAMED_SEMAPHORES is not set | |
CONFIG_FS_MQUEUE_MPATH="/var/mqueue" | |
# CONFIG_FS_RAMMAP is not set | |
# CONFIG_FS_FAT is not set | |
# CONFIG_FS_NXFFS is not set | |
# CONFIG_FS_ROMFS is not set | |
# CONFIG_FS_CROMFS is not set | |
# CONFIG_FS_TMPFS is not set | |
# CONFIG_FS_SMARTFS is not set | |
# CONFIG_FS_BINFS is not set | |
CONFIG_FS_PROCFS=y | |
# CONFIG_FS_PROCFS_REGISTER is not set | |
# | |
# Exclude individual procfs entries | |
# | |
# CONFIG_FS_PROCFS_EXCLUDE_PROCESS is not set | |
# CONFIG_FS_PROCFS_EXCLUDE_BLOCKS is not set | |
# CONFIG_FS_PROCFS_EXCLUDE_MOUNT is not set | |
# CONFIG_FS_PROCFS_EXCLUDE_USAGE is not set | |
# CONFIG_FS_PROCFS_EXCLUDE_UPTIME is not set | |
# CONFIG_FS_PROCFS_EXCLUDE_MEMINFO is not set | |
# CONFIG_FS_PROCFS_INCLUDE_PROGMEM is not set | |
# CONFIG_FS_PROCFS_EXCLUDE_MOUNTS is not set | |
# CONFIG_FS_UNIONFS is not set | |
# | |
# Graphics Support | |
# | |
# CONFIG_NX is not set | |
# CONFIG_NXFONTS is not set | |
# | |
# Font Cache Pixel Depths | |
# | |
# CONFIG_NXFONTS_DISABLE_1BPP is not set | |
# CONFIG_NXFONTS_DISABLE_2BPP is not set | |
# CONFIG_NXFONTS_DISABLE_4BPP is not set | |
# CONFIG_NXFONTS_DISABLE_8BPP is not set | |
# CONFIG_NXFONTS_DISABLE_16BPP is not set | |
# CONFIG_NXFONTS_DISABLE_24BPP is not set | |
# CONFIG_NXFONTS_DISABLE_32BPP is not set | |
CONFIG_NXFONTS_PACKEDMSFIRST=y | |
# CONFIG_NXGLIB is not set | |
# | |
# Memory Management | |
# | |
# CONFIG_MM_SMALL is not set | |
CONFIG_MM_REGIONS=2 | |
CONFIG_ARCH_HAVE_HEAP2=y | |
CONFIG_HEAP2_BASE=0xD0000000 | |
CONFIG_HEAP2_SIZE=8081408 | |
# CONFIG_GRAN is not set | |
# | |
# Common I/O Buffer Support | |
# | |
# CONFIG_MM_IOB is not set | |
# | |
# Audio Support | |
# | |
# CONFIG_AUDIO is not set | |
# | |
# Wireless Support | |
# | |
# CONFIG_WIRELESS is not set | |
# | |
# Binary Loader | |
# | |
# CONFIG_BINFMT_DISABLE is not set | |
# CONFIG_BINFMT_EXEPATH is not set | |
# CONFIG_NXFLAT is not set | |
# CONFIG_ELF is not set | |
CONFIG_BUILTIN=y | |
# CONFIG_PIC is not set | |
# CONFIG_SYMTAB_ORDEREDBYNAME is not set | |
# | |
# Library Routines | |
# | |
# | |
# Standard C Library Options | |
# | |
# | |
# Standard C I/O | |
# | |
# CONFIG_STDIO_DISABLE_BUFFERING is not set | |
CONFIG_STDIO_BUFFER_SIZE=64 | |
CONFIG_STDIO_LINEBUFFER=y | |
CONFIG_NUNGET_CHARS=2 | |
# CONFIG_NOPRINTF_FIELDWIDTH is not set | |
# CONFIG_LIBC_FLOATINGPOINT is not set | |
CONFIG_LIBC_LONG_LONG=y | |
# CONFIG_LIBC_SCANSET is not set | |
# CONFIG_EOL_IS_CR is not set | |
# CONFIG_EOL_IS_LF is not set | |
# CONFIG_EOL_IS_BOTH_CRLF is not set | |
CONFIG_EOL_IS_EITHER_CRLF=y | |
# CONFIG_MEMCPY_VIK is not set | |
# CONFIG_LIBM is not set | |
# | |
# Architecture-Specific Support | |
# | |
CONFIG_ARCH_LOWPUTC=y | |
# CONFIG_ARCH_ROMGETC is not set | |
# CONFIG_LIBC_ARCH_MEMCPY is not set | |
# CONFIG_LIBC_ARCH_MEMCMP is not set | |
# CONFIG_LIBC_ARCH_MEMMOVE is not set | |
# CONFIG_LIBC_ARCH_MEMSET is not set | |
# CONFIG_LIBC_ARCH_STRCHR is not set | |
# CONFIG_LIBC_ARCH_STRCMP is not set | |
# CONFIG_LIBC_ARCH_STRCPY is not set | |
# CONFIG_LIBC_ARCH_STRNCPY is not set | |
# CONFIG_LIBC_ARCH_STRLEN is not set | |
# CONFIG_LIBC_ARCH_STRNLEN is not set | |
# CONFIG_LIBC_ARCH_ELF is not set | |
# CONFIG_ARMV7M_MEMCPY is not set | |
# | |
# stdlib Options | |
# | |
CONFIG_LIB_RAND_ORDER=1 | |
CONFIG_LIB_HOMEDIR="/" | |
# | |
# Program Execution Options | |
# | |
# CONFIG_LIBC_EXECFUNCS is not set | |
CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=1024 | |
CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=2048 | |
# | |
# errno Decode Support | |
# | |
# CONFIG_LIBC_STRERROR is not set | |
# CONFIG_LIBC_PERROR_STDOUT is not set | |
# | |
# memcpy/memset Options | |
# | |
# CONFIG_MEMSET_OPTSPEED is not set | |
# CONFIG_LIBC_DLLFCN is not set | |
# CONFIG_LIBC_MODLIB is not set | |
# CONFIG_LIBC_WCHAR is not set | |
# CONFIG_LIBC_LOCALE is not set | |
# CONFIG_LIBC_LZF is not set | |
# | |
# Time/Time Zone Support | |
# | |
# CONFIG_LIBC_LOCALTIME is not set | |
# CONFIG_TIME_EXTENDED is not set | |
CONFIG_ARCH_HAVE_TLS=y | |
# | |
# Thread Local Storage (TLS) | |
# | |
# CONFIG_TLS is not set | |
# | |
# Network-Related Options | |
# | |
# CONFIG_LIBC_IPv4_ADDRCONV is not set | |
# CONFIG_LIBC_IPv6_ADDRCONV is not set | |
# CONFIG_LIBC_NETDB is not set | |
# | |
# NETDB Support | |
# | |
# CONFIG_NETDB_HOSTFILE is not set | |
# CONFIG_LIBC_IOCTL_VARIADIC is not set | |
CONFIG_LIB_SENDFILE_BUFSIZE=512 | |
# | |
# Non-standard Library Support | |
# | |
# CONFIG_LIB_CRC64_FAST is not set | |
# CONFIG_LIB_KBDCODEC is not set | |
# CONFIG_LIB_SLCDCODEC is not set | |
# CONFIG_LIB_HEX2BIN is not set | |
# | |
# Basic CXX Support | |
# | |
# CONFIG_C99_BOOL8 is not set | |
CONFIG_HAVE_CXX=y | |
# CONFIG_CXX_NEWLONG is not set | |
# | |
# LLVM C++ Library (libcxx) | |
# | |
# CONFIG_LIBCXX is not set | |
# | |
# uClibc++ Standard C++ Library | |
# | |
# CONFIG_UCLIBCXX is not set | |
# | |
# Application Configuration | |
# | |
# | |
# Built-In Applications | |
# | |
CONFIG_BUILTIN_PROXY_STACKSIZE=1024 | |
# | |
# CAN Utilities | |
# | |
# | |
# Examples | |
# | |
# CONFIG_EXAMPLES_ADXL372_TEST is not set | |
# CONFIG_EXAMPLES_APA102 is not set | |
# CONFIG_EXAMPLES_BUTTONS is not set | |
# CONFIG_EXAMPLES_CCTYPE is not set | |
# CONFIG_EXAMPLES_CHAT is not set | |
# CONFIG_EXAMPLES_CONFIGDATA is not set | |
# CONFIG_EXAMPLES_CXXTEST is not set | |
# CONFIG_EXAMPLES_DHCPD is not set | |
CONFIG_EXAMPLES_FB=y | |
CONFIG_EXAMPLES_FB_DEFAULTFB="/dev/fb0" | |
CONFIG_EXAMPLES_FB_PRIORITY=100 | |
CONFIG_EXAMPLES_FB_STACKSIZE=2048 | |
# CONFIG_EXAMPLES_FTPC is not set | |
# CONFIG_EXAMPLES_FTPD is not set | |
# CONFIG_EXAMPLES_HELLO is not set | |
# CONFIG_EXAMPLES_HELLOXX is not set | |
# CONFIG_EXAMPLES_HIDKBD is not set | |
# CONFIG_EXAMPLES_IGMP is not set | |
# CONFIG_EXAMPLES_INA219 is not set | |
# CONFIG_EXAMPLES_JSON is not set | |
# CONFIG_EXAMPLES_LSM330SPI_TEST is not set | |
# CONFIG_EXAMPLES_LVGLDEMO is not set | |
# CONFIG_EXAMPLES_MAX31855 is not set | |
# CONFIG_EXAMPLES_MEDIA is not set | |
# CONFIG_EXAMPLES_MM is not set | |
# CONFIG_EXAMPLES_MODBUS is not set | |
# CONFIG_EXAMPLES_MOUNT is not set | |
CONFIG_EXAMPLES_NSH=y | |
CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y | |
# CONFIG_EXAMPLES_NULL is not set | |
# CONFIG_EXAMPLES_NXDEMO is not set | |
# CONFIG_EXAMPLES_NXFFS is not set | |
# CONFIG_EXAMPLES_OBD2 is not set | |
# CONFIG_EXAMPLES_OSTEST is not set | |
# CONFIG_EXAMPLES_PCA9635 is not set | |
# CONFIG_EXAMPLES_PDCURSES is not set | |
# CONFIG_EXAMPLES_POSIXSPAWN is not set | |
# CONFIG_EXAMPLES_POWERLED is not set | |
# CONFIG_EXAMPLES_POWERMONITOR is not set | |
# CONFIG_EXAMPLES_PPPD is not set | |
# CONFIG_EXAMPLES_RFID_READUID is not set | |
# CONFIG_EXAMPLES_RGBLED is not set | |
# CONFIG_EXAMPLES_SENDMAIL is not set | |
# CONFIG_EXAMPLES_SERIALBLASTER is not set | |
# CONFIG_EXAMPLES_SERIALRX is not set | |
# CONFIG_EXAMPLES_SERLOOP is not set | |
# CONFIG_EXAMPLES_SLCD is not set | |
# CONFIG_EXAMPLES_SMART is not set | |
# CONFIG_EXAMPLES_SMART_TEST is not set | |
# CONFIG_EXAMPLES_SMP is not set | |
# CONFIG_EXAMPLES_SMPS is not set | |
# CONFIG_EXAMPLES_STAT is not set | |
# CONFIG_EXAMPLES_TCPECHO is not set | |
# CONFIG_EXAMPLES_TIFF is not set | |
CONFIG_EXAMPLES_TOUCHSCREEN=y | |
CONFIG_EXAMPLES_TOUCHSCREEN_MINOR=0 | |
CONFIG_EXAMPLES_TOUCHSCREEN_DEVPATH="/dev/input0" | |
# CONFIG_EXAMPLES_TOUCHSCREEN_MOUSE is not set | |
# CONFIG_EXAMPLES_USBSERIAL is not set | |
# CONFIG_EXAMPLES_USERFS is not set | |
# CONFIG_EXAMPLES_WATCHDOG is not set | |
# CONFIG_EXAMPLES_WEBSERVER is not set | |
# CONFIG_EXAMPLES_XBC_TEST is not set | |
# | |
# File System Utilities | |
# | |
# CONFIG_FSUTILS_INIFILE is not set | |
# CONFIG_FSUTILS_PASSWD is not set | |
# | |
# GPS Utilities | |
# | |
# CONFIG_GPSUTILS_MINMEA_LIB is not set | |
# | |
# Graphics Support | |
# | |
# CONFIG_GRAPHICS_FT80X is not set | |
# CONFIG_GRAPHICS_LVGL is not set | |
# | |
# NxWidgets/NxWM | |
# | |
# CONFIG_GRAPHICS_PDCURSES is not set | |
# CONFIG_TIFF is not set | |
# CONFIG_GRAPHICS_TRAVELER is not set | |
# | |
# Interpreters | |
# | |
# CONFIG_INTERPRETERS_BAS is not set | |
# CONFIG_INTERPRETERS_FICL is not set | |
# CONFIG_INTERPRETERS_MICROPYTHON is not set | |
# CONFIG_INTERPRETERS_MINIBASIC is not set | |
# CONFIG_INTERPRETERS_PCODE is not set | |
# | |
# FreeModBus | |
# | |
# CONFIG_MODBUS is not set | |
# | |
# Network Utilities | |
# | |
# CONFIG_NETUTILS_CODECS is not set | |
# CONFIG_NETUTILS_ESP8266 is not set | |
# CONFIG_NETUTILS_FTPC is not set | |
# CONFIG_NETUTILS_JSON is not set | |
# CONFIG_NETUTILS_SMTP is not set | |
# | |
# NSH Library | |
# | |
CONFIG_NSH_LIBRARY=y | |
# CONFIG_NSH_MOTD is not set | |
# | |
# Command Line Configuration | |
# | |
CONFIG_NSH_READLINE=y | |
# CONFIG_NSH_CLE is not set | |
CONFIG_NSH_LINELEN=64 | |
# CONFIG_NSH_DISABLE_SEMICOLON is not set | |
CONFIG_NSH_CMDPARMS=y | |
CONFIG_NSH_MAXARGUMENTS=6 | |
CONFIG_NSH_ARGCAT=y | |
CONFIG_NSH_NESTDEPTH=3 | |
# CONFIG_NSH_DISABLEBG is not set | |
CONFIG_NSH_BUILTIN_APPS=y | |
# | |
# Disable Individual commands | |
# | |
# CONFIG_NSH_DISABLE_BASENAME is not set | |
# CONFIG_NSH_DISABLE_CAT is not set | |
# CONFIG_NSH_DISABLE_CD is not set | |
# CONFIG_NSH_DISABLE_CP is not set | |
# CONFIG_NSH_DISABLE_CMP is not set | |
CONFIG_NSH_DISABLE_DATE=y | |
# CONFIG_NSH_DISABLE_DD is not set | |
# CONFIG_NSH_DISABLE_DF is not set | |
# CONFIG_NSH_DISABLE_DIRNAME is not set | |
# CONFIG_NSH_DISABLE_ECHO is not set | |
# CONFIG_NSH_DISABLE_EXEC is not set | |
# CONFIG_NSH_DISABLE_EXIT is not set | |
# CONFIG_NSH_DISABLE_FREE is not set | |
# CONFIG_NSH_DISABLE_GET is not set | |
# CONFIG_NSH_DISABLE_HELP is not set | |
# CONFIG_NSH_DISABLE_HEXDUMP is not set | |
# CONFIG_NSH_DISABLE_IFCONFIG is not set | |
# CONFIG_NSH_DISABLE_IFUPDOWN is not set | |
# CONFIG_NSH_DISABLE_KILL is not set | |
# CONFIG_NSH_DISABLE_LOSETUP is not set | |
CONFIG_NSH_DISABLE_LOSMART=y | |
# CONFIG_NSH_DISABLE_LS is not set | |
# CONFIG_NSH_DISABLE_MB is not set | |
# CONFIG_NSH_DISABLE_MKDIR is not set | |
# CONFIG_NSH_DISABLE_MKRD is not set | |
# CONFIG_NSH_DISABLE_MH is not set | |
# CONFIG_NSH_DISABLE_MOUNT is not set | |
# CONFIG_NSH_DISABLE_MV is not set | |
# CONFIG_NSH_DISABLE_MW is not set | |
CONFIG_NSH_DISABLE_PRINTF=y | |
# CONFIG_NSH_DISABLE_PS is not set | |
# CONFIG_NSH_DISABLE_PUT is not set | |
# CONFIG_NSH_DISABLE_PWD is not set | |
# CONFIG_NSH_DISABLE_RM is not set | |
# CONFIG_NSH_DISABLE_RMDIR is not set | |
# CONFIG_NSH_DISABLE_SET is not set | |
# CONFIG_NSH_DISABLE_SH is not set | |
# CONFIG_NSH_DISABLE_SLEEP is not set | |
# CONFIG_NSH_DISABLE_TIME is not set | |
# CONFIG_NSH_DISABLE_TEST is not set | |
# CONFIG_NSH_DISABLE_TELNETD is not set | |
CONFIG_NSH_DISABLE_TRUNCATE=y | |
# CONFIG_NSH_DISABLE_UMOUNT is not set | |
# CONFIG_NSH_DISABLE_UNAME is not set | |
# CONFIG_NSH_DISABLE_UNSET is not set | |
# CONFIG_NSH_DISABLE_USLEEP is not set | |
# CONFIG_NSH_DISABLE_WGET is not set | |
# CONFIG_NSH_DISABLE_XD is not set | |
CONFIG_NSH_MMCSDMINOR=0 | |
# | |
# Configure Command Options | |
# | |
# CONFIG_NSH_CMDOPT_DD_STATS is not set | |
CONFIG_NSH_CODECS_BUFSIZE=128 | |
CONFIG_NSH_CMDOPT_HEXDUMP=y | |
CONFIG_NSH_PROC_MOUNTPOINT="/proc" | |
CONFIG_NSH_FILEIOSIZE=512 | |
# | |
# Scripting Support | |
# | |
# CONFIG_NSH_DISABLESCRIPT is not set | |
# CONFIG_NSH_DISABLE_ITEF is not set | |
# CONFIG_NSH_DISABLE_LOOPS is not set | |
# | |
# Console Configuration | |
# | |
CONFIG_NSH_CONSOLE=y | |
# CONFIG_NSH_ALTCONDEV is not set | |
CONFIG_NSH_ARCHINIT=y | |
# CONFIG_NSH_LOGIN is not set | |
# CONFIG_NSH_CONSOLE_LOGIN is not set | |
# | |
# Platform-specific Support | |
# | |
# CONFIG_PLATFORM_CONFIGDATA is not set | |
CONFIG_HAVE_CXXINITIALIZE=y | |
# | |
# System Libraries and NSH Add-Ons | |
# | |
# CONFIG_SYSTEM_CLE is not set | |
# CONFIG_SYSTEM_CUTERM is not set | |
# CONFIG_SYSTEM_HEX2BIN is not set | |
# CONFIG_SYSTEM_HEXED is not set | |
# CONFIG_SYSTEM_I2CTOOL is not set | |
# CONFIG_SYSTEM_INSTALL is not set | |
# CONFIG_SYSTEM_RAMTEST is not set | |
CONFIG_READLINE_HAVE_EXTMATCH=y | |
CONFIG_SYSTEM_READLINE=y | |
CONFIG_READLINE_ECHO=y | |
# CONFIG_READLINE_TABCOMPLETION is not set | |
# CONFIG_READLINE_CMD_HISTORY is not set | |
# CONFIG_SYSTEM_SETLOGMASK is not set | |
# CONFIG_SYSTEM_SUDOKU is not set | |
# CONFIG_SYSTEM_SYSTEM is not set | |
# CONFIG_SYSTEM_TEE is not set | |
# CONFIG_SYSTEM_UBLOXMODEM is not set | |
# CONFIG_SYSTEM_VI is not set | |
# CONFIG_SYSTEM_ZMODEM is not set | |
# | |
# Wireless Libraries and NSH Add-Ons | |
# | |
# | |
# Bluetooth applications | |
# | |
# CONFIG_BTSAK is not set | |
# | |
# IEEE 802.15.4 applications | |
# | |
# CONFIG_IEEE802154_LIBMAC is not set | |
# CONFIG_IEEE802154_LIBUTILS is not set | |
# CONFIG_IEEE802154_I8SAK is not set |
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/************************************************************************************ | |
* configs/stm32f429i-disco/include/board.h | |
* include/arch/board/board.h | |
* | |
* Copyright (C) 2012, 2015-2016 Gregory Nutt. All rights reserved. | |
* Author: Gregory Nutt <[email protected]> | |
* | |
* Redistribution and use in source and binary forms, with or without | |
* modification, are permitted provided that the following conditions | |
* are met: | |
* | |
* 1. Redistributions of source code must retain the above copyright | |
* notice, this list of conditions and the following disclaimer. | |
* 2. Redistributions in binary form must reproduce the above copyright | |
* notice, this list of conditions and the following disclaimer in | |
* the documentation and/or other materials provided with the | |
* distribution. | |
* 3. Neither the name NuttX nor the names of its contributors may be | |
* used to endorse or promote products derived from this software | |
* without specific prior written permission. | |
* | |
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS | |
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE | |
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, | |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, | |
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS | |
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED | |
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT | |
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN | |
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | |
* POSSIBILITY OF SUCH DAMAGE. | |
* | |
************************************************************************************/ | |
#ifndef __CONFIG_STM32F429I_DISCO_INCLUDE_BOARD_H | |
#define __CONFIG_STM32F429I_DISCO_INCLUDE_BOARD_H | |
/************************************************************************************ | |
* Included Files | |
************************************************************************************/ | |
#include <nuttx/config.h> | |
#ifndef __ASSEMBLY__ | |
# include <stdint.h> | |
#endif | |
#include "stm32_rcc.h" | |
#include "stm32_sdio.h" | |
#include "stm32.h" | |
/************************************************************************************ | |
* Pre-processor Definitions | |
************************************************************************************/ | |
/* Clocking *************************************************************************/ | |
/* The STM32F4 Discovery board features a single 8MHz crystal. Space is provided | |
* for a 32kHz RTC backup crystal, but it is not stuffed. | |
* | |
* This is the canonical configuration: | |
* System Clock source : PLL (HSE) | |
* SYSCLK(Hz) : 180000000 Determined by PLL configuration | |
* HCLK(Hz) : 180000000 (STM32_RCC_CFGR_HPRE) | |
* AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) | |
* APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1) | |
* APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2) | |
* HSE Frequency(Hz) : 8000000 (STM32_BOARD_XTAL) | |
* PLLM : 8 (STM32_PLLCFG_PLLM) | |
* PLLN : 336 (STM32_PLLCFG_PLLN) | |
* PLLP : 2 (STM32_PLLCFG_PLLP) | |
* PLLQ : 7 (STM32_PLLCFG_PLLQ) | |
* Main regulator output voltage : Scale1 mode Needed for high speed SYSCLK | |
* Flash Latency(WS) : 5 | |
* Prefetch Buffer : OFF | |
* Instruction cache : ON | |
* Data cache : ON | |
* Require 48MHz for USB OTG FS, : Enabled | |
* SDIO and RNG clock | |
*/ | |
/* HSI - 16 MHz RC factory-trimmed | |
* LSI - 32 KHz RC | |
* HSE - On-board crystal frequency is 8MHz | |
* LSE - 32.768 kHz | |
*/ | |
#define STM32_BOARD_XTAL 8000000ul | |
#define STM32_HSI_FREQUENCY 16000000ul | |
#define STM32_LSI_FREQUENCY 32000 | |
#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL | |
#define STM32_LSE_FREQUENCY 32768 | |
/* Main PLL Configuration. | |
* | |
* PLL source is HSE | |
* PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN | |
* = (8,000,000 / 8) * 336 | |
* = 336,000,000 | |
* SYSCLK = PLL_VCO / PLLP | |
* = 336,000,000 / 2 = 168,000,000 | |
* USB OTG FS, SDIO and RNG Clock | |
* = PLL_VCO / PLLQ | |
* = 48,000,000 | |
*/ | |
#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(8) | |
#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(336) | |
#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 | |
#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(7) | |
#define STM32_SYSCLK_FREQUENCY 168000000ul | |
/* AHB clock (HCLK) is SYSCLK (168MHz) */ | |
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ | |
#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY | |
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */ | |
/* APB1 clock (PCLK1) is HCLK/4 (42MHz) */ | |
#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ | |
#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) | |
/* Timers driven from APB1 will be twice PCLK1 */ | |
#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) | |
#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) | |
#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) | |
#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) | |
#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) | |
#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) | |
#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) | |
#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) | |
#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) | |
/* APB2 clock (PCLK2) is HCLK/2 (84MHz) */ | |
#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ | |
#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) | |
/* Timers driven from APB2 will be twice PCLK2 */ | |
#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) | |
#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) | |
#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) | |
#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) | |
#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) | |
/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx | |
* otherwise frequency is 2xAPBx. | |
* Note: TIM1,8 are on APB2, others on APB1 | |
*/ | |
#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY | |
#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY/2) | |
#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY/2) | |
#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY/2) | |
#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY/2) | |
#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY/2) | |
#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY/2) | |
#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY | |
/* LED definitions ******************************************************************/ | |
/* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in any | |
* way. The following definitions are used to access individual LEDs. | |
*/ | |
/* LED index values for use with board_userled() */ | |
#define BOARD_LED1 0 | |
#define BOARD_LED2 1 | |
#define BOARD_NLEDS 2 | |
#define BOARD_LED_GREEN BOARD_LED1 | |
#define BOARD_LED_ORANGE BOARD_LED2 | |
/* LED bits for use with board_userled_all() */ | |
#define BOARD_LED1_BIT (1 << BOARD_LED1) | |
#define BOARD_LED2_BIT (1 << BOARD_LED2) | |
/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 4 LEDs on board the | |
* stm32f429i-disco. The following definitions describe how NuttX controls the LEDs: | |
*/ | |
#define LED_STARTED 0 /* LED1 */ | |
#define LED_HEAPALLOCATE 1 /* LED2 */ | |
#define LED_IRQSENABLED 2 /* LED1 + LED2 */ | |
#define LED_STACKCREATED 3 /* LED3 */ | |
#define LED_INIRQ 4 /* LED1 + LED3 */ | |
#define LED_SIGNAL 5 /* LED2 + LED3 */ | |
#define LED_ASSERTION 6 /* LED1 + LED2 + LED3 */ | |
#define LED_PANIC 7 /* N/C + N/C + N/C + LED4 */ | |
/* Button definitions ***************************************************************/ | |
/* The STM32F4 Discovery supports one button: */ | |
#define BUTTON_USER 0 | |
#define NUM_BUTTONS 1 | |
#define BUTTON_USER_BIT (1 << BUTTON_USER) | |
/* Alternate function pin selections ************************************************/ | |
/* USART1: | |
* | |
* The STM32F4 Discovery has no on-board serial devices, but the console is | |
* brought out to PA9 (TX) and PA10 (RX) for connection to an external serial device. | |
* (See the README.txt file for other options) | |
*/ | |
#define GPIO_USART1_RX GPIO_USART1_RX_1 | |
#define GPIO_USART1_TX GPIO_USART1_TX_1 | |
/* PWM | |
* | |
* The STM32F4 Discovery has no real on-board PWM devices, but the board can be | |
* configured to output a pulse train using TIM4 CH2 on PD13. | |
*/ | |
#define GPIO_TIM4_CH2OUT GPIO_TIM4_CH2OUT_2 | |
/* I2C - There is a STMPE811 TouchPanel on I2C3 using these pins: */ | |
#define GPIO_I2C3_SCL GPIO_I2C3_SCL_1 | |
#define GPIO_I2C3_SDA GPIO_I2C3_SDA_1 | |
/* SPI - There is a MEMS device on SPI5 using these pins: */ | |
#define GPIO_SPI5_MISO GPIO_SPI5_MISO_1 | |
#define GPIO_SPI5_MOSI GPIO_SPI5_MOSI_1 | |
#define GPIO_SPI5_SCK GPIO_SPI5_SCK_1 | |
/* SPI - External SPI flash may be connected on SPI4: */ | |
#define GPIO_SPI4_MISO GPIO_SPI4_MISO_1 | |
#define GPIO_SPI4_MOSI GPIO_SPI4_MOSI_1 | |
#define GPIO_SPI4_SCK GPIO_SPI4_SCK_1 | |
/* FSMC - SDRAM */ | |
#define GPIO_FSMC_SDCKE1 GPIO_FSMC_SDCKE1_1 | |
#define GPIO_FSMC_SDNE1 GPIO_FSMC_SDNE1_1 | |
#define GPIO_FSMC_SDNWE GPIO_FSMC_SDNWE_1 | |
/* Timer Inputs/Outputs (see the README.txt file for options) */ | |
#define GPIO_TIM2_CH1IN GPIO_TIM2_CH1IN_2 | |
#define GPIO_TIM2_CH2IN GPIO_TIM2_CH2IN_1 | |
#define GPIO_TIM8_CH1IN GPIO_TIM8_CH1IN_1 | |
#define GPIO_TIM8_CH2IN GPIO_TIM8_CH2IN_1 | |
// #ifdef CONFIG_STM32_LTDC | |
// # ifdef CONFIG_STM32F429I_DISCO_ILI9341_FBIFACE | |
/* LCD | |
* | |
* The STM32F429I-DISCO board contains an onboard TFT LCD connected to the | |
* LTDC interface of the uC. The LCD is 240x320 pixels. Define the parameters | |
* of the LCD and the interface here. | |
*/ | |
/* Panel configuration | |
* | |
* LCD Panel is Saef Technology Limited (SF-TC240T-9229A2-T) with integrated | |
* Ilitek ILI9341 LCD Single Chip Driver (240RGBx320) | |
* | |
* PLLSAI settings | |
* PLLSAIN : 192 | |
* PLLSAIR : 4 | |
* PLLSAIQ : 7 | |
* PLLSAIDIVR : 8 | |
* | |
* Timings | |
* Horicontal Front Porch : 10 (STM32_LTDC_HFP) | |
* Horicontal Back Porch : 20 (STM32_LTDC_HBP) | |
* Vertical Front Porch : 4 (STM32_LTDC_VFP) | |
* Vertical Back Porch : 2 (STM32_LTDC_VBP) | |
* | |
* Horicontal Sync : 10 (STM32_LTDC_HSYNC) | |
* Vertical Sync : 4 (STM32_LTDC_VSYNC) | |
* | |
* Active Width : 240 (STM32_LTDC_ACTIVEW) | |
* Active Height : 320 (STM32_LTDC_ACTIVEH) | |
*/ | |
/* LTDC PLL configuration | |
* | |
* PLLSAI_VCO = STM32_HSE_FREQUENCY / PLLM | |
* = 8000000ul / 8 | |
* = 1,000,000 | |
* | |
* PLL LCD clock output | |
* = PLLSAI_VCO * PLLSAIN / PLLSAIR / PLLSAIDIVR | |
* = 1,000,000 * 192 / 4 /8 | |
* = 6,000,000 | |
*/ | |
/* Defined panel settings */ | |
// #if defined(CONFIG_STM32F429I_DISCO_ILI9341_FBIFACE_LANDSCAPE) || \ | |
// defined(CONFIG_STM32F429I_DISCO_ILI9341_FBIFACE_RLANDSCAPE) | |
# define BOARD_LTDC_WIDTH 800 | |
# define BOARD_LTDC_HEIGHT 480 | |
// #else | |
// # define BOARD_LTDC_WIDTH 240 | |
// # define BOARD_LTDC_HEIGHT 320 | |
// #endif | |
#define BOARD_LTDC_OUTPUT_BPP 16 | |
#define BOARD_LTDC_HFP 210 // 10 | |
#define BOARD_LTDC_HBP 46 // 20 | |
#define BOARD_LTDC_VFP 22 // 4 | |
#define BOARD_LTDC_VBP 23 // 2 | |
#define BOARD_LTDC_HSYNC 1 // 10 | |
#define BOARD_LTDC_VSYNC 1 // 2 | |
#define BOARD_LTDC_PLLSAIN 192 | |
#define BOARD_LTDC_PLLSAIR 4 | |
#define BOARD_LTDC_PLLSAIQ 7 | |
/* Division factor for LCD clock */ | |
#define STM32_RCC_DCKCFGR_PLLSAIDIVR RCC_DCKCFGR_PLLSAIDIVR_DIV8 | |
/* Pixel Clock Polarity */ | |
#define BOARD_LTDC_GCR_PCPOL 0 /* !LTDC_GCR_PCPOL */ | |
/* Data Enable Polarity */ | |
#define BOARD_LTDC_GCR_DEPOL 0 /* !LTDC_GCR_DEPOL */ | |
/* Vertical Sync Polarity */ | |
#define BOARD_LTDC_GCR_VSPOL 0 /* !LTDC_GCR_VSPOL */ | |
/* Horicontal Sync Polarity */ | |
#define BOARD_LTDC_GCR_HSPOL 0 /* !LTDC_GCR_HSPOL */ | |
/* GPIO pinset */ | |
#define GPIO_LTDC_PINS 18 /* 18-bit display */ | |
#define GPIO_LTDC_R2 GPIO_LTDC_R2_1 | |
#define GPIO_LTDC_R3 GPIO_LTDC_R3_1 | |
#define GPIO_LTDC_R4 GPIO_LTDC_R4_1 | |
#define GPIO_LTDC_R5 GPIO_LTDC_R5_1 | |
#define GPIO_LTDC_R6 GPIO_LTDC_R6_1 | |
#define GPIO_LTDC_R7 GPIO_LTDC_R7_1 | |
#define GPIO_LTDC_G2 GPIO_LTDC_G2_1 | |
#define GPIO_LTDC_G3 GPIO_LTDC_G3_1 | |
#define GPIO_LTDC_G4 GPIO_LTDC_G4_1 | |
#define GPIO_LTDC_G5 GPIO_LTDC_G5_1 | |
#define GPIO_LTDC_G6 GPIO_LTDC_G6_1 | |
#define GPIO_LTDC_G7 GPIO_LTDC_G7_1 | |
#define GPIO_LTDC_B2 GPIO_LTDC_B2_1 | |
#define GPIO_LTDC_B3 GPIO_LTDC_B3_1 | |
#define GPIO_LTDC_B4 GPIO_LTDC_B4_1 | |
#define GPIO_LTDC_B5 GPIO_LTDC_B5_1 | |
#define GPIO_LTDC_B6 GPIO_LTDC_B6_1 | |
#define GPIO_LTDC_B7 GPIO_LTDC_B7_1 | |
#define GPIO_LTDC_VSYNC GPIO_LTDC_VSYNC_1 | |
#define GPIO_LTDC_HSYNC GPIO_LTDC_HSYNC_1 | |
#define GPIO_LTDC_DE GPIO_LTDC_DE_1 | |
#define GPIO_LTDC_CLK GPIO_LTDC_CLK_1 | |
// #else | |
// /* Custom LCD display configuration */ | |
// # define BOARD_LTDC_WIDTH ??? | |
// # define BOARD_LTDC_HEIGHT ??? | |
// #define BOARD_LTDC_HFP ??? | |
// #define BOARD_LTDC_HBP ??? | |
// #define BOARD_LTDC_VFP ??? | |
// #define BOARD_LTDC_VBP ??? | |
// #define BOARD_LTDC_HSYNC ??? | |
// #define BOARD_LTDC_VSYNC ??? | |
// #define BOARD_LTDC_PLLSAIN ??? | |
// #define BOARD_LTDC_PLLSAIR ??? | |
// #define BOARD_LTDC_PLLSAIQ ??? | |
// /* Division factor for LCD clock */ | |
// #define STM32_RCC_DCKCFGR_PLLSAIDIVR ??? | |
// /* Pixel Clock Polarity */ | |
// #define BOARD_LTDC_GCR_PCPOL ??? | |
// /* Data Enable Polarity */ | |
// #define BOARD_LTDC_GCR_DEPOL ??? | |
// /* Vertical Sync Polarity */ | |
// #define BOARD_LTDC_GCR_VSPOL ??? | |
// /* Horicontal Sync Polarity */ | |
// #define BOARD_LTDC_GCR_HSPOL ??? | |
// /* GPIO pinset */ | |
// #define GPIO_LTDC_PINS ??? | |
// #define GPIO_LTDC_R2 ??? | |
// #define GPIO_LTDC_R3 ??? | |
// #define GPIO_LTDC_R4 ??? | |
// #define GPIO_LTDC_R5 ??? | |
// #define GPIO_LTDC_R6 ??? | |
// #define GPIO_LTDC_R7 ??? | |
// #define GPIO_LTDC_G2 ??? | |
// #define GPIO_LTDC_G3 ??? | |
// #define GPIO_LTDC_G4 ??? | |
// #define GPIO_LTDC_G5 ??? | |
// #define GPIO_LTDC_G6 ??? | |
// #define GPIO_LTDC_G7 ??? | |
// #define GPIO_LTDC_B2 ??? | |
// #define GPIO_LTDC_B3 ??? | |
// #define GPIO_LTDC_B4 ??? | |
// #define GPIO_LTDC_B5 ??? | |
// #define GPIO_LTDC_B6 ??? | |
// #define GPIO_LTDC_B7 ??? | |
// #define GPIO_LTDC_VSYNC ??? | |
// #define GPIO_LTDC_HSYNC ??? | |
// #define GPIO_LTDC_DE ??? | |
// #define GPIO_LTDC_CLK ??? | |
// #endif /* Custom LCD display */ | |
/* Configure PLLSAI */ | |
#define STM32_RCC_PLLSAICFGR_PLLSAIN (192 << 6) //RCC_PLLSAICFGR_PLLSAIN(BOARD_LTDC_PLLSAIN) | |
#define STM32_RCC_PLLSAICFGR_PLLSAIR (4 << 28) // RCC_PLLSAICFGR_PLLSAIR(BOARD_LTDC_PLLSAIR) | |
#define STM32_RCC_PLLSAICFGR_PLLSAIQ (7 << 24) // RCC_PLLSAICFGR_PLLSAIQ(BOARD_LTDC_PLLSAIQ) | |
#define STM32_RCC_DCKCFGR_PLLSAIDIVR (2 << 16) | |
// #endif /* CONFIG_STM32_LTDC */ | |
#endif /* __CONFIG_STM32F429I_DISCO_INCLUDE_BOARD_H */ |
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