verilog blinky

blinky.v

module bar (
clk,
rst,
dout
);

   parameter buswidth = 8;
   parameter n = 4;

   input clk;
   input rst;
   output [7:0] dout; // 8 bit register

   wire		clk;
   wire		rst;

   reg [7:0]	dout;

   always @ (posedge clk)
     begin: COUNTER
	if (rst == 1'b1) begin
	   dout <= #1 8'b00000000;
	end
	else begin
	   dout <= #1 dout + 1;
	end
     end // end of counter end of block COUNTER

endmodule // bar