SWO init STM32F415RG

void trace_init(uint32_t bitrate, uint32_t channelmask, uint32_t cpu_clock_frequency)
{
    CoreDebug->DEMCR = CoreDebug_DEMCR_TRCENA_Msk ;

    TPI->CSPSR = 1 ;        // Protocol width = 1 bit
    TPI->SPPR = 1 ;         // 1 = Manchester, 2 = Asynchronous
    TPI->ACPR = (cpu_clock_frequency / (2 * bitrate)) - 1 ;
    TPI->FFCR = 0 ;         // Turn off formatter, discard ETM output

    ITM->LAR = 0xC5ACCE55 ;     // unlock access to ITM
    ITM->TCR = ITM_TCR_SWOENA_Msk | ITM_TCR_ITMENA_Msk ;
    ITM->TPR = 0 ;              // Priviliged mode off
    ITM->TER = channelmask ;    // Emable stimulus channels
}

////////////////////////////////////////////////
//
// MCU specific initilization functions follow
//
////////////////////////////////////////////////

//
// STM32F4xx
//
void trace_init_STM32F4xx(uint32_t bitrate, uint32_t channelmask, uint32_t cpu_clock_frequency)
{
    trace_init(bitrate, channelmask, cpu_clock_frequency) ;
    RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN ;       // enable BPIOB clock
    GPIOB->MODER = (GPIOB->MODER & ~0x000000C0) | 0x00000080 ; // Alternate function for PB3
    GPIOB->AFR[0]  &= 0x0000F000 ;      // Set AF0 (==TRACESWO) on PB3
    GPIOB->OSPEEDR |= 0x000000C0 ;      // max speed on PB3
    GPIOB->PUPDR &= ~0x000000C0 ;       // no pull-up or pull-down on PB3
    DBGMCU->CR |= DBGMCU_CR_TRACE_IOEN ;    // Enable trace IO pins
}