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| /dts-v1/; | |
| / { | |
| compatible = "qcom,sdm845-mtp\0qcom,sdm845\0qcom,mtp"; | |
| qcom,board-id = <0x05 0x00>; | |
| model = "Qualcomm Technologies, Inc. SDM845 v2.1 OEM"; | |
| interrupt-parent = <0x01>; | |
| #address-cells = <0x02>; | |
| #size-cells = <0x02>; | |
| qcom,msm-id = <0x141 0x20001>; | |
| vendor { | |
| compatible = "simple-bus"; | |
| ranges = <0x00 0x00 0x00 0xffffffff>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| phandle = <0x4d5>; | |
| qcom,battery-data { | |
| qcom,batt-id-range-pct = <0x0f>; | |
| phandle = <0x500>; | |
| qcom,quectel_sa800u_chijin_6600mah { | |
| qcom,batt-id-kohm = <0x64>; | |
| qcom,fg-profile-data = <0x171f6bfc 0x96031107 0xbd1c4b02 0x100d300b 0x4118b522 0xd3cfb4b 0x6e000000 0x15000000 0xc8d4 0x100fad2 0x10000000 0xdcda85e5 0xa9ed1ef2 0x4ed0e03 0xf3e4c71b 0x4b000000 0x7000000 0xce208b04 0xff0ae705 0xba1cf702 0x430caa0b 0x1d18012a 0xe14d1b5b 0x7a000000 0xe000000 0xd1cc 0xe5c2cdbd 0xf000000 0x89e385e5 0x5cd504eb 0x30717ca 0x3ef32403 0x99000000 0x7000000 0x70179945 0xf004000 0x3b020afa 0xff000000 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>; | |
| qcom,fastchg-current-ma = <0xe74>; | |
| qcom,max-voltage-uv = <0x426030>; | |
| qcom,battery-beta = <0xd70>; | |
| qcom,fg-cc-cv-threshold-mv = <0x10f4>; | |
| qcom,checksum = <0x3a51>; | |
| qcom,battery-type = "quectel_sa800u_chijin_6600mah"; | |
| qcom,gui-version = "PMI8998GUI - 2.0.0.58"; | |
| qcom,nom-batt-capacity-mah = <0x19c8>; | |
| }; | |
| }; | |
| extcon_usb1 { | |
| compatible = "linux,extcon-usb-gpio"; | |
| status = "disabled"; | |
| phandle = <0x57d>; | |
| vbus-gpio = <0x509 0x08 0x00>; | |
| pinctrl-0 = <0x520>; | |
| pinctrl-names = "default"; | |
| }; | |
| ext_5v_boost { | |
| regulator-enable-ramp-delay = <0x640>; | |
| compatible = "regulator-fixed"; | |
| enable-active-high; | |
| gpio = <0x509 0x0a 0x00>; | |
| status = "ok"; | |
| phandle = <0x521>; | |
| pinctrl-0 = <0x50a 0x50b 0x50c>; | |
| regulator-name = "ext_5v_boost"; | |
| pinctrl-names = "default"; | |
| }; | |
| bt_wcn3990 { | |
| qca,bt-vdd-pa-voltage-level = <0x13e5c0 0x13e5c0>; | |
| qca,bt-vdd-core-voltage-level = <0x1b7740 0x1b7740>; | |
| compatible = "qca,wcn3990"; | |
| qca,bt-vdd-io-current-level = <0x01>; | |
| qca,bt-vdd-pa-supply = <0xed>; | |
| qca,bt-vdd-ldo-supply = <0xee>; | |
| qca,bt-vdd-core-supply = <0xec>; | |
| qca,bt-vdd-xtal-supply = <0xa3>; | |
| qca,bt-vdd-pa-current-level = <0x01>; | |
| qca,bt-vdd-core-current-level = <0x01>; | |
| qca,bt-vdd-ldo-voltage-level = <0x328980 0x328980>; | |
| qca,bt-vdd-xtal-voltage-level = <0x1f20c0 0x1f20c0>; | |
| qca,bt-vdd-ldo-current-level = <0x01>; | |
| phandle = <0x57c>; | |
| qca,bt-vdd-io-supply = <0x339>; | |
| qca,bt-vdd-xtal-current-level = <0x01>; | |
| qca,bt-vdd-io-voltage-level = <0x14a140 0x14a140>; | |
| }; | |
| }; | |
| reserved-memory { | |
| ranges; | |
| #address-cells = <0x02>; | |
| #size-cells = <0x02>; | |
| adsp_region { | |
| reusable; | |
| compatible = "shared-dma-pool"; | |
| alignment = <0x00 0x400000>; | |
| alloc-ranges = <0x00 0x00 0x00 0xffffffff>; | |
| size = <0x00 0x1000000>; | |
| phandle = <0xbf>; | |
| }; | |
| linux,cma { | |
| reusable; | |
| compatible = "shared-dma-pool"; | |
| alignment = <0x00 0x400000>; | |
| alloc-ranges = <0x00 0x00 0x00 0xffffffff>; | |
| size = <0x00 0x2000000>; | |
| linux,cma-default; | |
| }; | |
| adsp_region@0x8c500000 { | |
| compatible = "removed-dma-pool"; | |
| no-map; | |
| phandle = <0xb2>; | |
| reg = <0x00 0x8c500000 0x00 0x1a00000>; | |
| }; | |
| slpi_region@0x96700000 { | |
| compatible = "removed-dma-pool"; | |
| no-map; | |
| phandle = <0xb7>; | |
| reg = <0x00 0x96700000 0x00 0x1400000>; | |
| }; | |
| cont_splash_region@9d400000 { | |
| label = "cont_splash_region"; | |
| phandle = <0x4dc>; | |
| reg = <0x00 0x9d400000 0x00 0x2400000>; | |
| }; | |
| modem_region@0x8e000000 { | |
| compatible = "removed-dma-pool"; | |
| no-map; | |
| phandle = <0xae>; | |
| reg = <0x00 0x8e000000 0x00 0x7800000>; | |
| }; | |
| secure_display_region { | |
| reusable; | |
| compatible = "shared-dma-pool"; | |
| alignment = <0x00 0x400000>; | |
| alloc-ranges = <0x00 0x00 0x00 0xffffffff>; | |
| size = <0x00 0x5c00000>; | |
| phandle = <0x1af>; | |
| }; | |
| secure_sp_region { | |
| reusable; | |
| compatible = "shared-dma-pool"; | |
| alignment = <0x00 0x400000>; | |
| alloc-ranges = <0x00 0x00 0x00 0xffffffff>; | |
| size = <0x00 0x800000>; | |
| phandle = <0x1ae>; | |
| }; | |
| hyp_region@85700000 { | |
| no-map; | |
| phandle = <0x4d7>; | |
| reg = <0x00 0x85700000 0x00 0x600000>; | |
| }; | |
| mem_dump_region { | |
| reusable; | |
| compatible = "shared-dma-pool"; | |
| size = <0x00 0x2400000>; | |
| phandle = <0x11b>; | |
| }; | |
| camera_region@0x8bf00000 { | |
| compatible = "removed-dma-pool"; | |
| no-map; | |
| phandle = <0x1c0>; | |
| reg = <0x00 0x8bf00000 0x00 0x500000>; | |
| }; | |
| mba_region@0x96500000 { | |
| compatible = "removed-dma-pool"; | |
| no-map; | |
| phandle = <0xb1>; | |
| reg = <0x00 0x96500000 0x00 0x200000>; | |
| }; | |
| removed_region@85fc0000 { | |
| no-map; | |
| phandle = <0x4d9>; | |
| reg = <0x00 0x85fc0000 0x00 0x2f40000>; | |
| }; | |
| qseecom_ta_region { | |
| reusable; | |
| compatible = "shared-dma-pool"; | |
| alignment = <0x00 0x400000>; | |
| alloc-ranges = <0x00 0x00 0x00 0xffffffff>; | |
| size = <0x00 0x1000000>; | |
| phandle = <0x1ad>; | |
| }; | |
| cdsp_region@0x95d00000 { | |
| compatible = "removed-dma-pool"; | |
| no-map; | |
| phandle = <0xbc>; | |
| reg = <0x00 0x95d00000 0x00 0x800000>; | |
| }; | |
| ipa_gsi_region@0x8c410000 { | |
| compatible = "removed-dma-pool"; | |
| no-map; | |
| phandle = <0x4da>; | |
| reg = <0x00 0x8c410000 0x00 0x5000>; | |
| }; | |
| ips_fw_region@0x8c400000 { | |
| compatible = "removed-dma-pool"; | |
| no-map; | |
| phandle = <0xe9>; | |
| reg = <0x00 0x8c400000 0x00 0x10000>; | |
| }; | |
| gpu_region@0x8c415000 { | |
| compatible = "removed-dma-pool"; | |
| no-map; | |
| phandle = <0x2ab>; | |
| reg = <0x00 0x8c415000 0x00 0x2000>; | |
| }; | |
| xbl_region@85e00000 { | |
| no-map; | |
| phandle = <0x4d8>; | |
| reg = <0x00 0x85e00000 0x00 0x100000>; | |
| }; | |
| video_region@0x95800000 { | |
| compatible = "removed-dma-pool"; | |
| no-map; | |
| phandle = <0xc1>; | |
| reg = <0x00 0x95800000 0x00 0x500000>; | |
| }; | |
| wlan_fw_region@0x8df00000 { | |
| compatible = "removed-dma-pool"; | |
| no-map; | |
| phandle = <0x4db>; | |
| reg = <0x00 0x8df00000 0x00 0x100000>; | |
| }; | |
| qseecom_region@0x8ab00000 { | |
| compatible = "shared-dma-pool"; | |
| no-map; | |
| phandle = <0x1ac>; | |
| reg = <0x00 0x8ab00000 0x00 0x1400000>; | |
| }; | |
| pil_spss_region@0x97b00000 { | |
| compatible = "removed-dma-pool"; | |
| no-map; | |
| phandle = <0xbb>; | |
| reg = <0x00 0x97b00000 0x00 0x100000>; | |
| }; | |
| }; | |
| regulator-pm8998-s4 { | |
| compatible = "qcom,stub-regulator"; | |
| qcom,hpm-min-load = <0x186a0>; | |
| phandle = <0x4dd>; | |
| regulator-min-microvolt = <0x1b7740>; | |
| regulator-max-microvolt = <0x1b7740>; | |
| regulator-name = "pm8998_s4"; | |
| }; | |
| __symbols__ { | |
| quat_aux_pcm_sleep = "/soc/pinctrl@03400000/quat_aux_pcm/quat_aux_pcm_sleep"; | |
| ts_release = "/soc/pinctrl@03400000/pmx_ts_release/ts_release"; | |
| dai_quin_tdm_tx_0 = "/soc/qcom,msm-dai-tdm-quin-tx/qcom,msm-dai-q6-tdm-quin-tx-0"; | |
| quat_mi2s_sd0_active = "/soc/pinctrl@03400000/quat_mi2s_sd0/quat_mi2s_sd0_active"; | |
| funnel_in2_in_replicator_swao = "/soc/funnel@0x6043000/ports/port@2/endpoint"; | |
| quec_output_gpios_init = "/soc/pinctrl@03400000/quec_gpio_init/quec_output_gpios_init"; | |
| quat_mi2s_mclk_active = "/soc/pinctrl@03400000/quat_mi2s_mclk/quat_mi2s_mclk_active"; | |
| tpda_llm_gold = "/soc/tpda@78d0000"; | |
| pcie1_perst_default = "/soc/pinctrl@03400000/pcie1/pcie1_perst_default"; | |
| L1_D_600 = "/cpus/cpu@600/l1-dcache"; | |
| cti2_apss = "/soc/cti@7900000"; | |
| usb_audio_tx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-usb-audio-tx"; | |
| slv_qhs_a1_noc_cfg = "/soc/ad-hoc-bus/slv-qhs-a1-noc-cfg"; | |
| funnel_modem_out_funnel_in2 = "/soc/funnel@6832000/ports/port@0/endpoint"; | |
| cam_vfe_lite = "/soc/qcom,vfe-lite@acc4000"; | |
| removed_region = "/reserved-memory/removed_region@85fc0000"; | |
| qupv3_se11_i2c_sleep = "/soc/pinctrl@03400000/qupv3_se11_i2c_pins/qupv3_se11_i2c_sleep"; | |
| pm8998_div_clk2 = "/soc/qcom,spmi@c440000/qcom,pm8998@0/qcom,clkdiv@5c00"; | |
| pcie_0_gdsc = "/soc/qcom,gdsc@0x16b004"; | |
| cti3 = "/soc/cti@6013000"; | |
| slv_qhs_vsense_ctrl_cfg = "/soc/ad-hoc-bus/slv-qhs-vsense-ctrl-cfg"; | |
| bcm_alc = "/soc/ad-hoc-bus/bcm-alc"; | |
| slv_srvc_aggre2_noc = "/soc/ad-hoc-bus/slv-srvc-aggre2-noc"; | |
| cam_jpeg_dma = "/soc/qcom,jpegdma@0xac52000"; | |
| modem_pa = "/soc/qmi-tmd-devices/modem/modem_pa"; | |
| cam_cci = "/soc/qcom,cci@ac4a000"; | |
| jtag_mm0 = "/soc/jtagmm@7040000"; | |
| ufs_dev_reset_deassert = "/soc/pinctrl@03400000/ufs_dev_reset_deassert"; | |
| pop_trip = "/soc/thermal-zones/pop-mem-step/trips/pop-trip"; | |
| etm2_out_funnel_apss = "/soc/etm@7240000/port/endpoint"; | |
| sec_mi2s_sleep = "/soc/pinctrl@03400000/sec_mi2s/sec_mi2s_sleep"; | |
| bcm_sn0 = "/soc/ad-hoc-bus/bcm-sn0"; | |
| hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc = "/soc/qcom,gdsc@0x17d048"; | |
| dai_sec_tdm_tx_0 = "/soc/qcom,msm-dai-tdm-sec-tx/qcom,msm-dai-q6-tdm-sec-tx-0"; | |
| mas_qxm_venus1 = "/soc/ad-hoc-bus/mas-qxm-venus1"; | |
| tpdm_north_out_tpda = "/soc/tpdm@6a24000/port/endpoint"; | |
| quat_mi2s_sd1_sleep = "/soc/pinctrl@03400000/quat_mi2s_sd1/quat_mi2s_sd1_sleep"; | |
| funnel_apss_merg_in_tpda_olc = "/soc/funnel@7810000/ports/port@2/endpoint"; | |
| llcc_bwmon = "/soc/qcom,llcc-bwmon"; | |
| qupv3_se9_i2c_sleep = "/soc/pinctrl@03400000/qupv3_se9_i2c_pins/qupv3_se9_i2c_sleep"; | |
| etm7 = "/soc/etm@7740000"; | |
| cam_sensor_mclk3_suspend = "/soc/pinctrl@03400000/cam_sensor_mclk3_suspend"; | |
| lt9611_pins = "/soc/pinctrl@03400000/ext_bridge_mux/lt9611_pins"; | |
| sdc2_cmd_ds_400KHz = "/soc/pinctrl@03400000/sdc2_cmd_ds_400KHz"; | |
| pm8005_revid = "/soc/qcom,spmi@c440000/qcom,pm8005@4/qcom,revid@100"; | |
| L2_100 = "/cpus/cpu@100/l2-cache"; | |
| funnel_qatb_in_tpda = "/soc/funnel@6005000/ports/port@1/endpoint"; | |
| pm8998_l5 = "/soc/rpmh-regulator-ldoa5/regulator-l5"; | |
| replicator_swao_out_funnel_in2 = "/soc/replicator@6b0a000/ports/port@2/endpoint"; | |
| cam_ipe0 = "/soc/qcom,ipe0"; | |
| cti12 = "/soc/cti@601c000"; | |
| intc = "/soc/interrupt-controller@17a00000"; | |
| slv_qhs_llcc = "/soc/ad-hoc-bus/slv-qhs-llcc"; | |
| cam_vfe1 = "/soc/qcom,vfe1@acb6000"; | |
| qupv3_se12_i2c_pins = "/soc/pinctrl@03400000/qupv3_se12_i2c_pins"; | |
| tpdm_ddr_out_funnel_ddr_0 = "/soc/tpdm@69e0000/port/endpoint"; | |
| iommu_slim_qca_ctrl_cb = "/soc/slim@17240000/qcom,iommu_slim_ctrl_cb"; | |
| mas_qhm_qup2 = "/soc/ad-hoc-bus/mas-qhm-qup2"; | |
| mas_qnm_gladiator_sodv = "/soc/ad-hoc-bus/mas-qnm-gladiator-sodv"; | |
| qupv3_se10_spi_pins = "/soc/pinctrl@03400000/qupv3_se10_spi_pins"; | |
| qupv3_se1_spi = "/soc/spi@884000"; | |
| pri_aux_pcm_sync_sleep = "/soc/pinctrl@03400000/pri_aux_pcm_sync/pri_aux_pcm_sync_sleep"; | |
| pm8998_s6_level_ao = "/soc/rpmh-regulator-mxlvl/regulator-s6-level-ao"; | |
| tpda_in_tpdm_center = "/soc/tpda@6004000/ports/port@1/endpoint"; | |
| funnel_apss_merg_in_tpda_llm_silver = "/soc/funnel@7810000/ports/port@4/endpoint"; | |
| cci0_suspend = "/soc/pinctrl@03400000/cci0_suspend"; | |
| cam_sensor_iris_active = "/soc/pinctrl@03400000/cam_sensor_iris_active"; | |
| swao_csr = "/soc/csr@6b0e000"; | |
| pm8998_tz = "/soc/qcom,spmi@c440000/qcom,pm8998@0/qcom,temp-alarm@2400"; | |
| pm8998_l28 = "/soc/rpmh-regulator-ldoa28/regulator-l28"; | |
| dai_quin_auxpcm = "/soc/qcom,msm-quin-auxpcm"; | |
| bcm_sh0_display = "/soc/ad-hoc-bus/bcm-sh0_display"; | |
| usb_audio_rx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-usb-audio-rx"; | |
| qupv3_se0_i2c_pins = "/soc/pinctrl@03400000/qupv3_se0_i2c_pins"; | |
| mas_qnm_snoc_gc = "/soc/ad-hoc-bus/mas-qnm-snoc-gc"; | |
| afe_loopback_tx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-afe-loopback-tx"; | |
| slv_qhs_compute_dsp_cfg = "/soc/ad-hoc-bus/slv-qhs-compute-dsp-cfg"; | |
| fg_int_default = "/soc/pinctrl@03400000/fg_int_default"; | |
| usb_qmp_dp_phy = "/soc/ssphy@88e8000"; | |
| l3_cpu0 = "/soc/qcom,l3-cpu0"; | |
| L1_TLB_200 = "/cpus/cpu@200/l1-tlb"; | |
| qupv3_se3_i2c = "/soc/i2c@88c000"; | |
| bcm_sn12 = "/soc/ad-hoc-bus/bcm-sn12"; | |
| sdhc_2 = "/soc/sdhci@8804000"; | |
| qupv3_se0_i2c_active = "/soc/pinctrl@03400000/qupv3_se0_i2c_pins/qupv3_se0_i2c_active"; | |
| xbl_region = "/reserved-memory/xbl_region@85e00000"; | |
| qupv3_se5_i2c_active = "/soc/pinctrl@03400000/qupv3_se5_i2c_pins/qupv3_se5_i2c_active"; | |
| dai_pri_tdm_tx_0 = "/soc/qcom,msm-dai-tdm-pri-tx/qcom,msm-dai-q6-tdm-pri-tx-0"; | |
| vendor = "/vendor"; | |
| ad_hoc_bus = "/soc/ad-hoc-bus"; | |
| msm_dai_mi2s = "/soc/qcom,msm-dai-mi2s"; | |
| bcm_mm2_display = "/soc/ad-hoc-bus/bcm-mm2_display"; | |
| cpu1_trip = "/soc/thermal-zones/cpu1-silver-lowf/trips/cpu1-trip"; | |
| funnel_dl_mm_in_tpdm_mm = "/soc/funnel@6c0b000/ports/port@1/endpoint"; | |
| quat_tdm_dout_sleep = "/soc/pinctrl@03400000/quat_tdm_dout/quat_tdm_dout_sleep"; | |
| qupv3_se0_spi_active = "/soc/pinctrl@03400000/qupv3_se0_spi_pins/qupv3_se0_spi_active"; | |
| qupv3_se5_spi_active = "/soc/pinctrl@03400000/qupv3_se5_spi_pins/qupv3_se5_spi_active"; | |
| qcom_cedev = "/soc/qcedev@1de0000"; | |
| qupv3_se13_i2c_active = "/soc/pinctrl@03400000/qupv3_se13_i2c_pins/qupv3_se13_i2c_active"; | |
| qupv3_se10_2uart_sleep = "/soc/pinctrl@03400000/qupv3_se10_2uart_pins/qupv3_se10_2uart_sleep"; | |
| bcm_mm0 = "/soc/ad-hoc-bus/bcm-mm0"; | |
| turing_etm0_out_funnel_turing_1 = "/soc/turing_etm0/port/endpoint"; | |
| ts_int_suspend = "/soc/pinctrl@03400000/ts_mux/ts_int_suspend"; | |
| pri_aux_pcm_clk_sleep = "/soc/pinctrl@03400000/pri_aux_pcm_clk/pri_aux_pcm_clk_sleep"; | |
| tpda_olc_in_tpdm_olc = "/soc/tpda@7832000/ports/port@1/endpoint"; | |
| usb_nop_phy = "/soc/usb_nop_phy"; | |
| cti_cpu4 = "/soc/cti@7420000"; | |
| qupv3_se5_spi = "/soc/spi@894000"; | |
| qupv3_se7_spi_sleep = "/soc/pinctrl@03400000/qupv3_se7_spi_pins/qupv3_se7_spi_sleep"; | |
| pm8998_l18 = "/soc/rpmh-regulator-ldoa18/regulator-l18"; | |
| qupv3_se13_spi_active = "/soc/pinctrl@03400000/qupv3_se13_spi_pins/qupv3_se13_spi_active"; | |
| cpug2_trip = "/soc/thermal-zones/cpu2-gold-lowf/trips/cpug2-trip"; | |
| bcm_cn0 = "/soc/ad-hoc-bus/bcm-cn0"; | |
| funnel_apss_in_etm1 = "/soc/funnel@7800000/ports/port@2/endpoint"; | |
| etm5_out_funnel_apss = "/soc/etm@7540000/port/endpoint"; | |
| pri_aux_pcm_sync_active = "/soc/pinctrl@03400000/pri_aux_pcm_sync/pri_aux_pcm_sync_active"; | |
| bcm_sn9 = "/soc/ad-hoc-bus/bcm-sn9"; | |
| modem_etm0_out_funnel_in2 = "/soc/modem_etm0/port/endpoint"; | |
| bcm_sh2 = "/soc/ad-hoc-bus/bcm-sh2"; | |
| secure_sp_mem = "/reserved-memory/secure_sp_region"; | |
| slv_qns_memnoc_gc = "/soc/ad-hoc-bus/slv-qns-memnoc-gc"; | |
| pm8005_tz = "/soc/qcom,spmi@c440000/qcom,pm8005@4/qcom,temp-alarm@2400"; | |
| tpda_llm_silver_in_tpdm_llm_silver = "/soc/tpda@78c0000/ports/port@1/endpoint"; | |
| slv_ipa_core_slave = "/soc/ad-hoc-bus/slv-ipa-core-slave"; | |
| quat_tdm_din_sleep = "/soc/pinctrl@03400000/quat_tdm_din/quat_tdm_din_sleep"; | |
| mmss_trip = "/soc/thermal-zones/mmss-lowf/trips/mmss-trip"; | |
| slv_qhs_imem_cfg = "/soc/ad-hoc-bus/slv-qhs-imem-cfg"; | |
| hdmi_det_suspend = "/soc/pinctrl@03400000/hdmidet_suspend/hdmi_det_suspend"; | |
| qupv3_se7_i2c = "/soc/i2c@89c000"; | |
| pm8998_temp_alarm = "/soc/thermal-zones/pm8998_tz"; | |
| i2c_freq_100Khz = "/soc/qcom,cci@ac4a000/qcom,i2c_standard_mode"; | |
| slv_qns_a2noc_snoc = "/soc/ad-hoc-bus/slv-qns-a2noc-snoc"; | |
| funnel_in2_in_modem_etm0 = "/soc/funnel@0x6043000/ports/port@1/endpoint"; | |
| trigout_a = "/soc/pinctrl@03400000/trigout_a"; | |
| mas_qhm_tsif = "/soc/ad-hoc-bus/mas-qhm-tsif"; | |
| tmc_etf_in_funnel_merg = "/soc/tmc@6047000/ports/port@1/endpoint"; | |
| fab_mem_noc_display = "/soc/ad-hoc-bus/fab-mem_noc_display"; | |
| cti1 = "/soc/cti@6011000"; | |
| smp2pgpio_ssr_smp2p_2_out = "/soc/qcom,smp2pgpio-ssr-smp2p-2-out"; | |
| flash_led3_iris_en = "/soc/pinctrl@03400000/flash_led3_iris/flash_led3_iris_en"; | |
| gfx3d_user = "/soc/qcom,kgsl-iommu/gfx3d_user"; | |
| pm8998_lvs2 = "/soc/rpmh-regulator-vsa2/regulator-lvs2"; | |
| mdm2ap_sleep = "/soc/pinctrl@03400000/mdm2ap/mdm2ap_sleep"; | |
| pil_video_mem = "/reserved-memory/video_region@0x95800000"; | |
| cpucc_debug = "/soc/syscon@17970018"; | |
| mas_xm_sdc4 = "/soc/ad-hoc-bus/mas-xm-sdc4"; | |
| qupv3_se4_i2c_sleep = "/soc/pinctrl@03400000/qupv3_se4_i2c_pins/qupv3_se4_i2c_sleep"; | |
| qupv3_se9_spi = "/soc/spi@a84000"; | |
| wcd_usbc_analog_en1_idle = "/soc/pinctrl@03400000/wcd_usbc_analog_en1/wcd_usbc_ana_en1_idle"; | |
| tpdm_llm_gold_out_tpda_llm_gold = "/soc/tpdm@78b0000/port/endpoint"; | |
| replicator_swao_out_eud = "/soc/replicator@6b0a000/ports/port@1/endpoint"; | |
| clock_aop = "/soc/qcom,aopclk"; | |
| pil_ipa_fw_mem = "/reserved-memory/ips_fw_region@0x8c400000"; | |
| replicator_in_tmc_etf = "/soc/replicator@6046000/ports/port@1/endpoint"; | |
| L2_400 = "/cpus/cpu@400/l2-cache"; | |
| etm5 = "/soc/etm@7540000"; | |
| pcm2 = "/soc/qcom,msm-ultra-low-latency"; | |
| memlat_cpu0 = "/soc/qcom,memlat-cpu0"; | |
| qusb_phy0 = "/soc/qusb@88e2000"; | |
| cam_sensor_mclk0_suspend = "/soc/pinctrl@03400000/cam_sensor_mclk0_suspend"; | |
| mas_qxm_camnoc_hf0_uncomp = "/soc/ad-hoc-bus/mas-qxm-camnoc-hf0-uncomp"; | |
| tmc_etf_swao_out_replicator = "/soc/tmc@6b09000/ports/port@0/endpoint"; | |
| gmu_kernel = "/soc/qcom,gmu/gmu_kernel"; | |
| mas_qnm_aggre2_noc = "/soc/ad-hoc-bus/mas-qnm-aggre2-noc"; | |
| pm8005_s2_level = "/soc/rpmh-regulator-msslvl/regulator-s2-level"; | |
| wcd_gnd_mic_swap_active = "/soc/pinctrl@03400000/wcd_gnd_mic_swap/wcd_gnd_mic_swap_active"; | |
| tpdm_apss_out_tpda_apss = "/soc/tpdm@7860000/port/endpoint"; | |
| pm8998_l3 = "/soc/rpmh-regulator-ldoa3/regulator-l3"; | |
| cti10 = "/soc/cti@601a000"; | |
| tert_mi2s_sd0_active = "/soc/pinctrl@03400000/tert_mi2s_sd0/tert_mi2s_sd0_active"; | |
| slv_qhs_pimem_cfg = "/soc/ad-hoc-bus/slv-qhs-pimem-cfg"; | |
| pil_adsp_mem = "/reserved-memory/adsp_region@0x8c500000"; | |
| slv_qns_llcc = "/soc/ad-hoc-bus/slv-qns-llcc"; | |
| pri_mi2s_mclk_active = "/soc/pinctrl@03400000/pri_mi2s_mclk/pri_mi2s_mclk_active"; | |
| spmi_debug_bus = "/soc/qcom,spmi-debug@6b22000"; | |
| qupv3_se8_spi_pins = "/soc/pinctrl@03400000/qupv3_se8_spi_pins"; | |
| voice = "/soc/qcom,msm-pcm-voice"; | |
| smp2pgpio_smp2p_3_out = "/soc/qcom,smp2pgpio-smp2p-3-out"; | |
| mas_qxm_mdp1 = "/soc/ad-hoc-bus/mas-qxm-mdp1"; | |
| int_fm_tx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-int-fm-tx"; | |
| sdc2_data_ds_400KHz = "/soc/pinctrl@03400000/sdc2_data_ds_400KHz"; | |
| smp2pgpio_ssr_smp2p_3_in = "/soc/qcom,smp2pgpio-ssr-smp2p-3-in"; | |
| pcie0_wake_default = "/soc/pinctrl@03400000/pcie0/pcie0_wake_default"; | |
| pm8998_l26 = "/soc/rpmh-regulator-ldoa26/regulator-l26"; | |
| sb_8_tx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-8-tx"; | |
| gpi_dma0 = "/soc/qcom,gpi-dma@0x800000"; | |
| L1_TLB_500 = "/cpus/cpu@500/l1-tlb"; | |
| tpdm_qm_out_tpda = "/soc/tpdm@69d0000/port/endpoint"; | |
| cti1_apss = "/soc/cti@78f0000"; | |
| msm_bus = "/soc/qcom,kgsl-busmon"; | |
| qupv3_se14_i2c_sleep = "/soc/pinctrl@03400000/qupv3_se14_i2c_pins/qupv3_se14_i2c_sleep"; | |
| tsif1_signals_active = "/soc/pinctrl@03400000/tsif1_signals_active"; | |
| gpu_cx_hw_ctrl = "/soc/syscon@0x5091540"; | |
| tpda_spss = "/soc/tpda@6882000"; | |
| qupv3_se6_ctsrx = "/soc/pinctrl@03400000/qupv3_se6_4uart_pins/qupv3_se6_ctsrx"; | |
| camera_rear_avdd_en_default = "/soc/qcom,spmi@c440000/qcom,pm8998@0/pinctrl@c000/camera_rear_avdd_en/camera_rear_avdd_en_default"; | |
| sdc2_clk_on = "/soc/pinctrl@03400000/sdc2_clk_on"; | |
| tpdm_ddr = "/soc/tpdm@69e0000"; | |
| slv_qhs_display_cfg = "/soc/ad-hoc-bus/slv-qhs-display-cfg"; | |
| mas_xm_ufs_mem = "/soc/ad-hoc-bus/mas-xm-ufs-mem"; | |
| funnel_in0_out_funnel_merg = "/soc/funnel@0x6041000/ports/port@0/endpoint"; | |
| funnel_turing = "/soc/funnel@6861000"; | |
| clock_gfx = "/soc/qcom,gfxcc@5090000"; | |
| funnel_swao_out_tmc_etf_swao = "/soc/funnel@0x6b08000/ports/port@0/endpoint"; | |
| qupv3_se11_spi = "/soc/spi@a8c000"; | |
| atest_usb13_suspend = "/soc/pinctrl@03400000/atest_usb13/atest_usb13_suspend"; | |
| cti1_dlmm = "/soc/cti@6c0a000"; | |
| stm = "/soc/stm@6002000"; | |
| hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc = "/soc/qcom,gdsc@0x17d040"; | |
| qupv3_se6_tx = "/soc/pinctrl@03400000/qupv3_se6_4uart_pins/qupv3_se6_tx"; | |
| sb_5_tx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-5-tx"; | |
| glink_lpass = "/soc/qcom,glink-ssr-adsp"; | |
| ddr_trip = "/soc/thermal-zones/ddr-lowf/trips/ddr-trip"; | |
| qupv3_se2_spi_sleep = "/soc/pinctrl@03400000/qupv3_se2_spi_pins/qupv3_se2_spi_sleep"; | |
| slv_srvc_snoc = "/soc/ad-hoc-bus/slv-srvc-snoc"; | |
| afe = "/soc/qcom,msm-pcm-afe"; | |
| cam_sensor_rear2_suspend = "/soc/pinctrl@03400000/cam_sensor_rear2_suspend"; | |
| cam_csiphy3 = "/soc/qcom,csiphy@ac68000"; | |
| cti_cpu2 = "/soc/cti@7220000"; | |
| pm8998_l16 = "/soc/rpmh-regulator-ldoa16/regulator-l16"; | |
| jtag_mm7 = "/soc/jtagmm@7740000"; | |
| mdss_dsi1_pll = "/soc/qcom,mdss_dsi_pll@ae96a00"; | |
| pm8998_s7 = "/soc/rpmh-regulator-smpa7/regulator-s7"; | |
| cam_sensor_rear_active = "/soc/pinctrl@03400000/cam_sensor_rear_active"; | |
| hyp_region = "/reserved-memory/hyp_region@85700000"; | |
| ife_1_gdsc = "/soc/qcom,gdsc@0xad0a004"; | |
| qupv3_se13_i2c = "/soc/i2c@a94000"; | |
| bcm_sn7 = "/soc/ad-hoc-bus/bcm-sn7"; | |
| tpda_in_funnel_dl_mm = "/soc/tpda@6004000/ports/port@2/endpoint"; | |
| bcm_sh0 = "/soc/ad-hoc-bus/bcm-sh0"; | |
| mdss_dsi_phy0 = "/soc/qcom,mdss_dsi_phy0@ae94400"; | |
| voip = "/soc/qcom,msm-voip-dsp"; | |
| funnel_lpass_1 = "/soc/funnel_1@6845000"; | |
| anoc_1_pcie_tbu = "/soc/apps-smmu@0x15000000/anoc_1_pcie_tbu@0x150e1000"; | |
| sb_2_tx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-2-tx"; | |
| slv_qhs_qupv3_north = "/soc/ad-hoc-bus/slv-qhs-qupv3-north"; | |
| qcom_tzlog = "/soc/tz-log@146bf720"; | |
| devfreq_l3lat_4 = "/soc/qcom,cpu4-l3lat-mon"; | |
| emerg_config6 = "/soc/thermal-zones/cpu2-gold-step/trips/emerg-config6"; | |
| cam_sensor_iris_suspend = "/soc/pinctrl@03400000/cam_sensor_iris_suspend"; | |
| tpda_spss_out_funnel_spss = "/soc/tpda@6882000/ports/port@0/endpoint"; | |
| sdc2_clk_ds_200MHz = "/soc/pinctrl@03400000/sdc2_clk_ds_200MHz"; | |
| modem_skin = "/soc/qmi-tmd-devices/modem/modem_skin"; | |
| glink_qos_adsp = "/soc/qcom,glink-qos-config-adsp"; | |
| tpda_in_funnel_lpass = "/soc/tpda@6004000/ports/port@4/endpoint"; | |
| clock_videocc = "/soc/qcom,videocc@ab00000"; | |
| int_fm_rx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-int-fm-rx"; | |
| slv_qhs_glm = "/soc/ad-hoc-bus/slv-qhs-glm"; | |
| tpdm_pimem_out_tpda = "/soc/tpdm@6850000/port/endpoint"; | |
| qupv3_se15_spi = "/soc/spi@a9c000"; | |
| sec_mi2s_mclk_sleep = "/soc/pinctrl@03400000/sec_mi2s_mclk/sec_mi2s_mclk_sleep"; | |
| cont_splash_memory = "/reserved-memory/cont_splash_region@9d400000"; | |
| sb_8_rx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-8-rx"; | |
| anoc_2_tbu = "/soc/apps-smmu@0x15000000/anoc_2_tbu@0x150c9000"; | |
| L1_I_300 = "/cpus/cpu@300/l1-icache"; | |
| tpda_modem = "/soc/tpda@6831000"; | |
| mas_xm_sdc2 = "/soc/ad-hoc-bus/mas-xm-sdc2"; | |
| qupv3_se12_spi_sleep = "/soc/pinctrl@03400000/qupv3_se12_spi_pins/qupv3_se12_spi_sleep"; | |
| usb1 = "/soc/ssusb@a800000"; | |
| dai_tert_tdm_tx_0 = "/soc/qcom,msm-dai-tdm-tert-tx/qcom,msm-dai-q6-tdm-tert-tx-0"; | |
| qupv3_se7_i2c_pins = "/soc/pinctrl@03400000/qupv3_se7_i2c_pins"; | |
| mas_xm_usb3_0 = "/soc/ad-hoc-bus/mas-xm-usb3-0"; | |
| L2_700 = "/cpus/cpu@700/l2-cache"; | |
| pm8998_adc_tm = "/soc/qcom,spmi@c440000/qcom,pm8998@0/vadc@3400"; | |
| ts_active = "/soc/pinctrl@03400000/ts_mux/ts_active"; | |
| pcie0_1v5_on = "/soc/pinctrl@03400000/pcie0/pcie0_1v5_on"; | |
| qupv3_se5_spi_pins = "/soc/pinctrl@03400000/qupv3_se5_spi_pins"; | |
| funnel_spss_out_funnel_in0 = "/soc/funnel@6883000/ports/port@0/endpoint"; | |
| L1_D_200 = "/cpus/cpu@200/l1-dcache"; | |
| pcie1_clkreq_default = "/soc/pinctrl@03400000/pcie1/pcie1_clkreq_default"; | |
| mas_qxm_camnoc_sf = "/soc/ad-hoc-bus/mas-qxm-camnoc-sf"; | |
| ts_int_input = "/soc/pinctrl@03400000/ts_int_input"; | |
| cpu0_trip = "/soc/thermal-zones/cpu0-silver-lowf/trips/cpu0-trip"; | |
| etm3 = "/soc/etm@7340000"; | |
| mas_acm_l3 = "/soc/ad-hoc-bus/mas-acm-l3"; | |
| pcm0 = "/soc/qcom,msm-pcm"; | |
| slv_qhs_gpuss_cfg = "/soc/ad-hoc-bus/slv-qhs-gpuss-cfg"; | |
| gpu_gx_domain_addr = "/soc/syscon@0x5091508"; | |
| glink_spss = "/soc/qcom,glink-ssr-spss"; | |
| dai_mi2s5 = "/soc/qcom,msm-dai-mi2s/qcom,msm-dai-q6-mi2s-senary"; | |
| sb_5_rx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-5-rx"; | |
| rot_reg = "/soc/qcom,mdss_rotator@ae00000/qcom,rot-reg-bus"; | |
| mas_llcc_mc_display = "/soc/ad-hoc-bus/mas-llcc-mc_display"; | |
| fab_camnoc_virt = "/soc/ad-hoc-bus/fab-camnoc_virt"; | |
| pm8998_l1 = "/soc/rpmh-regulator-ldoa1/regulator-l1"; | |
| quat_aux_pcm_dout_active = "/soc/pinctrl@03400000/quat_aux_pcm_dout/quat_aux_pcm_dout_active"; | |
| flash_led3_front_en = "/soc/pinctrl@03400000/flash_led3_front/flash_led3_front_en"; | |
| slv_qxs_pimem = "/soc/ad-hoc-bus/slv-qxs-pimem"; | |
| funnel_in2_in_gfx = "/soc/funnel@0x6943000/ports/port@1/endpoint"; | |
| cpug1_trip = "/soc/thermal-zones/cpu1-gold-lowf/trips/cpug1-trip"; | |
| mas_qhm_qdss_bam = "/soc/ad-hoc-bus/mas-qhm-qdss-bam"; | |
| tpda_llm_silver = "/soc/tpda@78c0000"; | |
| sde_dp_usbplug_cc_suspend = "/soc/pinctrl@03400000/sde_dp_usbplug_cc_suspend"; | |
| funnel_qatb = "/soc/funnel@6005000"; | |
| sb_2_rx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-2-rx"; | |
| pm8998_l24 = "/soc/rpmh-regulator-ldoa24/regulator-l24"; | |
| fab_gladiator_noc = "/soc/ad-hoc-bus/fab-gladiator_noc"; | |
| usb30_prim_gdsc = "/soc/qcom,gdsc@0x10f004"; | |
| bcm_acv = "/soc/ad-hoc-bus/bcm-acv"; | |
| CPU6 = "/cpus/cpu@600"; | |
| slv_qhs_venus_cfg = "/soc/ad-hoc-bus/slv-qhs-venus-cfg"; | |
| dummy_eud = "/soc/dummy_sink"; | |
| pri_mi2s_sd1_sleep = "/soc/pinctrl@03400000/pri_mi2s_sd1/pri_mi2s_sd1_sleep"; | |
| slv_qns_cnoc = "/soc/ad-hoc-bus/slv-qns-cnoc"; | |
| CPU_COST_1 = "/energy-costs/core-cost1"; | |
| mem_client_3_size = "/soc/qcom,memshare/qcom,client_3"; | |
| slv_qns_camnoc_uncomp = "/soc/ad-hoc-bus/slv-qns-camnoc-uncomp"; | |
| cti0_ddr0 = "/soc/cti@69e1000"; | |
| smp2pgpio_smp2p_1_in = "/soc/qcom,smp2pgpio-smp2p-1-in"; | |
| qupv3_se7_i2c_sleep = "/soc/pinctrl@03400000/qupv3_se7_i2c_pins/qupv3_se7_i2c_sleep"; | |
| mas_qnm_memnoc = "/soc/ad-hoc-bus/mas-qnm-memnoc"; | |
| clk40M = "/soc/can_clock"; | |
| qupv3_se1_i2c_active = "/soc/pinctrl@03400000/qupv3_se1_i2c_pins/qupv3_se1_i2c_active"; | |
| qupv3_se6_i2c_active = "/soc/pinctrl@03400000/qupv3_se6_i2c_pins/qupv3_se6_i2c_active"; | |
| slv_qhs_tlmm_south = "/soc/ad-hoc-bus/slv-qhs-tlmm-south"; | |
| tert_aux_pcm_din_active = "/soc/pinctrl@03400000/tert_aux_pcm_din/tert_aux_pcm_din_active"; | |
| tpda_llm_gold_in_tpdm_llm_gold = "/soc/tpda@78d0000/ports/port@1/endpoint"; | |
| stub_codec = "/soc/qcom,msm-stub-codec"; | |
| cti8 = "/soc/cti@6018000"; | |
| ipe_1_gdsc = "/soc/qcom,gdsc@0xad08004"; | |
| cam_csiphy1 = "/soc/qcom,csiphy@ac66000"; | |
| system_heap = "/soc/qcom,ion/qcom,ion-heap@25"; | |
| cti_cpu0 = "/soc/cti@7020000"; | |
| pm8998_l14 = "/soc/rpmh-regulator-ldoa14/regulator-l14"; | |
| qupv3_se1_spi_active = "/soc/pinctrl@03400000/qupv3_se1_spi_pins/qupv3_se1_spi_active"; | |
| qupv3_se6_spi_active = "/soc/pinctrl@03400000/qupv3_se6_spi_pins/qupv3_se6_spi_active"; | |
| qupv3_se14_i2c_active = "/soc/pinctrl@03400000/qupv3_se14_i2c_pins/qupv3_se14_i2c_active"; | |
| qupv3_se14_spi_pins = "/soc/pinctrl@03400000/qupv3_se14_spi_pins"; | |
| jtag_mm5 = "/soc/jtagmm@7540000"; | |
| dai_quat_auxpcm = "/soc/qcom,msm-quat-auxpcm"; | |
| funnel_qatb_in_funnel_lpass_1 = "/soc/funnel@6005000/ports/port@2/endpoint"; | |
| pm8998_s5 = "/soc/rpmh-regulator-smpa5/regulator-s5"; | |
| bcm_sn5 = "/soc/ad-hoc-bus/bcm-sn5"; | |
| sde_dsi1_active = "/soc/pinctrl@03400000/sde_dsi1_active"; | |
| slv_qns_llcc_display = "/soc/ad-hoc-bus/slv-qns-llcc_display"; | |
| pil_mba_mem = "/reserved-memory/mba_region@0x96500000"; | |
| qupv3_se14_spi_active = "/soc/pinctrl@03400000/qupv3_se14_spi_pins/qupv3_se14_spi_active"; | |
| tpda_out_funnel_qatb = "/soc/tpda@6004000/ports/port@0/endpoint"; | |
| cam_fd = "/soc/qcom,fd@ac5a000"; | |
| qupv3_se0_i2c = "/soc/i2c@880000"; | |
| audio_apr = "/soc/qcom,msm-audio-apr"; | |
| tpdm_swao1 = "/soc/tpdm@6b03000"; | |
| funnel_swao_in_sensor_etm0 = "/soc/funnel@0x6b08000/ports/port@1/endpoint"; | |
| slv_qhs_ufs_card_cfg = "/soc/ad-hoc-bus/slv-qhs-ufs-card-cfg"; | |
| qupv3_se4_i2c_pins = "/soc/pinctrl@03400000/qupv3_se4_i2c_pins"; | |
| funnel_apss_out_funnel_apss_merg = "/soc/funnel@7800000/ports/port@0/endpoint"; | |
| incall_music_rx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-incall-music-rx"; | |
| emerg_config4 = "/soc/thermal-zones/cpu0-gold-step/trips/emerg-config4"; | |
| LLCC_4 = "/soc/qcom,llcc@1100000/llcc_4_dcache"; | |
| ts_int_suspend1 = "/soc/pinctrl@03400000/pmx_ts_int_suspend/ts_int_suspend1"; | |
| slv_qns2_mem_noc = "/soc/ad-hoc-bus/slv-qns2-mem-noc"; | |
| smp2pgpio_smp2p_15_in = "/soc/qcom,smp2pgpio-smp2p-15-in"; | |
| mas_qxm_ipa = "/soc/ad-hoc-bus/mas-qxm-ipa"; | |
| sec_aux_pcm_dout_sleep = "/soc/pinctrl@03400000/sec_aux_pcm_dout/sec_aux_pcm_dout_sleep"; | |
| qupv3_se2_spi_pins = "/soc/pinctrl@03400000/qupv3_se2_spi_pins"; | |
| pri_mi2s_ws_sleep = "/soc/pinctrl@03400000/pri_mi2s_ws/pri_mi2s_ws_sleep"; | |
| tpda_llm_gold_out_funnel_apss_merg = "/soc/tpda@78d0000/ports/port@0/endpoint"; | |
| mas_qxm_camnoc_sf_uncomp = "/soc/ad-hoc-bus/mas-qxm-camnoc-sf-uncomp"; | |
| tert_mi2s_sleep = "/soc/pinctrl@03400000/tert_mi2s/tert_mi2s_sleep"; | |
| L1_I_600 = "/cpus/cpu@600/l1-icache"; | |
| ts_reset_suspend = "/soc/pinctrl@03400000/ts_mux/ts_reset_suspend"; | |
| key_home_default = "/soc/qcom,spmi@c440000/qcom,pm8998@0/pinctrl@c000/key_home/key_home_default"; | |
| slv_qns_gnoc_memnoc = "/soc/ad-hoc-bus/slv-qns-gnoc-memnoc"; | |
| cti0_apss = "/soc/cti@78e0000"; | |
| tpda_olc = "/soc/tpda@7832000"; | |
| mas_qxm_venus_arm9 = "/soc/ad-hoc-bus/mas-qxm-venus-arm9"; | |
| qupv3_se2_spi = "/soc/spi@888000"; | |
| fab_ipa_virt = "/soc/ad-hoc-bus/fab-ipa_virt"; | |
| ipa_hw = "/soc/qcom,ipa@01e00000"; | |
| bt_sco_tx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-bt-sco-tx"; | |
| cpubw = "/soc/qcom,cpubw"; | |
| L1_D_500 = "/cpus/cpu@500/l1-dcache"; | |
| smp2pgpio_ipa_1_out = "/soc/qcom,smp2pgpio-ipa-1-out"; | |
| slv_qhs_a2_noc_cfg = "/soc/ad-hoc-bus/slv-qhs-a2-noc-cfg"; | |
| slv_qhs_memnoc = "/soc/ad-hoc-bus/slv-qhs-memnoc"; | |
| tert_aux_pcm_dout_active = "/soc/pinctrl@03400000/tert_aux_pcm_dout/tert_aux_pcm_dout_active"; | |
| funnel_apss = "/soc/funnel@7800000"; | |
| tpda = "/soc/tpda@6004000"; | |
| hlos1_vote_mmnoc_mmu_tbu_sf_gdsc = "/soc/qcom,gdsc@0x17d044"; | |
| ts_int_active = "/soc/pinctrl@03400000/pmx_ts_int_active/ts_int_active"; | |
| ipa_smmu_wlan = "/soc/qcom,ipa@01e00000/ipa_smmu_wlan"; | |
| etm1 = "/soc/etm@7140000"; | |
| cti0_dlmm = "/soc/cti@6c09000"; | |
| snoc_cnoc_keepalive = "/soc/qcom,snoc_cnoc_keepalive"; | |
| cam_bps = "/soc/qcom,bps"; | |
| qupv3_se5_spi_sleep = "/soc/pinctrl@03400000/qupv3_se5_spi_pins/qupv3_se5_spi_sleep"; | |
| devfreq_cpufreq = "/soc/devfreq-cpufreq"; | |
| dai_mi2s3 = "/soc/qcom,msm-dai-mi2s/qcom,msm-dai-q6-mi2s-quat"; | |
| qupv3_se4_i2c = "/soc/i2c@890000"; | |
| cam_sensor_rear2_active = "/soc/pinctrl@03400000/cam_sensor_rear2_active"; | |
| pil_slpi_mem = "/reserved-memory/slpi_region@0x96700000"; | |
| smp2pgpio_ipa_1_in = "/soc/qcom,smp2pgpio-ipa-1-in"; | |
| CLUSTER_COST_0 = "/energy-costs/cluster-cost0"; | |
| pm8005_gpios = "/soc/qcom,spmi@c440000/qcom,pm8005@4/pinctrl@c000"; | |
| funnel_in2_in_funnel_apss_merg = "/soc/funnel@0x6043000/ports/port@4/endpoint"; | |
| ipa_smmu_ap = "/soc/qcom,ipa@01e00000/ipa_smmu_ap"; | |
| etm1_out_funnel_apss = "/soc/etm@7140000/port/endpoint"; | |
| mas_qnm_mnoc_hf = "/soc/ad-hoc-bus/mas-qnm-mnoc-hf"; | |
| mnoc_sf_0_tbu = "/soc/apps-smmu@0x15000000/mnoc_sf_0_tbu@0x150d5000"; | |
| tpdm_llm_silver_out_tpda_llm_silver = "/soc/tpdm@78a0000/port/endpoint"; | |
| bcm_ce0 = "/soc/ad-hoc-bus/bcm-ce0"; | |
| ife_0_gdsc = "/soc/qcom,gdsc@0xad09004"; | |
| gfx3d_secure = "/soc/qcom,kgsl-iommu/gfx3d_secure"; | |
| qupv3_se6_spi = "/soc/spi@898000"; | |
| compr = "/soc/qcom,msm-compr-dsp"; | |
| gpubw = "/soc/qcom,gpubw"; | |
| pm8998_l22 = "/soc/rpmh-regulator-ldoa22/regulator-l22"; | |
| smp2pgpio_rdbg_5_in = "/soc/qcom,smp2pgpio-rdbg-5-in"; | |
| tpda_in_tpdm_pimem = "/soc/tpda@6004000/ports/port@10/endpoint"; | |
| mas_qxm_gpu = "/soc/ad-hoc-bus/mas-qxm-gpu"; | |
| tpda_olc_out_funnel_apss_merg = "/soc/tpda@7832000/ports/port@0/endpoint"; | |
| fd_iova_mem_map = "/soc/qcom,cam_smmu/msm_cam_smmu_fd/iova-mem-map"; | |
| funnel_in2_in_gfx_cx = "/soc/funnel@0x6943000/ports/port@2/endpoint"; | |
| tert_aux_pcm_active = "/soc/pinctrl@03400000/tert_aux_pcm/tert_aux_pcm_active"; | |
| funnel_apss_in_etm6 = "/soc/funnel@7800000/ports/port@7/endpoint"; | |
| qupv3_se13_i2c_pins = "/soc/pinctrl@03400000/qupv3_se13_i2c_pins"; | |
| CPU4 = "/cpus/cpu@400"; | |
| sdc2_clk_ds_100MHz = "/soc/pinctrl@03400000/sdc2_clk_ds_100MHz"; | |
| quat_mi2s_active = "/soc/pinctrl@03400000/quat_mi2s/quat_mi2s_active"; | |
| slim_aud = "/soc/slim@171c0000"; | |
| soc = "/soc"; | |
| pcie1_wake_default = "/soc/pinctrl@03400000/pcie1/pcie1_wake_default"; | |
| clock_gcc = "/soc/qcom,gcc@100000"; | |
| funnel_swao_in_tpda_swao = "/soc/funnel@0x6b08000/ports/port@2/endpoint"; | |
| bcm_mc0 = "/soc/ad-hoc-bus/bcm-mc0"; | |
| qupv3_se11_spi_pins = "/soc/pinctrl@03400000/qupv3_se11_spi_pins"; | |
| cci1_suspend = "/soc/pinctrl@03400000/cci1_suspend"; | |
| mdss_dsi0 = "/soc/qcom,mdss_dsi_ctrl0@ae94000"; | |
| qupv3_se2_i2c_sleep = "/soc/pinctrl@03400000/qupv3_se2_i2c_pins/qupv3_se2_i2c_sleep"; | |
| mdm_trip = "/soc/thermal-zones/mdm-core-lowf/trips/mdm-trip"; | |
| tpdm_spss = "/soc/tpdm@6880000"; | |
| qupv3_se15_spi_sleep = "/soc/pinctrl@03400000/qupv3_se15_spi_pins/qupv3_se15_spi_sleep"; | |
| tmc_etr = "/soc/tmc@6048000"; | |
| cam_lrme = "/soc/qcom,lrme@ac6b000"; | |
| pm8998_trip1 = "/soc/thermal-zones/pm8998_tz/trips/pm8998-trip1"; | |
| gpu_gx_gdsc = "/soc/qcom,gdsc@0x509100c"; | |
| qcom_rng = "/soc/qrng@793000"; | |
| qupv3_se8_i2c = "/soc/i2c@a80000"; | |
| pm8998_vadc = "/soc/qcom,spmi@c440000/qcom,pm8998@0/vadc@3100"; | |
| mas_qhm_cnoc = "/soc/ad-hoc-bus/mas-qhm-cnoc"; | |
| slv_qhs_sdc4 = "/soc/ad-hoc-bus/slv-qhs-sdc4"; | |
| mas_qxm_camnoc_hf1 = "/soc/ad-hoc-bus/mas-qxm-camnoc-hf1"; | |
| pil_modem = "/soc/qcom,mss@4080000"; | |
| bt_sco_rx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-bt-sco-rx"; | |
| funnel_ddr_0_in_tpdm_ddr = "/soc/funnel@69e2000/ports/port@1/endpoint"; | |
| wcd_gnd_mic_swap_idle = "/soc/pinctrl@03400000/wcd_gnd_mic_swap/wcd_gnd_mic_swap_idle"; | |
| gfx_out_funnel_in2 = "/soc/qcom,kgsl-3d0@5000000/qcom,gpu-coresights/qcom,gpu-coresight@0/port/endpoint"; | |
| dai_quat_tdm_rx_0 = "/soc/qcom,msm-dai-tdm-quat-rx/qcom,msm-dai-q6-tdm-quat-rx-0"; | |
| sdc2_data_on = "/soc/pinctrl@03400000/sdc2_data_on"; | |
| smp2pgpio_rdbg_2_in = "/soc/qcom,smp2pgpio-rdbg-2-in"; | |
| funnel_in0_in_stm = "/soc/funnel@0x6041000/ports/port@3/endpoint"; | |
| slv_qhs_snoc_cfg = "/soc/ad-hoc-bus/slv-qhs-snoc-cfg"; | |
| tsens1 = "/soc/tsens@c223000"; | |
| jpeg_iova_mem_map = "/soc/qcom,cam_smmu/msm_cam_smmu_jpeg/iova-mem-map"; | |
| qupv3_se1_i2c_pins = "/soc/pinctrl@03400000/qupv3_se1_i2c_pins"; | |
| L1_TLB_100 = "/cpus/cpu@100/l1-tlb"; | |
| smp2pgpio_ssr_smp2p_3_out = "/soc/qcom,smp2pgpio-ssr-smp2p-3-out"; | |
| cti6 = "/soc/cti@6016000"; | |
| sdc2_clk_ds_50MHz = "/soc/pinctrl@03400000/sdc2_clk_ds_50MHz"; | |
| modem_current = "/soc/qmi-tmd-devices/modem/modem_current"; | |
| qupv3_0 = "/soc/qcom,qupv3_0_geni_se@8c0000"; | |
| mas_qnm_apps = "/soc/ad-hoc-bus/mas-qnm-apps"; | |
| bcm_mm3_display = "/soc/ad-hoc-bus/bcm-mm3_display"; | |
| qcom_seecom = "/soc/qseecom@86d00000"; | |
| pm8998_l12 = "/soc/rpmh-regulator-ldoa12/regulator-l12"; | |
| mas_qhm_memnoc_cfg = "/soc/ad-hoc-bus/mas-qhm-memnoc-cfg"; | |
| jtag_mm3 = "/soc/jtagmm@7340000"; | |
| mas_xm_ufs_card = "/soc/ad-hoc-bus/mas-xm-ufs-card"; | |
| L1_D_0 = "/cpus/cpu@0/l1-dcache"; | |
| pm8998_s3 = "/soc/rpmh-regulator-smpa3/regulator-s3"; | |
| quat_mi2s_sd2_sleep = "/soc/pinctrl@03400000/quat_mi2s_sd2/quat_mi2s_sd2_sleep"; | |
| qupv3_se10_2uart_pins = "/soc/pinctrl@03400000/qupv3_se10_2uart_pins"; | |
| gpu1_trip_l = "/soc/thermal-zones/gpu1-lowf/trips/gpu1-trip_l"; | |
| bcm_sn3 = "/soc/ad-hoc-bus/bcm-sn3"; | |
| quat_tdm_sleep = "/soc/pinctrl@03400000/quat_tdm/quat_tdm_sleep"; | |
| dbm_1p5 = "/soc/dbm@a6f8000"; | |
| qupv3_se9_2uart_sleep = "/soc/pinctrl@03400000/qupv3_se9_2uart_pins/qupv3_se9_2uart_sleep"; | |
| l3_1_trip = "/soc/thermal-zones/kryo-l3-1-lowf/trips/l3-1-trip"; | |
| dai_dp = "/soc/qcom,msm-dai-q6-dp"; | |
| quat_tdm_dout_active = "/soc/pinctrl@03400000/quat_tdm_dout/quat_tdm_dout_active"; | |
| cpug0_trip = "/soc/thermal-zones/cpu0-gold-lowf/trips/cpug0-trip"; | |
| devfreq_l3lat_0 = "/soc/qcom,cpu0-l3lat-mon"; | |
| tpda_in_funnel_turing = "/soc/tpda@6004000/ports/port@5/endpoint"; | |
| hostless = "/soc/qcom,msm-pcm-hostless"; | |
| emerg_config2 = "/soc/thermal-zones/cpu2-silver-step/trips/emerg-config2"; | |
| LLCC_2 = "/soc/qcom,llcc@1100000/llcc_2_dcache"; | |
| cx_cdev = "/soc/rpmh-regulator-cxlvl/regulator-cdev"; | |
| usb_qmp_phy = "/soc/ssphy@88eb000"; | |
| sec_aux_pcm_din_sleep = "/soc/pinctrl@03400000/sec_aux_pcm_din/sec_aux_pcm_din_sleep"; | |
| qupv3_se12_i2c_sleep = "/soc/pinctrl@03400000/qupv3_se12_i2c_pins/qupv3_se12_i2c_sleep"; | |
| pm8998_l8 = "/soc/rpmh-regulator-ldoa8/regulator-l8"; | |
| pri_aux_pcm_din_active = "/soc/pinctrl@03400000/pri_aux_pcm_din/pri_aux_pcm_din_active"; | |
| bcm_mc0_display = "/soc/ad-hoc-bus/bcm-mc0_display"; | |
| tmc_etf_swao = "/soc/tmc@6b09000"; | |
| cti15 = "/soc/cti@601f000"; | |
| mdss_mdp = "/soc/qcom,mdss_mdp@ae00000"; | |
| cdsp_vdd = "/soc/qmi-tmd-devices/cdsp/cdsp_vdd"; | |
| qupv3_se10_2uart_active = "/soc/pinctrl@03400000/qupv3_se10_2uart_pins/qupv3_se10_2uart_active"; | |
| led_wifi_default = "/soc/qcom,spmi@c440000/qcom,pm8998@0/pinctrl@c000/led_wifi/led_wifi_default"; | |
| slv_qns2_mem_noc_display = "/soc/ad-hoc-bus/slv-qns2-mem-noc_display"; | |
| energy_costs = "/energy-costs"; | |
| etm4_out_funnel_apss = "/soc/etm@7440000/port/endpoint"; | |
| slv_srvc_memnoc = "/soc/ad-hoc-bus/slv-srvc-memnoc"; | |
| pm8998_revid = "/soc/qcom,spmi@c440000/qcom,pm8998@0/qcom,revid@100"; | |
| mas_qxm_mdp0_display = "/soc/ad-hoc-bus/mas-qxm-mdp0_display"; | |
| cam_sensor_mclk3_active = "/soc/pinctrl@03400000/cam_sensor_mclk3_active"; | |
| slv_qhs_usb3_1 = "/soc/ad-hoc-bus/slv-qhs-usb3-1"; | |
| quat_aux_pcm_din_sleep = "/soc/pinctrl@03400000/quat_aux_pcm_din/quat_aux_pcm_din_sleep"; | |
| lmh_dcvs0 = "/soc/qcom,cpucc@0x17d41000/qcom,limits-dcvs@0"; | |
| pri_mi2s_sd1_active = "/soc/pinctrl@03400000/pri_mi2s_sd1/pri_mi2s_sd1_active"; | |
| quat_mi2s_mclk_sleep = "/soc/pinctrl@03400000/quat_mi2s_mclk/quat_mi2s_mclk_sleep"; | |
| tpdm_modem = "/soc/tpdm@6830000"; | |
| sec_aux_pcm_active = "/soc/pinctrl@03400000/sec_aux_pcm/sec_aux_pcm_active"; | |
| mas_ipa_core_master = "/soc/ad-hoc-bus/mas-ipa-core-master"; | |
| qupv3_se10_i2c = "/soc/i2c@a88000"; | |
| qupv3_se0_spi_sleep = "/soc/pinctrl@03400000/qupv3_se0_spi_pins/qupv3_se0_spi_sleep"; | |
| pm8005_s3 = "/soc/rpmh-regulator-smpc3/regulator-s3"; | |
| tpdm_olc = "/soc/tpdm@7830000"; | |
| ts_int_output_high = "/soc/pinctrl@03400000/ts_int_output_high"; | |
| firmware = "/firmware"; | |
| dai_mi2s1 = "/soc/qcom,msm-dai-mi2s/qcom,msm-dai-q6-mi2s-sec"; | |
| bcm_sn15 = "/soc/ad-hoc-bus/bcm-sn15"; | |
| slv_qns_gladiator_sodv = "/soc/ad-hoc-bus/slv-qns-gladiator-sodv"; | |
| funnel_in0_in_funnel_spss = "/soc/funnel@0x6041000/ports/port@1/endpoint"; | |
| L3_0 = "/cpus/cpu@0/l2-cache/l3-cache"; | |
| ipe_0_gdsc = "/soc/qcom,gdsc@0xad07004"; | |
| quat_aux_pcm_dout_sleep = "/soc/pinctrl@03400000/quat_aux_pcm_dout/quat_aux_pcm_dout_sleep"; | |
| mas_qxm_pimem = "/soc/ad-hoc-bus/mas-qxm-pimem"; | |
| qupv3_se10_i2c_pins = "/soc/pinctrl@03400000/qupv3_se10_i2c_pins"; | |
| qupv3_se12_spi = "/soc/spi@a90000"; | |
| L2_300 = "/cpus/cpu@300/l2-cache"; | |
| iommu_slim_aud_ctrl_cb = "/soc/slim@171c0000/qcom,iommu_slim_ctrl_cb"; | |
| cam_sensor_mclk1_suspend = "/soc/pinctrl@03400000/cam_sensor_mclk1_suspend"; | |
| dai_hdmi = "/soc/qcom,msm-dai-q6-hdmi"; | |
| cpu_pmu = "/soc/cpu-pmu"; | |
| cam_res_mgr_suspend = "/soc/pinctrl@03400000/cam_res_mgr_suspend"; | |
| cci1_active = "/soc/pinctrl@03400000/cci1_active"; | |
| slv_qxs_pcie = "/soc/ad-hoc-bus/slv-qxs-pcie"; | |
| glink_cdsp = "/soc/qcom,glink-ssr-cdsp"; | |
| bcm_mm3 = "/soc/ad-hoc-bus/bcm-mm3"; | |
| tpdm_mm = "/soc/tpdm@6c08000"; | |
| devfreq_memlat_4 = "/soc/qcom,cpu4-memlat-mon"; | |
| quat_mi2s_sleep = "/soc/pinctrl@03400000/quat_mi2s/quat_mi2s_sleep"; | |
| tmc_etr_in_replicator = "/soc/tmc@6048000/port/endpoint"; | |
| funnel_turing_1_in_turing_etm0 = "/soc/funnel_1@6861000/ports/port@1/endpoint"; | |
| fab_system_noc = "/soc/ad-hoc-bus/fab-system_noc"; | |
| sde_dsi_suspend = "/soc/pinctrl@03400000/pmx_sde/sde_dsi_suspend"; | |
| cti_cpu7 = "/soc/cti@7720000"; | |
| pm8998_l20 = "/soc/rpmh-regulator-ldoa20/regulator-l20"; | |
| sde_dp_aux_suspend = "/soc/pinctrl@03400000/sde_dp_aux_suspend"; | |
| spss_etm0_out_funnel_spss = "/soc/spss_etm0/port/endpoint"; | |
| funnel_apss_in_etm4 = "/soc/funnel@7800000/ports/port@5/endpoint"; | |
| pcie0 = "/soc/qcom,pcie@0x1c00000"; | |
| funnel_lpass_1_in_audio_etm0 = "/soc/funnel_1@6845000/ports/port@1/endpoint"; | |
| tpda_in_tpdm_qm = "/soc/tpda@6004000/ports/port@8/endpoint"; | |
| sde_dp = "/soc/qcom,dp_display@0"; | |
| sde_rscc = "/soc/qcom,sde_rscc@af20000"; | |
| qupv3_se14_i2c = "/soc/i2c@a98000"; | |
| funnel_turing_out_tpda = "/soc/funnel@6861000/ports/port@0/endpoint"; | |
| CPU2 = "/cpus/cpu@200"; | |
| dcc = "/soc/dcc_v2@10a2000"; | |
| qupv3_se9_spi_pins = "/soc/pinctrl@03400000/qupv3_se9_spi_pins"; | |
| glink_qos_wdsp = "/soc/qcom,glink-qos-config-wdsp"; | |
| tpda_in_tpdm_prng = "/soc/tpda@6004000/ports/port@7/endpoint"; | |
| bcm_sh5 = "/soc/ad-hoc-bus/bcm-sh5"; | |
| qupv3_se10_spi_sleep = "/soc/pinctrl@03400000/qupv3_se10_spi_pins/qupv3_se10_spi_sleep"; | |
| pri_aux_pcm_clk_active = "/soc/pinctrl@03400000/pri_aux_pcm_clk/pri_aux_pcm_clk_active"; | |
| lrme_iova_mem_map = "/soc/qcom,cam_smmu/msm_cam_smmu_lrme/iova-mem-map"; | |
| key_vol_up_default = "/soc/qcom,spmi@c440000/qcom,pm8998@0/pinctrl@c000/key_vol_up/key_vol_up_default"; | |
| qupv3_se6_4uart = "/soc/qcom,qup_uart@0x898000"; | |
| adsp_tbu = "/soc/apps-smmu@0x15000000/adsp_tbu@0x150dd000"; | |
| L1_TLB_400 = "/cpus/cpu@400/l1-tlb"; | |
| slv_qhs_sdc2 = "/soc/ad-hoc-bus/slv-qhs-sdc2"; | |
| ufs_ice = "/soc/ufsice@1d90000"; | |
| funnel_merg_out_tmc_etf = "/soc/funnel@6045000/ports/port@0/endpoint"; | |
| mas_qnm_cnoc = "/soc/ad-hoc-bus/mas-qnm-cnoc"; | |
| qupv3_se6_rts = "/soc/pinctrl@03400000/qupv3_se6_4uart_pins/qupv3_se6_rts"; | |
| slv_qhs_spdm = "/soc/ad-hoc-bus/slv-qhs-spdm"; | |
| cam_csid0 = "/soc/qcom,csid0@acb3000"; | |
| pil_gpu_mem = "/reserved-memory/gpu_region@0x8c415000"; | |
| pm8998_div_clk3 = "/soc/qcom,spmi@c440000/qcom,pm8998@0/qcom,clkdiv@5d00"; | |
| pm8998_coincell = "/soc/qcom,spmi@c440000/qcom,pm8998@0/qcom,coincell@2800"; | |
| cti4 = "/soc/cti@6014000"; | |
| mas_qnm_mnoc_sf = "/soc/ad-hoc-bus/mas-qnm-mnoc-sf"; | |
| qupv3_se8_spi_sleep = "/soc/pinctrl@03400000/qupv3_se8_spi_pins/qupv3_se8_spi_sleep"; | |
| tpda_spss_in_tpdm_spss = "/soc/tpda@6882000/ports/port@1/endpoint"; | |
| hlos1_vote_aggre_noc_mmu_tbu2_gdsc = "/soc/qcom,gdsc@0x17d038"; | |
| qupv3_se2_i2c_active = "/soc/pinctrl@03400000/qupv3_se2_i2c_pins/qupv3_se2_i2c_active"; | |
| qupv3_se7_i2c_active = "/soc/pinctrl@03400000/qupv3_se7_i2c_pins/qupv3_se7_i2c_active"; | |
| pm8998_l10 = "/soc/rpmh-regulator-ldoa10/regulator-l10"; | |
| etm7_out_funnel_apss = "/soc/etm@7740000/port/endpoint"; | |
| titan_top_gdsc = "/soc/qcom,gdsc@0xad0b134"; | |
| bcm_mm0_display = "/soc/ad-hoc-bus/bcm-mm0_display"; | |
| jtag_mm1 = "/soc/jtagmm@7140000"; | |
| smp2pgpio_ssr_smp2p_5_in = "/soc/qcom,smp2pgpio-ssr-smp2p-5-in"; | |
| wcd_usbc_analog_en2_active = "/soc/pinctrl@03400000/wcd_usbc_analog_en2/wcd_usbc_ana_en2_active"; | |
| funnel_lpass_1_out_funnel_qatb = "/soc/funnel_1@6845000/ports/port@0/endpoint"; | |
| bwmon = "/soc/qcom,cpu-bwmon"; | |
| funnel_qatb_out_funnel_in0 = "/soc/funnel@6005000/ports/port@0/endpoint"; | |
| bcm_sn1 = "/soc/ad-hoc-bus/bcm-sn1"; | |
| qupv3_se2_spi_active = "/soc/pinctrl@03400000/qupv3_se2_spi_pins/qupv3_se2_spi_active"; | |
| qupv3_se7_spi_active = "/soc/pinctrl@03400000/qupv3_se7_spi_pins/qupv3_se7_spi_active"; | |
| qupv3_se10_i2c_active = "/soc/pinctrl@03400000/qupv3_se10_i2c_pins/qupv3_se10_i2c_active"; | |
| qupv3_se15_i2c_active = "/soc/pinctrl@03400000/qupv3_se15_i2c_pins/qupv3_se15_i2c_active"; | |
| funnel_apss_merg_in_tpda_apss = "/soc/funnel@7810000/ports/port@3/endpoint"; | |
| mas_pm_gnoc_cfg = "/soc/ad-hoc-bus/mas-pm-gnoc-cfg"; | |
| pil_ipa_gsi_mem = "/reserved-memory/ipa_gsi_region@0x8c410000"; | |
| smp2pgpio_rdbg_1_out = "/soc/qcom,smp2pgpio-rdbg-1-out"; | |
| slv_qns_pcie_snoc = "/soc/ad-hoc-bus/slv-qns-pcie-snoc"; | |
| mnoc_hf_0_tbu = "/soc/apps-smmu@0x15000000/mnoc_hf_0_tbu@0x150cd000"; | |
| slv_ebi_display = "/soc/ad-hoc-bus/slv-ebi_display"; | |
| icp_iova_mem_map = "/soc/qcom,cam_smmu/msm_cam_smmu_icp/iova-mem-map"; | |
| nfc_int_active = "/soc/pinctrl@03400000/nfc/nfc_int_active"; | |
| emerg_config0 = "/soc/thermal-zones/cpu0-silver-step/trips/emerg-config0"; | |
| tert_mi2s_mclk_active = "/soc/pinctrl@03400000/tert_mi2s_mclk/tert_mi2s_mclk_active"; | |
| replicator_qdss = "/soc/replicator@6046000"; | |
| qupv3_se10_spi_active = "/soc/pinctrl@03400000/qupv3_se10_spi_pins/qupv3_se10_spi_active"; | |
| qupv3_se15_spi_active = "/soc/pinctrl@03400000/qupv3_se15_spi_pins/qupv3_se15_spi_active"; | |
| slv_qhs_pdm = "/soc/ad-hoc-bus/slv-qhs-pdm"; | |
| funnel_qatb_in_funnel_turing_1 = "/soc/funnel@6005000/ports/port@3/endpoint"; | |
| slv_srvc_mnoc = "/soc/ad-hoc-bus/slv-srvc-mnoc"; | |
| pm8998_l6 = "/soc/rpmh-regulator-ldoa6/regulator-l6"; | |
| smp2pgpio_ssr_smp2p_2_in = "/soc/qcom,smp2pgpio-ssr-smp2p-2-in"; | |
| tpdm_prng_out_tpda = "/soc/tpdm@684c000/port/endpoint"; | |
| cam_ipe1 = "/soc/qcom,ipe1"; | |
| cti13 = "/soc/cti@601d000"; | |
| flash_led3_iris_dis = "/soc/pinctrl@03400000/flash_led3_iris/flash_led3_iris_dis"; | |
| sb_7_tx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-7-tx"; | |
| routing = "/soc/qcom,msm-pcm-routing"; | |
| mas_qhm_a2noc_cfg = "/soc/ad-hoc-bus/mas-qhm-a2noc-cfg"; | |
| slv_qhs_ipa = "/soc/ad-hoc-bus/slv-qhs-ipa"; | |
| slv_qhs_aoss = "/soc/ad-hoc-bus/slv-qhs-aoss"; | |
| qupv3_se5_i2c_sleep = "/soc/pinctrl@03400000/qupv3_se5_i2c_pins/qupv3_se5_i2c_sleep"; | |
| tpda_modem_in_tpdm_modem = "/soc/tpda@6831000/ports/port@1/endpoint"; | |
| slv_qns_mem_noc_hf = "/soc/ad-hoc-bus/slv-qns-mem-noc-hf"; | |
| sdc2_clk_ds_400KHz = "/soc/pinctrl@03400000/sdc2_clk_ds_400KHz"; | |
| tert_mi2s_sd0_sleep = "/soc/pinctrl@03400000/tert_mi2s_sd0/tert_mi2s_sd0_sleep"; | |
| tpdm_pimem = "/soc/tpdm@6850000"; | |
| tpdm_turing_out_funnel_turing = "/soc/tpdm@6860000/port/endpoint"; | |
| funnel_ddr_0 = "/soc/funnel@69e2000"; | |
| pmi8998_bob = "/soc/rpmh-regulator-bobb1/regulator-bob"; | |
| kgsl_smmu = "/soc/arm,smmu-kgsl@5040000"; | |
| l3_cdsp = "/soc/qcom,l3-cdsp"; | |
| sb_4_tx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-4-tx"; | |
| camera_trip = "/soc/thermal-zones/camera-lowf/trips/camera-trip"; | |
| L1_I_200 = "/cpus/cpu@200/l1-icache"; | |
| bcm_qup0 = "/soc/ad-hoc-bus/bcm-qup0"; | |
| quat_aux_pcm_active = "/soc/pinctrl@03400000/quat_aux_pcm/quat_aux_pcm_active"; | |
| smp2pgpio_rdbg_5_out = "/soc/qcom,smp2pgpio-rdbg-5-out"; | |
| bps_gdsc = "/soc/qcom,gdsc@0xad06004"; | |
| L2_600 = "/cpus/cpu@600/l2-cache"; | |
| pm8998_l4_level = "/soc/rpmh-regulator-lmxlvl/regulator-l4-level"; | |
| sensor_etm0_out_funnel_swao = "/soc/sensor_etm0/port/endpoint"; | |
| qupv3_se8_i2c_pins = "/soc/pinctrl@03400000/qupv3_se8_i2c_pins"; | |
| funnel_in2_in_funnel_modem = "/soc/funnel@0x6043000/ports/port@3/endpoint"; | |
| gpu_trip0 = "/soc/thermal-zones/gpu-virt-max-step/trips/gpu-trip0"; | |
| key_cam_focus_default = "/soc/qcom,spmi@c440000/qcom,pm8998@0/pinctrl@c000/key_cam_focus/key_cam_focus_default"; | |
| cam_sensor_rear_vana = "/soc/pinctrl@03400000/cam_sensor_rear_vana"; | |
| mas_qnm_snoc_sf = "/soc/ad-hoc-bus/mas-qnm-snoc-sf"; | |
| L1_D_100 = "/cpus/cpu@100/l1-dcache"; | |
| fab_aggre1_noc = "/soc/ad-hoc-bus/fab-aggre1_noc"; | |
| qupv3_se6_spi_pins = "/soc/pinctrl@03400000/qupv3_se6_spi_pins"; | |
| funnel_turing_1 = "/soc/funnel_1@6861000"; | |
| tpdm_spss_out_tpda_spss = "/soc/tpdm@6880000/port/endpoint"; | |
| l3_0_trip = "/soc/thermal-zones/kryo-l3-0-lowf/trips/l3-0-trip"; | |
| slv_srvc_gnoc = "/soc/ad-hoc-bus/slv-srvc-gnoc"; | |
| cam_res_mgr_active = "/soc/pinctrl@03400000/cam_res_mgr_active"; | |
| bcm_mm1 = "/soc/ad-hoc-bus/bcm-mm1"; | |
| tmc_etf = "/soc/tmc@6047000"; | |
| nfc_enable_suspend = "/soc/pinctrl@03400000/nfc/nfc_enable_suspend"; | |
| lsm = "/soc/qcom,msm-lsm-client"; | |
| gpu0_trip_l = "/soc/thermal-zones/gpu0-lowf/trips/gpu0-trip"; | |
| eud = "/soc/qcom,msm-eud@88e0000"; | |
| sb_1_tx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-1-tx"; | |
| compress = "/soc/qcom,msm-compress-dsp"; | |
| mas_acm_tcu = "/soc/ad-hoc-bus/mas-acm-tcu"; | |
| mas_qhm_snoc_cfg = "/soc/ad-hoc-bus/mas-qhm-snoc-cfg"; | |
| cti_cpu5 = "/soc/cti@7520000"; | |
| sdc2_clk_off = "/soc/pinctrl@03400000/sdc2_clk_off"; | |
| pm8998_l19 = "/soc/rpmh-regulator-ldoa19/regulator-l19"; | |
| quat_mi2s_sd3_active = "/soc/pinctrl@03400000/quat_mi2s_sd3/quat_mi2s_sd3_active"; | |
| glink_mpss = "/soc/qcom,glink-ssr-modem"; | |
| qupv3_se15_i2c_sleep = "/soc/pinctrl@03400000/qupv3_se15_i2c_pins/qupv3_se15_i2c_sleep"; | |
| qseecom_ta_mem = "/reserved-memory/qseecom_ta_region"; | |
| tert_mi2s_mclk_sleep = "/soc/pinctrl@03400000/tert_mi2s_mclk/tert_mi2s_mclk_sleep"; | |
| funnel_apss_in_etm2 = "/soc/funnel@7800000/ports/port@3/endpoint"; | |
| CPU0 = "/cpus/cpu@0"; | |
| tpda_swao_in_tpdm_swao0 = "/soc/tpda@6b01000/ports/port@1/endpoint"; | |
| funnel_in2_out_funnel_merg = "/soc/funnel@0x6043000/ports/port@0/endpoint"; | |
| refgen = "/soc/refgen-regulator@ff1000"; | |
| bcm_sh3 = "/soc/ad-hoc-bus/bcm-sh3"; | |
| L1_TLB_700 = "/cpus/cpu@700/l1-tlb"; | |
| qupv3_se1_i2c = "/soc/i2c@884000"; | |
| sb_7_rx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-7-rx"; | |
| tsif0_signals_active = "/soc/pinctrl@03400000/tsif0_signals_active"; | |
| tpdm_modem_out_tpda_modem = "/soc/tpdm@6830000/port/endpoint"; | |
| tpda_apss = "/soc/tpda@7862000"; | |
| replicator_swao_in_tmc_etf_swao = "/soc/replicator@6b0a000/ports/port@0/endpoint"; | |
| pil_camera_mem = "/reserved-memory/camera_region@0x8bf00000"; | |
| slv_qns_memnoc_sf = "/soc/ad-hoc-bus/slv-qns-memnoc-sf"; | |
| tpdm_vsense_out_tpda = "/soc/tpdm@6840000/port/endpoint"; | |
| wdog = "/soc/qcom,wdt@17980000"; | |
| qupv3_se3_spi_sleep = "/soc/pinctrl@03400000/qupv3_se3_spi_pins/qupv3_se3_spi_sleep"; | |
| cam_sensor_mclk2_active = "/soc/pinctrl@03400000/cam_sensor_mclk2_active"; | |
| mas_qnm_mnoc_hf_display = "/soc/ad-hoc-bus/mas-qnm-mnoc-hf_display"; | |
| pri_mi2s_sd0_active = "/soc/pinctrl@03400000/pri_mi2s_sd0/pri_mi2s_sd0_active"; | |
| pm8998_div_clk1 = "/soc/qcom,spmi@c440000/qcom,pm8998@0/qcom,clkdiv@5b00"; | |
| cti2 = "/soc/cti@6012000"; | |
| cam_sensor_front_active = "/soc/pinctrl@03400000/cam_sensor_front_active"; | |
| qupv3_se10_2uart = "/soc/qcom,qup_uart@0xa88000"; | |
| cti1_ddr1 = "/soc/cti@69e5000"; | |
| qupv3_se3_spi = "/soc/spi@88c000"; | |
| sde_te_suspend = "/soc/pinctrl@03400000/pmx_sde_te/sde_te_suspend"; | |
| pdc = "/soc/interrupt-controller@0xb220000"; | |
| sb_4_rx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-4-rx"; | |
| pri_mi2s_sck_sleep = "/soc/pinctrl@03400000/pri_mi2s_sck/pri_mi2s_sck_sleep"; | |
| sec_mi2s_sd0_sleep = "/soc/pinctrl@03400000/sec_mi2s_sd0/sec_mi2s_sd0_sleep"; | |
| tpdm_olc_out_tpda_olc = "/soc/tpdm@7830000/port/endpoint"; | |
| gpu_gx_sw_reset = "/soc/syscon@0x5091008"; | |
| mas_qxm_venus0 = "/soc/ad-hoc-bus/mas-qxm-venus0"; | |
| sdc2_cmd_off = "/soc/pinctrl@03400000/sdc2_cmd_off"; | |
| smp2pgpio_wlan_1_in = "/soc/qcom,smp2pgpio-wlan-1-in"; | |
| slv_qhs_ddrss_cfg = "/soc/ad-hoc-bus/slv-qhs-ddrss-cfg"; | |
| mas_xm_pcie3_1 = "/soc/ad-hoc-bus/mas-xm-pcie3-1"; | |
| etm6 = "/soc/etm@7640000"; | |
| qusb_phy1 = "/soc/qusb@88e3000"; | |
| ufs_card_gdsc = "/soc/qcom,gdsc@0x175004"; | |
| qupv3_se5_i2c = "/soc/i2c@894000"; | |
| funnel_apss_merg_in_funnel_apss = "/soc/funnel@7810000/ports/port@1/endpoint"; | |
| qcom_msmhdcp = "/soc/qcom,msm_hdcp"; | |
| smp2pgpio_smp2p_3_in = "/soc/qcom,smp2pgpio-smp2p-3-in"; | |
| qupv3_se15_spi_pins = "/soc/pinctrl@03400000/qupv3_se15_spi_pins"; | |
| cci0_active = "/soc/pinctrl@03400000/cci0_active"; | |
| cti11 = "/soc/cti@601b000"; | |
| sb_1_rx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-1-rx"; | |
| cam_jpeg_enc = "/soc/qcom,jpegenc@ac4e000"; | |
| wil6210 = "/soc/qcom,cpucc@0x17d41000/qcom,wil6210"; | |
| incall_record_tx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-incall-record-tx"; | |
| cam_vfe0 = "/soc/qcom,vfe0@acaf000"; | |
| afe_pcm_tx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-be-afe-pcm-tx"; | |
| qupv3_se0_i2c_sleep = "/soc/pinctrl@03400000/qupv3_se0_i2c_pins/qupv3_se0_i2c_sleep"; | |
| tsif0_sync_active = "/soc/pinctrl@03400000/tsif0_sync_active"; | |
| mas_qhm_qup1 = "/soc/ad-hoc-bus/mas-qhm-qup1"; | |
| qupv3_se13_spi_sleep = "/soc/pinctrl@03400000/qupv3_se13_spi_pins/qupv3_se13_spi_sleep"; | |
| slv_qhs_qupv3_south = "/soc/ad-hoc-bus/slv-qhs-qupv3-south"; | |
| incall_music_2_rx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-incall-music-2-rx"; | |
| pm8998_rtc = "/soc/qcom,spmi@c440000/qcom,pm8998@0/qcom,pm8998_rtc"; | |
| pcie0_3v3_on = "/soc/pinctrl@03400000/pcie0/pcie0_3v3_on"; | |
| atest_usb13_active = "/soc/pinctrl@03400000/atest_usb13/atest_usb13_active"; | |
| qupv3_se5_i2c_pins = "/soc/pinctrl@03400000/qupv3_se5_i2c_pins"; | |
| sdc2_cmd_ds_50MHz = "/soc/pinctrl@03400000/sdc2_cmd_ds_50MHz"; | |
| funnel_in2 = "/soc/funnel@0x6043000"; | |
| qupv3_se7_spi = "/soc/spi@89c000"; | |
| mas_xm_qdss_etr = "/soc/ad-hoc-bus/mas-xm-qdss-etr"; | |
| qupv3_se3_spi_pins = "/soc/pinctrl@03400000/qupv3_se3_spi_pins"; | |
| L1_I_500 = "/cpus/cpu@500/l1-icache"; | |
| slv_qhs_pcie_gen3_cfg = "/soc/ad-hoc-bus/slv-qhs-pcie-gen3-cfg"; | |
| ufs_phy_gdsc = "/soc/qcom,gdsc@0x177004"; | |
| gpi_dma1 = "/soc/qcom,gpi-dma@0xa00000"; | |
| thermal_zones = "/soc/thermal-zones"; | |
| ap2mdm_active = "/soc/pinctrl@03400000/ap2mdm/ap2mdm_active"; | |
| cmd_db = "/soc/qcom,cmd-db@861e0000"; | |
| vcodec1_gdsc = "/soc/qcom,gdsc@0xab008b4"; | |
| ts_reset_active = "/soc/pinctrl@03400000/pmx_ts_reset_active/ts_reset_active"; | |
| pcie0_clkreq_default = "/soc/pinctrl@03400000/pcie0/pcie0_clkreq_default"; | |
| funnel_modem = "/soc/funnel@6832000"; | |
| L1_D_400 = "/cpus/cpu@400/l1-dcache"; | |
| tpdm_lpass = "/soc/tpdm@6844000"; | |
| funnel_apss_merg_in_tpda_llm_gold = "/soc/funnel@7810000/ports/port@5/endpoint"; | |
| ts_int_output_low = "/soc/pinctrl@03400000/ts_int_output_low"; | |
| bcm_sn11 = "/soc/ad-hoc-bus/bcm-sn11"; | |
| hlos1_vote_aggre_noc_mmu_tbu1_gdsc = "/soc/qcom,gdsc@0x17d034"; | |
| qupv3_se9_i2c = "/soc/i2c@a84000"; | |
| mas_xm_pcie_0 = "/soc/ad-hoc-bus/mas-xm-pcie-0"; | |
| L1_TLB_0 = "/cpus/cpu@0/l1-tlb"; | |
| smp2pgpio_smp2p_1_out = "/soc/qcom,smp2pgpio-smp2p-1-out"; | |
| wcd_usbc_analog_en1_active = "/soc/pinctrl@03400000/wcd_usbc_analog_en1/wcd_usbc_ana_en1_active"; | |
| devfreq_memlat_0 = "/soc/qcom,cpu0-memlat-mon"; | |
| qupv3_se10_i2c_sleep = "/soc/pinctrl@03400000/qupv3_se10_i2c_pins/qupv3_se10_i2c_sleep"; | |
| nfc_enable_active = "/soc/pinctrl@03400000/nfc/nfc_enable_active"; | |
| cti_cpu3 = "/soc/cti@7320000"; | |
| slv_qhs_clk_ctl = "/soc/ad-hoc-bus/slv-qhs-clk-ctl"; | |
| pm8998_l17 = "/soc/rpmh-regulator-ldoa17/regulator-l17"; | |
| funnel_apss_in_etm0 = "/soc/funnel@7800000/ports/port@1/endpoint"; | |
| cti0_swao = "/soc/cti@6b04000"; | |
| cam_sensor_rear_suspend = "/soc/pinctrl@03400000/cam_sensor_rear_suspend"; | |
| bcm_sn8 = "/soc/ad-hoc-bus/bcm-sn8"; | |
| bcm_sh1 = "/soc/ad-hoc-bus/bcm-sh1"; | |
| spkr_i2s_clk_active = "/soc/pinctrl@03400000/spkr_i2s_clk_pin/spkr_i2s_clk_active"; | |
| tpdm_swao0_out_tpda_swao = "/soc/tpdm@6b02000/port/endpoint"; | |
| quat_tdm_din_active = "/soc/pinctrl@03400000/quat_tdm_din/quat_tdm_din_active"; | |
| etm0_out_funnel_apss = "/soc/etm@7040000/port/endpoint"; | |
| mdss_dsi_phy1 = "/soc/qcom,mdss_dsi_phy0@ae96400"; | |
| tpdm_llm_silver = "/soc/tpdm@78a0000"; | |
| tpdm_prng = "/soc/tpdm@684c000"; | |
| incall_record_rx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-incall-record-rx"; | |
| slv_qns_pcie_a1noc_snoc = "/soc/ad-hoc-bus/slv-qns-pcie-a1noc-snoc"; | |
| funnel_swao = "/soc/funnel@0x6b08000"; | |
| bcm_ip0 = "/soc/ad-hoc-bus/bcm-ip0"; | |
| qupv3_se8_i2c_sleep = "/soc/pinctrl@03400000/qupv3_se8_i2c_pins/qupv3_se8_i2c_sleep"; | |
| afe_pcm_rx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-be-afe-pcm-rx"; | |
| sec_mi2s_sd1_active = "/soc/pinctrl@03400000/sec_mi2s_sd1/sec_mi2s_sd1_active"; | |
| emerg_config7 = "/soc/thermal-zones/cpu3-gold-step/trips/emerg-config7"; | |
| smp2pgpio_sleepstate_3_out = "/soc/qcom,smp2pgpio-sleepstate-gpio-3-out"; | |
| mas_qhm_a1noc_cfg = "/soc/ad-hoc-bus/mas-qhm-a1noc-cfg"; | |
| i2c_freq_400Khz = "/soc/qcom,cci@ac4a000/qcom,i2c_fast_mode"; | |
| rsc_disp = "/soc/ad-hoc-bus/rsc-disp"; | |
| cti0 = "/soc/cti@6010000"; | |
| qupv3_se14_i2c_pins = "/soc/pinctrl@03400000/qupv3_se14_i2c_pins"; | |
| mas_qhm_spdm = "/soc/ad-hoc-bus/mas-qhm-spdm"; | |
| glink_spi_xprt_wdsp = "/soc/qcom,glink-spi-xprt-wdsp"; | |
| smp2pgpio_smp2p_5_out = "/soc/qcom,smp2pgpio-smp2p-5-out"; | |
| llcc = "/soc/qcom,llcc@1100000/qcom,sdm845-llcc"; | |
| pm8998_lvs1 = "/soc/rpmh-regulator-vsa1/regulator-lvs1"; | |
| wlan_trip = "/soc/thermal-zones/wlan-lowf/trips/wlan-trip"; | |
| qupv3_se12_spi_pins = "/soc/pinctrl@03400000/qupv3_se12_spi_pins"; | |
| tpdm_vsense = "/soc/tpdm@6840000"; | |
| slv_qhs_mdsp_ms_mpu_cfg = "/soc/ad-hoc-bus/slv-qhs-mdsp-ms-mpu-cfg"; | |
| i2c_freq_custom = "/soc/qcom,cci@ac4a000/qcom,i2c_custom_mode"; | |
| mas_xm_usb3_1 = "/soc/ad-hoc-bus/mas-xm-usb3-1"; | |
| qupv3_se3_i2c_active = "/soc/pinctrl@03400000/qupv3_se3_i2c_pins/qupv3_se3_i2c_active"; | |
| qupv3_se8_i2c_active = "/soc/pinctrl@03400000/qupv3_se8_i2c_pins/qupv3_se8_i2c_active"; | |
| pcm_noirq = "/soc/qcom,msm-pcm-dsp-noirq"; | |
| qupv3_se11_i2c = "/soc/i2c@a8c000"; | |
| hwevent = "/soc/hwevent@0x014066f0"; | |
| hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc = "/soc/qcom,gdsc@0x17d03c"; | |
| pri_aux_pcm_dout_active = "/soc/pinctrl@03400000/pri_aux_pcm_dout/pri_aux_pcm_dout_active"; | |
| fab_mmss_noc_display = "/soc/ad-hoc-bus/fab-mmss_noc_display"; | |
| etm4 = "/soc/etm@7440000"; | |
| pcm1 = "/soc/qcom,msm-pcm-low-latency"; | |
| qupv3_se2_i2c_pins = "/soc/pinctrl@03400000/qupv3_se2_i2c_pins"; | |
| qupv3_se3_spi_active = "/soc/pinctrl@03400000/qupv3_se3_spi_pins/qupv3_se3_spi_active"; | |
| qupv3_se8_spi_active = "/soc/pinctrl@03400000/qupv3_se8_spi_pins/qupv3_se8_spi_active"; | |
| qupv3_se11_i2c_active = "/soc/pinctrl@03400000/qupv3_se11_i2c_pins/qupv3_se11_i2c_active"; | |
| quat_mi2s_sd0_sleep = "/soc/pinctrl@03400000/quat_mi2s_sd0/quat_mi2s_sd0_sleep"; | |
| dai_sec_auxpcm = "/soc/qcom,msm-sec-auxpcm"; | |
| msm_vidc = "/soc/qcom,vidc@aa00000"; | |
| dsp_trip = "/soc/thermal-zones/mdm-dsp-lowf/trips/dsp-trip"; | |
| replicator_swao = "/soc/replicator@6b0a000"; | |
| msm_gpu = "/soc/qcom,kgsl-3d0@5000000"; | |
| funnel_ddr_0_out_tpda = "/soc/funnel@69e2000/ports/port@0/endpoint"; | |
| qupv3_se0_spi_pins = "/soc/pinctrl@03400000/qupv3_se0_spi_pins"; | |
| dai_quin_tdm_rx_0 = "/soc/qcom,msm-dai-tdm-quin-rx/qcom,msm-dai-q6-tdm-quin-rx-0"; | |
| pm8998_l2 = "/soc/rpmh-regulator-ldoa2/regulator-l2"; | |
| hdmi_det_active = "/soc/pinctrl@03400000/hdmidet_active/hdmi_det_active"; | |
| slv_xs_qdss_stm = "/soc/ad-hoc-bus/slv-xs-qdss-stm"; | |
| dai_quat_tdm_tx_0 = "/soc/qcom,msm-dai-tdm-quat-tx/qcom,msm-dai-q6-tdm-quat-tx-0"; | |
| funnel_gfx = "/soc/funnel@0x6943000"; | |
| qupv3_se11_spi_active = "/soc/pinctrl@03400000/qupv3_se11_spi_pins/qupv3_se11_spi_active"; | |
| adsp_mem = "/reserved-memory/adsp_region"; | |
| pmx_sde = "/soc/pinctrl@03400000/pmx_sde"; | |
| slv_ebi = "/soc/ad-hoc-bus/slv-ebi"; | |
| qupv3_se13_spi = "/soc/spi@a94000"; | |
| usb30_sec_gdsc = "/soc/qcom,gdsc@0x110004"; | |
| pm8998_s6_level = "/soc/rpmh-regulator-mxlvl/regulator-s6-level"; | |
| quat_mi2s_sd2_active = "/soc/pinctrl@03400000/quat_mi2s_sd2/quat_mi2s_sd2_active"; | |
| tspp = "/soc/msm_tspp@0x8880000"; | |
| tpdm_llm_gold = "/soc/tpdm@78b0000"; | |
| afe_proxy_tx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-afe-proxy-tx"; | |
| pm8998_gpios = "/soc/qcom,spmi@c440000/qcom,pm8998@0/pinctrl@c000"; | |
| mas_qxm_mdp0 = "/soc/ad-hoc-bus/mas-qxm-mdp0"; | |
| tpda_llm_silver_out_funnel_apss_merg = "/soc/tpda@78c0000/ports/port@0/endpoint"; | |
| slv_qhs_cpr_cx = "/soc/ad-hoc-bus/slv-qhs-cpr-cx"; | |
| funnel_in0 = "/soc/funnel@0x6041000"; | |
| slv_qns_memnoc_snoc = "/soc/ad-hoc-bus/slv-qns-memnoc-snoc"; | |
| funnel_dl_mm_out_tpda = "/soc/funnel@6c0b000/ports/port@0/endpoint"; | |
| pm8998_l25 = "/soc/rpmh-regulator-ldoa25/regulator-l25"; | |
| L1_D_700 = "/cpus/cpu@700/l1-dcache"; | |
| tert_aux_pcm_din_sleep = "/soc/pinctrl@03400000/tert_aux_pcm_din/tert_aux_pcm_din_sleep"; | |
| qupv3_se6_spi_sleep = "/soc/pinctrl@03400000/qupv3_se6_spi_pins/qupv3_se6_spi_sleep"; | |
| mas_qxm_mdp1_display = "/soc/ad-hoc-bus/mas-qxm-mdp1_display"; | |
| aoss1_trip = "/soc/thermal-zones/aoss1-lowf/trips/aoss1-trip"; | |
| slv_qhs_aop = "/soc/ad-hoc-bus/slv-qhs-aop"; | |
| dai_sec_tdm_rx_0 = "/soc/qcom,msm-dai-tdm-sec-rx/qcom,msm-dai-q6-tdm-sec-rx-0"; | |
| qupv3_se15_i2c = "/soc/i2c@a9c000"; | |
| adsp_vdd = "/soc/qmi-tmd-devices/adsp/adsp_vdd"; | |
| tert_aux_pcm_dout_sleep = "/soc/pinctrl@03400000/tert_aux_pcm_dout/tert_aux_pcm_dout_sleep"; | |
| smp2pgpio_rdbg_1_in = "/soc/qcom,smp2pgpio-rdbg-1-in"; | |
| CPU7 = "/cpus/cpu@700"; | |
| snd_934x = "/soc/qcom,msm-audio-apr/sound-tavil"; | |
| qmp_aop = "/soc/qcom,qmp-aop@c300000"; | |
| wlan_fw_region = "/reserved-memory/wlan_fw_region@0x8df00000"; | |
| sde_dsi1_suspend = "/soc/pinctrl@03400000/sde_dsi1_suspend"; | |
| etm3_out_funnel_apss = "/soc/etm@7340000/port/endpoint"; | |
| slv_qhs_ufs_mem_cfg = "/soc/ad-hoc-bus/slv-qhs-ufs-mem-cfg"; | |
| tpdm_center_out_tpda = "/soc/tpdm@6c28000/port/endpoint"; | |
| cam_sensor_mclk1_active = "/soc/pinctrl@03400000/cam_sensor_mclk1_active"; | |
| sde_dp_aux_active = "/soc/pinctrl@03400000/sde_dp_aux_active"; | |
| quat_tdm_active = "/soc/pinctrl@03400000/quat_tdm/quat_tdm_active"; | |
| funnel_modem_in_tpda_modem = "/soc/funnel@6832000/ports/port@1/endpoint"; | |
| cti0_ddr1 = "/soc/cti@69e4000"; | |
| ts_int_default = "/soc/pinctrl@03400000/ts_int_defalut"; | |
| cdc_reset_active = "/soc/pinctrl@03400000/cdc_reset_ctrl/cdc_reset_active"; | |
| iommu_qupv3_0_geni_se_cb = "/soc/qcom,qupv3_0_geni_se@8c0000/qcom,iommu_qupv3_0_geni_se_cb"; | |
| ts_reset_suspend1 = "/soc/pinctrl@03400000/pmx_ts_reset_suspend/ts_reset_suspend1"; | |
| qupv3_se7_4uart_active = "/soc/pinctrl@03400000/qupv3_se7_4uart_pins/qupv3_se7_4uart_active"; | |
| fab_mem_noc = "/soc/ad-hoc-bus/fab-mem_noc"; | |
| slv_xs_sys_tcu_cfg = "/soc/ad-hoc-bus/slv-xs-sys-tcu-cfg"; | |
| sde_te_active = "/soc/pinctrl@03400000/pmx_sde_te/sde_te_active"; | |
| cti9 = "/soc/cti@6019000"; | |
| quat_mi2s_sd3_sleep = "/soc/pinctrl@03400000/quat_mi2s_sd3/quat_mi2s_sd3_sleep"; | |
| qupv3_se9_2uart_active = "/soc/pinctrl@03400000/qupv3_se9_2uart_pins/qupv3_se9_2uart_active"; | |
| cam_csiphy2 = "/soc/qcom,csiphy@ac67000"; | |
| L2_0 = "/cpus/cpu@0/l2-cache"; | |
| sdc2_cmd_ds_200MHz = "/soc/pinctrl@03400000/sdc2_cmd_ds_200MHz"; | |
| audio_etm0_out_funnel_lpass_1 = "/soc/audio_etm0/port/endpoint"; | |
| cti_cpu1 = "/soc/cti@7120000"; | |
| pm8998_l15 = "/soc/rpmh-regulator-ldoa15/regulator-l15"; | |
| mas_qnm_pcie_anoc = "/soc/ad-hoc-bus/mas-qnm-pcie-anoc"; | |
| mas_alc = "/soc/ad-hoc-bus/mas-alc"; | |
| jtag_mm6 = "/soc/jtagmm@7640000"; | |
| cam_sensor_mclk2_suspend = "/soc/pinctrl@03400000/cam_sensor_mclk2_suspend"; | |
| L2_200 = "/cpus/cpu@200/l2-cache"; | |
| wcd_intr_default = "/soc/pinctrl@03400000/wcd9xxx_intr/wcd_intr_default"; | |
| bcm_sn6 = "/soc/ad-hoc-bus/bcm-sn6"; | |
| qupv3_se11_i2c_pins = "/soc/pinctrl@03400000/qupv3_se11_i2c_pins"; | |
| spkr_i2s_clk_sleep = "/soc/pinctrl@03400000/spkr_i2s_clk_pin/spkr_i2s_clk_sleep"; | |
| qupv3_se3_i2c_sleep = "/soc/pinctrl@03400000/qupv3_se3_i2c_pins/qupv3_se3_i2c_sleep"; | |
| pm8998_s9_level = "/soc/rpmh-regulator-cxlvl/regulator-s9-level"; | |
| smp2pgpio_rdbg_2_out = "/soc/qcom,smp2pgpio-rdbg-2-out"; | |
| proxy_tx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-proxy-tx"; | |
| led_bt_default = "/soc/qcom,spmi@c440000/qcom,pm8998@0/pinctrl@c000/led_bt/led_bt_default"; | |
| mnoc_hf_1_tbu = "/soc/apps-smmu@0x15000000/mnoc_hf_1_tbu@0x150d1000"; | |
| slv_qhs_mnoc_cfg = "/soc/ad-hoc-bus/slv-qhs-mnoc-cfg"; | |
| tpdm_mm_out_funnel_dl_mm = "/soc/tpdm@6c08000/port/endpoint"; | |
| cdc_reset_sleep = "/soc/pinctrl@03400000/cdc_reset_ctrl/cdc_reset_sleep"; | |
| qupv3_se7_4uart_sleep = "/soc/pinctrl@03400000/qupv3_se7_4uart_pins/qupv3_se7_4uart_sleep"; | |
| emerg_config5 = "/soc/thermal-zones/cpu1-gold-step/trips/emerg-config5"; | |
| storage_cd = "/soc/pinctrl@03400000/storage_cd"; | |
| apps_smmu = "/soc/apps-smmu@0x15000000"; | |
| mas_qnm_snoc = "/soc/ad-hoc-bus/mas-qnm-snoc"; | |
| fab_config_noc = "/soc/ad-hoc-bus/fab-config_noc"; | |
| funnel_apss_merg_out_funnel_in2 = "/soc/funnel@7810000/ports/port@0/endpoint"; | |
| cam_sensor_depth_active = "/soc/pinctrl@03400000/cam_sensor_depth_active"; | |
| afe_proxy_rx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-afe-proxy-rx"; | |
| dai_pri_tdm_rx_0 = "/soc/qcom,msm-dai-tdm-pri-rx/qcom,msm-dai-q6-tdm-pri-rx-0"; | |
| funnel_in0_in_funnel_qatb = "/soc/funnel@0x6041000/ports/port@2/endpoint"; | |
| tpdm_apss = "/soc/tpdm@7860000"; | |
| max_6dof_active = "/soc/pinctrl@03400000/max_6dof_active"; | |
| modem_proc = "/soc/qmi-tmd-devices/modem/modem_proc"; | |
| pil_gpu = "/soc/qcom,kgsl-hyp"; | |
| clock_dispcc = "/soc/qcom,dispcc@af00000"; | |
| slv_qhs_camera_cfg = "/soc/ad-hoc-bus/slv-qhs-camera-cfg"; | |
| slv_srvc_aggre1_noc = "/soc/ad-hoc-bus/slv-srvc-aggre1-noc"; | |
| ife_iova_mem_map = "/soc/qcom,cam_smmu/msm_cam_smmu_ife/iova-mem-map"; | |
| loopback = "/soc/qcom,msm-pcm-loopback"; | |
| vcodec0_gdsc = "/soc/qcom,gdsc@0xab00874"; | |
| usb0 = "/soc/ssusb@a600000"; | |
| tpdm_qm = "/soc/tpdm@69d0000"; | |
| L1_TLB_300 = "/cpus/cpu@300/l1-tlb"; | |
| slv_qhs_spss_cfg = "/soc/ad-hoc-bus/slv-qhs-spss-cfg"; | |
| cam_sensor_front_suspend = "/soc/pinctrl@03400000/cam_sensor_front_suspend"; | |
| pcie0_perst_default = "/soc/pinctrl@03400000/pcie0/pcie0_perst_default"; | |
| qupv3_se9_2uart_pins = "/soc/pinctrl@03400000/qupv3_se9_2uart_pins"; | |
| etm2 = "/soc/etm@7240000"; | |
| bcm_mm1_display = "/soc/ad-hoc-bus/bcm-mm1_display"; | |
| glink_dsps = "/soc/qcom,glink-ssr-dsps"; | |
| funnel_turing_in_tpdm_turing = "/soc/funnel@6861000/ports/port@1/endpoint"; | |
| cpu3_trip = "/soc/thermal-zones/cpu3-silver-lowf/trips/cpu3-trip"; | |
| disp_rsc = "/soc/mailbox@af20000"; | |
| slv_qxs_imem = "/soc/ad-hoc-bus/slv-qxs-imem"; | |
| qupv3_se13_i2c_sleep = "/soc/pinctrl@03400000/qupv3_se13_i2c_pins/qupv3_se13_i2c_sleep"; | |
| dai_mi2s4 = "/soc/qcom,msm-dai-mi2s/qcom,msm-dai-q6-mi2s-quin"; | |
| secure_display_memory = "/reserved-memory/secure_display_region"; | |
| fab_mmss_noc = "/soc/ad-hoc-bus/fab-mmss_noc"; | |
| gmu_user = "/soc/qcom,gmu/gmu_user"; | |
| etm6_out_funnel_apss = "/soc/etm@7640000/port/endpoint"; | |
| rsc_apps = "/soc/ad-hoc-bus/rsc-apps"; | |
| slv_qns_mem_noc_hf_display = "/soc/ad-hoc-bus/slv-qns-mem-noc-hf_display"; | |
| max_rst_suspend = "/soc/pinctrl@03400000/max_rst_suspend"; | |
| mas_llcc_mc = "/soc/ad-hoc-bus/mas-llcc-mc"; | |
| CLUSTER_COST_1 = "/energy-costs/cluster-cost1"; | |
| pm8005_s1_level = "/soc/rpmh-regulator-gfxlvl/regulator-s1-level"; | |
| funnel_apss_merg = "/soc/funnel@7810000"; | |
| qupv3_se6_4uart_pins = "/soc/pinctrl@03400000/qupv3_se6_4uart_pins"; | |
| fab_aggre2_noc = "/soc/ad-hoc-bus/fab-aggre2_noc"; | |
| sec_mi2s_active = "/soc/pinctrl@03400000/sec_mi2s/sec_mi2s_active"; | |
| qupv3_se0_spi = "/soc/spi@880000"; | |
| fab_dc_noc = "/soc/ad-hoc-bus/fab-dc_noc"; | |
| funnel_merg_in_funnel_in2 = "/soc/funnel@6045000/ports/port@2/endpoint"; | |
| tsif1_sync_active = "/soc/pinctrl@03400000/tsif1_sync_active"; | |
| qupv3_se1_spi_sleep = "/soc/pinctrl@03400000/qupv3_se1_spi_pins/qupv3_se1_spi_sleep"; | |
| sec_aux_pcm_dout_active = "/soc/pinctrl@03400000/sec_aux_pcm_dout/sec_aux_pcm_dout_active"; | |
| funnel_lpass_out_tpda = "/soc/funnel@6845000/ports/port@0/endpoint"; | |
| proxy_rx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-proxy-rx"; | |
| mas_qxm_crypto = "/soc/ad-hoc-bus/mas-qxm-crypto"; | |
| pm8998_l23 = "/soc/rpmh-regulator-ldoa23/regulator-l23"; | |
| fab_mc_virt_display = "/soc/ad-hoc-bus/fab-mc_virt_display"; | |
| replicator_out_tmc_etr = "/soc/replicator@6046000/ports/port@0/endpoint"; | |
| pri_mi2s_ws_active = "/soc/pinctrl@03400000/pri_mi2s_ws/pri_mi2s_ws_active"; | |
| key_cam_snapshot_default = "/soc/qcom,spmi@c440000/qcom,pm8998@0/pinctrl@c000/key_cam_snapshot/key_cam_snapshot_default"; | |
| sdc2_cmd_on = "/soc/pinctrl@03400000/sdc2_cmd_on"; | |
| gmu = "/soc/qcom,gmu"; | |
| slv_qns_cnoc_a2noc = "/soc/ad-hoc-bus/slv-qns-cnoc-a2noc"; | |
| tert_aux_pcm_sleep = "/soc/pinctrl@03400000/tert_aux_pcm/tert_aux_pcm_sleep"; | |
| funnel_apss_in_etm7 = "/soc/funnel@7800000/ports/port@8/endpoint"; | |
| CPU5 = "/cpus/cpu@500"; | |
| slv_qns_a1noc_snoc = "/soc/ad-hoc-bus/slv-qns-a1noc-snoc"; | |
| pri_mi2s_sck_active = "/soc/pinctrl@03400000/pri_mi2s_sck/pri_mi2s_sck_active"; | |
| ufsphy_mem = "/soc/ufsphy_mem@1d87000"; | |
| sec_mi2s_sd0_active = "/soc/pinctrl@03400000/sec_mi2s_sd0/sec_mi2s_sd0_active"; | |
| dai_tert_auxpcm = "/soc/qcom,msm-tert-auxpcm"; | |
| sdc2_data_off = "/soc/pinctrl@03400000/sdc2_data_off"; | |
| funnel_dl_mm = "/soc/funnel@6c0b000"; | |
| qupv3_se7_4uart = "/soc/qcom,qup_uart@0x89c000"; | |
| qupv3_se2_i2c = "/soc/i2c@888000"; | |
| venus_gdsc = "/soc/qcom,gdsc@0xab00814"; | |
| mdss_dsi1 = "/soc/qcom,mdss_dsi_ctrl1@ae96000"; | |
| tpda_in_tpdm_north = "/soc/tpda@6004000/ports/port@9/endpoint"; | |
| CPU_COST_0 = "/energy-costs/core-cost0"; | |
| pm8998_trip2 = "/soc/thermal-zones/pm8998_tz/trips/pm8998-trip2"; | |
| slv_qhs_pcie0_cfg = "/soc/ad-hoc-bus/slv-qhs-pcie0-cfg"; | |
| mdm2ap_active = "/soc/pinctrl@03400000/mdm2ap/mdm2ap_active"; | |
| mincpubw = "/soc/qcom,mincpubw"; | |
| tpda_swao_out_funnel_swao = "/soc/tpda@6b01000/ports/port@0/endpoint"; | |
| ipcb_tgu = "/soc/tgu@6b0c000"; | |
| devfreq_compute = "/soc/qcom,devfreq-compute"; | |
| funnel_lpass = "/soc/funnel@6845000"; | |
| dai_quat_tdm_rx_1 = "/soc/qcom,msm-dai-tdm-quat-rx/qcom,msm-dai-q6-tdm-quat-rx-1"; | |
| compute_dsp_tbu = "/soc/apps-smmu@0x15000000/compute_dsp_tbu@0x150d9000"; | |
| qseecom_mem = "/reserved-memory/qseecom_region@0x8ab00000"; | |
| L1_I_100 = "/cpus/cpu@100/l1-icache"; | |
| dai_pri_auxpcm = "/soc/qcom,msm-pri-auxpcm"; | |
| sec_mi2s_mclk_active = "/soc/pinctrl@03400000/sec_mi2s_mclk/sec_mi2s_mclk_active"; | |
| cti7 = "/soc/cti@6017000"; | |
| qupv3_1 = "/soc/qcom,qupv3_1_geni_se@ac0000"; | |
| L2_500 = "/cpus/cpu@500/l2-cache"; | |
| mdss_rotator = "/soc/qcom,mdss_rotator@ae00000"; | |
| cam_csiphy0 = "/soc/qcom,csiphy@ac65000"; | |
| ap2mdm_sleep = "/soc/pinctrl@03400000/ap2mdm/ap2mdm_sleep"; | |
| pm8998_l13 = "/soc/rpmh-regulator-ldoa13/regulator-l13"; | |
| i2c_freq_1Mhz = "/soc/qcom,cci@ac4a000/qcom,i2c_fast_plus_mode"; | |
| qupv3_se4_spi = "/soc/spi@890000"; | |
| jtag_mm4 = "/soc/jtagmm@7440000"; | |
| ebi_cdev = "/soc/rpmh-regulator-ebilvl/regulator-cdev"; | |
| pmi8998_bob_ao = "/soc/rpmh-regulator-bobb1/regulator-bob-ao"; | |
| flash_led3_front_dis = "/soc/pinctrl@03400000/flash_led3_front/flash_led3_front_dis"; | |
| qupv3_se9_i2c_pins = "/soc/pinctrl@03400000/qupv3_se9_i2c_pins"; | |
| pm8998_s4 = "/regulator-pm8998-s4"; | |
| pil_cdsp_mem = "/reserved-memory/cdsp_region@0x95d00000"; | |
| pri_aux_pcm_dout_sleep = "/soc/pinctrl@03400000/pri_aux_pcm_dout/pri_aux_pcm_dout_sleep"; | |
| smp2pgpio_ssr_smp2p_1_in = "/soc/qcom,smp2pgpio-ssr-smp2p-1-in"; | |
| qupv3_se11_spi_sleep = "/soc/pinctrl@03400000/qupv3_se11_spi_pins/qupv3_se11_spi_sleep"; | |
| bcm_sn4 = "/soc/ad-hoc-bus/bcm-sn4"; | |
| mdss_core_gdsc = "/soc/qcom,gdsc@0xaf03000"; | |
| qupv3_se7_spi_pins = "/soc/pinctrl@03400000/qupv3_se7_spi_pins"; | |
| cam_sensor_depth_suspend = "/soc/pinctrl@03400000/cam_sensor_depth_suspend"; | |
| tpdm_center = "/soc/tpdm@6c28000"; | |
| mas_qnm_mnoc_sf_display = "/soc/ad-hoc-bus/mas-qnm-mnoc-sf_display"; | |
| tpdm_swao0 = "/soc/tpdm@6b02000"; | |
| tert_mi2s_active = "/soc/pinctrl@03400000/tert_mi2s/tert_mi2s_active"; | |
| emerg_config3 = "/soc/thermal-zones/cpu3-silver-step/trips/emerg-config3"; | |
| LLCC_3 = "/soc/qcom,llcc@1100000/llcc_3_dcache"; | |
| pil_spss_mem = "/reserved-memory/pil_spss_region@0x97b00000"; | |
| funnel_in2_in_funnel_gfx = "/soc/funnel@0x6043000/ports/port@5/endpoint"; | |
| sdc2_data_ds_200MHz = "/soc/pinctrl@03400000/sdc2_data_ds_200MHz"; | |
| qupv3_se6_i2c = "/soc/i2c@898000"; | |
| pm8998_l9 = "/soc/rpmh-regulator-ldoa9/regulator-l9"; | |
| dump_mem = "/reserved-memory/mem_dump_region"; | |
| quat_mi2s_sd1_active = "/soc/pinctrl@03400000/quat_mi2s_sd1/quat_mi2s_sd1_active"; | |
| max_6dof_suspend = "/soc/pinctrl@03400000/max_6dof_suspend"; | |
| qupv3_se9_spi_sleep = "/soc/pinctrl@03400000/qupv3_se9_spi_pins/qupv3_se9_spi_sleep"; | |
| L1_TLB_600 = "/cpus/cpu@600/l1-tlb"; | |
| smp2pgpio_ssr_smp2p_1_out = "/soc/qcom,smp2pgpio-ssr-smp2p-1-out"; | |
| quec_input_gpios_init = "/soc/pinctrl@03400000/quec_gpio_init/quec_input_gpios_init"; | |
| pm8998_l27_level = "/soc/rpmh-regulator-lcxlvl/regulator-l27-level"; | |
| ufs_dev_reset_assert = "/soc/pinctrl@03400000/ufs_dev_reset_assert"; | |
| sb_3_tx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-3-tx"; | |
| aoss0_trip = "/soc/thermal-zones/aoss0-lowf/trips/aoss0-trip"; | |
| lmh_dcvs1 = "/soc/qcom,cpucc@0x17d41000/qcom,limits-dcvs@1"; | |
| funnel_spss_in_tpda_spss = "/soc/funnel@6883000/ports/port@1/endpoint"; | |
| tert_mi2s_sd1_sleep = "/soc/pinctrl@03400000/tert_mi2s_sd1/tert_mi2s_sd1_sleep"; | |
| L1_I_0 = "/cpus/cpu@0/l1-icache"; | |
| sec_aux_pcm_din_active = "/soc/pinctrl@03400000/sec_aux_pcm_din/sec_aux_pcm_din_active"; | |
| eud_in_replicator_swao = "/soc/dummy_sink/port/endpoint"; | |
| qupv3_se8_spi = "/soc/spi@a80000"; | |
| pcie_1_gdsc = "/soc/qcom,gdsc@0x18d004"; | |
| hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc = "/soc/qcom,gdsc@0x17d030"; | |
| funnel_lpass_in_tpdm_lpass = "/soc/funnel@6845000/ports/port@1/endpoint"; | |
| nfc_clk_default = "/soc/qcom,spmi@c440000/qcom,pm8998@0/pinctrl@c000/nfc_clk/nfc_clk_default"; | |
| etm0 = "/soc/etm@7040000"; | |
| cam_sensor_mclk0_active = "/soc/pinctrl@03400000/cam_sensor_mclk0_active"; | |
| qupv3_se4_i2c_active = "/soc/pinctrl@03400000/qupv3_se4_i2c_pins/qupv3_se4_i2c_active"; | |
| qupv3_se9_i2c_active = "/soc/pinctrl@03400000/qupv3_se9_i2c_pins/qupv3_se9_i2c_active"; | |
| slv_qhs_tlmm_north = "/soc/ad-hoc-bus/slv-qhs-tlmm-north"; | |
| llccbw = "/soc/qcom,llccbw"; | |
| smmu_rot_sec = "/soc/qcom,mdss_rotator@ae00000/qcom,smmu_rot_sec_cb"; | |
| camera_rear_dvdd_en_default = "/soc/qcom,spmi@c440000/qcom,pm8998@0/pinctrl@c000/camera_rear_dvdd_en/camera_rear_dvdd_en_default"; | |
| apps_rsc = "/soc/mailbox@179e0000"; | |
| dai_mi2s2 = "/soc/qcom,msm-dai-mi2s/qcom,msm-dai-q6-mi2s-tert"; | |
| mas_qnm_aggre1_noc = "/soc/ad-hoc-bus/mas-qnm-aggre1-noc"; | |
| l3_cpu4 = "/soc/qcom,l3-cpu4"; | |
| sb_0_tx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-0-tx"; | |
| qupv3_se4_spi_active = "/soc/pinctrl@03400000/qupv3_se4_spi_pins/qupv3_se4_spi_active"; | |
| qupv3_se9_spi_active = "/soc/pinctrl@03400000/qupv3_se9_spi_pins/qupv3_se9_spi_active"; | |
| qupv3_se12_i2c_active = "/soc/pinctrl@03400000/qupv3_se12_i2c_pins/qupv3_se12_i2c_active"; | |
| sdc2_cmd_ds_100MHz = "/soc/pinctrl@03400000/sdc2_cmd_ds_100MHz"; | |
| tpdm_swao1_out_tpda_swao = "/soc/tpdm@6b03000/port/endpoint"; | |
| tpda_in_tpdm_vsense = "/soc/tpda@6004000/ports/port@6/endpoint"; | |
| tpda_swao = "/soc/tpda@6b01000"; | |
| smp2pgpio_smp2p_2_out = "/soc/qcom,smp2pgpio-smp2p-2-out"; | |
| pil_modem_mem = "/reserved-memory/modem_region@0x8e000000"; | |
| qupv3_se6_i2c_sleep = "/soc/pinctrl@03400000/qupv3_se6_i2c_pins/qupv3_se6_i2c_sleep"; | |
| slv_qhs_prng = "/soc/ad-hoc-bus/slv-qhs-prng"; | |
| funnel_spss_in_spss_etm0 = "/soc/funnel@6883000/ports/port@2/endpoint"; | |
| mx_cdev = "/soc/rpmh-regulator-mxlvl/mx-cdev-lvl"; | |
| qupv3_se12_spi_active = "/soc/pinctrl@03400000/qupv3_se12_spi_pins/qupv3_se12_spi_active"; | |
| funnel_merg_in_funnel_in0 = "/soc/funnel@6045000/ports/port@1/endpoint"; | |
| slv_qxs_pcie_gen3 = "/soc/ad-hoc-bus/slv-qxs-pcie-gen3"; | |
| smp2pgpio_ssr_smp2p_5_out = "/soc/qcom,smp2pgpio-ssr-smp2p-5-out"; | |
| hdmi_dba = "/soc/qcom,msm-hdmi-dba-codec-rx"; | |
| sb_6_rx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-6-rx"; | |
| slv_qhs_phy_refgen_south = "/soc/ad-hoc-bus/slv-qhs-phy-refgen-south"; | |
| slv_srvc_cnoc = "/soc/ad-hoc-bus/slv-srvc-cnoc"; | |
| pm8998_l21 = "/soc/rpmh-regulator-ldoa21/regulator-l21"; | |
| dai_tert_tdm_rx_0 = "/soc/qcom,msm-dai-tdm-tert-rx/qcom,msm-dai-q6-tdm-tert-rx-0"; | |
| tpda_in_funnel_ddr_0 = "/soc/tpda@6004000/ports/port@3/endpoint"; | |
| slpi_vdd = "/soc/qmi-tmd-devices/slpi/slpi_vdd"; | |
| sde_dsi_active = "/soc/pinctrl@03400000/pmx_sde/sde_dsi_active"; | |
| pri_aux_pcm_din_sleep = "/soc/pinctrl@03400000/pri_aux_pcm_din/pri_aux_pcm_din_sleep"; | |
| kgsl_msm_iommu = "/soc/qcom,kgsl-iommu"; | |
| funnel_apss_in_etm5 = "/soc/funnel@7800000/ports/port@6/endpoint"; | |
| sec_aux_pcm_sleep = "/soc/pinctrl@03400000/sec_aux_pcm/sec_aux_pcm_sleep"; | |
| pcie1 = "/soc/qcom,pcie@0x1c08000"; | |
| CPU3 = "/cpus/cpu@300"; | |
| tpda_modem_out_funnel_modem = "/soc/tpda@6831000/ports/port@0/endpoint"; | |
| clock_debug = "/soc/qcom,cc-debug@100000"; | |
| smp2pgpio_smp2p_5_in = "/soc/qcom,smp2pgpio-smp2p-5-in"; | |
| qupv3_se6_i2c_pins = "/soc/pinctrl@03400000/qupv3_se6_i2c_pins"; | |
| gfx_cx_out_funnel_in2 = "/soc/qcom,kgsl-3d0@5000000/qcom,gpu-coresights/qcom,gpu-coresight@1/port/endpoint"; | |
| msm_dai_tdm_quat_rx = "/soc/qcom,msm-dai-tdm-quat-rx"; | |
| slv_qhs_tsif = "/soc/ad-hoc-bus/slv-qhs-tsif"; | |
| L1_I_400 = "/cpus/cpu@400/l1-icache"; | |
| pm8998_trip0 = "/soc/thermal-zones/pm8998_tz/trips/pm8998-trip0"; | |
| ssc_sensors = "/soc/qcom,msm-ssc-sensors"; | |
| sb_3_rx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-3-rx"; | |
| clock_cpucc = "/soc/qcom,cpucc@0x17d41000"; | |
| hvx_trip = "/soc/thermal-zones/compute-hvx-lowf/trips/hvx-trip"; | |
| mas_qhm_mnoc_cfg = "/soc/ad-hoc-bus/mas-qhm-mnoc-cfg"; | |
| pri_mi2s_sd0_sleep = "/soc/pinctrl@03400000/pri_mi2s_sd0/pri_mi2s_sd0_sleep"; | |
| qupv3_se4_spi_pins = "/soc/pinctrl@03400000/qupv3_se4_spi_pins"; | |
| mas_qxm_camnoc_hf0 = "/soc/ad-hoc-bus/mas-qxm-camnoc-hf0"; | |
| qupv3_se10_spi = "/soc/spi@a88000"; | |
| cam_csid1 = "/soc/qcom,csid1@acba000"; | |
| tlmm = "/soc/pinctrl@03400000"; | |
| spss_utils = "/soc/qcom,spss_utils"; | |
| tpdm_turing = "/soc/tpdm@6860000"; | |
| glink_fifo_wdsp = "/soc/qcom,glink-fifo-config-wdsp"; | |
| tsens0 = "/soc/tsens@c222000"; | |
| L1_D_300 = "/cpus/cpu@300/l1-dcache"; | |
| cpas_cdm_iova_mem_map = "/soc/qcom,cam_smmu/msm_cam_smmu_cpas_cdm/iova-mem-map"; | |
| cti5 = "/soc/cti@6015000"; | |
| iommu_qupv3_1_geni_se_cb = "/soc/qcom,qupv3_1_geni_se@ac0000/qcom,iommu_qupv3_1_geni_se_cb"; | |
| clock_camcc = "/soc/qcom,camcc@ad00000"; | |
| pm8998_l1_ao = "/soc/rpmh-regulator-ldoa1/regulator-l1-ao"; | |
| sec_mi2s_sd1_sleep = "/soc/pinctrl@03400000/sec_mi2s_sd1/sec_mi2s_sd1_sleep"; | |
| clock_rpmh = "/soc/qcom,rpmhclk"; | |
| slv_qhs_qdss_cfg = "/soc/ad-hoc-bus/slv-qhs-qdss-cfg"; | |
| pm8998_l11 = "/soc/rpmh-regulator-ldoa11/regulator-l11"; | |
| funnel_spss = "/soc/funnel@6883000"; | |
| cpu2_trip = "/soc/thermal-zones/cpu2-silver-lowf/trips/cpu2-trip"; | |
| slv_qhs_crypto0_cfg = "/soc/ad-hoc-bus/slv-qhs-crypto0-cfg"; | |
| jtag_mm2 = "/soc/jtagmm@7240000"; | |
| pm8998_s2 = "/soc/rpmh-regulator-smpa2/regulator-s2"; | |
| smp2pgpio_smp2p_2_in = "/soc/qcom,smp2pgpio-smp2p-2-in"; | |
| mdss_dsi0_pll = "/soc/qcom,mdss_dsi_pll@ae94a00"; | |
| nfc_int_suspend = "/soc/pinctrl@03400000/nfc/nfc_int_suspend"; | |
| max_rst_active = "/soc/pinctrl@03400000/max_rst_active"; | |
| bcm_sn2 = "/soc/ad-hoc-bus/bcm-sn2"; | |
| mas_xm_gic = "/soc/ad-hoc-bus/mas-xm-gic"; | |
| qupv3_se12_i2c = "/soc/i2c@a90000"; | |
| csr = "/soc/csr@6001000"; | |
| tmc_etf_out_replicator = "/soc/tmc@6047000/ports/port@0/endpoint"; | |
| sb_0_rx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-0-rx"; | |
| modem_vdd = "/soc/qmi-tmd-devices/modem/modem_vdd"; | |
| memlat_cpu4 = "/soc/qcom,memlat-cpu4"; | |
| ipa_smmu_uc = "/soc/qcom,ipa@01e00000/ipa_smmu_uc"; | |
| emerg_config1 = "/soc/thermal-zones/cpu1-silver-step/trips/emerg-config1"; | |
| cpug3_trip = "/soc/thermal-zones/cpu3-gold-lowf/trips/cpug3-trip"; | |
| LLCC_1 = "/soc/qcom,llcc@1100000/llcc_1_dcache"; | |
| btfmslim_codec = "/soc/slim@17240000/wcn3990"; | |
| qupv3_se4_spi_sleep = "/soc/pinctrl@03400000/qupv3_se4_spi_pins/qupv3_se4_spi_sleep"; | |
| mas_qxm_rot = "/soc/ad-hoc-bus/mas-qxm-rot"; | |
| tpdm_lpass_out_funnel_lpass = "/soc/tpdm@6844000/port/endpoint"; | |
| pm8998_s1_level = "/soc/rpmh-regulator-ebilvl/regulator-s1"; | |
| pm8998_l7 = "/soc/rpmh-regulator-ldoa7/regulator-l7"; | |
| cti14 = "/soc/cti@601e000"; | |
| cam_sensor_fisheye_active = "/soc/pinctrl@03400000/cam_sensor_fisheye_active"; | |
| clock_gpucc = "/soc/qcom,gpucc@5090000"; | |
| qupv3_se14_spi = "/soc/spi@a98000"; | |
| anoc_1_tbu = "/soc/apps-smmu@0x15000000/anoc_1_tbu@0x150c5000"; | |
| slv_qhs_dcc_cfg = "/soc/ad-hoc-bus/slv-qhs-dcc-cfg"; | |
| slv_qhs_usb3_0 = "/soc/ad-hoc-bus/slv-qhs-usb3-0"; | |
| ufshc_mem = "/soc/ufshc@1d84000"; | |
| mdss_dp_pll = "/soc/qcom,mdss_dp_pll@c011000"; | |
| qcom_crypto = "/soc/qcrypto@1de0000"; | |
| spmi_bus = "/soc/qcom,spmi@c440000"; | |
| smp2pgpio_smp2p_15_out = "/soc/qcom,smp2pgpio-smp2p-15-out"; | |
| slv_qhs_tcsr = "/soc/ad-hoc-bus/slv-qhs-tcsr"; | |
| gpu_cx_gdsc = "/soc/qcom,gdsc@0x509106c"; | |
| pri_mi2s_mclk_sleep = "/soc/pinctrl@03400000/pri_mi2s_mclk/pri_mi2s_mclk_sleep"; | |
| stm_out_funnel_in0 = "/soc/stm@6002000/port/endpoint"; | |
| qupv3_se15_i2c_pins = "/soc/pinctrl@03400000/qupv3_se15_i2c_pins"; | |
| tpda_apss_out_funnel_apss_merg = "/soc/tpda@7862000/ports/port@0/endpoint"; | |
| funnel_turing_1_out_funnel_qatb = "/soc/funnel_1@6861000/ports/port@0/endpoint"; | |
| smmu_sde_sec = "/soc/qcom,mdss_mdp@ae00000/qcom,smmu_sde_sec_cb"; | |
| dai_mi2s0 = "/soc/qcom,msm-dai-mi2s/qcom,msm-dai-q6-mi2s-prim"; | |
| sde_dp_usbplug_cc_active = "/soc/pinctrl@03400000/sde_dp_usbplug_cc_active"; | |
| slv_qns_apps_io = "/soc/ad-hoc-bus/slv-qns-apps-io"; | |
| tpda_apss_in_tpdm_apss = "/soc/tpda@7862000/ports/port@1/endpoint"; | |
| cam_a5 = "/soc/qcom,a5@ac00000"; | |
| qupv3_se13_spi_pins = "/soc/pinctrl@03400000/qupv3_se13_spi_pins"; | |
| tpdm_north = "/soc/tpdm@6a24000"; | |
| wcd_usbc_analog_en2_idle = "/soc/pinctrl@03400000/wcd_usbc_analog_en2/wcd_usbc_ana_en2_idle"; | |
| cam_csid_lite = "/soc/qcom,csid-lite@acc8000"; | |
| bcm_sn14 = "/soc/ad-hoc-bus/bcm-sn14"; | |
| smmu_rot_unsec = "/soc/qcom,mdss_rotator@ae00000/qcom,smmu_rot_unsec_cb"; | |
| pm8998_s9_level_ao = "/soc/rpmh-regulator-cxlvl/regulator-s9-level-ao"; | |
| sdc2_data_ds_50MHz = "/soc/pinctrl@03400000/sdc2_data_ds_50MHz"; | |
| fab_mc_virt = "/soc/ad-hoc-bus/fab-mc_virt"; | |
| qupv3_se1_i2c_sleep = "/soc/pinctrl@03400000/qupv3_se1_i2c_pins/qupv3_se1_i2c_sleep"; | |
| tmc_etf_swao_in_funnel_swao = "/soc/tmc@6b09000/ports/port@1/endpoint"; | |
| mas_qxm_camnoc_hf1_uncomp = "/soc/ad-hoc-bus/mas-qxm-camnoc-hf1-uncomp"; | |
| qupv3_se14_spi_sleep = "/soc/pinctrl@03400000/qupv3_se14_spi_pins/qupv3_se14_spi_sleep"; | |
| funnel_merg = "/soc/funnel@6045000"; | |
| tert_mi2s_sd1_active = "/soc/pinctrl@03400000/tert_mi2s_sd1/tert_mi2s_sd1_active"; | |
| bcm_mm2 = "/soc/ad-hoc-bus/bcm-mm2"; | |
| qupv3_se3_i2c_pins = "/soc/pinctrl@03400000/qupv3_se3_i2c_pins"; | |
| qupv3_se7_4uart_pins = "/soc/pinctrl@03400000/qupv3_se7_4uart_pins"; | |
| qupv3_se9_2uart = "/soc/qcom,qup_uart@0xa84000"; | |
| funnel_gfx_out_funnel_in2 = "/soc/funnel@0x6943000/ports/port@0/endpoint"; | |
| qupv3_se1_spi_pins = "/soc/pinctrl@03400000/qupv3_se1_spi_pins"; | |
| cti_cpu6 = "/soc/cti@7620000"; | |
| slv_qhs_apss = "/soc/ad-hoc-bus/slv-qhs-apss"; | |
| msm_audio_ion = "/soc/qcom,msm-audio-ion"; | |
| quat_aux_pcm_din_active = "/soc/pinctrl@03400000/quat_aux_pcm_din/quat_aux_pcm_din_active"; | |
| cam_sensor_fisheye_suspend = "/soc/pinctrl@03400000/cam_sensor_fisheye_suspend"; | |
| sdc2_data_ds_100MHz = "/soc/pinctrl@03400000/sdc2_data_ds_100MHz"; | |
| funnel_apss_in_etm3 = "/soc/funnel@7800000/ports/port@4/endpoint"; | |
| slim_qca = "/soc/slim@17240000"; | |
| CPU1 = "/cpus/cpu@100"; | |
| mas_qxm_rot_display = "/soc/ad-hoc-bus/mas-qxm-rot_display"; | |
| tpda_swao_in_tpdm_swao1 = "/soc/tpda@6b01000/ports/port@2/endpoint"; | |
| L1_I_700 = "/cpus/cpu@700/l1-icache"; | |
| bcm_sh4 = "/soc/ad-hoc-bus/bcm-sh4"; | |
| }; | |
| soc { | |
| compatible = "simple-bus"; | |
| ranges = <0x00 0x00 0x00 0xffffffff>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| phandle = <0x2ba>; | |
| rpmh-regulator-lcxlvl { | |
| compatible = "qcom,rpmh-arc-regulator"; | |
| qcom,resource-name = "lcx.lvl"; | |
| mboxes = <0x8a 0x00>; | |
| regulator-l27-level { | |
| phandle = <0xb5>; | |
| regulator-min-microvolt = <0x01>; | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x10000>; | |
| regulator-name = "pm8998_l27_level"; | |
| }; | |
| }; | |
| qcom,gdsc@0x18d004 { | |
| compatible = "qcom,gdsc"; | |
| status = "ok"; | |
| phandle = <0x26a>; | |
| reg = <0x18d004 0x04>; | |
| regulator-name = "pcie_1_gdsc"; | |
| qcom,poll-cfg-gdscr; | |
| }; | |
| qcrypto@1de0000 { | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| compatible = "qcom,qcrypto"; | |
| clocks = <0x22 0x11 0x22 0x11 0x22 0x0f 0x22 0x10>; | |
| qcom,ce-hw-instance = <0x00>; | |
| qcom,msm-bus,vectors-KBps = <0x7d 0x200 0x00 0x00 0x7d 0x200 0x60180 0x60180>; | |
| qcom,bam-ee = <0x00>; | |
| qcom,use-sw-aes-ccm-algo; | |
| reg-names = "crypto-base\0crypto-bam-base"; | |
| qcom,bam-pipe-pair = <0x02>; | |
| qcom,use-sw-aead-algo; | |
| qcom,request-bw-before-clk; | |
| clock-names = "core_clk_src\0core_clk\0iface_clk\0bus_clk"; | |
| qcom,use-sw-hmac-algo; | |
| qcom,msm-bus,name = "qcrypto-noc"; | |
| qcom,ce-opp-freq = <0xa37d070>; | |
| qcom,ce-device = <0x00>; | |
| interrupts = <0x00 0x110 0x00>; | |
| phandle = <0x328>; | |
| qcom,use-sw-aes-xts-algo; | |
| qcom,clk-mgmt-sus-res; | |
| reg = <0x1de0000 0x20000 0x1dc4000 0x24000>; | |
| iommus = <0x29 0x704 0x01 0x29 0x714 0x01>; | |
| qcom,use-sw-ahash-algo; | |
| qcom,ce-hw-shared; | |
| qcom,use-sw-aes-cbc-ecb-ctr-algo; | |
| qcom,smmu-s1-enable; | |
| }; | |
| etm@7440000 { | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| coresight-name = "coresight-etm4"; | |
| clock-names = "apb_pclk"; | |
| cpu = <0x15>; | |
| phandle = <0x3a6>; | |
| arm,primecell-periphid = <0xbb95d>; | |
| reg = <0x7440000 0x1000>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x196>; | |
| phandle = <0x19f>; | |
| }; | |
| }; | |
| }; | |
| qcom,pcie@0x1c00000 { | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| qcom,pcie-phy-ver = <0x30>; | |
| qcom,l1ss-supported; | |
| clocks = <0x22 0x36 0x21 0x00 0x22 0x31 0x22 0x33 0x22 0x35 0x22 0x37 0x22 0x34 0x22 0x38 0x22 0x06 0x22 0x42 0x22 0x41>; | |
| qcom,msi-gicm-base = <0x2c0>; | |
| qcom,msm-bus,vectors-KBps = <0x2d 0x200 0x00 0x00 0x2d 0x200 0x1f4 0x320>; | |
| vreg-0.9-supply = <0x2f>; | |
| resets = <0x22 0x01 0x22 0x18>; | |
| qcom,boot-option = <0x01>; | |
| reg-names = "parf\0phy\0dm_core\0elbi\0conf\0io\0bars"; | |
| gdsc-vdd-supply = <0x265>; | |
| qcom,vreg-0.9-voltage-level = <0xd6d80 0xd6d80 0x5dc0>; | |
| qcom,ep-latency = <0x0a>; | |
| qcom,vreg-cx-voltage-level = <0x10000 0x81 0x00>; | |
| clock-names = "pcie_0_pipe_clk\0pcie_0_ref_clk_src\0pcie_0_aux_clk\0pcie_0_cfg_ahb_clk\0pcie_0_mstr_axi_clk\0pcie_0_slv_axi_clk\0pcie_0_ldo\0pcie_0_slv_q2a_axi_clk\0pcie_tbu_clk\0pcie_phy_refgen_clk\0pcie_phy_aux_clk"; | |
| vreg-cx-supply = <0x1b>; | |
| interrupt-map-mask = <0x00 0x00 0x00 0xffffffff>; | |
| iommu-map = <0x00 0x29 0x1c10 0x01 0x100 0x29 0x1c11 0x01 0x200 0x29 0x1c12 0x01 0x300 0x29 0x1c13 0x01 0x400 0x29 0x1c14 0x01 0x500 0x29 0x1c15 0x01 0x600 0x29 0x1c16 0x01 0x700 0x29 0x1c17 0x01 0x800 0x29 0x1c18 0x01 0x900 0x29 0x1c19 0x01 0xa00 0x29 0x1c1a 0x01 0xb00 0x29 0x1c1b 0x01 0xc00 0x29 0x1c1c 0x01 0xd00 0x29 0x1c1d 0x01 0xe00 0x29 0x1c1e 0x01 0xf00 0x29 0x1c1f 0x01>; | |
| qcom,msm-bus,name = "pcie0"; | |
| ranges = <0x1000000 0x00 0x60200000 0x60200000 0x00 0x100000 0x2000000 0x00 0x60300000 0x60300000 0x00 0xd00000>; | |
| perst-gpio = <0x34 0x23 0x00>; | |
| status = "disabled"; | |
| linux,pci-domain = <0x00>; | |
| #interrupt-cells = <0x01>; | |
| interrupt-parent = <0xa1>; | |
| #address-cells = <0x03>; | |
| interrupts = <0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f 0x20 0x21 0x22 0x23 0x24 0x25>; | |
| interrupt-map = <0x00 0x00 0x00 0x00 0x01 0x00 0x8d 0x00 0x00 0x00 0x00 0x01 0x01 0x00 0x95 0x00 0x00 0x00 0x00 0x02 0x01 0x00 0x96 0x00 0x00 0x00 0x00 0x03 0x01 0x00 0x97 0x00 0x00 0x00 0x00 0x04 0x01 0x00 0x98 0x00 0x00 0x00 0x00 0x05 0x01 0x00 0x8c 0x00 0x00 0x00 0x00 0x06 0x01 0x00 0x2a0 0x00 0x00 0x00 0x00 0x07 0x01 0x00 0x2a1 0x00 0x00 0x00 0x00 0x08 0x01 0x00 0x2a2 0x00 0x00 0x00 0x00 0x09 0x01 0x00 0x2a3 0x00 0x00 0x00 0x00 0x0a 0x01 0x00 0x2a4 0x00 0x00 0x00 0x00 0x0b 0x01 0x00 0x2a5 0x00 0x00 0x00 0x00 0x0c 0x01 0x00 0x2a6 0x00 0x00 0x00 0x00 0x0d 0x01 0x00 0x2a7 0x00 0x00 0x00 0x00 0x0e 0x01 0x00 0x2a8 0x00 0x00 0x00 0x00 0x0f 0x01 0x00 0x2a9 0x00 0x00 0x00 0x00 0x10 0x01 0x00 0x2aa 0x00 0x00 0x00 0x00 0x11 0x01 0x00 0x2ab 0x00 0x00 0x00 0x00 0x12 0x01 0x00 0x2ac 0x00 0x00 0x00 0x00 0x13 0x01 0x00 0x2ad 0x00 0x00 0x00 0x00 0x14 0x01 0x00 0x2ae 0x00 0x00 0x00 0x00 0x15 0x01 0x00 0x2af 0x00 0x00 0x00 0x00 0x16 0x01 0x00 0x2b0 0x00 0x00 0x00 0x00 0x17 0x01 0x00 0x2b1 0x00 0x00 0x00 0x00 0x18 0x01 0x00 0x2b2 0x00 0x00 0x00 0x00 0x19 0x01 0x00 0x2b3 0x00 0x00 0x00 0x00 0x1a 0x01 0x00 0x2b4 0x00 0x00 0x00 0x00 0x1b 0x01 0x00 0x2b5 0x00 0x00 0x00 0x00 0x1c 0x01 0x00 0x2b6 0x00 0x00 0x00 0x00 0x1d 0x01 0x00 0x2b7 0x00 0x00 0x00 0x00 0x1e 0x01 0x00 0x2b8 0x00 0x00 0x00 0x00 0x1f 0x01 0x00 0x2b9 0x00 0x00 0x00 0x00 0x20 0x01 0x00 0x2ba 0x00 0x00 0x00 0x00 0x21 0x01 0x00 0x2bb 0x00 0x00 0x00 0x00 0x22 0x01 0x00 0x2bc 0x00 0x00 0x00 0x00 0x23 0x01 0x00 0x2bd 0x00 0x00 0x00 0x00 0x24 0x01 0x00 0x2be 0x00 0x00 0x00 0x00 0x25 0x01 0x00 0x2bf 0x00>; | |
| qcom,use-19p2mhz-aux-clk; | |
| #size-cells = <0x02>; | |
| vreg-1.8-supply = <0x2e>; | |
| phandle = <0xa1>; | |
| qcom,phy-status-offset = <0x974>; | |
| wake-gpio = <0x34 0x25 0x00>; | |
| qcom,vreg-1.8-voltage-level = <0x124f80 0x124f80 0x5dc0>; | |
| qcom,aux-clk-sync; | |
| reg = <0x1c00000 0x2000 0x1c06000 0x1000 0x60000000 0xf1d 0x60000f20 0xa8 0x60100000 0x100000 0x60200000 0x100000 0x60300000 0xd00000>; | |
| pinctrl-0 = <0x262 0x263 0x264>; | |
| max-clock-frequency-hz = <0x00 0x00 0x124f800 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x5f5e100 0x00>; | |
| qcom,msi-gicm-addr = <0x17a00040>; | |
| qcom,l1-supported; | |
| reset-names = "pcie_0_core_reset\0pcie_0_phy_reset"; | |
| qcom,phy-sequence = <0x804 0x01 0x00 0x34 0x14 0x00 0x138 0x30 0x00 0x48 0x07 0x00 0x15c 0x06 0x00 0x90 0x01 0x00 0x88 0x20 0x00 0xf0 0x00 0x00 0xf8 0x01 0x00 0xf4 0xc9 0x00 0x11c 0xff 0x00 0x120 0x3f 0x00 0x164 0x01 0x00 0x154 0x00 0x00 0x148 0x0a 0x00 0x5c 0x19 0x00 0x38 0x90 0x00 0xb0 0x82 0x00 0xc0 0x02 0x00 0xbc 0xea 0x00 0xb8 0xab 0x00 0xa0 0x00 0x00 0x9c 0x0d 0x00 0x98 0x04 0x00 0x13c 0x00 0x00 0x60 0x06 0x00 0x68 0x16 0x00 0x70 0x36 0x00 0x184 0x01 0x00 0x138 0x33 0x00 0x3c 0x02 0x00 0x40 0x06 0x00 0x80 0x04 0x00 0xdc 0x00 0x00 0xd8 0x3f 0x00 0x0c 0x09 0x00 0x10 0x01 0x00 0x1c 0x40 0x00 0x20 0x01 0x00 0x14 0x02 0x00 0x18 0x00 0x00 0x24 0x7e 0x00 0x28 0x15 0x00 0x244 0x02 0x00 0x2a4 0x12 0x00 0x260 0x10 0x00 0x28c 0x06 0x00 0x504 0x03 0x00 0x500 0x10 0x00 0x50c 0x14 0x00 0x4d4 0x0e 0x00 0x4d8 0x04 0x00 0x4dc 0x1a 0x00 0x434 0x4b 0x00 0x414 0x04 0x00 0x40c 0x04 0x00 0x4f8 0x71 0x00 0x564 0x59 0x00 0x568 0x59 0x00 0x4fc 0x80 0x00 0x51c 0x40 0x00 0x444 0x71 0x00 0x43c 0x40 0x00 0x854 0x04 0x00 0x62c 0x52 0x00 0x654 0x10 0x00 0x65c 0x1a 0x00 0x660 0x06 0x00 0x8c8 0x83 0x00 0x8cc 0x09 0x00 0x8d0 0xa2 0x00 0x8d4 0x40 0x00 0x8c4 0x02 0x00 0x9ac 0x00 0x00 0x8a0 0x01 0x00 0x9e0 0x00 0x00 0x9dc 0x20 0x00 0x9a8 0x00 0x00 0x8a4 0x01 0x00 0x8a8 0x73 0x00 0x9d8 0xbb 0x00 0x9b0 0x03 0x00 0xa0c 0x0d 0x00 0x86c 0x00 0x00 0x644 0x00 0x00 0x804 0x03 0x00 0x800 0x00 0x00 0x808 0x03 0x00>; | |
| interrupt-names = "int_msi\0int_a\0int_b\0int_c\0int_d\0int_global_int\0msi_0\0msi_1\0msi_2\0msi_3\0msi_4\0msi_5\0msi_6\0msi_7\0msi_8\0msi_9\0msi_10\0msi_11\0msi_12\0msi_13\0msi_14\0msi_15\0msi_16\0msi_17\0msi_18\0msi_19\0msi_20\0msi_21\0msi_22\0msi_23\0msi_24\0msi_25\0msi_26\0msi_27\0msi_28\0msi_29\0msi_30\0msi_31"; | |
| qcom,smmu-sid-base = <0x1c10>; | |
| pinctrl-names = "default"; | |
| cell-index = <0x00>; | |
| }; | |
| qcom,smp2pgpio_test_smp2p_3_out { | |
| gpios = <0x1b7 0x00 0x00>; | |
| compatible = "qcom,smp2pgpio_test_smp2p_3_out"; | |
| }; | |
| cti@601d000 { | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti13"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x393>; | |
| arm,primecell-periphid = <0x3b966>; | |
| reg = <0x601d000 0x1000>; | |
| }; | |
| qcom,dsi-display@16 { | |
| compatible = "qcom,dsi-display"; | |
| clocks = <0x2bc 0x06 0x2bc 0x09>; | |
| lab-supply = <0x4e2>; | |
| pinctrl-1 = <0x41c 0x41e>; | |
| clock-names = "mux_byte_clk\0mux_pixel_clk"; | |
| vddio-supply = <0x120>; | |
| qcom,dsi-panel = <0x4f3>; | |
| label = "dsi_dual_nt36850_truly_cmd_display"; | |
| ibb-supply = <0x4e3>; | |
| phandle = <0x550>; | |
| qcom,dsi-ctrl = <0x2c3 0x2c4>; | |
| qcom,display-type = "primary"; | |
| qcom,panel-mode-gpio = <0x34 0x34 0x00>; | |
| pinctrl-0 = <0x41b 0x41d>; | |
| qcom,platform-te-gpio = <0x34 0x0a 0x00>; | |
| qcom,dsi-phy = <0x2c5 0x2c6>; | |
| qcom,platform-reset-gpio = <0x34 0x06 0x00>; | |
| pinctrl-names = "panel_active\0panel_suspend"; | |
| }; | |
| qcom,dsi-display@7 { | |
| compatible = "qcom,dsi-display"; | |
| clocks = <0x2bd 0x18 0x2bd 0x1b>; | |
| lab-supply = <0x4e2>; | |
| pinctrl-1 = <0x41c 0x41e>; | |
| clock-names = "mux_byte_clk\0mux_pixel_clk"; | |
| vddio-supply = <0x120>; | |
| qcom,dsi-panel = <0x4ea>; | |
| label = "dsi_nt35597_truly_dsc_video_display"; | |
| ibb-supply = <0x4e3>; | |
| phandle = <0x547>; | |
| qcom,dsi-ctrl = <0x2c4>; | |
| qcom,display-type = "primary"; | |
| qcom,panel-mode-gpio = <0x34 0x34 0x00>; | |
| pinctrl-0 = <0x41b 0x41d>; | |
| qcom,platform-te-gpio = <0x34 0x0a 0x00>; | |
| qcom,dsi-phy = <0x2c6>; | |
| qcom,platform-reset-gpio = <0x34 0x06 0x00>; | |
| pinctrl-names = "panel_active\0panel_suspend"; | |
| }; | |
| jtagmm@7240000 { | |
| compatible = "qcom,jtagv8-mm"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "etm-base"; | |
| clock-names = "core_clk"; | |
| phandle = <0x2f0>; | |
| reg = <0x7240000 0x1000>; | |
| qcom,coresight-jtagmm-cpu = <0x13>; | |
| }; | |
| rpmh-regulator-ldoa15 { | |
| qcom,supported-modes = <0x02 0x04>; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "ldoa15"; | |
| mboxes = <0x8a 0x00>; | |
| qcom,regulator-type = "pmic4-ldo"; | |
| qcom,mode-threshold-currents = <0x00 0x01>; | |
| regulator-l15 { | |
| qcom,init-mode = <0x02>; | |
| phandle = <0x342>; | |
| qcom,init-voltage = <0x1b7740>; | |
| regulator-min-microvolt = <0x1b7740>; | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x1b7740>; | |
| regulator-name = "pm8998_l15"; | |
| }; | |
| }; | |
| gpio5_pwm { | |
| compatible = "gpio5-pwm"; | |
| pinctrl-1 = <0x3eb>; | |
| qcom,fan-en-gpio = <0x34 0x2c 0x00>; | |
| gpio5-pwm-period-ns = <0xc350>; | |
| pinctrl-0 = <0x51f>; | |
| qcom,fan-fg-gpio = <0x34 0x1e 0x2004>; | |
| gpio5-pwm-duty-ns = <0x2710>; | |
| gpio5-pwm-state = <0x00>; | |
| pwms = <0x51e 0x00 0x00>; | |
| pinctrl-names = "default"; | |
| }; | |
| qcom,glink-qos-config-wdsp { | |
| compatible = "qcom,glink-qos-config"; | |
| qcom,tput-stats-cycle = <0x0a>; | |
| qcom,mtu-size = <0x800>; | |
| qcom,flow-info = <0x80 0x00 0x70 0x01 0x60 0x02 0x50 0x03>; | |
| phandle = <0xe0>; | |
| }; | |
| qcom,msm-dai-tdm-tert-rx { | |
| compatible = "qcom,msm-dai-tdm"; | |
| qcom,msm-cpudai-tdm-group-port-id = <0x9020>; | |
| qcom,msm-cpudai-tdm-clk-internal = <0x01>; | |
| qcom,msm-cpudai-tdm-sync-mode = <0x01>; | |
| qcom,msm-cpudai-tdm-clk-rate = <0x177000>; | |
| qcom,msm-cpudai-tdm-data-out = <0x00>; | |
| qcom,msm-cpudai-tdm-data-delay = <0x01>; | |
| qcom,msm-cpudai-tdm-group-id = <0x9120>; | |
| qcom,msm-cpudai-tdm-invert-sync = <0x01>; | |
| qcom,msm-cpudai-tdm-group-num-ports = <0x01>; | |
| qcom,msm-cpudai-tdm-sync-src = <0x01>; | |
| qcom,msm-dai-q6-tdm-tert-rx-0 { | |
| compatible = "qcom,msm-dai-q6-tdm"; | |
| qcom,msm-cpudai-tdm-dev-id = <0x9020>; | |
| phandle = <0x2a6>; | |
| qcom,msm-cpudai-tdm-data-align = <0x00>; | |
| }; | |
| }; | |
| qcom,cpu0-memlat-mon { | |
| compatible = "qcom,arm-memlat-mon"; | |
| qcom,cachemiss-ev = <0x2a>; | |
| phandle = <0x30d>; | |
| qcom,target-dev = <0x84>; | |
| qcom,core-dev-table = <0x493e0 0x2fa 0xb6d00 0x6b8 0x114900 0x826 0x15f900 0xb71 0x185100 0xf27>; | |
| qcom,cpulist = <0x11 0x12 0x13 0x14>; | |
| }; | |
| qcom,lpm-levels { | |
| compatible = "qcom,lpm-levels"; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| qcom,pm-cluster@0 { | |
| qcom,psci-mode-shift = <0x04>; | |
| qcom,clstr-tmr-add = <0x3e8>; | |
| #address-cells = <0x01>; | |
| label = "L3"; | |
| #size-cells = <0x00>; | |
| reg = <0x00>; | |
| qcom,psci-mode-mask = <0xfff>; | |
| qcom,pm-cluster-level@0 { | |
| qcom,time-overhead = <0x63>; | |
| qcom,latency-us = <0x33>; | |
| label = "l3-wfi"; | |
| qcom,energy-overhead = <0x10eeb>; | |
| qcom,ss-power = <0x1c4>; | |
| reg = <0x00>; | |
| qcom,psci-mode = <0x01>; | |
| }; | |
| qcom,pm-cpu@0 { | |
| qcom,psci-mode-shift = <0x00>; | |
| qcom,cpu = <0x11 0x12 0x13 0x14>; | |
| qcom,ref-premature-cnt = <0x01>; | |
| qcom,tmr-add = <0x3e8>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| qcom,ref-stddev = <0x1f4>; | |
| qcom,psci-mode-mask = <0x0f>; | |
| qcom,pm-cpu-level@2 { | |
| qcom,time-overhead = <0x258>; | |
| qcom,psci-cpu-mode = <0x04>; | |
| qcom,latency-us = <0x213>; | |
| label = "rail-pc"; | |
| qcom,energy-overhead = <0x7a120>; | |
| qcom,ss-power = <0x49>; | |
| qcom,is-reset; | |
| reg = <0x02>; | |
| qcom,use-broadcast-timer; | |
| }; | |
| qcom,pm-cpu-level@0 { | |
| qcom,time-overhead = <0x64>; | |
| qcom,psci-cpu-mode = <0x01>; | |
| qcom,latency-us = <0x2b>; | |
| label = "wfi"; | |
| qcom,energy-overhead = <0x2710>; | |
| qcom,ss-power = <0x96>; | |
| reg = <0x00>; | |
| }; | |
| qcom,pm-cpu-level@1 { | |
| qcom,time-overhead = <0x1f4>; | |
| qcom,psci-cpu-mode = <0x03>; | |
| qcom,latency-us = <0x1cd>; | |
| label = "pc"; | |
| qcom,energy-overhead = <0x61a80>; | |
| qcom,ss-power = <0x64>; | |
| qcom,is-reset; | |
| reg = <0x01>; | |
| qcom,use-broadcast-timer; | |
| }; | |
| }; | |
| qcom,pm-cluster-level@1 { | |
| qcom,time-overhead = <0x1388>; | |
| qcom,latency-us = <0x19a2>; | |
| label = "llcc-off"; | |
| qcom,energy-overhead = "\0=\t"; | |
| qcom,ss-power = <0x6c>; | |
| qcom,is-reset; | |
| reg = <0x01>; | |
| qcom,psci-mode = <0xc24>; | |
| qcom,notify-rpm; | |
| qcom,min-child-idx = <0x02>; | |
| }; | |
| qcom,pm-cpu@1 { | |
| qcom,psci-mode-shift = <0x00>; | |
| qcom,cpu = <0x15 0x16 0x17 0x18>; | |
| qcom,ref-premature-cnt = <0x03>; | |
| qcom,tmr-add = <0x64>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| qcom,ref-stddev = <0x64>; | |
| qcom,psci-mode-mask = <0x0f>; | |
| qcom,pm-cpu-level@2 { | |
| qcom,time-overhead = <0x3e8>; | |
| qcom,psci-cpu-mode = <0x04>; | |
| qcom,latency-us = <0x425>; | |
| label = "rail-pc"; | |
| qcom,energy-overhead = <0x688c1>; | |
| qcom,ss-power = <0x190>; | |
| qcom,is-reset; | |
| reg = <0x02>; | |
| qcom,use-broadcast-timer; | |
| }; | |
| qcom,pm-cpu-level@0 { | |
| qcom,time-overhead = <0x53>; | |
| qcom,psci-cpu-mode = <0x01>; | |
| qcom,latency-us = <0x2b>; | |
| label = "wfi"; | |
| qcom,energy-overhead = <0x96ef>; | |
| qcom,ss-power = <0x1c6>; | |
| reg = <0x00>; | |
| }; | |
| qcom,pm-cpu-level@1 { | |
| qcom,time-overhead = <0x375>; | |
| qcom,psci-cpu-mode = <0x03>; | |
| qcom,latency-us = <0x26d>; | |
| label = "pc"; | |
| qcom,energy-overhead = <0x661b1>; | |
| qcom,ss-power = <0x1b4>; | |
| qcom,is-reset; | |
| reg = <0x01>; | |
| qcom,use-broadcast-timer; | |
| }; | |
| }; | |
| }; | |
| }; | |
| cti@601a000 { | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti10"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x390>; | |
| arm,primecell-periphid = <0x3b966>; | |
| reg = <0x601a000 0x1000>; | |
| }; | |
| qcom,msm-dai-q6 { | |
| compatible = "qcom,msm-dai-q6"; | |
| qcom,msm-dai-q6-sb-8-rx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| phandle = <0x4b8>; | |
| qcom,msm-dai-q6-dev-id = <0x4010>; | |
| }; | |
| qcom,msm-dai-q6-sb-5-rx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| phandle = <0x29b>; | |
| qcom,msm-dai-q6-dev-id = <0x400a>; | |
| }; | |
| qcom,msm-dai-q6-sb-2-rx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| phandle = <0x28c>; | |
| qcom,msm-dai-q6-dev-id = <0x4004>; | |
| }; | |
| qcom,msm-dai-q6-usb-audio-tx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| phandle = <0x2a1>; | |
| qcom,msm-dai-q6-dev-id = <0x7001>; | |
| }; | |
| qcom,msm-dai-q6-usb-audio-rx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| phandle = <0x2a0>; | |
| qcom,msm-dai-q6-dev-id = <0x7000>; | |
| }; | |
| qcom,msm-dai-q6-incall-music-2-rx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| phandle = <0x29a>; | |
| qcom,msm-dai-q6-dev-id = <0x8002>; | |
| }; | |
| qcom,msm-dai-q6-incall-record-tx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| phandle = <0x298>; | |
| qcom,msm-dai-q6-dev-id = <0x8004>; | |
| }; | |
| qcom,msm-dai-q6-sb-7-tx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| phandle = <0x29e>; | |
| qcom,msm-dai-q6-dev-id = <0x400f>; | |
| }; | |
| qcom,msm-dai-q6-sb-4-tx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| phandle = <0x291>; | |
| qcom,msm-dai-q6-dev-id = <0x4009>; | |
| }; | |
| qcom,msm-dai-q6-bt-sco-tx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| phandle = <0x4ba>; | |
| qcom,msm-dai-q6-dev-id = <0x3001>; | |
| }; | |
| qcom,msm-dai-q6-sb-1-tx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| phandle = <0x28b>; | |
| qcom,msm-dai-q6-dev-id = <0x4003>; | |
| }; | |
| qcom,msm-dai-q6-incall-record-rx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| phandle = <0x297>; | |
| qcom,msm-dai-q6-dev-id = <0x8003>; | |
| }; | |
| qcom,msm-dai-q6-sb-7-rx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| phandle = <0x29d>; | |
| qcom,msm-dai-q6-dev-id = <0x400e>; | |
| }; | |
| qcom,msm-dai-q6-sb-4-rx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| phandle = <0x290>; | |
| qcom,msm-dai-q6-dev-id = <0x4008>; | |
| }; | |
| qcom,msm-dai-q6-bt-sco-rx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| phandle = <0x4b9>; | |
| qcom,msm-dai-q6-dev-id = <0x3000>; | |
| }; | |
| qcom,msm-dai-q6-sb-1-rx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| phandle = <0x28a>; | |
| qcom,msm-dai-q6-dev-id = <0x4002>; | |
| }; | |
| qcom,msm-dai-q6-afe-loopback-tx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| phandle = <0x4bd>; | |
| qcom,msm-dai-q6-dev-id = <0x6001>; | |
| }; | |
| qcom,msm-dai-q6-int-fm-tx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| phandle = <0x4bc>; | |
| qcom,msm-dai-q6-dev-id = <0x3005>; | |
| }; | |
| qcom,msm-dai-q6-proxy-tx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| phandle = <0x4bf>; | |
| qcom,msm-dai-q6-dev-id = <0x2003>; | |
| }; | |
| qcom,msm-dai-q6-int-fm-rx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| phandle = <0x4bb>; | |
| qcom,msm-dai-q6-dev-id = <0x3004>; | |
| }; | |
| qcom,msm-dai-q6-proxy-rx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| phandle = <0x4be>; | |
| qcom,msm-dai-q6-dev-id = <0x2002>; | |
| }; | |
| qcom,msm-dai-q6-sb-3-tx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| phandle = <0x28f>; | |
| qcom,msm-dai-q6-dev-id = <0x4007>; | |
| }; | |
| qcom,msm-dai-q6-sb-0-tx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| phandle = <0x289>; | |
| qcom,msm-dai-q6-dev-id = <0x4001>; | |
| }; | |
| qcom,msm-dai-q6-sb-6-rx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| phandle = <0x29c>; | |
| qcom,msm-dai-q6-dev-id = <0x400c>; | |
| }; | |
| qcom,msm-dai-q6-sb-3-rx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| phandle = <0x28e>; | |
| qcom,msm-dai-q6-dev-id = <0x4006>; | |
| }; | |
| qcom,msm-dai-q6-sb-0-rx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| phandle = <0x288>; | |
| qcom,msm-dai-q6-dev-id = <0x4000>; | |
| }; | |
| qcom,msm-dai-q6-afe-proxy-tx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| phandle = <0x296>; | |
| qcom,msm-dai-q6-dev-id = <0xf0>; | |
| }; | |
| qcom,msm-dai-q6-afe-proxy-rx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| phandle = <0x295>; | |
| qcom,msm-dai-q6-dev-id = <0xf1>; | |
| }; | |
| qcom,msm-dai-q6-be-afe-pcm-tx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| phandle = <0x294>; | |
| qcom,msm-dai-q6-dev-id = <0xe1>; | |
| }; | |
| qcom,msm-dai-q6-sb-8-tx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| phandle = <0x29f>; | |
| qcom,msm-dai-q6-dev-id = <0x4011>; | |
| }; | |
| qcom,msm-dai-q6-be-afe-pcm-rx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| phandle = <0x293>; | |
| qcom,msm-dai-q6-dev-id = <0xe0>; | |
| }; | |
| qcom,msm-dai-q6-sb-5-tx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| phandle = <0x292>; | |
| qcom,msm-dai-q6-dev-id = <0x400b>; | |
| }; | |
| qcom,msm-dai-q6-sb-2-tx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| phandle = <0x28d>; | |
| qcom,msm-dai-q6-dev-id = <0x4005>; | |
| }; | |
| qcom,msm-dai-q6-incall-music-rx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| phandle = <0x299>; | |
| qcom,msm-dai-q6-dev-id = <0x8005>; | |
| }; | |
| }; | |
| gpio-regulator@0 { | |
| regulator-enable-ramp-delay = <0x64>; | |
| compatible = "regulator-fixed"; | |
| enable-active-high; | |
| gpio = <0x34 0x5d 0x00>; | |
| phandle = <0x518>; | |
| regulator-min-microvolt = <0x2ab980>; | |
| reg = <0x00 0x00>; | |
| regulator-max-microvolt = <0x2ab980>; | |
| regulator-name = "actuator_regulator"; | |
| }; | |
| i2c@884000 { | |
| compatible = "qcom,i2c-geni"; | |
| clocks = <0x22 0x4e 0x22 0x6c 0x22 0x6d>; | |
| qcom,wrapper-core = <0x35>; | |
| pinctrl-1 = <0x3c>; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| status = "disabled"; | |
| #address-cells = <0x01>; | |
| interrupts = <0x00 0x25a 0x00>; | |
| #size-cells = <0x00>; | |
| dma-names = "tx\0rx"; | |
| phandle = <0x2cc>; | |
| reg = <0x884000 0x4000>; | |
| pinctrl-0 = <0x3b>; | |
| dmas = <0x38 0x00 0x01 0x03 0x40 0x00 0x38 0x01 0x01 0x03 0x40 0x00>; | |
| pinctrl-names = "default\0sleep"; | |
| }; | |
| tmc@6048000 { | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "tmc-base\0bam-base"; | |
| coresight-name = "coresight-tmc-etr"; | |
| clock-names = "apb_pclk"; | |
| interrupts = <0x00 0x10e 0x01>; | |
| arm,sg-enable; | |
| phandle = <0x358>; | |
| arm,primecell-periphid = <0x3b961>; | |
| reg = <0x6048000 0x1000 0x6064000 0x15000>; | |
| coresight-ctis = <0x133 0x134>; | |
| interrupt-names = "byte-cntr-irq"; | |
| arm,buffer-size = <0x400000>; | |
| coresight-csr = <0x128>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x135>; | |
| phandle = <0x123>; | |
| slave-mode; | |
| }; | |
| }; | |
| }; | |
| i2c@a90000 { | |
| compatible = "qcom,i2c-geni"; | |
| clocks = <0x22 0x64 0x22 0x6e 0x22 0x6f>; | |
| qcom,wrapper-core = <0x5b>; | |
| pinctrl-1 = <0x68>; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| status = "disabled"; | |
| #address-cells = <0x01>; | |
| interrupts = <0x00 0x165 0x00>; | |
| #size-cells = <0x00>; | |
| dma-names = "tx\0rx"; | |
| phandle = <0x2e2>; | |
| reg = <0xa90000 0x4000>; | |
| pinctrl-0 = <0x67>; | |
| dmas = <0x5e 0x00 0x04 0x03 0x40 0x00 0x5e 0x01 0x04 0x03 0x40 0x00>; | |
| pinctrl-names = "default\0sleep"; | |
| }; | |
| spi@884000 { | |
| compatible = "qcom,spi-geni"; | |
| clocks = <0x22 0x4e 0x22 0x6c 0x22 0x6d>; | |
| qcom,wrapper-core = <0x35>; | |
| reg-names = "se_phys"; | |
| pinctrl-1 = <0x4c>; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| status = "disabled"; | |
| #address-cells = <0x01>; | |
| interrupts = <0x00 0x25a 0x00>; | |
| #size-cells = <0x00>; | |
| dma-names = "tx\0rx"; | |
| phandle = <0x2d4>; | |
| reg = <0x884000 0x4000>; | |
| pinctrl-0 = <0x4b>; | |
| dmas = <0x38 0x00 0x01 0x01 0x40 0x00 0x38 0x01 0x01 0x01 0x40 0x00>; | |
| spi-max-frequency = <0x2faf080>; | |
| pinctrl-names = "default\0sleep"; | |
| }; | |
| kryo3xx-erp { | |
| compatible = "arm,arm64-kryo3xx-cpu-erp"; | |
| interrupts = <0x01 0x06 0x04 0x01 0x07 0x04 0x00 0x22 0x04 0x00 0x23 0x04>; | |
| interrupt-names = "l1-l2-faultirq\0l1-l2-errirq\0l3-scu-errirq\0l3-scu-faultirq"; | |
| }; | |
| qcom,smp2pgpio-sleepstate-gpio-3-out { | |
| compatible = "qcom,smp2pgpio"; | |
| gpio-controller; | |
| #interrupt-cells = <0x02>; | |
| phandle = <0x1ba>; | |
| qcom,entry-name = "sleepstate"; | |
| #gpio-cells = <0x02>; | |
| qcom,remote-pid = <0x03>; | |
| interrupt-controller; | |
| }; | |
| spi@a90000 { | |
| compatible = "qcom,spi-geni"; | |
| clocks = <0x22 0x64 0x22 0x6e 0x22 0x6f>; | |
| qcom,wrapper-core = <0x5b>; | |
| reg-names = "se_phys"; | |
| pinctrl-1 = <0x77>; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| status = "disabled"; | |
| #address-cells = <0x01>; | |
| interrupts = <0x00 0x165 0x00>; | |
| #size-cells = <0x00>; | |
| dma-names = "tx\0rx"; | |
| phandle = <0x2ea>; | |
| reg = <0xa90000 0x4000>; | |
| pinctrl-0 = <0x76>; | |
| dmas = <0x5e 0x00 0x04 0x01 0x40 0x00 0x5e 0x01 0x04 0x01 0x40 0x00>; | |
| spi-max-frequency = <0x2faf080>; | |
| pinctrl-names = "default\0sleep"; | |
| }; | |
| tpdm@6b03000 { | |
| qcom,msr-fix-req; | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "tpdm-base"; | |
| coresight-name = "coresight-tpdm-swao-1"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x357>; | |
| arm,primecell-periphid = <0x3b968>; | |
| reg = <0x6b03000 0x1000>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x132>; | |
| phandle = <0x130>; | |
| }; | |
| }; | |
| }; | |
| funnel@0x6943000 { | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "funnel-base"; | |
| coresight-name = "coresight-funnel-gfx"; | |
| clock-names = "apb_pclk"; | |
| status = "disabled"; | |
| phandle = <0x35f>; | |
| arm,primecell-periphid = <0x3b908>; | |
| reg = <0x6943000 0x1000>; | |
| ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@1 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x147>; | |
| phandle = <0x2ae>; | |
| slave-mode; | |
| }; | |
| }; | |
| port@2 { | |
| reg = <0x01>; | |
| endpoint { | |
| remote-endpoint = <0x148>; | |
| phandle = <0x2af>; | |
| slave-mode; | |
| }; | |
| }; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x146>; | |
| phandle = <0x145>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| rpmh-regulator-smpa2 { | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "smpa2"; | |
| mboxes = <0x8a 0x00>; | |
| regulator-s2 { | |
| phandle = <0x338>; | |
| qcom,init-voltage = <0x10c8e0>; | |
| regulator-min-microvolt = <0x10c8e0>; | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x10c8e0>; | |
| regulator-name = "pm8998_s2"; | |
| }; | |
| }; | |
| rpmh-regulator-ldoa7 { | |
| qcom,supported-modes = <0x02 0x04>; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "ldoa7"; | |
| mboxes = <0x8a 0x00>; | |
| qcom,regulator-type = "pmic4-ldo"; | |
| qcom,mode-threshold-currents = <0x00 0x2710>; | |
| regulator-l7 { | |
| qcom,init-mode = <0x02>; | |
| phandle = <0xec>; | |
| qcom,init-voltage = <0x1b7740>; | |
| regulator-min-microvolt = <0x1b7740>; | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x1b7740>; | |
| regulator-name = "pm8998_l7"; | |
| }; | |
| }; | |
| qcom,cam-lrme { | |
| compatible = "qcom,cam-lrme"; | |
| status = "ok"; | |
| arch-compat = "lrme"; | |
| }; | |
| i2c@a88000 { | |
| clocks = <0x22 0x60 0x22 0x6e 0x22 0x6f>; | |
| qcom,wrapper-core = <0x5b>; | |
| pinctrl-1 = <0x64>; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| status = "ok"; | |
| #address-cells = <0x01>; | |
| interrupts = <0x00 0x163 0x00>; | |
| #size-cells = <0x00>; | |
| dma-names = "tx\0rx"; | |
| phandle = <0x2e0>; | |
| reg = <0xa88000 0x4000>; | |
| pinctrl-0 = <0x63>; | |
| dmas = <0x5e 0x00 0x02 0x03 0x40 0x00 0x5e 0x01 0x02 0x03 0x40 0x00>; | |
| pinctrl-names = "default\0sleep"; | |
| qcom,smb1355@c { | |
| compatible = "qcom,i2c-pmic"; | |
| qcom,periph-map = <0x10 0x12 0x13 0x16>; | |
| #interrupt-cells = <0x03>; | |
| interrupt-parent = <0x2f6>; | |
| #address-cells = <0x01>; | |
| interrupts = <0x00 0xd1 0x00 0x08>; | |
| #size-cells = <0x00>; | |
| phandle = <0x51d>; | |
| reg = <0x0c>; | |
| interrupt_names = "smb1355_1"; | |
| interrupt-controller; | |
| qcom,revid@100 { | |
| compatible = "qcom,qpnp-revid"; | |
| phandle = <0x51c>; | |
| reg = <0x100 0x100>; | |
| }; | |
| qcom,smb1355-charger@1000 { | |
| io-channels = <0x4fb 0x02 0x4fb 0x0c>; | |
| compatible = "qcom,smb1355"; | |
| qcom,pmic-revid = <0x51c>; | |
| io-channel-names = "charger_temp\0charger_temp_max"; | |
| status = "ok"; | |
| interrupt-parent = <0x51d>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| phandle = <0x57b>; | |
| reg = <0x1000 0x700>; | |
| qcom,disable-ctm; | |
| qcom,chgr@1000 { | |
| interrupts = <0x10 0x01 0x01>; | |
| reg = <0x1000 0x100>; | |
| interrupt-names = "chg-state-change"; | |
| }; | |
| qcom,chgr-misc@1600 { | |
| interrupts = <0x16 0x01 0x01 0x16 0x06 0x01>; | |
| reg = <0x1600 0x100>; | |
| interrupt-names = "wdog-bark\0temperature-change"; | |
| }; | |
| }; | |
| }; | |
| qcom,smb1355@8 { | |
| compatible = "qcom,i2c-pmic"; | |
| qcom,periph-map = <0x10 0x12 0x13 0x16>; | |
| #interrupt-cells = <0x03>; | |
| interrupt-parent = <0x2f6>; | |
| #address-cells = <0x01>; | |
| interrupts = <0x00 0xd1 0x00 0x08>; | |
| #size-cells = <0x00>; | |
| phandle = <0x51b>; | |
| reg = <0x08>; | |
| interrupt_names = "smb1355_0"; | |
| interrupt-controller; | |
| qcom,revid@100 { | |
| compatible = "qcom,qpnp-revid"; | |
| phandle = <0x51a>; | |
| reg = <0x100 0x100>; | |
| }; | |
| qcom,smb1355-charger@1000 { | |
| io-channels = <0x4fb 0x02 0x4fb 0x0c>; | |
| compatible = "qcom,smb1355"; | |
| qcom,pmic-revid = <0x51a>; | |
| io-channel-names = "charger_temp\0charger_temp_max"; | |
| status = "ok"; | |
| interrupt-parent = <0x51b>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| phandle = <0x57a>; | |
| reg = <0x1000 0x700>; | |
| qcom,disable-ctm; | |
| qcom,chgr@1000 { | |
| interrupts = <0x10 0x01 0x01>; | |
| reg = <0x1000 0x100>; | |
| interrupt-names = "chg-state-change"; | |
| }; | |
| qcom,chgr-misc@1600 { | |
| interrupts = <0x16 0x01 0x01 0x16 0x06 0x01>; | |
| reg = <0x1600 0x100>; | |
| interrupt-names = "wdog-bark\0temperature-change"; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,a5@ac00000 { | |
| clock-rates = <0x00 0x00 0xbebc200 0x00 0x00 0x00 0x00 0x17d78400 0x00 0x00 0xbebc200 0x00 0x00 0x00 0x00 0x23c34600>; | |
| compatible = "qcom,cam-a5"; | |
| clocks = <0x22 0x0c 0x22 0x0d 0xa5 0x17 0xa5 0x55 0xa5 0x09 0xa5 0x06 0xa5 0x1d 0xa5 0x1e>; | |
| reg-names = "a5_qgic\0a5_sierra\0a5_csr"; | |
| clock-names = "gcc_cam_ahb_clk\0gcc_cam_axi_clk\0soc_fast_ahb\0soc_ahb_clk\0cpas_ahb_clk\0camnoc_axi_clk\0icp_clk\0icp_clk_src"; | |
| regulator-names = "camss-vdd"; | |
| fw_name = "CAMERA_ICP.elf"; | |
| status = "ok"; | |
| interrupts = <0x00 0x1cf 0x00>; | |
| camss-vdd-supply = <0x1bb>; | |
| ubwc-cfg = <0x7b 0x1ef>; | |
| phandle = <0x97>; | |
| reg = <0xac00000 0x6000 0xac10000 0x8000 0xac18000 0x3000>; | |
| interrupt-names = "a5"; | |
| reg-cam-base = <0x00 0x10000 0x18000>; | |
| cell-index = <0x00>; | |
| clock-cntl-level = "svs\0turbo"; | |
| }; | |
| refgen-regulator@ff1000 { | |
| regulator-enable-ramp-delay = <0x05>; | |
| compatible = "qcom,refgen-regulator"; | |
| proxy-supply = <0x122>; | |
| qcom,proxy-consumer-enable; | |
| status = "ok"; | |
| phandle = <0x122>; | |
| reg = <0xff1000 0x60>; | |
| regulator-name = "refgen"; | |
| }; | |
| cti@7720000 { | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti-cpu7"; | |
| clock-names = "apb_pclk"; | |
| cpu = <0x18>; | |
| phandle = <0x39d>; | |
| arm,primecell-periphid = <0x3b966>; | |
| reg = <0x7720000 0x1000>; | |
| }; | |
| qcom,camera-flash@3 { | |
| compatible = "qcom,camera-flash"; | |
| flash-source = <0x514>; | |
| status = "ok"; | |
| torch-source = <0x515>; | |
| phandle = <0x570>; | |
| reg = <0x03 0x00>; | |
| switch-source = <0x517>; | |
| cell-index = <0x03>; | |
| }; | |
| qcom,msm-audio-ion { | |
| compatible = "qcom,msm-audio-ion"; | |
| qcom,smmu-enabled; | |
| phandle = <0x4c4>; | |
| iommus = <0x29 0x1821 0x00>; | |
| qcom,smmu-version = <0x02>; | |
| qcom,smmu-sid-mask = <0x00 0x0f>; | |
| }; | |
| qcom,cmd-db@861e0000 { | |
| compatible = "qcom,cmd-db"; | |
| phandle = <0x32d>; | |
| reg = <0xc3f000c 0x08>; | |
| }; | |
| cti@6c09000 { | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti-dlmm_cti0"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x383>; | |
| arm,primecell-periphid = <0x3b966>; | |
| reg = <0x6c09000 0x1000>; | |
| }; | |
| spi@a88000 { | |
| compatible = "qcom,spi-geni"; | |
| clocks = <0x22 0x60 0x22 0x6e 0x22 0x6f>; | |
| qcom,wrapper-core = <0x5b>; | |
| reg-names = "se_phys"; | |
| pinctrl-1 = <0x73>; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| status = "disabled"; | |
| #address-cells = <0x01>; | |
| interrupts = <0x00 0x163 0x00>; | |
| #size-cells = <0x00>; | |
| dma-names = "tx\0rx"; | |
| phandle = <0x2e8>; | |
| reg = <0xa88000 0x4000>; | |
| pinctrl-0 = <0x72>; | |
| dmas = <0x5e 0x00 0x02 0x01 0x40 0x00 0x5e 0x01 0x02 0x01 0x40 0x00>; | |
| spi-max-frequency = <0x2faf080>; | |
| pinctrl-names = "default\0sleep"; | |
| }; | |
| tpda@6004000 { | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "tpda-base"; | |
| coresight-name = "coresight-tpda"; | |
| clock-names = "apb_pclk"; | |
| qcom,tc-elem-size = <0x0d 0x20>; | |
| qcom,dsb-elem-size = <0x00 0x20 0x02 0x20 0x03 0x20 0x05 0x20 0x06 0x20 0x0a 0x20 0x0b 0x20 0x0d 0x20>; | |
| phandle = <0x360>; | |
| arm,primecell-periphid = <0x3b969>; | |
| reg = <0x6004000 0x1000>; | |
| qcom,tpda-atid = <0x41>; | |
| qcom,bc-elem-size = <0x0a 0x20 0x0d 0x20>; | |
| qcom,cmb-elem-size = <0x03 0x40 0x07 0x40 0x09 0x40 0x0d 0x40>; | |
| ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@7 { | |
| reg = <0x09>; | |
| endpoint { | |
| remote-endpoint = <0x150>; | |
| phandle = <0x176>; | |
| slave-mode; | |
| }; | |
| }; | |
| port@5 { | |
| reg = <0x06>; | |
| endpoint { | |
| remote-endpoint = <0x14e>; | |
| phandle = <0x16d>; | |
| slave-mode; | |
| }; | |
| }; | |
| port@10 { | |
| reg = <0x0d>; | |
| endpoint { | |
| remote-endpoint = <0x153>; | |
| phandle = <0x175>; | |
| slave-mode; | |
| }; | |
| }; | |
| port@3 { | |
| reg = <0x03>; | |
| endpoint { | |
| remote-endpoint = <0x14c>; | |
| phandle = <0x172>; | |
| slave-mode; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x14a>; | |
| phandle = <0x15e>; | |
| slave-mode; | |
| }; | |
| }; | |
| port@8 { | |
| reg = <0x0a>; | |
| endpoint { | |
| remote-endpoint = <0x151>; | |
| phandle = <0x160>; | |
| slave-mode; | |
| }; | |
| }; | |
| port@6 { | |
| reg = <0x07>; | |
| endpoint { | |
| remote-endpoint = <0x14f>; | |
| phandle = <0x177>; | |
| slave-mode; | |
| }; | |
| }; | |
| port@4 { | |
| reg = <0x05>; | |
| endpoint { | |
| remote-endpoint = <0x14d>; | |
| phandle = <0x159>; | |
| slave-mode; | |
| }; | |
| }; | |
| port@2 { | |
| reg = <0x02>; | |
| endpoint { | |
| remote-endpoint = <0x14b>; | |
| phandle = <0x16a>; | |
| slave-mode; | |
| }; | |
| }; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x149>; | |
| phandle = <0x182>; | |
| }; | |
| }; | |
| port@9 { | |
| reg = <0x0b>; | |
| endpoint { | |
| remote-endpoint = <0x152>; | |
| phandle = <0x15f>; | |
| slave-mode; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_ctrl1@ae96000 { | |
| compatible = "qcom,dsi-ctrl-hw-v2.2"; | |
| clocks = <0x20 0x05 0x20 0x06 0x20 0x07 0x20 0x1c 0x20 0x1d 0x20 0x15>; | |
| reg-names = "dsi_ctrl\0disp_cc_base"; | |
| clock-names = "byte_clk\0byte_clk_rcg\0byte_intf_clk\0pixel_clk\0pixel_clk_rcg\0esc_clk"; | |
| vdda-1p2-supply = <0x2e>; | |
| interrupt-parent = <0x2c>; | |
| interrupts = <0x05 0x00>; | |
| label = "dsi-ctrl-1"; | |
| phandle = <0x2c4>; | |
| reg = <0xae96000 0x400 0xaf08000 0x04>; | |
| qcom,null-insertion-enabled; | |
| cell-index = <0x01>; | |
| qcom,core-supply-entries { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| qcom,core-supply-entry@0 { | |
| qcom,supply-name = "refgen"; | |
| qcom,supply-disable-load = <0x00>; | |
| qcom,supply-max-voltage = <0x00>; | |
| qcom,supply-enable-load = <0x00>; | |
| qcom,supply-min-voltage = <0x00>; | |
| reg = <0x00>; | |
| }; | |
| }; | |
| qcom,ctrl-supply-entries { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| qcom,ctrl-supply-entry@0 { | |
| qcom,supply-name = "vdda-1p2"; | |
| qcom,supply-disable-load = <0x04>; | |
| qcom,supply-max-voltage = <0x124f80>; | |
| qcom,supply-enable-load = <0x5528>; | |
| qcom,supply-min-voltage = <0x124f80>; | |
| reg = <0x00>; | |
| }; | |
| }; | |
| }; | |
| qcom,glink-spi-xprt-wdsp { | |
| compatible = "qcom,glink-spi-xprt"; | |
| qcom,ramp-time = <0x10 0x20 0x30 0x40>; | |
| label = "wdsp"; | |
| qcom,qos-config = <0xe0>; | |
| qcom,remote-fifo-config = <0xdf>; | |
| phandle = <0x321>; | |
| }; | |
| usb_nop_phy { | |
| compatible = "usb-nop-xceiv"; | |
| phandle = <0x4d0>; | |
| }; | |
| rpmh-regulator-ldoa23 { | |
| qcom,supported-modes = <0x02 0x04>; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "ldoa23"; | |
| mboxes = <0x8a 0x00>; | |
| qcom,regulator-type = "pmic4-ldo"; | |
| qcom,mode-threshold-currents = <0x00 0x2710>; | |
| regulator-l23 { | |
| qcom,init-mode = <0x02>; | |
| phandle = <0x349>; | |
| qcom,init-voltage = <0x2dc6c0>; | |
| regulator-min-microvolt = <0x2dc6c0>; | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x328980>; | |
| regulator-name = "pm8998_l23"; | |
| }; | |
| }; | |
| funnel@0x6041000 { | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "funnel-base"; | |
| coresight-name = "coresight-funnel-in0"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x35d>; | |
| arm,primecell-periphid = <0x3b908>; | |
| reg = <0x6041000 0x1000>; | |
| ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@3 { | |
| reg = <0x07>; | |
| endpoint { | |
| remote-endpoint = <0x13f>; | |
| phandle = <0x13b>; | |
| slave-mode; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x03>; | |
| endpoint { | |
| remote-endpoint = <0x13d>; | |
| phandle = <0x17e>; | |
| slave-mode; | |
| }; | |
| }; | |
| port@2 { | |
| reg = <0x06>; | |
| endpoint { | |
| remote-endpoint = <0x13e>; | |
| phandle = <0x181>; | |
| slave-mode; | |
| }; | |
| }; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x13c>; | |
| phandle = <0x139>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| slim@17240000 { | |
| compatible = "qcom,slim-ngd"; | |
| qcom,iommu-s1-bypass; | |
| reg-names = "slimbus_physical\0slimbus_bam_physical"; | |
| status = "ok"; | |
| interrupts = <0x00 0x123 0x00 0x00 0x124 0x00>; | |
| phandle = <0x31c>; | |
| reg = <0x17240000 0x2c000 0x17204000 0x20000>; | |
| interrupt-names = "slimbus_irq\0slimbus_bam_irq"; | |
| cell-index = <0x03>; | |
| qcom,iommu_slim_ctrl_cb { | |
| compatible = "qcom,iommu-slim-ctrl-cb"; | |
| phandle = <0x31d>; | |
| iommus = <0x29 0x1813 0x00>; | |
| }; | |
| wcn3990 { | |
| qcom,btfm-slim-ifd = "btfmslim_slave_ifd"; | |
| compatible = "qcom,btfmslim_slave"; | |
| qcom,btfm-slim-ifd-elemental-addr = [00 00 20 02 17 02]; | |
| phandle = <0x31e>; | |
| elemental-addr = [00 01 20 02 17 02]; | |
| }; | |
| }; | |
| ssusb@a800000 { | |
| qcom,use-pdc-interrupts; | |
| qcom,msm-bus,num-paths = <0x02>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| qcom,core-clk-rate = <0x7f28155>; | |
| compatible = "qcom,dwc-usb3-msm"; | |
| clocks = <0x22 0x9a 0x22 0x13 0x22 0x0a 0x22 0x9c 0x22 0x9e 0x22 0xa9 0x22 0xa4>; | |
| qcom,msm-bus,vectors-KBps = <0x65 0x200 0x00 0x00 0x01 0x2ef 0x00 0x00 0x65 0x200 0x3a980 0xaae60 0x01 0x2ef 0x00 0x9c40>; | |
| resets = <0x22 0x10>; | |
| qcom,smmu-s1-bypass; | |
| reg-names = "core_base\0ahb2phy_base"; | |
| vbus_dwc3-supply = <0x521>; | |
| clock-names = "core_clk\0iface_clk\0bus_aggr_clk\0utmi_clk\0sleep_clk\0cfg_ahb_clk\0xo"; | |
| qcom,core-clk-rate-hs = <0x3f940ab>; | |
| qcom,msm-bus,name = "usb1"; | |
| ranges; | |
| USB3_GDSC-supply = <0x2b7>; | |
| status = "ok"; | |
| #address-cells = <0x01>; | |
| interrupts = <0x00 0x1eb 0x00 0x00 0x87 0x00 0x00 0x1e7 0x00 0x00 0x1ea 0x00>; | |
| #size-cells = <0x01>; | |
| phandle = <0x4d1>; | |
| reg = <0xa800000 0xf8c00 0x88ee000 0x400>; | |
| iommus = <0x29 0x760 0x00>; | |
| reset-names = "core_reset"; | |
| interrupt-names = "dp_hs_phy_irq\0pwr_event_irq\0ss_phy_irq\0dm_hs_phy_irq"; | |
| qcom,dwc-usb3-msm-tx-fifo-size = <0x5328>; | |
| dwc3@a800000 { | |
| usb-phy = <0x2b8 0x2b9>; | |
| compatible = "snps,dwc3"; | |
| snps,disable-clk-gating; | |
| snps,usb3_lpm_capable; | |
| linux,sysdev_is_parent; | |
| tx-fifo-resize; | |
| interrupts = <0x00 0x8a 0x00>; | |
| snps,has-lpm-erratum; | |
| reg = <0xa800000 0xcd00>; | |
| snps,hird-threshold = [10]; | |
| dr_mode = "host"; | |
| usb-core-id = <0x01>; | |
| }; | |
| }; | |
| qcom,smp2pgpio-smp2p-15-in { | |
| compatible = "qcom,smp2pgpio"; | |
| gpio-controller; | |
| #interrupt-cells = <0x02>; | |
| phandle = <0x1b0>; | |
| qcom,entry-name = "smp2p"; | |
| #gpio-cells = <0x02>; | |
| qcom,is-inbound; | |
| qcom,remote-pid = <0x0f>; | |
| interrupt-controller; | |
| }; | |
| qcom,cam-cdm-intf { | |
| compatible = "qcom,cam-cdm-intf"; | |
| cdm-client-names = "vfe\0jpegdma\0jpegenc\0fd\0lrmecdm"; | |
| status = "ok"; | |
| label = "cam-cdm-intf"; | |
| num-hw-cdm = <0x01>; | |
| cell-index = <0x00>; | |
| }; | |
| tpda@78d0000 { | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "tpda-base"; | |
| coresight-name = "coresight-tpda-llm-gold"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x36e>; | |
| arm,primecell-periphid = <0x3b969>; | |
| reg = <0x78d0000 0x1000>; | |
| qcom,tpda-atid = <0x49>; | |
| qcom,cmb-elem-size = <0x00 0x20>; | |
| ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@1 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x168>; | |
| phandle = <0x169>; | |
| slave-mode; | |
| }; | |
| }; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x167>; | |
| phandle = <0x191>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| sensor_etm0 { | |
| compatible = "qcom,coresight-remote-etm"; | |
| coresight-name = "coresight-sensor-etm0"; | |
| qcom,inst-id = <0x08>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x188>; | |
| phandle = <0x12c>; | |
| }; | |
| }; | |
| }; | |
| qcom,msm-core@780000 { | |
| compatible = "qcom,apss-core-ea"; | |
| reg = <0x780000 0x1000>; | |
| }; | |
| qcom,dsi-display@14 { | |
| compatible = "qcom,dsi-display"; | |
| clocks = <0x2bc 0x06 0x2bc 0x09>; | |
| lab-supply = <0x4e2>; | |
| pinctrl-1 = <0x41c 0x41e>; | |
| clock-names = "mux_byte_clk\0mux_pixel_clk"; | |
| vddio-supply = <0x120>; | |
| qcom,dsi-panel = <0x4f1>; | |
| label = "dsi_dual_nt35597_video_display"; | |
| ibb-supply = <0x4e3>; | |
| phandle = <0x54e>; | |
| qcom,dsi-ctrl = <0x2c3 0x2c4>; | |
| qcom,display-type = "primary"; | |
| qcom,panel-mode-gpio = <0x34 0x34 0x00>; | |
| pinctrl-0 = <0x41b 0x41d>; | |
| qcom,dsi-phy = <0x2c5 0x2c6>; | |
| qcom,platform-reset-gpio = <0x34 0x06 0x00>; | |
| pinctrl-names = "panel_active\0panel_suspend"; | |
| }; | |
| qcom,gdsc@0x17d03c { | |
| compatible = "qcom,gdsc"; | |
| status = "ok"; | |
| phandle = <0x1aa>; | |
| reg = <0x17d03c 0x04>; | |
| qcom,no-status-check-on-disable; | |
| qcom,gds-timeout = <0x1f4>; | |
| regulator-name = "hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc"; | |
| }; | |
| qcom,dsi-display@5 { | |
| compatible = "qcom,dsi-display"; | |
| clocks = <0x2bc 0x06 0x2bc 0x09>; | |
| lab-supply = <0x4e2>; | |
| pinctrl-1 = <0x41c 0x41e>; | |
| clock-names = "mux_byte_clk\0mux_pixel_clk"; | |
| vddio-supply = <0x120>; | |
| qcom,dsi-panel = <0x4e8>; | |
| label = "dsi_dual_nt35597_truly_cmd_display"; | |
| ibb-supply = <0x4e3>; | |
| phandle = <0x545>; | |
| qcom,dsi-ctrl = <0x2c3 0x2c4>; | |
| qcom,display-type = "primary"; | |
| qcom,panel-mode-gpio = <0x34 0x34 0x00>; | |
| pinctrl-0 = <0x41b 0x41d>; | |
| qcom,platform-te-gpio = <0x34 0x0a 0x00>; | |
| qcom,dsi-phy = <0x2c5 0x2c6>; | |
| qcom,platform-reset-gpio = <0x34 0x06 0x00>; | |
| pinctrl-names = "panel_active\0panel_suspend"; | |
| }; | |
| rpmh-regulator-ldoa13 { | |
| qcom,supported-modes = <0x02 0x04>; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "ldoa13"; | |
| mboxes = <0x8a 0x00>; | |
| qcom,regulator-type = "pmic4-ldo"; | |
| qcom,mode-threshold-currents = <0x00 0x2710>; | |
| regulator-l13 { | |
| qcom,init-mode = <0x02>; | |
| phandle = <0x341>; | |
| qcom,init-voltage = <0x1b7740>; | |
| regulator-min-microvolt = <0x1b7740>; | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x2d2a80>; | |
| regulator-name = "pm8998_l13"; | |
| }; | |
| }; | |
| qcom,memlat-cpu0 { | |
| compatible = "qcom,devbw"; | |
| qcom,active-only; | |
| qcom,src-dst-ports = <0x01 0x200>; | |
| governor = "powersave"; | |
| qcom,bw-tbl = <0x2fa 0x478 0x6b8 0x826 0xa25 0xb71 0xf27 0x134f 0x172b 0x1ae1>; | |
| phandle = <0x84>; | |
| }; | |
| qrng@793000 { | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| compatible = "qcom,msm-rng"; | |
| clocks = <0x22 0x48>; | |
| qcom,msm-bus,vectors-KBps = <0x01 0x26a 0x00 0x00 0x01 0x26a 0x00 0x493e0>; | |
| clock-names = "iface_clk"; | |
| qcom,no-qrng-config; | |
| qcom,msm-bus,name = "msm-rng-noc"; | |
| qcom,msm-rng-iface-clk; | |
| phandle = <0x324>; | |
| reg = <0x793000 0x1000>; | |
| }; | |
| cti@7020000 { | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti-cpu0"; | |
| clock-names = "apb_pclk"; | |
| cpu = <0x11>; | |
| phandle = <0x396>; | |
| arm,primecell-periphid = <0x3b966>; | |
| reg = <0x7020000 0x1000>; | |
| }; | |
| qcom,msm-audio-apr { | |
| compatible = "qcom,msm-audio-apr"; | |
| phandle = <0x4c0>; | |
| qcom,subsys-name = "apr_adsp"; | |
| sound-tavil { | |
| asoc-platform = <0x271 0x272 0x273 0x274 0x275 0x276 0x277 0x278 0x279 0x27a 0x27b 0x27c 0x27d>; | |
| qcom,msm-mbhc-hs-mic-max-threshold-mv = <0x6a4>; | |
| asoc-codec-names = "msm-stub-codec.1\0msm-ext-disp-audio-codec-rx"; | |
| qcom,tavil-mclk-clk-freq = <0x927c00>; | |
| compatible = "qcom,sdm845-asoc-snd-tavil"; | |
| qcom,audio-routing = "AIF4 VI\0MCLK\0RX_BIAS\0MCLK\0MADINPUT\0MCLK\0hifi amp\0LINEOUT1\0hifi amp\0LINEOUT2\0AMIC1\0MIC BIAS1\0MIC BIAS1\0Handset Mic\0AMIC2\0MIC BIAS2\0MIC BIAS2\0Headset Mic\0AMIC3\0MIC BIAS3\0MIC BIAS3\0ANCRight Headset Mic\0AMIC4\0MIC BIAS4\0MIC BIAS4\0ANCLeft Headset Mic\0AMIC5\0MIC BIAS1\0MIC BIAS1\0Handset Mic\0DMIC0\0MIC BIAS1\0MIC BIAS1\0Digital Mic0\0DMIC1\0MIC BIAS1\0MIC BIAS1\0Digital Mic1\0DMIC2\0MIC BIAS3\0MIC BIAS3\0Digital Mic2\0DMIC3\0MIC BIAS3\0MIC BIAS3\0Digital Mic3\0DMIC4\0MIC BIAS4\0MIC BIAS4\0Digital Mic4\0DMIC5\0MIC BIAS4\0MIC BIAS4\0Digital Mic5\0SpkrLeft IN\0SPK1 OUT\0SpkrRight IN\0SPK2 OUT"; | |
| qcom,auxpcm-audio-intf; | |
| pinctrl-1 = <0x410>; | |
| asoc-codec = <0x4b4 0x530>; | |
| qcom,wsa-devs = <0x532 0x533 0x534 0x535>; | |
| qcom,msm-mi2s-master = <0x01 0x01 0x01 0x01>; | |
| qcom,model = "sdm845-tavil-snd-card"; | |
| status = "okay"; | |
| qcom,msm-mbhc-gnd-swh = <0x01>; | |
| qcom,usbc-analog-en2-gpio = <0x34 0x33 0x00>; | |
| asoc-cpu-names = "msm-dai-q6-hdmi.8\0msm-dai-q6-dp.24608\0msm-dai-q6-mi2s.0\0msm-dai-q6-mi2s.1\0msm-dai-q6-mi2s.2\0msm-dai-q6-mi2s.3\0msm-dai-q6-auxpcm.1\0msm-dai-q6-auxpcm.2\0msm-dai-q6-auxpcm.3\0msm-dai-q6-auxpcm.4\0msm-dai-q6-dev.16384\0msm-dai-q6-dev.16385\0msm-dai-q6-dev.16386\0msm-dai-q6-dev.16387\0msm-dai-q6-dev.16388\0msm-dai-q6-dev.16389\0msm-dai-q6-dev.16390\0msm-dai-q6-dev.16391\0msm-dai-q6-dev.16392\0msm-dai-q6-dev.16393\0msm-dai-q6-dev.16395\0msm-dai-q6-dev.224\0msm-dai-q6-dev.225\0msm-dai-q6-dev.241\0msm-dai-q6-dev.240\0msm-dai-q6-dev.32771\0msm-dai-q6-dev.32772\0msm-dai-q6-dev.32773\0msm-dai-q6-dev.32770\0msm-dai-q6-dev.16394\0msm-dai-q6-dev.16396\0msm-dai-q6-dev.16398\0msm-dai-q6-dev.16399\0msm-dai-q6-dev.16401\0msm-dai-q6-dev.28672\0msm-dai-q6-dev.28673\0msm-dai-q6-tdm.36864\0msm-dai-q6-tdm.36865\0msm-dai-q6-tdm.36880\0msm-dai-q6-tdm.36881\0msm-dai-q6-tdm.36896\0msm-dai-q6-tdm.36897\0msm-dai-q6-tdm.36912\0msm-dai-q6-tdm.36913\0msm-dai-q6-tdm.36914"; | |
| qcom,hph-en1-gpio = <0x52f>; | |
| qcom,mi2s-audio-intf; | |
| phandle = <0x4c1>; | |
| qcom,usbc-analog-en1-gpio = <0x531>; | |
| qcom,wcn-btfm; | |
| qcom,msm-mbhc-hs-mic-min-threshold-mv = <0x32>; | |
| qcom,hph-en0-gpio = <0x52e>; | |
| pinctrl-0 = <0x411>; | |
| asoc-platform-names = "msm-pcm-dsp.0\0msm-pcm-dsp.1\0msm-pcm-dsp.2\0msm-voip-dsp\0msm-pcm-voice\0msm-pcm-loopback\0msm-compress-dsp\0msm-pcm-hostless\0msm-pcm-afe\0msm-lsm-client\0msm-pcm-routing\0msm-compr-dsp\0msm-pcm-dsp-noirq"; | |
| qcom,msm-mbhc-hphl-swh = <0x01>; | |
| qcom,ext-disp-audio-rx; | |
| qcom,wsa-max-devs = <0x02>; | |
| qcom,wsa-aux-dev-prefix = "SpkrLeft\0SpkrRight\0SpkrLeft\0SpkrRight"; | |
| asoc-cpu = <0x27e 0x27f 0x280 0x281 0x282 0x283 0x284 0x285 0x286 0x287 0x288 0x289 0x28a 0x28b 0x28c 0x28d 0x28e 0x28f 0x290 0x291 0x292 0x293 0x294 0x295 0x296 0x297 0x298 0x299 0x29a 0x29b 0x29c 0x29d 0x29e 0x29f 0x2a0 0x2a1 0x2a2 0x2a3 0x2a4 0x2a5 0x2a6 0x2a7 0x2a8 0x2a9 0x2aa>; | |
| pinctrl-names = "aud_active\0aud_sleep"; | |
| }; | |
| }; | |
| qcom,wdt@17980000 { | |
| qcom,wakeup-enable; | |
| compatible = "qcom,msm-watchdog"; | |
| qcom,pet-time = <0x2490>; | |
| qcom,ipi-ping; | |
| reg-names = "wdt-base"; | |
| interrupts = <0x00 0x00 0x00 0x00 0x01 0x00>; | |
| qcom,bark-time = <0x2af8>; | |
| phandle = <0x31f>; | |
| reg = <0x17980000 0x1000>; | |
| }; | |
| funnel_1@6861000 { | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "funnel-base-dummy\0funnel-base-real"; | |
| coresight-name = "coresight-funnel-turing-1"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x373>; | |
| arm,primecell-periphid = <0x3b908>; | |
| reg = <0x6867000 0x10 0x6861000 0x1000>; | |
| qcom,duplicate-funnel; | |
| ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@1 { | |
| reg = <0x01>; | |
| endpoint { | |
| remote-endpoint = <0x170>; | |
| phandle = <0x186>; | |
| slave-mode; | |
| }; | |
| }; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x16f>; | |
| phandle = <0x184>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,csiphy@ac66000 { | |
| phandle = <0x8e>; | |
| }; | |
| tpda@6b01000 { | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "tpda-base"; | |
| coresight-name = "coresight-tpda-swao"; | |
| clock-names = "apb_pclk"; | |
| qcom,dsb-elem-size = <0x01 0x20>; | |
| phandle = <0x355>; | |
| arm,primecell-periphid = <0x3b969>; | |
| reg = <0x6b01000 0x1000>; | |
| qcom,tpda-atid = <0x47>; | |
| qcom,cmb-elem-size = <0x00 0x40>; | |
| ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@1 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x12f>; | |
| phandle = <0x131>; | |
| slave-mode; | |
| }; | |
| }; | |
| port@2 { | |
| reg = <0x01>; | |
| endpoint { | |
| remote-endpoint = <0x130>; | |
| phandle = <0x132>; | |
| slave-mode; | |
| }; | |
| }; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x12e>; | |
| phandle = <0x12d>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| cti@6017000 { | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti7"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x38e>; | |
| arm,primecell-periphid = <0x3b966>; | |
| reg = <0x6017000 0x1000>; | |
| }; | |
| qcom,dispcc@af00000 { | |
| compatible = "qcom,dispcc-sdm845-v2\0syscon"; | |
| #reset-cells = <0x01>; | |
| reg-names = "cc_base"; | |
| vdd_cx-supply = <0x1b>; | |
| #clock-cells = <0x01>; | |
| phandle = <0x20>; | |
| reg = <0xaf00000 0x10000>; | |
| }; | |
| funnel@6005000 { | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "funnel-base"; | |
| coresight-name = "coresight-funnel-qatb"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x37f>; | |
| arm,primecell-periphid = <0x3b908>; | |
| reg = <0x6005000 0x1000>; | |
| ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@3 { | |
| reg = <0x07>; | |
| endpoint { | |
| remote-endpoint = <0x184>; | |
| phandle = <0x16f>; | |
| slave-mode; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x182>; | |
| phandle = <0x149>; | |
| slave-mode; | |
| }; | |
| }; | |
| port@2 { | |
| reg = <0x06>; | |
| endpoint { | |
| remote-endpoint = <0x183>; | |
| phandle = <0x15b>; | |
| slave-mode; | |
| }; | |
| }; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x181>; | |
| phandle = <0x13e>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,csid-lite@acc8000 { | |
| clock-rates = <0x00 0x00 0x00 0x00 0x00 0x00 0x16e36000 0x00 0x00 0x00 0x18148d00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x20113a80 0x00 0x00 0x00 0x23c34600 0x00>; | |
| compatible = "qcom,csid-lite170"; | |
| clocks = <0x22 0x0c 0x22 0x0d 0xa5 0x55 0xa5 0x09 0xa5 0x54 0xa5 0x32 0xa5 0x33 0xa5 0x31 0xa5 0x0a 0xa5 0x2f 0xa5 0x30 0xa5 0x06>; | |
| reg-names = "csid-lite"; | |
| clock-control-debugfs = "true"; | |
| clock-names = "camera_ahb\0camera_axi\0soc_ahb_clk\0cpas_ahb_clk\0slow_ahb_clk_src\0ife_csid_clk\0ife_csid_clk_src\0ife_cphy_rx_clk\0cphy_rx_clk_src\0ife_clk\0ife_clk_src\0camnoc_axi_clk"; | |
| regulator-names = "camss"; | |
| status = "ok"; | |
| interrupts = <0x00 0x1d4 0x00>; | |
| phandle = <0x95>; | |
| reg = <0xacc8000 0x1000>; | |
| src-clock-name = "ife_csid_clk_src"; | |
| interrupt-names = "csid-lite"; | |
| reg-cam-base = <0xc8000>; | |
| cell-index = <0x02>; | |
| camss-supply = <0x1bb>; | |
| clock-cntl-level = "svs\0turbo"; | |
| }; | |
| tpdm@6850000 { | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "tpdm-base"; | |
| coresight-name = "coresight-tpdm-pimem"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x377>; | |
| arm,primecell-periphid = <0x3b968>; | |
| reg = <0x6850000 0x1000>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x175>; | |
| phandle = <0x153>; | |
| }; | |
| }; | |
| }; | |
| qcom,smp2pgpio-sleepstate-3-out { | |
| gpios = <0x1ba 0x00 0x00>; | |
| compatible = "qcom,smp2pgpio_sleepstate_3_out"; | |
| }; | |
| cti@6014000 { | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti4"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x38b>; | |
| arm,primecell-periphid = <0x3b966>; | |
| reg = <0x6014000 0x1000>; | |
| }; | |
| qusb@88e2000 { | |
| qcom,efuse-bit-pos = <0x19>; | |
| compatible = "qcom,qusb2phy-v2"; | |
| clocks = <0x21 0x00 0x22 0xa9>; | |
| resets = <0x22 0x08>; | |
| qcom,qusb-phy-init-seq = <0x23 0x210 0x03 0x04 0x7c 0x18c 0x80 0x2c 0x0a 0x184 0x19 0xb4 0x40 0x194 0x20 0x198 0x21 0x214 0x08 0x220 0x58 0x224 0x45 0x240 0x29 0x244 0xca 0x248 0x04 0x24c 0x03 0x250 0x00 0x23c 0x22 0x210>; | |
| reg-names = "qusb_phy_base\0efuse_addr\0refgen_north_bg_reg_addr"; | |
| pinctrl-1 = <0x2b6>; | |
| clock-names = "ref_clk_src\0cfg_ahb_clk"; | |
| qcom,override-bias-ctrl2; | |
| vdda18-supply = <0x121>; | |
| qcom,efuse-num-bits = <0x03>; | |
| qcom,qusb-phy-reg-offset = <0x240 0x1a0 0x210 0x230 0xa8 0x254 0x198 0x228 0x22c 0x27c 0x280 0x284 0x288 0x2a0>; | |
| qcom,vdd-voltage-level = <0x00 0xd6d80 0xd6d80>; | |
| phandle = <0x2b3>; | |
| vdd-supply = <0x2f>; | |
| reg = <0x88e2000 0x400 0x7801e8 0x04 0x88e7014 0x04>; | |
| vdda33-supply = <0xba>; | |
| pinctrl-0 = <0x2b5>; | |
| reset-names = "phy_reset"; | |
| pinctrl-names = "atest_usb13_suspend\0atest_usb13_active"; | |
| phy_type = "utmi"; | |
| }; | |
| qcom,smp2pgpio-ssr-smp2p-1-in { | |
| compatible = "qcom,smp2pgpio"; | |
| gpio-controller; | |
| #interrupt-cells = <0x02>; | |
| phandle = <0xaf>; | |
| qcom,entry-name = "slave-kernel"; | |
| #gpio-cells = <0x02>; | |
| qcom,is-inbound; | |
| qcom,remote-pid = <0x01>; | |
| interrupt-controller; | |
| }; | |
| qcom,msm_fastrpc { | |
| compatible = "qcom,msm-fastrpc-compute"; | |
| qcom,rpc-latency-us = <0x263>; | |
| qcom,msm_fastrpc_compute_cb11 { | |
| compatible = "qcom,msm-fastrpc-compute-cb"; | |
| dma-coherent; | |
| label = "adsprpc-smd"; | |
| iommus = <0x29 0x1823 0x00>; | |
| }; | |
| qcom,msm_fastrpc_compute_cb8 { | |
| compatible = "qcom,msm-fastrpc-compute-cb"; | |
| dma-coherent; | |
| label = "cdsprpc-smd"; | |
| iommus = <0x29 0x1408 0x30>; | |
| }; | |
| qcom,msm_fastrpc_compute_cb6 { | |
| compatible = "qcom,msm-fastrpc-compute-cb"; | |
| dma-coherent; | |
| label = "cdsprpc-smd"; | |
| iommus = <0x29 0x1406 0x30>; | |
| }; | |
| qcom,msm_fastrpc_compute_cb4 { | |
| compatible = "qcom,msm-fastrpc-compute-cb"; | |
| dma-coherent; | |
| label = "cdsprpc-smd"; | |
| iommus = <0x29 0x1404 0x30>; | |
| }; | |
| qcom,msm_fastrpc_compute_cb2 { | |
| compatible = "qcom,msm-fastrpc-compute-cb"; | |
| dma-coherent; | |
| label = "cdsprpc-smd"; | |
| iommus = <0x29 0x1402 0x30>; | |
| }; | |
| qcom,msm_fastrpc_compute_cb12 { | |
| compatible = "qcom,msm-fastrpc-compute-cb"; | |
| dma-coherent; | |
| label = "adsprpc-smd"; | |
| iommus = <0x29 0x1824 0x00>; | |
| }; | |
| qcom,msm_fastrpc_compute_cb9 { | |
| compatible = "qcom,msm-fastrpc-compute-cb"; | |
| dma-coherent; | |
| label = "cdsprpc-smd"; | |
| iommus = <0x29 0x1409 0x30>; | |
| qcom,secure-context-bank; | |
| }; | |
| qcom,msm_fastrpc_compute_cb10 { | |
| compatible = "qcom,msm-fastrpc-compute-cb"; | |
| dma-coherent; | |
| label = "cdsprpc-smd"; | |
| iommus = <0x29 0x140a 0x30>; | |
| qcom,secure-context-bank; | |
| }; | |
| qcom,msm_fastrpc_compute_cb7 { | |
| compatible = "qcom,msm-fastrpc-compute-cb"; | |
| dma-coherent; | |
| label = "cdsprpc-smd"; | |
| iommus = <0x29 0x1407 0x30>; | |
| }; | |
| qcom,msm_fastrpc_compute_cb5 { | |
| compatible = "qcom,msm-fastrpc-compute-cb"; | |
| dma-coherent; | |
| label = "cdsprpc-smd"; | |
| iommus = <0x29 0x1405 0x30>; | |
| }; | |
| qcom,msm_fastrpc_compute_cb3 { | |
| compatible = "qcom,msm-fastrpc-compute-cb"; | |
| dma-coherent; | |
| label = "cdsprpc-smd"; | |
| iommus = <0x29 0x1403 0x30>; | |
| }; | |
| qcom,msm_fastrpc_compute_cb1 { | |
| compatible = "qcom,msm-fastrpc-compute-cb"; | |
| dma-coherent; | |
| label = "cdsprpc-smd"; | |
| iommus = <0x29 0x1401 0x30>; | |
| }; | |
| }; | |
| qcom,ipc-spinlock@1f40000 { | |
| compatible = "qcom,ipc-spinlock-sfpb"; | |
| qcom,num-locks = <0x08>; | |
| reg = <0x1f40000 0x8000>; | |
| }; | |
| qcom,lpass@17300000 { | |
| qcom,proxy-timeout-ms = <0x2710>; | |
| compatible = "qcom,pil-tz-generic"; | |
| qcom,vdd_cx-uV-uA = <0x181 0x186a0>; | |
| clocks = <0x21 0x00>; | |
| qcom,proxy-clock-names = "xo"; | |
| qcom,firmware-name = "adsp"; | |
| qcom,gpio-proxy-unvote = <0xb3 0x02 0x00>; | |
| qcom,gpio-stop-ack = <0xb3 0x03 0x00>; | |
| clock-names = "xo"; | |
| qcom,gpio-err-ready = <0xb3 0x01 0x00>; | |
| qcom,smem-id = <0x1a7>; | |
| qcom,pas-id = <0x01>; | |
| qcom,gpio-err-fatal = <0xb3 0x00 0x00>; | |
| vdd_cx-supply = <0x1b>; | |
| status = "ok"; | |
| interrupts = <0x00 0xa2 0x01>; | |
| mbox-names = "adsp-pil"; | |
| memory-region = <0xb2>; | |
| mboxes = <0x80 0x00>; | |
| qcom,proxy-reg-names = "vdd_cx"; | |
| qcom,ssctl-instance-id = <0x14>; | |
| reg = <0x17300000 0x100>; | |
| qcom,signal-aop; | |
| qcom,gpio-force-stop = <0xb4 0x00 0x00>; | |
| qcom,sysmon-id = <0x01>; | |
| }; | |
| etm@7340000 { | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| coresight-name = "coresight-etm3"; | |
| clock-names = "apb_pclk"; | |
| cpu = <0x14>; | |
| phandle = <0x3a5>; | |
| arm,primecell-periphid = <0xbb95d>; | |
| reg = <0x7340000 0x1000>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x195>; | |
| phandle = <0x19e>; | |
| }; | |
| }; | |
| }; | |
| rpmh-regulator-ldoa5 { | |
| qcom,supported-modes = <0x02 0x04>; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "ldoa5"; | |
| mboxes = <0x8a 0x00>; | |
| qcom,regulator-type = "pmic4-ldo"; | |
| qcom,mode-threshold-currents = <0x00 0x01>; | |
| regulator-l5 { | |
| qcom,init-mode = <0x02>; | |
| phandle = <0xeb>; | |
| qcom,init-voltage = "\0\f5"; | |
| regulator-min-microvolt = "\0\f5"; | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = "\0\f5"; | |
| regulator-name = "pm8998_l5"; | |
| }; | |
| }; | |
| qocm,wcd-dsp-glink { | |
| compatible = "qcom,wcd-dsp-glink"; | |
| }; | |
| qcom,smp2pgpio-smp2p-1-in { | |
| compatible = "qcom,smp2pgpio"; | |
| gpio-controller; | |
| #interrupt-cells = <0x02>; | |
| phandle = <0x1b2>; | |
| qcom,entry-name = "smp2p"; | |
| #gpio-cells = <0x02>; | |
| qcom,is-inbound; | |
| qcom,remote-pid = <0x01>; | |
| interrupt-controller; | |
| }; | |
| qcom,memshare { | |
| compatible = "qcom,memshare"; | |
| qcom,client_1 { | |
| compatible = "qcom,memshare-peripheral"; | |
| qcom,peripheral-size = <0x00>; | |
| label = "modem"; | |
| qcom,client-id = <0x00>; | |
| qcom,allocate-boot-time; | |
| }; | |
| qcom,client_2 { | |
| compatible = "qcom,memshare-peripheral"; | |
| qcom,peripheral-size = <0x00>; | |
| label = "modem"; | |
| qcom,client-id = <0x02>; | |
| }; | |
| qcom,client_3 { | |
| compatible = "qcom,memshare-peripheral"; | |
| qcom,peripheral-size = <0x500000>; | |
| label = "modem"; | |
| qcom,client-id = <0x01>; | |
| qcom,allocate-on-request; | |
| phandle = <0x4d3>; | |
| }; | |
| }; | |
| mailbox@179e0000 { | |
| compatible = "qcom,tcs-drv"; | |
| qcom,drv-id = <0x02>; | |
| #mbox-cells = <0x01>; | |
| interrupts = <0x00 0x05 0x00>; | |
| label = "apps_rsc"; | |
| phandle = <0x8a>; | |
| reg = <0x179e0000 0x100 0x179e0d00 0x3000>; | |
| qcom,tcs-config = <0x02 0x02 0x00 0x03 0x01 0x03 0x03 0x01>; | |
| }; | |
| qcom,smp2pgpio_test_smp2p_15_in { | |
| gpios = <0x1b0 0x00 0x00>; | |
| compatible = "qcom,smp2pgpio_test_smp2p_15_in"; | |
| }; | |
| rpmh-regulator-ebilvl { | |
| compatible = "qcom,rpmh-arc-regulator"; | |
| qcom,resource-name = "ebi.lvl"; | |
| mboxes = <0x8a 0x00>; | |
| regulator-cdev { | |
| compatible = "qcom,rpmh-reg-cdev"; | |
| mboxes = <0x80 0x00>; | |
| phandle = <0x102>; | |
| qcom,reg-resource-name = "ebi"; | |
| #cooling-cells = <0x02>; | |
| }; | |
| regulator-s1 { | |
| phandle = <0x337>; | |
| regulator-min-microvolt = <0x01>; | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x10000>; | |
| regulator-name = "pm8998_s1_level"; | |
| }; | |
| }; | |
| qcom,gdsc@0x16b004 { | |
| compatible = "qcom,gdsc"; | |
| status = "ok"; | |
| phandle = <0x265>; | |
| reg = <0x16b004 0x04>; | |
| regulator-name = "pcie_0_gdsc"; | |
| qcom,poll-cfg-gdscr; | |
| }; | |
| qcom,camera-flash@1 { | |
| compatible = "qcom,camera-flash"; | |
| flash-source = <0x50f 0x510>; | |
| status = "ok"; | |
| torch-source = <0x511 0x512>; | |
| phandle = <0x56e>; | |
| reg = <0x01 0x00>; | |
| switch-source = <0x513>; | |
| cell-index = <0x01>; | |
| }; | |
| funnel@6045000 { | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "funnel-base"; | |
| coresight-name = "coresight-funnel-merg"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x35a>; | |
| arm,primecell-periphid = <0x3b908>; | |
| reg = <0x6045000 0x1000>; | |
| ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@1 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x139>; | |
| phandle = <0x13c>; | |
| slave-mode; | |
| }; | |
| }; | |
| port@2 { | |
| reg = <0x02>; | |
| endpoint { | |
| remote-endpoint = <0x13a>; | |
| phandle = <0x140>; | |
| slave-mode; | |
| }; | |
| }; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x138>; | |
| phandle = <0x137>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| jtagmm@7140000 { | |
| compatible = "qcom,jtagv8-mm"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "etm-base"; | |
| clock-names = "core_clk"; | |
| phandle = <0x2ef>; | |
| reg = <0x7140000 0x1000>; | |
| qcom,coresight-jtagmm-cpu = <0x12>; | |
| }; | |
| cti@6011000 { | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti1"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x388>; | |
| arm,primecell-periphid = <0x3b966>; | |
| reg = <0x6011000 0x1000>; | |
| }; | |
| qcom,smp2pgpio_client_rdbg_1_in { | |
| gpios = <0x25 0x00 0x00>; | |
| compatible = "qcom,smp2pgpio_client_rdbg_1_in"; | |
| }; | |
| rpmh-regulator-mxlvl { | |
| compatible = "qcom,rpmh-arc-regulator"; | |
| qcom,resource-name = "mx.lvl"; | |
| mboxes = <0x8a 0x00>; | |
| regulator-s6-level-ao { | |
| phandle = <0x9e>; | |
| regulator-min-microvolt = <0x01>; | |
| qcom,set = <0x01>; | |
| regulator-max-microvolt = <0x10000>; | |
| regulator-name = "pm8998_s6_level_ao"; | |
| }; | |
| regulator-s6-level { | |
| phandle = <0x8c>; | |
| regulator-min-microvolt = <0x01>; | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x10000>; | |
| regulator-name = "pm8998_s6_level"; | |
| }; | |
| mx-cdev-lvl { | |
| regulator-cdev-supply = <0x8c>; | |
| compatible = "qcom,regulator-cooling-device"; | |
| regulator-levels = <0x101 0x01>; | |
| phandle = <0x101>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| }; | |
| cti@78e0000 { | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti-apss_cti0"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x385>; | |
| arm,primecell-periphid = <0x3b966>; | |
| reg = <0x78e0000 0x1000>; | |
| }; | |
| rpmh-regulator-ldoa21 { | |
| qcom,supported-modes = <0x02 0x04>; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "ldoa21"; | |
| mboxes = <0x8a 0x00>; | |
| qcom,regulator-type = "pmic4-ldo"; | |
| qcom,mode-threshold-currents = <0x00 0x2710>; | |
| regulator-l21 { | |
| qcom,init-mode = <0x02>; | |
| phandle = <0x347>; | |
| qcom,init-voltage = <0x294280>; | |
| regulator-min-microvolt = <0x294280>; | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x2d2a80>; | |
| regulator-name = "pm8998_l21"; | |
| }; | |
| }; | |
| spss_etm0 { | |
| compatible = "qcom,coresight-dummy"; | |
| coresight-name = "coresight-spss-etm0"; | |
| qcom,dummy-source; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x18b>; | |
| phandle = <0x180>; | |
| }; | |
| }; | |
| }; | |
| gpio_keys { | |
| compatible = "gpio-keys"; | |
| label = "gpio-keys"; | |
| pinctrl-0 = <0x2fa 0x2fb>; | |
| pinctrl-names = "default"; | |
| vol_up { | |
| gpios = <0xe6 0x06 0x01>; | |
| linux,can-disable; | |
| debounce-interval = <0x0f>; | |
| label = "volume_up"; | |
| linux,input-type = <0x01>; | |
| gpio-key,wakeup; | |
| linux,code = <0x73>; | |
| }; | |
| cam_snapshot { | |
| gpios = <0xe6 0x07 0x01>; | |
| linux,can-disable; | |
| debounce-interval = <0x0f>; | |
| label = "cam_snapshot"; | |
| linux,input-type = <0x01>; | |
| gpio-key,wakeup; | |
| linux,code = <0x2fe>; | |
| }; | |
| }; | |
| qcom,gcc@100000 { | |
| compatible = "qcom,gcc-sdm845-v2.1\0syscon"; | |
| #reset-cells = <0x01>; | |
| reg-names = "cc_base"; | |
| vdd_cx-supply = <0x1b>; | |
| #clock-cells = <0x01>; | |
| phandle = <0x22>; | |
| reg = <0x100000 0x1f0000>; | |
| vdd_cx_ao-supply = <0x8b>; | |
| }; | |
| qcom,ipc_router { | |
| compatible = "qcom,ipc_router"; | |
| qcom,node-id = <0x01>; | |
| }; | |
| tpdm@78b0000 { | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "tpdm-base"; | |
| coresight-name = "coresight-tpdm-llm-gold"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x36f>; | |
| arm,primecell-periphid = <0x3b968>; | |
| reg = <0x78b0000 0x1000>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x169>; | |
| phandle = <0x168>; | |
| }; | |
| }; | |
| }; | |
| replicator@6b0a000 { | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "replicator-base"; | |
| coresight-name = "coresight-replicator-swao"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x352>; | |
| arm,primecell-periphid = <0x3b909>; | |
| reg = <0x6b0a000 0x1000>; | |
| ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@1 { | |
| reg = <0x01>; | |
| endpoint { | |
| remote-endpoint = <0x126>; | |
| phandle = <0x187>; | |
| }; | |
| }; | |
| port@2 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x127>; | |
| phandle = <0x142>; | |
| }; | |
| }; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x125>; | |
| phandle = <0x129>; | |
| slave-mode; | |
| }; | |
| }; | |
| }; | |
| }; | |
| tpdm@6c08000 { | |
| qcom,msr-fix-req; | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "tpdm-base"; | |
| coresight-name = "coresight-tpdm-mm"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x371>; | |
| arm,primecell-periphid = <0x3b968>; | |
| reg = <0x6c08000 0x1000>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x16c>; | |
| phandle = <0x16b>; | |
| }; | |
| }; | |
| }; | |
| qcom,gdsc@0xad08004 { | |
| compatible = "qcom,gdsc"; | |
| qcom,support-hw-trigger; | |
| status = "ok"; | |
| phandle = <0x1c4>; | |
| reg = <0xad08004 0x04>; | |
| regulator-name = "ipe_1_gdsc"; | |
| qcom,poll-cfg-gdscr; | |
| }; | |
| qcom,dsi-display@12 { | |
| compatible = "qcom,dsi-display"; | |
| clocks = <0x2bc 0x06 0x2bc 0x09>; | |
| pinctrl-1 = <0x41c 0x41e>; | |
| clock-names = "mux_byte_clk\0mux_pixel_clk"; | |
| qcom,dsi-panel = <0x4ef>; | |
| label = "dsi_sim_dsc_375_cmd_display"; | |
| phandle = <0x54c>; | |
| qcom,dsi-ctrl = <0x2c3>; | |
| qcom,display-type = "primary"; | |
| pinctrl-0 = <0x41b 0x41d>; | |
| qcom,dsi-phy = <0x2c5>; | |
| pinctrl-names = "panel_active\0panel_suspend"; | |
| }; | |
| qcom,dsi-display@3 { | |
| compatible = "qcom,dsi-display"; | |
| clocks = <0x2bc 0x06 0x2bc 0x09>; | |
| lab-supply = <0x4e2>; | |
| pinctrl-1 = <0x41c 0x41e>; | |
| clock-names = "mux_byte_clk\0mux_pixel_clk"; | |
| vddio-supply = <0x120>; | |
| qcom,dsi-panel = <0x4e6>; | |
| label = "dsi_dual_sharp_1080_120hz_cmd_display"; | |
| ibb-supply = <0x4e3>; | |
| phandle = <0x543>; | |
| qcom,dsi-ctrl = <0x2c3 0x2c4>; | |
| qcom,display-type = "primary"; | |
| qcom,panel-mode-gpio = <0x34 0x34 0x00>; | |
| pinctrl-0 = <0x41b 0x41d>; | |
| qcom,platform-te-gpio = <0x34 0x0a 0x00>; | |
| qcom,dsi-phy = <0x2c5 0x2c6>; | |
| qcom,platform-reset-gpio = <0x34 0x06 0x00>; | |
| pinctrl-names = "panel_active\0panel_suspend"; | |
| }; | |
| rpmh-regulator-ldoa11 { | |
| qcom,supported-modes = <0x02 0x04>; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "ldoa11"; | |
| mboxes = <0x8a 0x00>; | |
| qcom,regulator-type = "pmic4-ldo"; | |
| qcom,mode-threshold-currents = <0x00 0x01>; | |
| regulator-l11 { | |
| qcom,init-mode = <0x02>; | |
| phandle = <0x340>; | |
| qcom,init-voltage = <0xf4240>; | |
| regulator-min-microvolt = <0xf4240>; | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0xffdc0>; | |
| regulator-name = "pm8998_l11"; | |
| }; | |
| }; | |
| tsens@c223000 { | |
| compatible = "qcom,sdm845-tsens"; | |
| reg-names = "tsens_srot_physical\0tsens_tm_physical"; | |
| #thermal-sensor-cells = <0x01>; | |
| interrupts = <0x00 0x1fb 0x00 0x00 0x1fd 0x00>; | |
| phandle = <0xf0>; | |
| reg = <0xc223000 0x04 0xc265000 0x1ff>; | |
| interrupt-names = "tsens-upper-lower\0tsens-critical"; | |
| }; | |
| qcom,mdss_dsi_phy0@ae94400 { | |
| compatible = "qcom,dsi-phy-v3.0"; | |
| reg-names = "dsi_phy"; | |
| qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; | |
| qcom,platform-strength-ctrl = [55 03 55 03 55 03 55 03 55 00]; | |
| gdsc-supply = <0x19>; | |
| label = "dsi-phy-0"; | |
| phandle = <0x2c5>; | |
| reg = <0xae94400 0x7c0>; | |
| vdda-0p9-supply = <0x2f>; | |
| cell-index = <0x00>; | |
| qcom,platform-lane-config = <0x00 0x00 0x00 0x00 0x80>; | |
| qcom,phy-supply-entries { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| qcom,phy-supply-entry@0 { | |
| qcom,supply-name = "vdda-0p9"; | |
| qcom,supply-disable-load = <0x20>; | |
| qcom,supply-max-voltage = <0xd6d80>; | |
| qcom,supply-enable-load = <0x8ca0>; | |
| qcom,supply-min-voltage = <0xd6d80>; | |
| reg = <0x00>; | |
| }; | |
| }; | |
| }; | |
| tpdm@69d0000 { | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "tpdm-base"; | |
| coresight-name = "coresight-tpdm-qm"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x369>; | |
| arm,primecell-periphid = <0x3b968>; | |
| reg = <0x69d0000 0x1000>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x160>; | |
| phandle = <0x151>; | |
| }; | |
| }; | |
| }; | |
| dummy_sink { | |
| compatible = "qcom,coresight-dummy"; | |
| coresight-name = "coresight-eud"; | |
| phandle = <0x3a0>; | |
| qcom,dummy-sink; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x187>; | |
| phandle = <0x126>; | |
| slave-mode; | |
| }; | |
| }; | |
| }; | |
| qcom,gdsc@0x509106c { | |
| compatible = "qcom,gdsc"; | |
| hw-ctrl-addr = <0x1a>; | |
| status = "ok"; | |
| parent-supply = <0x1b>; | |
| phandle = <0x1a3>; | |
| vdd_parent-supply = <0x1b>; | |
| reg = <0x509106c 0x04>; | |
| qcom,no-status-check-on-disable; | |
| qcom,gds-timeout = <0x1f4>; | |
| regulator-name = "gpu_cx_gdsc"; | |
| qcom,clk-dis-wait-val = <0x08>; | |
| }; | |
| qcom,ipe0 { | |
| clock-rates = <0x00 0x00 0x00 0x00 0x18148d00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x20113a80 0x00 0x00 0x00 0x00 0x23c34600>; | |
| compatible = "qcom,cam-ipe"; | |
| clocks = <0xa5 0x34 0xa5 0x35 0xa5 0x36 0xa5 0x37 0xa5 0x38>; | |
| reg-names = "ipe0_top"; | |
| clock-control-debugfs = "true"; | |
| clock-names = "ipe_0_ahb_clk\0ipe_0_areg_clk\0ipe_0_axi_clk\0ipe_0_clk\0ipe_0_clk_src"; | |
| regulator-names = "ipe0-vdd"; | |
| status = "ok"; | |
| ipe0-vdd-supply = <0x1c3>; | |
| phandle = <0x98>; | |
| reg = <0xac87000 0x3000>; | |
| src-clock-name = "ipe_0_clk_src"; | |
| reg-cam-base = "\0\bp"; | |
| cell-index = <0x00>; | |
| clock-cntl-level = "svs\0svs_l1\0nominal\0turbo"; | |
| }; | |
| qcom,mss@4080000 { | |
| compatible = "qcom,pil-q6v55-mss"; | |
| qcom,override-acc; | |
| clocks = <0x21 0x00 0x22 0x2c 0x22 0x2f 0x22 0x0b 0x22 0x2d 0x22 0x30 0x22 0x2e 0x22 0x48>; | |
| qcom,proxy-clock-names = "xo\0prng_clk"; | |
| vdd_cx-voltage = <0x181>; | |
| qcom,gpio-shutdown-ack = <0xaf 0x07 0x00>; | |
| vdd_mss-supply = <0xad>; | |
| reg-names = "qdsp6_base\0halt_q6\0halt_modem\0halt_nc\0rmb_base\0restart_reg\0pdc_sync\0alt_reset"; | |
| qcom,firmware-name = "modem"; | |
| vdd_mss-uV = <0x181>; | |
| qcom,gpio-proxy-unvote = <0xaf 0x02 0x00>; | |
| qcom,sequential-fw-load; | |
| qcom,gpio-stop-ack = <0xaf 0x03 0x00>; | |
| clock-names = "xo\0iface_clk\0bus_clk\0mem_clk\0gpll0_mss_clk\0snoc_axi_clk\0mnoc_axi_clk\0prng_clk"; | |
| qcom,gpio-err-ready = <0xaf 0x01 0x00>; | |
| qcom,gpio-err-fatal = <0xaf 0x00 0x00>; | |
| vdd_cx-supply = <0x1b>; | |
| vdd_mx-supply = <0x8c>; | |
| status = "ok"; | |
| interrupts = <0x00 0x10a 0x01>; | |
| vdd_mx-uV = <0x181>; | |
| mbox-names = "mss-pil"; | |
| memory-region = <0xae>; | |
| mboxes = <0x80 0x00>; | |
| phandle = <0x319>; | |
| qcom,ssctl-instance-id = <0x12>; | |
| qcom,qdsp6v65-1-0; | |
| qcom,active-clock-names = "iface_clk\0bus_clk\0mem_clk\0gpll0_mss_clk\0snoc_axi_clk\0mnoc_axi_clk"; | |
| qcom,mem-protect-id = <0x0f>; | |
| reg = <0x4080000 0x100 0x1f63000 0x08 0x1f65000 0x08 0x1f64000 0x08 0x4180000 0x20 0xc2b0000 0x04 0xb2e0100 0x04 0x4180044 0x04>; | |
| qcom,pil-self-auth; | |
| qcom,mss_pdc_offset = <0x09>; | |
| qcom,signal-aop; | |
| qcom,gpio-force-stop = <0xb0 0x00 0x00>; | |
| qcom,sysmon-id = <0x00>; | |
| qcom,minidump-id = <0x03>; | |
| qcom,mba-mem@0 { | |
| compatible = "qcom,pil-mba-mem"; | |
| memory-region = <0xb1>; | |
| }; | |
| }; | |
| cti@7620000 { | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti-cpu6"; | |
| clock-names = "apb_pclk"; | |
| cpu = <0x17>; | |
| phandle = <0x39c>; | |
| arm,primecell-periphid = <0x3b966>; | |
| reg = <0x7620000 0x1000>; | |
| }; | |
| qcom,cam-req-mgr { | |
| compatible = "qcom,cam-req-mgr"; | |
| status = "ok"; | |
| }; | |
| qcom,mdss_dsi_pll@ae96a00 { | |
| compatible = "qcom,mdss_dsi_pll_10nm"; | |
| clocks = <0x20 0x00>; | |
| reg-names = "pll_base\0phy_base\0gdsc_base"; | |
| qcom,dsi-pll-ssc-mode = "down-spread"; | |
| clock-names = "iface_clk"; | |
| gdsc-supply = <0x19>; | |
| label = "MDSS DSI 1 PLL"; | |
| clock-rate = <0x00>; | |
| #clock-cells = <0x01>; | |
| phandle = <0x2bd>; | |
| reg = <0xae96a00 0x1e0 0xae96400 0x800 0xaf03000 0x08>; | |
| qcom,dsi-pll-ssc-en; | |
| cell-index = <0x01>; | |
| qcom,platform-supply-entries { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| qcom,platform-supply-entry@0 { | |
| qcom,supply-name = "gdsc"; | |
| qcom,supply-disable-load = <0x00>; | |
| qcom,supply-max-voltage = <0x00>; | |
| qcom,supply-enable-load = <0x00>; | |
| qcom,supply-min-voltage = <0x00>; | |
| reg = <0x00>; | |
| }; | |
| }; | |
| }; | |
| qcom,msm-pcm-dsp-noirq { | |
| compatible = "qcom,msm-pcm-dsp-noirq"; | |
| qcom,latency-level = "ultra"; | |
| qcom,msm-pcm-low-latency; | |
| phandle = <0x27d>; | |
| }; | |
| qcom,devfreq-compute { | |
| compatible = "qcom,arm-cpu-mon"; | |
| phandle = <0x313>; | |
| qcom,target-dev = <0x89>; | |
| qcom,core-dev-table = <0x1cb600 0x2fa 0x286e00 0xf27 0x29e500 0x1ae1>; | |
| qcom,cpulist = <0x15 0x16 0x17 0x18>; | |
| }; | |
| funnel@7810000 { | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "funnel-base"; | |
| coresight-name = "coresight-funnel-apss-merg"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x3a1>; | |
| arm,primecell-periphid = <0x3b908>; | |
| reg = <0x7810000 0x1000>; | |
| ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@5 { | |
| reg = <0x06>; | |
| endpoint { | |
| remote-endpoint = <0x191>; | |
| phandle = <0x167>; | |
| slave-mode; | |
| }; | |
| }; | |
| port@3 { | |
| reg = <0x04>; | |
| endpoint { | |
| remote-endpoint = <0x18f>; | |
| phandle = <0x161>; | |
| slave-mode; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x18d>; | |
| phandle = <0x19a>; | |
| slave-mode; | |
| }; | |
| }; | |
| port@4 { | |
| reg = <0x05>; | |
| endpoint { | |
| remote-endpoint = <0x190>; | |
| phandle = <0x164>; | |
| slave-mode; | |
| }; | |
| }; | |
| port@2 { | |
| reg = <0x02>; | |
| endpoint { | |
| remote-endpoint = <0x18e>; | |
| phandle = <0x178>; | |
| slave-mode; | |
| }; | |
| }; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x18c>; | |
| phandle = <0x144>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| audio_etm0 { | |
| compatible = "qcom,coresight-remote-etm"; | |
| coresight-name = "coresight-audio-etm0"; | |
| qcom,inst-id = <0x05>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x18a>; | |
| phandle = <0x15c>; | |
| }; | |
| }; | |
| }; | |
| qcom,msm_hdcp { | |
| compatible = "qcom,msm-hdcp"; | |
| phandle = <0x327>; | |
| }; | |
| i2c@88c000 { | |
| compatible = "qcom,i2c-geni"; | |
| clocks = <0x22 0x52 0x22 0x6c 0x22 0x6d>; | |
| qcom,wrapper-core = <0x35>; | |
| pinctrl-1 = <0x40>; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| status = "disabled"; | |
| #address-cells = <0x01>; | |
| interrupts = <0x00 0x25c 0x00>; | |
| #size-cells = <0x00>; | |
| dma-names = "tx\0rx"; | |
| phandle = <0x2ce>; | |
| reg = <0x88c000 0x4000>; | |
| pinctrl-0 = <0x3f>; | |
| dmas = <0x38 0x00 0x03 0x03 0x40 0x00 0x38 0x01 0x03 0x03 0x40 0x00>; | |
| pinctrl-names = "default\0sleep"; | |
| }; | |
| qcom,qup_uart@0x898000 { | |
| interrupts-extended = <0x01 0x00 0x25f 0x00 0x34 0x30 0x00>; | |
| compatible = "qcom,msm-geni-serial-hs"; | |
| clocks = <0x22 0x58 0x22 0x6c 0x22 0x6d>; | |
| qcom,wrapper-core = <0x35>; | |
| reg-names = "se_phys"; | |
| pinctrl-1 = <0x31 0x32 0x33>; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| qcom,wakeup-byte = <0xfd>; | |
| status = "ok"; | |
| phandle = <0x2c9>; | |
| reg = <0x898000 0x4000>; | |
| pinctrl-0 = <0x31 0x32 0x33>; | |
| pinctrl-names = "default\0sleep"; | |
| }; | |
| funnel_1@6845000 { | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "funnel-base-dummy\0funnel-base-real"; | |
| coresight-name = "coresight-funnel-lpass-1"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x365>; | |
| arm,primecell-periphid = <0x3b908>; | |
| reg = <0x6867010 0x10 0x6845000 0x1000>; | |
| qcom,duplicate-funnel; | |
| ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@1 { | |
| reg = <0x01>; | |
| endpoint { | |
| remote-endpoint = <0x15c>; | |
| phandle = <0x18a>; | |
| slave-mode; | |
| }; | |
| }; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x15b>; | |
| phandle = <0x183>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| pinctrl@03400000 { | |
| compatible = "qcom,sdm845-pinctrl-v2"; | |
| reg-names = "pinctrl_regs\0spi_cfg_regs"; | |
| gpio-controller; | |
| #interrupt-cells = <0x02>; | |
| interrupt-parent = <0x01>; | |
| interrupts = <0x00 0xd0 0x00>; | |
| phandle = <0x34>; | |
| reg = <0x3400000 0xc00000 0x179900f0 0x60>; | |
| #gpio-cells = <0x02>; | |
| interrupt-controller; | |
| ufs_dev_reset_deassert { | |
| phandle = <0xac>; | |
| config { | |
| pins = "ufs_reset"; | |
| drive-strength = <0x08>; | |
| bias-pull-down; | |
| output-high; | |
| }; | |
| }; | |
| cam_sensor_mclk3_suspend { | |
| phandle = <0x4a2>; | |
| config { | |
| pins = "gpio16"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| mux { | |
| pins = "gpio16"; | |
| function = "cam_mclk"; | |
| }; | |
| }; | |
| ap2mdm { | |
| ap2mdm_active { | |
| phandle = <0x4ae>; | |
| config { | |
| pins = "gpio21\0gpio23"; | |
| bias-disable; | |
| drive-strength = <0x10>; | |
| }; | |
| mux { | |
| pins = "gpio21\0gpio23"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| ap2mdm_sleep { | |
| phandle = <0x4af>; | |
| config { | |
| pins = "gpio21\0gpio23"; | |
| bias-disable; | |
| drive-strength = <0x08>; | |
| }; | |
| mux { | |
| pins = "gpio21\0gpio23"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| }; | |
| sdc2_cmd_ds_400KHz { | |
| phandle = <0x3fa>; | |
| config { | |
| pins = "sdc2_cmd"; | |
| drive-strength = <0x0a>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| qupv3_se12_i2c_pins { | |
| phandle = <0x48b>; | |
| qupv3_se12_i2c_sleep { | |
| phandle = <0x68>; | |
| config { | |
| drive-strength = <0x02>; | |
| bias-pull-up; | |
| }; | |
| mux { | |
| function = "gpio"; | |
| }; | |
| }; | |
| qupv3_se12_i2c_active { | |
| phandle = <0x67>; | |
| config { | |
| bias-disable; | |
| drive-strength = <0x02>; | |
| }; | |
| mux { | |
| function = "qup12"; | |
| }; | |
| }; | |
| }; | |
| tert_aux_pcm { | |
| tert_aux_pcm_active { | |
| phandle = <0x439>; | |
| config { | |
| pins = "gpio75\0gpio76"; | |
| bias-disable; | |
| drive-strength = <0x08>; | |
| output-high; | |
| }; | |
| mux { | |
| pins = "gpio75\0gpio76"; | |
| function = "ter_mi2s"; | |
| }; | |
| }; | |
| tert_aux_pcm_sleep { | |
| phandle = <0x438>; | |
| config { | |
| pins = "gpio75\0gpio76"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| mux { | |
| pins = "gpio75\0gpio76"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| }; | |
| qupv3_se10_spi_pins { | |
| phandle = <0x488>; | |
| qupv3_se10_spi_sleep { | |
| phandle = <0x73>; | |
| config { | |
| pins = "gpio53\0gpio54\0gpio55\0gpio56"; | |
| bias-disable; | |
| drive-strength = <0x06>; | |
| }; | |
| mux { | |
| pins = "gpio53\0gpio54\0gpio55\0gpio56"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| qupv3_se10_spi_active { | |
| phandle = <0x72>; | |
| config { | |
| pins = "gpio53\0gpio54\0gpio55\0gpio56"; | |
| bias-disable; | |
| drive-strength = <0x06>; | |
| }; | |
| mux { | |
| pins = "gpio53\0gpio54\0gpio55\0gpio56"; | |
| function = "qup10"; | |
| }; | |
| }; | |
| }; | |
| cci0_suspend { | |
| phandle = <0x1be>; | |
| config { | |
| pins = "gpio17\0gpio18"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| mux { | |
| pins = "gpio17\0gpio18"; | |
| function = "cci_i2c"; | |
| }; | |
| }; | |
| cam_sensor_iris_active { | |
| phandle = <0x4a5>; | |
| config { | |
| pins = "gpio9"; | |
| bias-disable; | |
| drive-strength = <0x02>; | |
| }; | |
| mux { | |
| pins = "gpio9"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| quat_aux_pcm_din { | |
| quat_aux_pcm_din_sleep { | |
| phandle = <0x440>; | |
| config { | |
| pins = "gpio60"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| mux { | |
| pins = "gpio60"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| quat_aux_pcm_din_active { | |
| phandle = <0x441>; | |
| config { | |
| pins = "gpio60"; | |
| bias-disable; | |
| drive-strength = <0x08>; | |
| }; | |
| mux { | |
| pins = "gpio60"; | |
| function = "qua_mi2s"; | |
| }; | |
| }; | |
| }; | |
| qupv3_se0_i2c_pins { | |
| phandle = <0x46a>; | |
| qupv3_se0_i2c_active { | |
| phandle = <0x39>; | |
| config { | |
| bias-disable; | |
| drive-strength = <0x02>; | |
| }; | |
| mux { | |
| function = "qup0"; | |
| }; | |
| }; | |
| qupv3_se0_i2c_sleep { | |
| phandle = <0x3a>; | |
| config { | |
| drive-strength = <0x02>; | |
| bias-pull-up; | |
| }; | |
| mux { | |
| function = "gpio"; | |
| }; | |
| }; | |
| }; | |
| fg_int_default { | |
| phandle = <0x3eb>; | |
| config { | |
| pins = "gpio27"; | |
| bias-disable; | |
| drive_strength = <0x02>; | |
| }; | |
| mux { | |
| pins = "gpio27"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| cdc_reset_ctrl { | |
| cdc_reset_active { | |
| phandle = <0x409>; | |
| config { | |
| pins = "gpio64"; | |
| drive-strength = <0x08>; | |
| bias-pull-down; | |
| output-high; | |
| }; | |
| mux { | |
| pins = "gpio64"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| cdc_reset_sleep { | |
| phandle = <0x408>; | |
| config { | |
| output-low; | |
| pins = "gpio64"; | |
| bias-disable; | |
| drive-strength = <0x02>; | |
| }; | |
| mux { | |
| pins = "gpio64"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| }; | |
| pmx_ts_release { | |
| ts_release { | |
| phandle = <0x427>; | |
| config { | |
| pins = "gpio125\0gpio104"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| mux { | |
| pins = "gpio125\0gpio104"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| }; | |
| usb2_5v_boost { | |
| usb2_5v_boost_default { | |
| phandle = <0x50a>; | |
| config { | |
| output-low; | |
| drive-strength = <0x02>; | |
| }; | |
| mux { | |
| function = "gpio"; | |
| }; | |
| }; | |
| }; | |
| flash_led3_iris { | |
| flash_led3_iris_en { | |
| phandle = <0x3ee>; | |
| config { | |
| pins = "gpio23"; | |
| bias-disable; | |
| drive_strength = <0x02>; | |
| output-high; | |
| }; | |
| mux { | |
| pins = "gpio23"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| flash_led3_iris_dis { | |
| phandle = <0x3ef>; | |
| config { | |
| output-low; | |
| pins = "gpio23"; | |
| bias-disable; | |
| drive_strength = <0x02>; | |
| }; | |
| mux { | |
| pins = "gpio23"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| }; | |
| trigout_a { | |
| phandle = <0x185>; | |
| config { | |
| pins = "gpio90"; | |
| bias-disable; | |
| drive-strength = <0x02>; | |
| }; | |
| mux { | |
| pins = "gpio90"; | |
| function = "qdss_cti"; | |
| }; | |
| }; | |
| cam_sensor_mclk0_suspend { | |
| phandle = <0x49c>; | |
| config { | |
| pins = "gpio13"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| mux { | |
| pins = "gpio13"; | |
| function = "cam_mclk"; | |
| }; | |
| }; | |
| sec_aux_pcm_dout { | |
| sec_aux_pcm_dout_sleep { | |
| phandle = <0x436>; | |
| config { | |
| pins = "gpio83"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| mux { | |
| pins = "gpio83"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| sec_aux_pcm_dout_active { | |
| phandle = <0x437>; | |
| config { | |
| pins = "gpio83"; | |
| bias-disable; | |
| drive-strength = <0x08>; | |
| }; | |
| mux { | |
| pins = "gpio83"; | |
| function = "sec_mi2s"; | |
| }; | |
| }; | |
| }; | |
| qupv3_se8_spi_pins { | |
| phandle = <0x481>; | |
| qupv3_se8_spi_sleep { | |
| phandle = <0x482>; | |
| config { | |
| pins = "gpio65\0gpio66\0gpio67\0gpio68"; | |
| bias-disable; | |
| drive-strength = <0x06>; | |
| }; | |
| mux { | |
| pins = "gpio65\0gpio66\0gpio67\0gpio68"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| qupv3_se8_spi_active { | |
| phandle = <0x6f>; | |
| config { | |
| pins = "gpio65\0gpio66\0gpio67\0gpio68"; | |
| bias-disable; | |
| drive-strength = <0x06>; | |
| }; | |
| mux { | |
| pins = "gpio65\0gpio66\0gpio67\0gpio68"; | |
| function = "qup8"; | |
| }; | |
| }; | |
| }; | |
| sdc2_data_ds_400KHz { | |
| phandle = <0x400>; | |
| config { | |
| pins = "sdc2_data"; | |
| drive-strength = <0x0a>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| ext_bridge_mux { | |
| lt9611_pins { | |
| phandle = <0x431>; | |
| config { | |
| bias-disable = <0x00>; | |
| drive-strength = <0x08>; | |
| }; | |
| mux { | |
| function = "gpio"; | |
| }; | |
| }; | |
| }; | |
| tsif1_signals_active { | |
| phandle = <0x11e>; | |
| tsif2_data { | |
| function = "tsif2_data"; | |
| }; | |
| tsif2_clk { | |
| pins = "gpio93"; | |
| function = "tsif2_clk"; | |
| }; | |
| signals_cfg { | |
| pins = "gpio93\0gpio94"; | |
| drive_strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| tsif2_en { | |
| pins = "gpio94"; | |
| function = "tsif2_en"; | |
| }; | |
| }; | |
| sec_mi2s_mclk { | |
| sec_mi2s_mclk_sleep { | |
| phandle = <0x44e>; | |
| config { | |
| pins = "gpio79"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| mux { | |
| pins = "gpio79"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| sec_mi2s_mclk_active { | |
| phandle = <0x44f>; | |
| config { | |
| pins = "gpio79"; | |
| bias-disable; | |
| drive-strength = <0x08>; | |
| }; | |
| mux { | |
| pins = "gpio79"; | |
| function = "sec_mi2s"; | |
| }; | |
| }; | |
| }; | |
| sdc2_clk_on { | |
| phandle = <0x3f2>; | |
| config { | |
| pins = "sdc2_clk"; | |
| bias-disable; | |
| drive-strength = <0x10>; | |
| }; | |
| }; | |
| usb2_1v2_en { | |
| usb2_1v2_en_default { | |
| phandle = <0x50c>; | |
| config { | |
| pins = "gpio135"; | |
| drive-strength = <0x02>; | |
| output-high; | |
| }; | |
| mux { | |
| pins = "gpio135"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| }; | |
| cam_sensor_rear2_suspend { | |
| phandle = <0x4aa>; | |
| config { | |
| output-low; | |
| pins = "gpio9"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| mux { | |
| pins = "gpio9"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| tert_mi2s { | |
| tert_mi2s_sleep { | |
| phandle = <0x452>; | |
| config { | |
| pins = "gpio75\0gpio76"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| mux { | |
| pins = "gpio75\0gpio76"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| tert_mi2s_active { | |
| phandle = <0x453>; | |
| config { | |
| pins = "gpio75\0gpio76"; | |
| bias-disable; | |
| drive-strength = <0x08>; | |
| output-high; | |
| }; | |
| mux { | |
| pins = "gpio75\0gpio76"; | |
| function = "ter_mi2s"; | |
| }; | |
| }; | |
| }; | |
| cam_sensor_rear_active { | |
| phandle = <0x49d>; | |
| }; | |
| cam_sensor_iris_suspend { | |
| phandle = <0x4a6>; | |
| config { | |
| output-low; | |
| pins = "gpio9"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| mux { | |
| pins = "gpio9"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| sdc2_clk_ds_200MHz { | |
| phandle = <0x3f7>; | |
| config { | |
| pins = "sdc2_clk"; | |
| bias-disable; | |
| drive-strength = <0x10>; | |
| }; | |
| }; | |
| qupv3_se7_i2c_pins { | |
| phandle = <0x47d>; | |
| qupv3_se7_i2c_sleep { | |
| phandle = <0x48>; | |
| config { | |
| pins = "gpio93\0gpio94"; | |
| drive-strength = <0x02>; | |
| bias-pull-up; | |
| }; | |
| mux { | |
| pins = "gpio93\0gpio94"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| qupv3_se7_i2c_active { | |
| phandle = <0x47>; | |
| config { | |
| pins = "gpio93\0gpio94"; | |
| bias-disable; | |
| drive-strength = <0x02>; | |
| }; | |
| mux { | |
| pins = "gpio93\0gpio94"; | |
| function = "qup7"; | |
| }; | |
| }; | |
| }; | |
| wcd_usbc_analog_en1 { | |
| wcd_usbc_ana_en1_idle { | |
| phandle = <0x40e>; | |
| config { | |
| output-low; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| mux { | |
| function = "gpio"; | |
| }; | |
| }; | |
| wcd_usbc_ana_en1_active { | |
| phandle = <0x40f>; | |
| config { | |
| bias-disable; | |
| drive-strength = <0x02>; | |
| output-high; | |
| }; | |
| mux { | |
| function = "gpio"; | |
| }; | |
| }; | |
| }; | |
| qupv3_se5_spi_pins { | |
| phandle = <0x479>; | |
| qupv3_se5_spi_active { | |
| phandle = <0x53>; | |
| config { | |
| bias-disable; | |
| drive-strength = <0x06>; | |
| }; | |
| mux { | |
| function = "qup5"; | |
| }; | |
| }; | |
| qupv3_se5_spi_sleep { | |
| phandle = <0x54>; | |
| config { | |
| bias-disable; | |
| drive-strength = <0x06>; | |
| }; | |
| mux { | |
| function = "gpio"; | |
| }; | |
| }; | |
| }; | |
| ts_int_input { | |
| phandle = <0x42b>; | |
| config { | |
| pins = "gpio125"; | |
| bias-disable; | |
| input-enable; | |
| }; | |
| mux { | |
| pins = "gpio125"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| sde_dp_usbplug_cc_suspend { | |
| phandle = <0x422>; | |
| config { | |
| pins = "gpio38"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| mux { | |
| pins = "gpio38"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| quat_aux_pcm { | |
| quat_aux_pcm_sleep { | |
| phandle = <0x43e>; | |
| config { | |
| pins = "gpio58\0gpio59"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| mux { | |
| pins = "gpio58\0gpio59"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| quat_aux_pcm_active { | |
| phandle = <0x43f>; | |
| config { | |
| pins = "gpio58\0gpio59"; | |
| bias-disable; | |
| drive-strength = <0x08>; | |
| output-high; | |
| }; | |
| mux { | |
| pins = "gpio58\0gpio59"; | |
| function = "qua_mi2s"; | |
| }; | |
| }; | |
| }; | |
| tert_mi2s_mclk { | |
| tert_mi2s_mclk_active { | |
| phandle = <0x451>; | |
| config { | |
| pins = "gpio74"; | |
| bias-disable; | |
| drive-strength = <0x08>; | |
| }; | |
| mux { | |
| pins = "gpio74"; | |
| function = "ter_mi2s"; | |
| }; | |
| }; | |
| tert_mi2s_mclk_sleep { | |
| phandle = <0x450>; | |
| config { | |
| pins = "gpio74"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| mux { | |
| pins = "gpio74"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| }; | |
| hdmidet_active { | |
| hdmi_det_active { | |
| phandle = <0x42f>; | |
| config { | |
| pins = "gpio121"; | |
| drive-strength = <0x10>; | |
| input-enable; | |
| bias-pull-up; | |
| }; | |
| mux { | |
| pins = "gpio121"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| }; | |
| qupv3_se14_spi_pins { | |
| phandle = <0x490>; | |
| qupv3_se14_spi_active { | |
| phandle = <0x7a>; | |
| config { | |
| pins = "gpio31\0gpio32\0gpio33\0gpio34"; | |
| bias-disable; | |
| drive-strength = <0x06>; | |
| }; | |
| mux { | |
| pins = "gpio31\0gpio32\0gpio33\0gpio34"; | |
| function = "qup14"; | |
| }; | |
| }; | |
| qupv3_se14_spi_sleep { | |
| phandle = <0x7b>; | |
| config { | |
| pins = "gpio31\0gpio32\0gpio33\0gpio34"; | |
| bias-disable; | |
| drive-strength = <0x06>; | |
| }; | |
| mux { | |
| pins = "gpio31\0gpio32\0gpio33\0gpio34"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| }; | |
| sde_dsi1_active { | |
| phandle = <0x406>; | |
| config { | |
| pins = "gpio8"; | |
| bias-disable = <0x00>; | |
| drive-strength = <0x08>; | |
| }; | |
| mux { | |
| pins = "gpio8"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| qupv3_se4_i2c_pins { | |
| phandle = <0x476>; | |
| qupv3_se4_i2c_sleep { | |
| phandle = <0x42>; | |
| config { | |
| pins = "gpio89\0gpio90"; | |
| drive-strength = <0x02>; | |
| bias-pull-up; | |
| }; | |
| mux { | |
| pins = "gpio89\0gpio90"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| qupv3_se4_i2c_active { | |
| phandle = <0x41>; | |
| config { | |
| pins = "gpio89\0gpio90"; | |
| bias-disable; | |
| drive-strength = <0x02>; | |
| }; | |
| mux { | |
| pins = "gpio89\0gpio90"; | |
| function = "qup4"; | |
| }; | |
| }; | |
| }; | |
| qupv3_se2_spi_pins { | |
| phandle = <0x46f>; | |
| qupv3_se2_spi_sleep { | |
| phandle = <0x4e>; | |
| }; | |
| qupv3_se2_spi_active { | |
| phandle = <0x4d>; | |
| }; | |
| }; | |
| quat_mi2s_sd2 { | |
| quat_mi2s_sd2_sleep { | |
| phandle = <0x460>; | |
| config { | |
| pins = "gpio62"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| mux { | |
| pins = "gpio62"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| quat_mi2s_sd2_active { | |
| phandle = <0x461>; | |
| config { | |
| pins = "gpio62"; | |
| bias-disable; | |
| drive-strength = <0x08>; | |
| }; | |
| mux { | |
| pins = "gpio62"; | |
| function = "qua_mi2s"; | |
| }; | |
| }; | |
| }; | |
| pri_mi2s_sck { | |
| pri_mi2s_sck_sleep { | |
| phandle = <0x446>; | |
| config { | |
| pins = "gpio65"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| mux { | |
| pins = "gpio65"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| pri_mi2s_sck_active { | |
| phandle = <0x447>; | |
| config { | |
| pins = "gpio65"; | |
| bias-disable; | |
| drive-strength = <0x08>; | |
| output-high; | |
| }; | |
| mux { | |
| pins = "gpio65"; | |
| function = "pri_mi2s"; | |
| }; | |
| }; | |
| }; | |
| quat_aux_pcm_dout { | |
| quat_aux_pcm_dout_active { | |
| phandle = <0x443>; | |
| config { | |
| pins = "gpio61"; | |
| bias-disable; | |
| drive-strength = <0x08>; | |
| }; | |
| mux { | |
| pins = "gpio61"; | |
| function = "qua_mi2s"; | |
| }; | |
| }; | |
| quat_aux_pcm_dout_sleep { | |
| phandle = <0x442>; | |
| config { | |
| pins = "gpio61"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| mux { | |
| pins = "gpio61"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| }; | |
| cam_sensor_rear2_active { | |
| phandle = <0x4a9>; | |
| config { | |
| pins = "gpio9"; | |
| bias-disable; | |
| drive-strength = <0x02>; | |
| }; | |
| mux { | |
| pins = "gpio9"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| nfc { | |
| nfc_int_active { | |
| phandle = <0x471>; | |
| config { | |
| pins = "gpio63"; | |
| drive-strength = <0x02>; | |
| bias-pull-up; | |
| }; | |
| mux { | |
| pins = "gpio63"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| nfc_enable_suspend { | |
| phandle = <0x474>; | |
| }; | |
| nfc_enable_active { | |
| phandle = <0x473>; | |
| }; | |
| nfc_int_suspend { | |
| phandle = <0x472>; | |
| config { | |
| pins = "gpio63"; | |
| drive-strength = <0x02>; | |
| bias-pull-up; | |
| }; | |
| mux { | |
| pins = "gpio63"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| }; | |
| qupv3_se13_i2c_pins { | |
| phandle = <0x48d>; | |
| qupv3_se13_i2c_active { | |
| phandle = <0x69>; | |
| config { | |
| pins = "gpio105\0gpio106"; | |
| bias-disable; | |
| drive-strength = <0x02>; | |
| }; | |
| mux { | |
| pins = "gpio105\0gpio106"; | |
| function = "qup13"; | |
| }; | |
| }; | |
| qupv3_se13_i2c_sleep { | |
| phandle = <0x6a>; | |
| config { | |
| pins = "gpio105\0gpio106"; | |
| drive-strength = <0x02>; | |
| bias-pull-up; | |
| }; | |
| mux { | |
| pins = "gpio105\0gpio106"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| }; | |
| sdc2_clk_ds_100MHz { | |
| phandle = <0x3f6>; | |
| config { | |
| pins = "sdc2_clk"; | |
| bias-disable; | |
| drive-strength = <0x10>; | |
| }; | |
| }; | |
| qupv3_se11_spi_pins { | |
| phandle = <0x48a>; | |
| qupv3_se11_spi_active { | |
| phandle = <0x74>; | |
| config { | |
| pins = "gpio31\0gpio32\0gpio33\0gpio34"; | |
| bias-disable; | |
| drive-strength = <0x06>; | |
| }; | |
| mux { | |
| pins = "gpio31\0gpio32\0gpio33\0gpio34"; | |
| function = "qup11"; | |
| }; | |
| }; | |
| qupv3_se11_spi_sleep { | |
| phandle = <0x75>; | |
| config { | |
| pins = "gpio31\0gpio32\0gpio33\0gpio34"; | |
| bias-disable; | |
| drive-strength = <0x06>; | |
| }; | |
| mux { | |
| pins = "gpio31\0gpio32\0gpio33\0gpio34"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| }; | |
| cci1_suspend { | |
| phandle = <0x1bf>; | |
| config { | |
| pins = "gpio19\0gpio20"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| mux { | |
| pins = "gpio19\0gpio20"; | |
| function = "cci_i2c"; | |
| }; | |
| }; | |
| quat_tdm_dout { | |
| quat_tdm_dout_sleep { | |
| phandle = <0x466>; | |
| config { | |
| pins = "gpio61"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| mux { | |
| pins = "gpio61"; | |
| function = "qua_mi2s"; | |
| }; | |
| }; | |
| quat_tdm_dout_active { | |
| phandle = <0x467>; | |
| config { | |
| pins = "gpio61"; | |
| bias-disable; | |
| drive-strength = <0x02>; | |
| }; | |
| mux { | |
| pins = "gpio61"; | |
| function = "qua_mi2s"; | |
| }; | |
| }; | |
| }; | |
| pmx_sde_te { | |
| sde_te_suspend { | |
| phandle = <0x41e>; | |
| config { | |
| pins = "gpio10"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| mux { | |
| pins = "gpio10"; | |
| function = "mdp_vsync"; | |
| }; | |
| }; | |
| sde_te_active { | |
| phandle = <0x41d>; | |
| config { | |
| pins = "gpio10"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| mux { | |
| pins = "gpio10"; | |
| function = "mdp_vsync"; | |
| }; | |
| }; | |
| }; | |
| sdc2_data_on { | |
| phandle = <0x3fe>; | |
| config { | |
| pins = "sdc2_data"; | |
| drive-strength = <0x0a>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| qupv3_se1_i2c_pins { | |
| phandle = <0x46c>; | |
| qupv3_se1_i2c_active { | |
| phandle = <0x3b>; | |
| config { | |
| pins = "gpio17\0gpio18"; | |
| bias-disable; | |
| drive-strength = <0x02>; | |
| }; | |
| mux { | |
| pins = "gpio17\0gpio18"; | |
| function = "qup1"; | |
| }; | |
| }; | |
| qupv3_se1_i2c_sleep { | |
| phandle = <0x3c>; | |
| config { | |
| pins = "gpio17\0gpio18"; | |
| drive-strength = <0x02>; | |
| bias-pull-up; | |
| }; | |
| mux { | |
| pins = "gpio17\0gpio18"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| }; | |
| sdc2_clk_ds_50MHz { | |
| phandle = <0x3f5>; | |
| config { | |
| pins = "sdc2_clk"; | |
| bias-disable; | |
| drive-strength = <0x10>; | |
| }; | |
| }; | |
| sec_mi2s_sd0 { | |
| sec_mi2s_sd0_sleep { | |
| phandle = <0x26f>; | |
| config { | |
| pins = "gpio82"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| mux { | |
| pins = "gpio82"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| sec_mi2s_sd0_active { | |
| phandle = <0x26c>; | |
| config { | |
| pins = "gpio82"; | |
| bias-disable; | |
| drive-strength = <0x08>; | |
| }; | |
| mux { | |
| pins = "gpio82"; | |
| function = "sec_mi2s"; | |
| }; | |
| }; | |
| }; | |
| qupv3_se10_2uart_pins { | |
| phandle = <0x487>; | |
| qupv3_se10_2uart_sleep { | |
| phandle = <0x5d>; | |
| config { | |
| pins = "gpio53\0gpio54"; | |
| bias-disable; | |
| drive-strength = <0x02>; | |
| }; | |
| mux { | |
| pins = "gpio53\0gpio54"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| qupv3_se10_2uart_active { | |
| phandle = <0x5c>; | |
| config { | |
| pins = "gpio53\0gpio54"; | |
| bias-disable; | |
| drive-strength = <0x02>; | |
| }; | |
| mux { | |
| pins = "gpio53\0gpio54"; | |
| function = "qup10"; | |
| }; | |
| }; | |
| }; | |
| tert_mi2s_sd1 { | |
| tert_mi2s_sd1_sleep { | |
| phandle = <0x456>; | |
| config { | |
| pins = "gpio78"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| mux { | |
| pins = "gpio78"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| tert_mi2s_sd1_active { | |
| phandle = <0x457>; | |
| config { | |
| pins = "gpio78"; | |
| bias-disable; | |
| drive-strength = <0x08>; | |
| }; | |
| mux { | |
| pins = "gpio78"; | |
| function = "ter_mi2s"; | |
| }; | |
| }; | |
| }; | |
| quat_mi2s_sd0 { | |
| quat_mi2s_sd0_active { | |
| phandle = <0x45d>; | |
| config { | |
| pins = "gpio60"; | |
| bias-disable; | |
| drive-strength = <0x08>; | |
| }; | |
| mux { | |
| pins = "gpio60"; | |
| function = "qua_mi2s"; | |
| }; | |
| }; | |
| quat_mi2s_sd0_sleep { | |
| phandle = <0x45c>; | |
| config { | |
| pins = "gpio60"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| mux { | |
| pins = "gpio60"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| }; | |
| cam_sensor_mclk3_active { | |
| phandle = <0x4a1>; | |
| config { | |
| pins = "gpio16"; | |
| bias-disable; | |
| drive-strength = <0x02>; | |
| }; | |
| mux { | |
| pins = "gpio16"; | |
| function = "cam_mclk"; | |
| }; | |
| }; | |
| flash_led3_front { | |
| flash_led3_front_en { | |
| phandle = <0x3ec>; | |
| config { | |
| pins = "gpio21"; | |
| bias-disable; | |
| drive_strength = <0x02>; | |
| output-high; | |
| }; | |
| mux { | |
| pins = "gpio21"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| flash_led3_front_dis { | |
| phandle = <0x3ed>; | |
| config { | |
| output-low; | |
| pins = "gpio21"; | |
| bias-disable; | |
| drive_strength = <0x02>; | |
| }; | |
| mux { | |
| pins = "gpio21"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| }; | |
| pri_mi2s_sd0 { | |
| pri_mi2s_sd0_active { | |
| phandle = <0x44b>; | |
| config { | |
| pins = "gpio67"; | |
| bias-disable; | |
| drive-strength = <0x08>; | |
| }; | |
| mux { | |
| pins = "gpio67"; | |
| function = "pri_mi2s"; | |
| }; | |
| }; | |
| pri_mi2s_sd0_sleep { | |
| phandle = <0x44a>; | |
| config { | |
| pins = "gpio67"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| mux { | |
| pins = "gpio67"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| }; | |
| ts_int_output_high { | |
| phandle = <0x429>; | |
| config { | |
| pins = "gpio125"; | |
| output-high; | |
| }; | |
| mux { | |
| pins = "gpio125"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| qupv3_se10_i2c_pins { | |
| phandle = <0x486>; | |
| qupv3_se10_i2c_active { | |
| phandle = <0x63>; | |
| config { | |
| pins = "gpio55\0gpio56"; | |
| bias-disable; | |
| drive-strength = <0x02>; | |
| }; | |
| mux { | |
| pins = "gpio55\0gpio56"; | |
| function = "qup10"; | |
| }; | |
| }; | |
| qupv3_se10_i2c_sleep { | |
| phandle = <0x64>; | |
| config { | |
| pins = "gpio55\0gpio56"; | |
| drive-strength = <0x02>; | |
| bias-pull-up; | |
| }; | |
| mux { | |
| pins = "gpio55\0gpio56"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| }; | |
| cam_sensor_mclk1_suspend { | |
| phandle = <0x4a0>; | |
| config { | |
| pins = "gpio14"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| mux { | |
| pins = "gpio14"; | |
| function = "cam_mclk"; | |
| }; | |
| }; | |
| cam_res_mgr_suspend { | |
| phandle = <0x4ad>; | |
| config { | |
| output-low; | |
| pins = "gpio8"; | |
| bias-disable; | |
| drive-strength = <0x02>; | |
| }; | |
| mux { | |
| pins = "gpio8"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| cci1_active { | |
| phandle = <0x1bd>; | |
| config { | |
| pins = "gpio19\0gpio20"; | |
| drive-strength = <0x02>; | |
| bias-pull-up; | |
| }; | |
| mux { | |
| pins = "gpio19\0gpio20"; | |
| function = "cci_i2c"; | |
| }; | |
| }; | |
| pmx_ts_reset_suspend { | |
| ts_reset_suspend1 { | |
| phandle = <0x426>; | |
| config { | |
| pins = "gpio104"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| mux { | |
| pins = "gpio104"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| }; | |
| sde_dp_aux_suspend { | |
| phandle = <0x420>; | |
| config { | |
| pins = "gpio43\0gpio51"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| mux { | |
| pins = "gpio43\0gpio51"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| pcie0 { | |
| pcie0_wake_default { | |
| phandle = <0x264>; | |
| config { | |
| pins = "gpio37"; | |
| drive-strength = <0x02>; | |
| bias-pull-up; | |
| }; | |
| mux { | |
| pins = "gpio37"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| pcie0_1v5_on { | |
| phandle = <0x405>; | |
| config { | |
| pins = "gpio90"; | |
| bias-disable; | |
| drive_strength = <0x02>; | |
| output-high; | |
| }; | |
| mux { | |
| pins = "gpio90"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| pcie0_3v3_on { | |
| phandle = <0x404>; | |
| config { | |
| pins = "gpio90"; | |
| bias-disable; | |
| drive_strength = <0x02>; | |
| output-high; | |
| }; | |
| mux { | |
| pins = "gpio90"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| pcie0_clkreq_default { | |
| phandle = <0x262>; | |
| config { | |
| pins = "gpio36"; | |
| drive-strength = <0x02>; | |
| bias-pull-up; | |
| }; | |
| mux { | |
| pins = "gpio36"; | |
| function = "pci_e0"; | |
| }; | |
| }; | |
| pcie0_perst_default { | |
| phandle = <0x263>; | |
| config { | |
| pins = "gpio35"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| mux { | |
| pins = "gpio35"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| }; | |
| qupv3_se9_spi_pins { | |
| phandle = <0x485>; | |
| qupv3_se9_spi_sleep { | |
| phandle = <0x71>; | |
| config { | |
| bias-disable; | |
| drive-strength = <0x06>; | |
| }; | |
| mux { | |
| function = "gpio"; | |
| }; | |
| }; | |
| qupv3_se9_spi_active { | |
| phandle = <0x70>; | |
| config { | |
| bias-disable; | |
| drive-strength = <0x06>; | |
| }; | |
| mux { | |
| function = "qup9"; | |
| }; | |
| }; | |
| }; | |
| quat_mi2s { | |
| quat_mi2s_active { | |
| phandle = <0x45b>; | |
| config { | |
| pins = "gpio58\0gpio59"; | |
| bias-disable; | |
| drive-strength = <0x08>; | |
| output-high; | |
| }; | |
| mux { | |
| pins = "gpio58\0gpio59"; | |
| function = "qua_mi2s"; | |
| }; | |
| }; | |
| quat_mi2s_sleep { | |
| phandle = <0x45a>; | |
| config { | |
| pins = "gpio58\0gpio59"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| mux { | |
| pins = "gpio58\0gpio59"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| }; | |
| quat_mi2s_mclk { | |
| quat_mi2s_mclk_active { | |
| phandle = <0x459>; | |
| config { | |
| pins = "gpio57"; | |
| bias-disable; | |
| drive-strength = <0x08>; | |
| }; | |
| mux { | |
| pins = "gpio57"; | |
| function = "qua_mi2s"; | |
| }; | |
| }; | |
| quat_mi2s_mclk_sleep { | |
| phandle = <0x458>; | |
| config { | |
| pins = "gpio57"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| mux { | |
| pins = "gpio57"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| }; | |
| atest_usb13 { | |
| atest_usb13_suspend { | |
| phandle = <0x2b5>; | |
| config { | |
| pins = "gpio99"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| mux { | |
| pins = "gpio99"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| atest_usb13_active { | |
| phandle = <0x2b6>; | |
| config { | |
| pins = "gpio99"; | |
| bias-disable; | |
| drive-strength = <0x0c>; | |
| }; | |
| mux { | |
| pins = "gpio99"; | |
| function = "atest_usb13"; | |
| }; | |
| }; | |
| }; | |
| sec_aux_pcm_din { | |
| sec_aux_pcm_din_sleep { | |
| phandle = <0x434>; | |
| config { | |
| pins = "gpio82"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| mux { | |
| pins = "gpio82"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| sec_aux_pcm_din_active { | |
| phandle = <0x435>; | |
| config { | |
| pins = "gpio82"; | |
| bias-disable; | |
| drive-strength = <0x08>; | |
| }; | |
| mux { | |
| pins = "gpio82"; | |
| function = "sec_mi2s"; | |
| }; | |
| }; | |
| }; | |
| sdc2_clk_ds_400KHz { | |
| phandle = <0x3f4>; | |
| config { | |
| pins = "sdc2_clk"; | |
| bias-disable; | |
| drive-strength = <0x10>; | |
| }; | |
| }; | |
| quat_tdm_din { | |
| quat_tdm_din_sleep { | |
| phandle = <0x468>; | |
| config { | |
| pins = "gpio60"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| mux { | |
| pins = "gpio60"; | |
| function = "qua_mi2s"; | |
| }; | |
| }; | |
| quat_tdm_din_active { | |
| phandle = <0x469>; | |
| config { | |
| pins = "gpio60"; | |
| bias-disable; | |
| drive-strength = <0x02>; | |
| }; | |
| mux { | |
| pins = "gpio60"; | |
| function = "qua_mi2s"; | |
| }; | |
| }; | |
| }; | |
| qupv3_se8_i2c_pins { | |
| phandle = <0x480>; | |
| qupv3_se8_i2c_sleep { | |
| phandle = <0x60>; | |
| config { | |
| pins = "gpio65\0gpio66"; | |
| drive-strength = <0x02>; | |
| bias-pull-up; | |
| }; | |
| mux { | |
| pins = "gpio65\0gpio66"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| qupv3_se8_i2c_active { | |
| phandle = <0x5f>; | |
| config { | |
| pins = "gpio65\0gpio66"; | |
| bias-disable; | |
| drive-strength = <0x02>; | |
| }; | |
| mux { | |
| pins = "gpio65\0gpio66"; | |
| function = "qup8"; | |
| }; | |
| }; | |
| }; | |
| cam_sensor_rear_vana { | |
| phandle = <0x4ab>; | |
| }; | |
| qupv3_se6_spi_pins { | |
| phandle = <0x47c>; | |
| qupv3_se6_spi_active { | |
| phandle = <0x55>; | |
| config { | |
| pins = "gpio45\0gpio46\0gpio47\0gpio48"; | |
| bias-disable; | |
| drive-strength = <0x06>; | |
| }; | |
| mux { | |
| pins = "gpio45\0gpio46\0gpio47\0gpio48"; | |
| function = "qup6"; | |
| }; | |
| }; | |
| qupv3_se6_spi_sleep { | |
| phandle = <0x56>; | |
| config { | |
| pins = "gpio45\0gpio46\0gpio47\0gpio48"; | |
| bias-disable; | |
| drive-strength = <0x06>; | |
| }; | |
| mux { | |
| pins = "gpio45\0gpio46\0gpio47\0gpio48"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| }; | |
| cam_res_mgr_active { | |
| phandle = <0x4ac>; | |
| }; | |
| sdc2_clk_off { | |
| phandle = <0x3f3>; | |
| config { | |
| pins = "sdc2_clk"; | |
| bias-disable; | |
| drive-strength = <0x02>; | |
| }; | |
| }; | |
| usb2_3v3_en { | |
| usb2_3v3_en_default { | |
| phandle = <0x50b>; | |
| config { | |
| drive-strength = <0x02>; | |
| output-high; | |
| }; | |
| mux { | |
| function = "gpio"; | |
| }; | |
| }; | |
| }; | |
| pmx_ts_int_suspend { | |
| ts_int_suspend1 { | |
| phandle = <0x424>; | |
| config { | |
| pins = "gpio125"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| mux { | |
| pins = "gpio125"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| }; | |
| sec_aux_pcm { | |
| sec_aux_pcm_active { | |
| phandle = <0x433>; | |
| config { | |
| pins = "gpio80\0gpio81"; | |
| bias-disable; | |
| drive-strength = <0x08>; | |
| }; | |
| mux { | |
| pins = "gpio80\0gpio81"; | |
| function = "sec_mi2s"; | |
| }; | |
| }; | |
| sec_aux_pcm_sleep { | |
| phandle = <0x432>; | |
| config { | |
| pins = "gpio80\0gpio81"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| mux { | |
| pins = "gpio80\0gpio81"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| }; | |
| tert_aux_pcm_din { | |
| tert_aux_pcm_din_active { | |
| phandle = <0x43b>; | |
| config { | |
| pins = "gpio77"; | |
| bias-disable; | |
| drive-strength = <0x08>; | |
| }; | |
| mux { | |
| pins = "gpio77"; | |
| function = "ter_mi2s"; | |
| }; | |
| }; | |
| tert_aux_pcm_din_sleep { | |
| phandle = <0x43a>; | |
| config { | |
| pins = "gpio77"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| mux { | |
| pins = "gpio77"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| }; | |
| tsif0_signals_active { | |
| phandle = <0x11c>; | |
| tsif1_data { | |
| function = "tsif1_data"; | |
| }; | |
| tsif1_en { | |
| pins = "gpio90"; | |
| function = "tsif1_en"; | |
| }; | |
| signals_cfg { | |
| pins = "gpio89\0gpio90"; | |
| drive_strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| tsif1_clk { | |
| pins = "gpio89"; | |
| function = "tsif1_clk"; | |
| }; | |
| }; | |
| cam_sensor_mclk2_active { | |
| phandle = <0x4a7>; | |
| config { | |
| pins = "gpio15"; | |
| bias-disable; | |
| drive-strength = <0x02>; | |
| }; | |
| mux { | |
| pins = "gpio15"; | |
| function = "cam_mclk"; | |
| }; | |
| }; | |
| cam_sensor_front_active { | |
| phandle = <0x4a3>; | |
| config { | |
| bias-disable; | |
| drive-strength = <0x02>; | |
| }; | |
| mux { | |
| function = "gpio"; | |
| }; | |
| }; | |
| sdc2_cmd_off { | |
| phandle = <0x3f9>; | |
| config { | |
| pins = "sdc2_cmd"; | |
| drive-strength = <0x02>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| qupv3_se15_spi_pins { | |
| phandle = <0x492>; | |
| qupv3_se15_spi_sleep { | |
| phandle = <0x7d>; | |
| config { | |
| pins = "gpio81\0gpio82\0gpio83\0gpio84"; | |
| bias-disable; | |
| drive-strength = <0x06>; | |
| }; | |
| mux { | |
| pins = "gpio81\0gpio82\0gpio83\0gpio84"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| qupv3_se15_spi_active { | |
| phandle = <0x7c>; | |
| config { | |
| pins = "gpio81\0gpio82\0gpio83\0gpio84"; | |
| bias-disable; | |
| drive-strength = <0x06>; | |
| }; | |
| mux { | |
| pins = "gpio81\0gpio82\0gpio83\0gpio84"; | |
| function = "qup15"; | |
| }; | |
| }; | |
| }; | |
| cci0_active { | |
| phandle = <0x1bc>; | |
| config { | |
| pins = "gpio17\0gpio18"; | |
| drive-strength = <0x02>; | |
| bias-pull-up; | |
| }; | |
| mux { | |
| pins = "gpio17\0gpio18"; | |
| function = "cci_i2c"; | |
| }; | |
| }; | |
| tsif0_sync_active { | |
| phandle = <0x11d>; | |
| tsif1_sync { | |
| }; | |
| }; | |
| qupv3_se5_i2c_pins { | |
| phandle = <0x478>; | |
| qupv3_se5_i2c_active { | |
| phandle = <0x43>; | |
| config { | |
| pins = "gpio85\0gpio86"; | |
| bias-disable; | |
| drive-strength = <0x02>; | |
| }; | |
| mux { | |
| pins = "gpio85\0gpio86"; | |
| function = "qup5"; | |
| }; | |
| }; | |
| qupv3_se5_i2c_sleep { | |
| phandle = <0x44>; | |
| config { | |
| pins = "gpio85\0gpio86"; | |
| drive-strength = <0x02>; | |
| bias-pull-up; | |
| }; | |
| mux { | |
| pins = "gpio85\0gpio86"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| }; | |
| sdc2_cmd_ds_50MHz { | |
| phandle = <0x3fb>; | |
| config { | |
| pins = "sdc2_cmd"; | |
| drive-strength = <0x0a>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| qupv3_se3_spi_pins { | |
| phandle = <0x475>; | |
| qupv3_se3_spi_sleep { | |
| phandle = <0x50>; | |
| config { | |
| bias-disable; | |
| drive-strength = <0x06>; | |
| }; | |
| mux { | |
| function = "gpio"; | |
| }; | |
| }; | |
| qupv3_se3_spi_active { | |
| phandle = <0x4f>; | |
| config { | |
| bias-disable; | |
| drive-strength = <0x06>; | |
| }; | |
| mux { | |
| function = "qup3"; | |
| }; | |
| }; | |
| }; | |
| mdm2ap { | |
| mdm2ap_sleep { | |
| phandle = <0x4b1>; | |
| config { | |
| pins = "gpio20"; | |
| bias-disable; | |
| drive-strength = <0x08>; | |
| }; | |
| mux { | |
| pins = "gpio20"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| mdm2ap_active { | |
| phandle = <0x4b0>; | |
| config { | |
| pins = "gpio20"; | |
| bias-disable; | |
| drive-strength = <0x08>; | |
| }; | |
| mux { | |
| pins = "gpio20"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| }; | |
| ts_int_output_low { | |
| phandle = <0x42a>; | |
| config { | |
| output-low; | |
| pins = "gpio125"; | |
| }; | |
| mux { | |
| pins = "gpio125"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| pmx_ts_reset_active { | |
| ts_reset_active { | |
| phandle = <0x425>; | |
| config { | |
| pins = "gpio104"; | |
| drive-strength = <0x08>; | |
| bias-pull-up; | |
| }; | |
| mux { | |
| pins = "gpio104"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| }; | |
| hdmidet_suspend { | |
| hdmi_det_suspend { | |
| phandle = <0x430>; | |
| config { | |
| pins = "gpio121"; | |
| bias-disable; | |
| drive-strength = <0x02>; | |
| }; | |
| mux { | |
| pins = "gpio121"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| }; | |
| ts_mux { | |
| ts_int_suspend { | |
| phandle = <0x42e>; | |
| config { | |
| pins = "gpio125"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| mux { | |
| pins = "gpio125"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| ts_active { | |
| phandle = <0x42c>; | |
| config { | |
| pins = "gpio104\0gpio125"; | |
| drive-strength = <0x10>; | |
| bias-pull-up; | |
| }; | |
| mux { | |
| pins = "gpio104\0gpio125"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| ts_reset_suspend { | |
| phandle = <0x42d>; | |
| config { | |
| pins = "gpio104"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| mux { | |
| pins = "gpio104"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| }; | |
| cam_sensor_rear_suspend { | |
| phandle = <0x49e>; | |
| }; | |
| pri_mi2s_mclk { | |
| pri_mi2s_mclk_active { | |
| phandle = <0x445>; | |
| config { | |
| pins = "gpio64"; | |
| bias-disable; | |
| drive-strength = <0x08>; | |
| output-high; | |
| }; | |
| mux { | |
| pins = "gpio64"; | |
| function = "pri_mi2s"; | |
| }; | |
| }; | |
| pri_mi2s_mclk_sleep { | |
| phandle = <0x444>; | |
| config { | |
| pins = "gpio64"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| mux { | |
| pins = "gpio64"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| }; | |
| qupv3_se14_i2c_pins { | |
| phandle = <0x48f>; | |
| qupv3_se14_i2c_sleep { | |
| phandle = <0x6c>; | |
| config { | |
| pins = "gpio33\0gpio34"; | |
| drive-strength = <0x02>; | |
| bias-pull-up; | |
| }; | |
| mux { | |
| pins = "gpio33\0gpio34"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| qupv3_se14_i2c_active { | |
| phandle = <0x6b>; | |
| config { | |
| pins = "gpio33\0gpio34"; | |
| bias-disable; | |
| drive-strength = <0x02>; | |
| }; | |
| mux { | |
| pins = "gpio33\0gpio34"; | |
| function = "qup14"; | |
| }; | |
| }; | |
| }; | |
| qupv3_se12_spi_pins { | |
| phandle = <0x48c>; | |
| qupv3_se12_spi_sleep { | |
| phandle = <0x77>; | |
| config { | |
| bias-disable; | |
| drive-strength = <0x06>; | |
| }; | |
| mux { | |
| function = "gpio"; | |
| }; | |
| }; | |
| qupv3_se12_spi_active { | |
| phandle = <0x76>; | |
| config { | |
| bias-disable; | |
| drive-strength = <0x06>; | |
| }; | |
| mux { | |
| function = "qup12"; | |
| }; | |
| }; | |
| }; | |
| wcd_usbc_analog_en2 { | |
| wcd_usbc_ana_en2_idle { | |
| phandle = <0x410>; | |
| config { | |
| output-low; | |
| pins = "gpio51"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| mux { | |
| pins = "gpio51"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| wcd_usbc_ana_en2_active { | |
| phandle = <0x411>; | |
| config { | |
| pins = "gpio51"; | |
| bias-disable; | |
| drive-strength = <0x02>; | |
| output-high; | |
| }; | |
| mux { | |
| pins = "gpio51"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| }; | |
| tert_aux_pcm_dout { | |
| tert_aux_pcm_dout_active { | |
| phandle = <0x43d>; | |
| config { | |
| pins = "gpio78"; | |
| bias-disable; | |
| drive-strength = <0x08>; | |
| }; | |
| mux { | |
| pins = "gpio78"; | |
| function = "ter_mi2s"; | |
| }; | |
| }; | |
| tert_aux_pcm_dout_sleep { | |
| phandle = <0x43c>; | |
| config { | |
| pins = "gpio78"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| mux { | |
| pins = "gpio78"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| }; | |
| wcd9xxx_intr { | |
| wcd_intr_default { | |
| phandle = <0x3f0>; | |
| config { | |
| pins = "gpio54"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| mux { | |
| pins = "gpio54"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| }; | |
| qupv3_se2_i2c_pins { | |
| phandle = <0x46e>; | |
| qupv3_se2_i2c_sleep { | |
| phandle = <0x3e>; | |
| }; | |
| qupv3_se2_i2c_active { | |
| phandle = <0x3d>; | |
| }; | |
| }; | |
| qupv3_se0_spi_pins { | |
| phandle = <0x46b>; | |
| qupv3_se0_spi_active { | |
| phandle = <0x49>; | |
| config { | |
| bias-disable; | |
| drive-strength = <0x06>; | |
| }; | |
| mux { | |
| function = "qup0"; | |
| }; | |
| }; | |
| qupv3_se0_spi_sleep { | |
| phandle = <0x4a>; | |
| config { | |
| bias-disable; | |
| drive-strength = <0x06>; | |
| }; | |
| mux { | |
| function = "gpio"; | |
| }; | |
| }; | |
| }; | |
| pmx_sde { | |
| phandle = <0x41a>; | |
| sde_dsi_suspend { | |
| phandle = <0x41c>; | |
| config { | |
| pins = "gpio6"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| mux { | |
| pins = "gpio6"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| sde_dsi_active { | |
| phandle = <0x41b>; | |
| config { | |
| pins = "gpio6"; | |
| bias-disable = <0x00>; | |
| drive-strength = <0x08>; | |
| }; | |
| mux { | |
| pins = "gpio6"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| }; | |
| pri_aux_pcm_clk { | |
| pri_aux_pcm_clk_sleep { | |
| phandle = <0x412>; | |
| config { | |
| pins = "gpio65"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| mux { | |
| pins = "gpio65"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| pri_aux_pcm_clk_active { | |
| phandle = <0x413>; | |
| config { | |
| pins = "gpio65"; | |
| bias-disable; | |
| drive-strength = <0x08>; | |
| output-high; | |
| }; | |
| mux { | |
| pins = "gpio65"; | |
| function = "pri_mi2s"; | |
| }; | |
| }; | |
| }; | |
| sde_dsi1_suspend { | |
| phandle = <0x407>; | |
| config { | |
| pins = "gpio8"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| mux { | |
| pins = "gpio8"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| quec_gpio_init { | |
| quec_output_gpios_init { | |
| phandle = <0x4b3>; | |
| config { | |
| pins = "gpio88"; | |
| bias-disable; | |
| drive-strength = <0x08>; | |
| output-high; | |
| }; | |
| mux { | |
| pins = "gpio88"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| quec_input_gpios_init { | |
| phandle = <0x4b2>; | |
| config { | |
| pins = "gpio0\0gpio3\0gpio22\0gpio24\0gpio26\0gpio40\0gpio41\0gpio49\0gpio52\0gpio91\0gpio92\0gpio95\0gpio96\0gpio116\0gpio122\0gpio124\0gpio128"; | |
| drive-strength = <0x02>; | |
| bias-pull-up; | |
| }; | |
| mux { | |
| pins = "gpio0\0gpio3\0gpio22\0gpio24\0gpio26\0gpio40\0gpio41\0gpio49\0gpio52\0gpio91\0gpio92\0gpio95\0gpio96\0gpio116\0gpio122\0gpio124\0gpio128"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| }; | |
| cam_sensor_mclk1_active { | |
| phandle = <0x49f>; | |
| config { | |
| pins = "gpio14"; | |
| bias-disable; | |
| drive-strength = <0x02>; | |
| }; | |
| mux { | |
| pins = "gpio14"; | |
| function = "cam_mclk"; | |
| }; | |
| }; | |
| sde_dp_aux_active { | |
| phandle = <0x41f>; | |
| config { | |
| pins = "gpio43\0gpio51"; | |
| bias-disable = <0x00>; | |
| drive-strength = <0x08>; | |
| }; | |
| mux { | |
| pins = "gpio43\0gpio51"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| pmx_ts_int_active { | |
| ts_int_active { | |
| phandle = <0x423>; | |
| config { | |
| pins = "gpio125"; | |
| drive-strength = <0x08>; | |
| bias-pull-up; | |
| }; | |
| mux { | |
| pins = "gpio125"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| }; | |
| sdc2_cmd_ds_200MHz { | |
| phandle = <0x3fd>; | |
| config { | |
| pins = "sdc2_cmd"; | |
| drive-strength = <0x0a>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| cam_sensor_mclk2_suspend { | |
| phandle = <0x4a8>; | |
| config { | |
| pins = "gpio15"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| mux { | |
| pins = "gpio15"; | |
| function = "cam_mclk"; | |
| }; | |
| }; | |
| qupv3_se11_i2c_pins { | |
| phandle = <0x489>; | |
| qupv3_se11_i2c_sleep { | |
| phandle = <0x66>; | |
| config { | |
| pins = "gpio31\0gpio32"; | |
| drive-strength = <0x02>; | |
| bias-pull-up; | |
| }; | |
| mux { | |
| pins = "gpio31\0gpio32"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| qupv3_se11_i2c_active { | |
| phandle = <0x65>; | |
| config { | |
| pins = "gpio31\0gpio32"; | |
| bias-disable; | |
| drive-strength = <0x02>; | |
| }; | |
| mux { | |
| pins = "gpio31\0gpio32"; | |
| function = "qup11"; | |
| }; | |
| }; | |
| }; | |
| storage_cd { | |
| phandle = <0x3f1>; | |
| config { | |
| pins = "gpio126"; | |
| drive-strength = <0x02>; | |
| bias-pull-up; | |
| }; | |
| mux { | |
| pins = "gpio126"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| cam_sensor_depth_active { | |
| phandle = <0x495>; | |
| config { | |
| pins = "gpio28\0gpio23"; | |
| bias-disable; | |
| drive-strength = <0x02>; | |
| }; | |
| mux { | |
| pins = "gpio28\0gpio23"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| wcd_gnd_mic_swap { | |
| wcd_gnd_mic_swap_active { | |
| phandle = <0x40d>; | |
| config { | |
| pins = "gpio51"; | |
| bias-disable; | |
| drive-strength = <0x02>; | |
| output-high; | |
| }; | |
| mux { | |
| pins = "gpio51"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| wcd_gnd_mic_swap_idle { | |
| phandle = <0x40c>; | |
| config { | |
| output-low; | |
| pins = "gpio51"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| mux { | |
| pins = "gpio51"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| }; | |
| max_6dof_active { | |
| phandle = <0x499>; | |
| config { | |
| pins = "gpio30\0gpio94"; | |
| bias-disable; | |
| drive-strength = <0x08>; | |
| }; | |
| mux { | |
| pins = "gpio30\0gpio94"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| quat_mi2s_sd3 { | |
| quat_mi2s_sd3_active { | |
| phandle = <0x463>; | |
| config { | |
| pins = "gpio63"; | |
| bias-disable; | |
| drive-strength = <0x08>; | |
| }; | |
| mux { | |
| pins = "gpio63"; | |
| function = "qua_mi2s"; | |
| }; | |
| }; | |
| quat_mi2s_sd3_sleep { | |
| phandle = <0x462>; | |
| config { | |
| pins = "gpio63"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| mux { | |
| pins = "gpio63"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| }; | |
| cam_sensor_front_suspend { | |
| phandle = <0x4a4>; | |
| config { | |
| output-low; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| mux { | |
| function = "gpio"; | |
| }; | |
| }; | |
| qupv3_se9_2uart_pins { | |
| phandle = <0x484>; | |
| qupv3_se9_2uart_sleep { | |
| phandle = <0x5a>; | |
| config { | |
| pins = "gpio4\0gpio5"; | |
| bias-disable; | |
| drive-strength = <0x02>; | |
| }; | |
| mux { | |
| pins = "gpio4\0gpio5"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| qupv3_se9_2uart_active { | |
| phandle = <0x59>; | |
| config { | |
| pins = "gpio4\0gpio5"; | |
| bias-disable; | |
| drive-strength = <0x02>; | |
| }; | |
| mux { | |
| pins = "gpio4\0gpio5"; | |
| function = "qup9"; | |
| }; | |
| }; | |
| }; | |
| max_rst_suspend { | |
| phandle = <0x498>; | |
| config { | |
| pins = "gpio31\0gpio77\0gpio78\0gpio32"; | |
| drive-strength = <0x08>; | |
| bias-pull-down; | |
| }; | |
| mux { | |
| pins = "gpio31\0gpio77\0gpio78\0gpio32"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| qupv3_se6_4uart_pins { | |
| phandle = <0x47b>; | |
| qupv3_se6_ctsrx { | |
| phandle = <0x31>; | |
| config { | |
| pins = "gpio45\0gpio48"; | |
| drive-strength = <0x02>; | |
| bias-no-pull; | |
| }; | |
| mux { | |
| pins = "gpio45\0gpio48"; | |
| function = "qup6"; | |
| }; | |
| }; | |
| qupv3_se6_tx { | |
| phandle = <0x33>; | |
| config { | |
| pins = "gpio47"; | |
| drive-strength = <0x02>; | |
| bias-pull-up; | |
| }; | |
| mux { | |
| pins = "gpio47"; | |
| function = "qup6"; | |
| }; | |
| }; | |
| qupv3_se6_rts { | |
| phandle = <0x32>; | |
| config { | |
| pins = "gpio46"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| mux { | |
| pins = "gpio46"; | |
| function = "qup6"; | |
| }; | |
| }; | |
| }; | |
| tsif1_sync_active { | |
| phandle = <0x11f>; | |
| tsif2_sync { | |
| function = "tsif2_sync"; | |
| drive_strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| sdc2_cmd_on { | |
| phandle = <0x3f8>; | |
| config { | |
| pins = "sdc2_cmd"; | |
| drive-strength = <0x0a>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| sdc2_data_off { | |
| phandle = <0x3ff>; | |
| config { | |
| pins = "sdc2_data"; | |
| drive-strength = <0x02>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| pri_aux_pcm_dout { | |
| pri_aux_pcm_dout_active { | |
| phandle = <0x419>; | |
| config { | |
| pins = "gpio68"; | |
| bias-disable; | |
| drive-strength = <0x08>; | |
| }; | |
| mux { | |
| pins = "gpio68"; | |
| function = "pri_mi2s"; | |
| }; | |
| }; | |
| pri_aux_pcm_dout_sleep { | |
| phandle = <0x418>; | |
| config { | |
| pins = "gpio68"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| mux { | |
| pins = "gpio68"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| }; | |
| sec_mi2s_sd1 { | |
| sec_mi2s_sd1_active { | |
| phandle = <0x26d>; | |
| config { | |
| pins = "gpio83"; | |
| bias-disable; | |
| drive-strength = <0x08>; | |
| }; | |
| mux { | |
| pins = "gpio83"; | |
| function = "sec_mi2s"; | |
| }; | |
| }; | |
| sec_mi2s_sd1_sleep { | |
| phandle = <0x270>; | |
| config { | |
| pins = "gpio83"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| mux { | |
| pins = "gpio83"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| }; | |
| pri_aux_pcm_din { | |
| pri_aux_pcm_din_active { | |
| phandle = <0x417>; | |
| config { | |
| pins = "gpio67"; | |
| bias-disable; | |
| drive-strength = <0x08>; | |
| }; | |
| mux { | |
| pins = "gpio67"; | |
| function = "pri_mi2s"; | |
| }; | |
| }; | |
| pri_aux_pcm_din_sleep { | |
| phandle = <0x416>; | |
| config { | |
| pins = "gpio67"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| mux { | |
| pins = "gpio67"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| }; | |
| qupv3_se9_i2c_pins { | |
| phandle = <0x483>; | |
| qupv3_se9_i2c_sleep { | |
| phandle = <0x62>; | |
| config { | |
| drive-strength = <0x02>; | |
| bias-pull-up; | |
| }; | |
| mux { | |
| function = "gpio"; | |
| }; | |
| }; | |
| qupv3_se9_i2c_active { | |
| phandle = <0x61>; | |
| config { | |
| bias-disable; | |
| drive-strength = <0x02>; | |
| }; | |
| mux { | |
| function = "qup9"; | |
| }; | |
| }; | |
| }; | |
| qupv3_se7_spi_pins { | |
| phandle = <0x47f>; | |
| qupv3_se7_spi_sleep { | |
| phandle = <0x58>; | |
| config { | |
| bias-disable; | |
| drive-strength = <0x06>; | |
| }; | |
| mux { | |
| function = "gpio"; | |
| }; | |
| }; | |
| qupv3_se7_spi_active { | |
| phandle = <0x57>; | |
| config { | |
| bias-disable; | |
| drive-strength = <0x06>; | |
| }; | |
| mux { | |
| function = "qup7"; | |
| }; | |
| }; | |
| }; | |
| cam_sensor_depth_suspend { | |
| phandle = <0x496>; | |
| config { | |
| pins = "gpio28\0gpio23"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| mux { | |
| pins = "gpio28\0gpio23"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| sdc2_data_ds_200MHz { | |
| phandle = <0x403>; | |
| config { | |
| pins = "sdc2_data"; | |
| drive-strength = <0x0a>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| ts_int_defalut { | |
| phandle = <0x428>; | |
| config { | |
| pins = "gpio125"; | |
| bias-disable; | |
| drive-strength = <0x10>; | |
| input-enable; | |
| }; | |
| mux { | |
| pins = "gpio125"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| max_6dof_suspend { | |
| phandle = <0x49a>; | |
| config { | |
| pins = "gpio30\0gpio94"; | |
| drive-strength = <0x08>; | |
| bias-pull-down; | |
| }; | |
| mux { | |
| pins = "gpio30\0gpio94"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| quat_mi2s_sd1 { | |
| quat_mi2s_sd1_sleep { | |
| phandle = <0x45e>; | |
| config { | |
| pins = "gpio61"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| mux { | |
| pins = "gpio61"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| quat_mi2s_sd1_active { | |
| phandle = <0x45f>; | |
| config { | |
| pins = "gpio61"; | |
| bias-disable; | |
| drive-strength = <0x08>; | |
| }; | |
| mux { | |
| pins = "gpio61"; | |
| function = "qua_mi2s"; | |
| }; | |
| }; | |
| }; | |
| ufs_dev_reset_assert { | |
| phandle = <0xab>; | |
| config { | |
| output-low; | |
| pins = "ufs_reset"; | |
| drive-strength = <0x08>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| pri_aux_pcm_sync { | |
| pri_aux_pcm_sync_sleep { | |
| phandle = <0x414>; | |
| config { | |
| pins = "gpio66"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| mux { | |
| pins = "gpio66"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| pri_aux_pcm_sync_active { | |
| phandle = <0x415>; | |
| config { | |
| pins = "gpio66"; | |
| bias-disable; | |
| drive-strength = <0x08>; | |
| output-high; | |
| }; | |
| mux { | |
| pins = "gpio66"; | |
| function = "pri_mi2s_ws"; | |
| }; | |
| }; | |
| }; | |
| pri_mi2s_sd1 { | |
| pri_mi2s_sd1_sleep { | |
| phandle = <0x44c>; | |
| config { | |
| pins = "gpio68"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| mux { | |
| pins = "gpio68"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| pri_mi2s_sd1_active { | |
| phandle = <0x44d>; | |
| config { | |
| pins = "gpio68"; | |
| bias-disable; | |
| drive-strength = <0x08>; | |
| }; | |
| mux { | |
| pins = "gpio68"; | |
| function = "pri_mi2s"; | |
| }; | |
| }; | |
| }; | |
| cam_sensor_mclk0_active { | |
| phandle = <0x49b>; | |
| config { | |
| pins = "gpio13"; | |
| bias-disable; | |
| drive-strength = <0x02>; | |
| }; | |
| mux { | |
| pins = "gpio13"; | |
| function = "cam_mclk"; | |
| }; | |
| }; | |
| spkr_i2s_clk_pin { | |
| spkr_i2s_clk_active { | |
| phandle = <0x40b>; | |
| config { | |
| pins = "gpio69"; | |
| bias-disable; | |
| drive-strength = <0x08>; | |
| }; | |
| mux { | |
| pins = "gpio69"; | |
| function = "spkr_i2s"; | |
| }; | |
| }; | |
| spkr_i2s_clk_sleep { | |
| phandle = <0x40a>; | |
| config { | |
| pins = "gpio69"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| mux { | |
| pins = "gpio69"; | |
| function = "spkr_i2s"; | |
| }; | |
| }; | |
| }; | |
| sdc2_cmd_ds_100MHz { | |
| phandle = <0x3fc>; | |
| config { | |
| pins = "sdc2_cmd"; | |
| drive-strength = <0x0a>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| pcie1 { | |
| pcie1_perst_default { | |
| phandle = <0x268>; | |
| config { | |
| pins = "gpio102"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| mux { | |
| pins = "gpio102"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| pcie1_clkreq_default { | |
| phandle = <0x267>; | |
| config { | |
| pins = "gpio103"; | |
| drive-strength = <0x02>; | |
| bias-pull-up; | |
| }; | |
| mux { | |
| pins = "gpio103"; | |
| function = "pci_e1"; | |
| }; | |
| }; | |
| pcie1_wake_default { | |
| phandle = <0x269>; | |
| config { | |
| pins = "gpio11"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| mux { | |
| pins = "gpio11"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| }; | |
| qupv3_se6_i2c_pins { | |
| phandle = <0x47a>; | |
| qupv3_se6_i2c_active { | |
| phandle = <0x45>; | |
| config { | |
| pins = "gpio45\0gpio46"; | |
| bias-disable; | |
| drive-strength = <0x02>; | |
| }; | |
| mux { | |
| pins = "gpio45\0gpio46"; | |
| function = "qup6"; | |
| }; | |
| }; | |
| qupv3_se6_i2c_sleep { | |
| phandle = <0x46>; | |
| config { | |
| pins = "gpio45\0gpio46"; | |
| drive-strength = <0x02>; | |
| bias-pull-up; | |
| }; | |
| mux { | |
| pins = "gpio45\0gpio46"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| }; | |
| qupv3_se4_spi_pins { | |
| phandle = <0x477>; | |
| qupv3_se4_spi_active { | |
| phandle = <0x51>; | |
| config { | |
| bias-disable; | |
| drive-strength = <0x06>; | |
| }; | |
| mux { | |
| function = "qup4"; | |
| }; | |
| }; | |
| qupv3_se4_spi_sleep { | |
| phandle = <0x52>; | |
| config { | |
| bias-disable; | |
| drive-strength = <0x06>; | |
| }; | |
| mux { | |
| function = "gpio"; | |
| }; | |
| }; | |
| }; | |
| quat_tdm { | |
| quat_tdm_sleep { | |
| phandle = <0x464>; | |
| config { | |
| pins = "gpio58\0gpio59"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| mux { | |
| pins = "gpio58\0gpio59"; | |
| function = "qua_mi2s"; | |
| }; | |
| }; | |
| quat_tdm_active { | |
| phandle = <0x465>; | |
| config { | |
| pins = "gpio58\0gpio59"; | |
| bias-disable; | |
| drive-strength = <0x08>; | |
| }; | |
| mux { | |
| pins = "gpio58\0gpio59"; | |
| function = "qua_mi2s"; | |
| }; | |
| }; | |
| }; | |
| max_rst_active { | |
| phandle = <0x497>; | |
| config { | |
| pins = "gpio31\0gpio77\0gpio78\0gpio32"; | |
| bias-disable; | |
| drive-strength = <0x08>; | |
| }; | |
| mux { | |
| pins = "gpio31\0gpio77\0gpio78\0gpio32"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| tert_mi2s_sd0 { | |
| tert_mi2s_sd0_active { | |
| phandle = <0x455>; | |
| config { | |
| pins = "gpio77"; | |
| bias-disable; | |
| drive-strength = <0x08>; | |
| }; | |
| mux { | |
| pins = "gpio77"; | |
| function = "ter_mi2s"; | |
| }; | |
| }; | |
| tert_mi2s_sd0_sleep { | |
| phandle = <0x454>; | |
| config { | |
| pins = "gpio77"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| mux { | |
| pins = "gpio77"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| }; | |
| pri_mi2s_ws { | |
| pri_mi2s_ws_sleep { | |
| phandle = <0x448>; | |
| config { | |
| pins = "gpio66"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| mux { | |
| pins = "gpio66"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| pri_mi2s_ws_active { | |
| phandle = <0x449>; | |
| config { | |
| pins = "gpio66"; | |
| bias-disable; | |
| drive-strength = <0x08>; | |
| output-high; | |
| }; | |
| mux { | |
| pins = "gpio66"; | |
| function = "pri_mi2s_ws"; | |
| }; | |
| }; | |
| }; | |
| cam_sensor_fisheye_active { | |
| phandle = <0x493>; | |
| config { | |
| pins = "gpio76\0gpio75"; | |
| bias-disable; | |
| drive-strength = <0x02>; | |
| }; | |
| mux { | |
| pins = "gpio76\0gpio75"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| qupv3_se15_i2c_pins { | |
| phandle = <0x491>; | |
| qupv3_se15_i2c_active { | |
| phandle = <0x6d>; | |
| config { | |
| pins = "gpio81\0gpio82"; | |
| bias-disable; | |
| drive-strength = <0x02>; | |
| }; | |
| mux { | |
| pins = "gpio81\0gpio82"; | |
| function = "qup15"; | |
| }; | |
| }; | |
| qupv3_se15_i2c_sleep { | |
| phandle = <0x6e>; | |
| config { | |
| pins = "gpio81\0gpio82"; | |
| drive-strength = <0x02>; | |
| bias-pull-up; | |
| }; | |
| mux { | |
| pins = "gpio81\0gpio82"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| }; | |
| sde_dp_usbplug_cc_active { | |
| phandle = <0x421>; | |
| config { | |
| pins = "gpio38"; | |
| bias-disable; | |
| drive-strength = <0x10>; | |
| }; | |
| mux { | |
| pins = "gpio38"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| qupv3_se13_spi_pins { | |
| phandle = <0x48e>; | |
| qupv3_se13_spi_active { | |
| phandle = <0x78>; | |
| config { | |
| pins = "gpio105\0gpio106\0gpio107\0gpio108"; | |
| bias-disable; | |
| drive-strength = <0x06>; | |
| }; | |
| mux { | |
| pins = "gpio105\0gpio106\0gpio107\0gpio108"; | |
| function = "qup13"; | |
| }; | |
| }; | |
| qupv3_se13_spi_sleep { | |
| phandle = <0x79>; | |
| config { | |
| pins = "gpio105\0gpio106\0gpio107\0gpio108"; | |
| bias-disable; | |
| drive-strength = <0x06>; | |
| }; | |
| mux { | |
| pins = "gpio105\0gpio106\0gpio107\0gpio108"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| }; | |
| sdc2_data_ds_50MHz { | |
| phandle = <0x401>; | |
| config { | |
| pins = "sdc2_data"; | |
| drive-strength = <0x0a>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| qupv3_se3_i2c_pins { | |
| phandle = <0x470>; | |
| qupv3_se3_i2c_active { | |
| phandle = <0x3f>; | |
| config { | |
| bias-disable; | |
| drive-strength = <0x02>; | |
| }; | |
| mux { | |
| function = "qup3"; | |
| }; | |
| }; | |
| qupv3_se3_i2c_sleep { | |
| phandle = <0x40>; | |
| config { | |
| drive-strength = <0x02>; | |
| bias-pull-up; | |
| }; | |
| mux { | |
| function = "gpio"; | |
| }; | |
| }; | |
| }; | |
| qupv3_se7_4uart_pins { | |
| phandle = <0x47e>; | |
| qupv3_se7_4uart_active { | |
| phandle = <0x36>; | |
| config { | |
| bias-disable; | |
| drive-strength = <0x02>; | |
| }; | |
| mux { | |
| function = "qup7"; | |
| }; | |
| }; | |
| qupv3_se7_4uart_sleep { | |
| phandle = <0x37>; | |
| config { | |
| bias-disable; | |
| drive-strength = <0x02>; | |
| }; | |
| mux { | |
| function = "gpio"; | |
| }; | |
| }; | |
| }; | |
| qupv3_se1_spi_pins { | |
| phandle = <0x46d>; | |
| qupv3_se1_spi_active { | |
| phandle = <0x4b>; | |
| config { | |
| pins = "gpio17\0gpio18\0gpio19\0gpio20"; | |
| bias-disable; | |
| drive-strength = <0x06>; | |
| }; | |
| mux { | |
| pins = "gpio17\0gpio18\0gpio19\0gpio20"; | |
| function = "qup1"; | |
| }; | |
| }; | |
| qupv3_se1_spi_sleep { | |
| phandle = <0x4c>; | |
| config { | |
| pins = "gpio17\0gpio18\0gpio19\0gpio20"; | |
| bias-disable; | |
| drive-strength = <0x06>; | |
| }; | |
| mux { | |
| pins = "gpio17\0gpio18\0gpio19\0gpio20"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| }; | |
| sec_mi2s { | |
| sec_mi2s_sleep { | |
| phandle = <0x26e>; | |
| config { | |
| pins = "gpio80\0gpio81"; | |
| bias-disable; | |
| drive-strength = <0x02>; | |
| input-enable; | |
| }; | |
| mux { | |
| pins = "gpio80\0gpio81"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| sec_mi2s_active { | |
| phandle = <0x26b>; | |
| config { | |
| pins = "gpio80\0gpio81"; | |
| bias-disable; | |
| drive-strength = <0x08>; | |
| }; | |
| mux { | |
| pins = "gpio80\0gpio81"; | |
| function = "sec_mi2s"; | |
| }; | |
| }; | |
| }; | |
| cam_sensor_fisheye_suspend { | |
| phandle = <0x494>; | |
| config { | |
| output-low; | |
| pins = "gpio76\0gpio75"; | |
| drive-strength = <0x02>; | |
| bias-pull-down; | |
| }; | |
| mux { | |
| pins = "gpio76\0gpio75"; | |
| function = "gpio"; | |
| }; | |
| }; | |
| sdc2_data_ds_100MHz { | |
| phandle = <0x402>; | |
| config { | |
| pins = "sdc2_data"; | |
| drive-strength = <0x0a>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| }; | |
| qcom,gdsc@0x10f004 { | |
| compatible = "qcom,gdsc"; | |
| status = "ok"; | |
| phandle = <0x2b0>; | |
| reg = <0x10f004 0x04>; | |
| regulator-name = "usb30_prim_gdsc"; | |
| qcom,poll-cfg-gdscr; | |
| }; | |
| audio_ext_clk_lnbb { | |
| compatible = "qcom,audio-ref-clk"; | |
| clocks = <0x21 0x02>; | |
| clock-names = "osr_clk"; | |
| status = "ok"; | |
| qcom,node_has_rpm_clock; | |
| #clock-cells = <0x01>; | |
| phandle = <0x53a>; | |
| }; | |
| cpu-pmu { | |
| compatible = "arm,armv8-pmuv3"; | |
| interrupts = <0x01 0x05 0x04>; | |
| qcom,irq-is-percpu; | |
| phandle = <0x311>; | |
| }; | |
| qcom,msm-gladiator-v3@17900000 { | |
| compatible = "qcom,msm-gladiator-v3"; | |
| reg-names = "gladiator_base"; | |
| interrupts = <0x00 0x11 0x00>; | |
| reg = <0x17900000 0xd080>; | |
| }; | |
| qcom,msm-quin-auxpcm { | |
| qcom,msm-auxpcm-interface = "quinary"; | |
| compatible = "qcom,msm-auxpcm-dev"; | |
| qcom,msm-cpudai-auxpcm-sync = <0x01 0x01>; | |
| qcom,msm-cpudai-auxpcm-frame = <0x05 0x04>; | |
| qcom,msm-cpudai-auxpcm-quant = <0x02 0x02>; | |
| qcom,msm-cpudai-afe-clk-ver = <0x02>; | |
| qcom,msm-cpudai-auxpcm-slot-mapping = <0x01 0x01>; | |
| qcom,msm-cpudai-auxpcm-num-slots = <0x01 0x01>; | |
| qcom,msm-cpudai-auxpcm-data = <0x00 0x00>; | |
| qcom,msm-cpudai-auxpcm-pcm-clk-rate = <0x1f4000 0x1f4000>; | |
| phandle = <0x4c2>; | |
| qcom,msm-cpudai-auxpcm-mode = <0x00 0x00>; | |
| }; | |
| cti@7900000 { | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti-apss_cti2"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x387>; | |
| arm,primecell-periphid = <0x3b966>; | |
| reg = <0x7900000 0x1000>; | |
| }; | |
| rpmh-regulator-ldoa3 { | |
| qcom,supported-modes = <0x02 0x04>; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "ldoa3"; | |
| mboxes = <0x8a 0x00>; | |
| qcom,regulator-type = "pmic4-ldo"; | |
| qcom,mode-threshold-currents = <0x00 0x01>; | |
| regulator-l3 { | |
| qcom,init-mode = <0x02>; | |
| phandle = <0x33b>; | |
| qcom,init-voltage = <0xf4240>; | |
| regulator-min-microvolt = <0xf4240>; | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0xf4240>; | |
| regulator-name = "pm8998_l3"; | |
| }; | |
| }; | |
| tgu@6b0c000 { | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| tgu-regs = <0x04>; | |
| reg-names = "tgu-base"; | |
| coresight-name = "coresight-tgu-ipcb"; | |
| clock-names = "apb_pclk"; | |
| tgu-steps = <0x03>; | |
| tgu-timer-counters = <0x08>; | |
| phandle = <0x39f>; | |
| arm,primecell-periphid = <0x3b999>; | |
| reg = <0x6b0c000 0x1000>; | |
| tgu-conditions = <0x04>; | |
| }; | |
| qmi-tmd-devices { | |
| compatible = "qcom,qmi_cooling_devices"; | |
| adsp { | |
| qcom,instance-id = <0x01>; | |
| adsp_vdd { | |
| qcom,qmi-dev-name = "cpuv_restriction_cold"; | |
| phandle = <0x104>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| }; | |
| cdsp { | |
| qcom,instance-id = <0x43>; | |
| cdsp_vdd { | |
| qcom,qmi-dev-name = "cpuv_restriction_cold"; | |
| phandle = <0x105>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| }; | |
| slpi { | |
| qcom,instance-id = <0x53>; | |
| slpi_vdd { | |
| qcom,qmi-dev-name = "cpuv_restriction_cold"; | |
| phandle = <0x106>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| }; | |
| modem { | |
| qcom,instance-id = <0x00>; | |
| modem_pa { | |
| qcom,qmi-dev-name = "pa"; | |
| phandle = <0x32f>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| modem_skin { | |
| qcom,qmi-dev-name = "modem_skin"; | |
| phandle = <0x332>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| modem_current { | |
| qcom,qmi-dev-name = "modem_current"; | |
| phandle = <0x331>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| modem_proc { | |
| qcom,qmi-dev-name = "modem"; | |
| phandle = <0x330>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| modem_vdd { | |
| qcom,qmi-dev-name = "cpuv_restriction_cold"; | |
| phandle = <0x103>; | |
| #cooling-cells = <0x02>; | |
| }; | |
| }; | |
| }; | |
| spi@88c000 { | |
| compatible = "qcom,spi-geni"; | |
| clocks = <0x22 0x52 0x22 0x6c 0x22 0x6d>; | |
| qcom,wrapper-core = <0x35>; | |
| reg-names = "se_phys"; | |
| pinctrl-1 = <0x50>; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| status = "disabled"; | |
| #address-cells = <0x01>; | |
| interrupts = <0x00 0x25c 0x00>; | |
| #size-cells = <0x00>; | |
| dma-names = "tx\0rx"; | |
| phandle = <0x2d6>; | |
| reg = <0x88c000 0x4000>; | |
| pinctrl-0 = <0x4f>; | |
| dmas = <0x38 0x00 0x03 0x01 0x40 0x00 0x38 0x01 0x03 0x01 0x40 0x00>; | |
| spi-max-frequency = <0x2faf080>; | |
| pinctrl-names = "default\0sleep"; | |
| }; | |
| qcom,smp2pgpio_test_smp2p_5_in { | |
| gpios = <0x1b8 0x00 0x00>; | |
| compatible = "qcom,smp2pgpio_test_smp2p_5_in"; | |
| }; | |
| qcom,chd_gold { | |
| compatible = "qcom,core-hang-detect"; | |
| qcom,threshold-arr = <0x17e40058 0x17e50058 0x17e60058 0x17e70058>; | |
| label = "gold"; | |
| qcom,config-arr = <0x17e40060 0x17e50060 0x17e60060 0x17e70060>; | |
| }; | |
| interrupt-controller@0xb220000 { | |
| compatible = "qcom,pdc-sdm845-v2"; | |
| #interrupt-cells = <0x03>; | |
| interrupt-parent = <0x7f>; | |
| phandle = <0x01>; | |
| reg = <0xb220000 0x400>; | |
| interrupt-controller; | |
| }; | |
| interrupt-controller@17a00000 { | |
| compatible = "arm,gic-v3"; | |
| #redistributor-regions = <0x01>; | |
| #interrupt-cells = <0x03>; | |
| interrupt-parent = <0x7f>; | |
| interrupts = <0x01 0x09 0x04>; | |
| ignored-save-restore-irqs = <0x26>; | |
| phandle = <0x7f>; | |
| reg = <0x17a00000 0x10000 0x17a60000 0x100000>; | |
| redistributor-stride = <0x00 0x20000>; | |
| interrupt-controller; | |
| }; | |
| syscon@0x5091540 { | |
| compatible = "syscon"; | |
| phandle = <0x1a>; | |
| reg = <0x5091540 0x04>; | |
| }; | |
| qcom,glink-ssr-dsps { | |
| compatible = "qcom,glink_ssr"; | |
| qcom,xprt = "smem"; | |
| qcom,notify-edges = <0xe5 0xe1 0xe3>; | |
| label = "slpi"; | |
| qcom,edge = "dsps"; | |
| phandle = <0xe2>; | |
| }; | |
| qcom,msm-compr-dsp { | |
| compatible = "qcom,msm-compr-dsp"; | |
| phandle = <0x27c>; | |
| }; | |
| jtagmm@7740000 { | |
| compatible = "qcom,jtagv8-mm"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "etm-base"; | |
| clock-names = "core_clk"; | |
| phandle = <0x2f5>; | |
| reg = <0x7740000 0x1000>; | |
| qcom,coresight-jtagmm-cpu = <0x18>; | |
| }; | |
| qcom,glink-smem-native-xprt-cdsp@86000000 { | |
| compatible = "qcom,glink-smem-native-xprt"; | |
| reg-names = "smem\0irq-reg-base"; | |
| interrupts = <0x00 0x23e 0x01>; | |
| label = "cdsp"; | |
| qcom,irq-mask = <0x10>; | |
| reg = <0x86000000 0x200000 0x1799000c 0x04>; | |
| }; | |
| qcom,smp2pgpio_test_smp2p_2_in { | |
| gpios = <0x1b4 0x00 0x00>; | |
| compatible = "qcom,smp2pgpio_test_smp2p_2_in"; | |
| }; | |
| qcom,dsi-display@20 { | |
| compatible = "qcom,dsi-display"; | |
| clocks = <0x2bc 0x06 0x2bc 0x09>; | |
| lab-supply = <0x4e2>; | |
| pinctrl-1 = <0x41c 0x41e>; | |
| clock-names = "mux_byte_clk\0mux_pixel_clk"; | |
| vddio-supply = <0x120>; | |
| qcom,dsi-panel = <0x4f7>; | |
| label = "dsi_innolux_td4328_1080p_cmd_display"; | |
| ibb-supply = <0x4e3>; | |
| qcom,5v-boost-gpio = <0x34 0x78 0x00>; | |
| phandle = <0x554>; | |
| qcom,dsi-ctrl = <0x2c3>; | |
| qcom,display-type = "primary"; | |
| pinctrl-0 = <0x41b 0x41d>; | |
| qcom,platform-mipi-mode-oe = <0x34 0x32 0x00>; | |
| qcom,platform-te-gpio = <0x34 0x0a 0x00>; | |
| qcom,dsi-phy = <0x2c5>; | |
| qcom,platform-reset-gpio = <0x34 0x06 0x00>; | |
| pinctrl-names = "panel_active\0panel_suspend"; | |
| }; | |
| qcom,msm-dai-tdm-quat-tx { | |
| compatible = "qcom,msm-dai-tdm"; | |
| qcom,msm-cpudai-tdm-group-port-id = <0x9031>; | |
| qcom,msm-cpudai-tdm-clk-internal = <0x01>; | |
| qcom,msm-cpudai-tdm-sync-mode = <0x01>; | |
| qcom,msm-cpudai-tdm-clk-rate = <0x177000>; | |
| qcom,msm-cpudai-tdm-data-out = <0x00>; | |
| qcom,msm-cpudai-tdm-data-delay = <0x01>; | |
| qcom,msm-cpudai-tdm-group-id = <0x9131>; | |
| qcom,msm-cpudai-tdm-invert-sync = <0x01>; | |
| qcom,msm-cpudai-tdm-group-num-ports = <0x01>; | |
| qcom,msm-cpudai-tdm-sync-src = <0x01>; | |
| qcom,msm-dai-q6-tdm-quat-tx-0 { | |
| compatible = "qcom,msm-dai-q6-tdm"; | |
| qcom,msm-cpudai-tdm-dev-id = <0x9031>; | |
| phandle = <0x2a9>; | |
| qcom,msm-cpudai-tdm-data-align = <0x00>; | |
| }; | |
| }; | |
| qcom,pcie@0x1c08000 { | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| qcom,l1ss-supported; | |
| clocks = <0x22 0x3e 0x21 0x00 0x22 0x39 0x22 0x3b 0x22 0x3d 0x22 0x3f 0x22 0x3c 0x22 0x40 0x22 0x06 0x22 0x42 0x22 0x41>; | |
| qcom,msi-gicm-base = <0x2e0>; | |
| qcom,msm-bus,vectors-KBps = <0x64 0x200 0x00 0x00 0x64 0x200 0x1f4 0x320>; | |
| vreg-0.9-supply = <0x2f>; | |
| resets = <0x22 0x02 0x22 0x19>; | |
| qcom,boot-option = <0x01>; | |
| reg-names = "parf\0phy\0dm_core\0elbi\0conf\0io\0bars"; | |
| gdsc-vdd-supply = <0x26a>; | |
| qcom,vreg-0.9-voltage-level = <0xd6d80 0xd6d80 0x5dc0>; | |
| qcom,ep-latency = <0x0a>; | |
| qcom,vreg-cx-voltage-level = <0x10000 0x101 0x00>; | |
| qcom,slv-addr-space-size = <0x20000000>; | |
| clock-names = "pcie_1_pipe_clk\0pcie_1_ref_clk_src\0pcie_1_aux_clk\0pcie_1_cfg_ahb_clk\0pcie_1_mstr_axi_clk\0pcie_1_slv_axi_clk\0pcie_1_ldo\0pcie_1_slv_q2a_axi_clk\0pcie_tbu_clk\0pcie_phy_refgen_clk\0pcie_phy_aux_clk"; | |
| vreg-cx-supply = <0x1b>; | |
| interrupt-map-mask = <0x00 0x00 0x00 0xffffffff>; | |
| iommu-map = <0x00 0x29 0x1c00 0x01 0x100 0x29 0x1c01 0x01 0x200 0x29 0x1c02 0x01 0x300 0x29 0x1c03 0x01 0x400 0x29 0x1c04 0x01 0x500 0x29 0x1c05 0x01 0x600 0x29 0x1c06 0x01 0x700 0x29 0x1c07 0x01 0x800 0x29 0x1c08 0x01 0x900 0x29 0x1c09 0x01 0xa00 0x29 0x1c0a 0x01 0xb00 0x29 0x1c0b 0x01 0xc00 0x29 0x1c0c 0x01 0xd00 0x29 0x1c0d 0x01 0xe00 0x29 0x1c0e 0x01 0xf00 0x29 0x1c0f 0x01>; | |
| qcom,msm-bus,name = "pcie1"; | |
| ranges = <0x1000000 0x00 0x40200000 0x40200000 0x00 0x100000 0x2000000 0x00 0x40300000 0x40300000 0x00 0x1fd00000>; | |
| perst-gpio = <0x34 0x66 0x00>; | |
| status = "disabled"; | |
| linux,pci-domain = <0x01>; | |
| #interrupt-cells = <0x01>; | |
| interrupt-parent = <0x266>; | |
| #address-cells = <0x03>; | |
| interrupts = <0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f 0x20 0x21 0x22 0x23 0x24 0x25>; | |
| interrupt-map = <0x00 0x00 0x00 0x00 0x7f 0x00 0x133 0x00 0x00 0x00 0x00 0x01 0x7f 0x00 0x1b2 0x00 0x00 0x00 0x00 0x02 0x7f 0x00 0x1b3 0x00 0x00 0x00 0x00 0x03 0x7f 0x00 0x1b6 0x00 0x00 0x00 0x00 0x04 0x7f 0x00 0x1b7 0x00 0x00 0x00 0x00 0x05 0x7f 0x00 0x132 0x00 0x00 0x00 0x00 0x06 0x7f 0x00 0x2c0 0x00 0x00 0x00 0x00 0x07 0x7f 0x00 0x2c1 0x00 0x00 0x00 0x00 0x08 0x7f 0x00 0x2c2 0x00 0x00 0x00 0x00 0x09 0x7f 0x00 0x2c3 0x00 0x00 0x00 0x00 0x0a 0x7f 0x00 0x2c4 0x00 0x00 0x00 0x00 0x0b 0x7f 0x00 0x2c5 0x00 0x00 0x00 0x00 0x0c 0x7f 0x00 0x2c6 0x00 0x00 0x00 0x00 0x0d 0x7f 0x00 0x2c7 0x00 0x00 0x00 0x00 0x0e 0x7f 0x00 0x2c8 0x00 0x00 0x00 0x00 0x0f 0x7f 0x00 0x2c9 0x00 0x00 0x00 0x00 0x10 0x7f 0x00 0x2ca 0x00 0x00 0x00 0x00 0x11 0x7f 0x00 0x2cb 0x00 0x00 0x00 0x00 0x12 0x7f 0x00 0x2cc 0x00 0x00 0x00 0x00 0x13 0x7f 0x00 0x2cd 0x00 0x00 0x00 0x00 0x14 0x7f 0x00 0x2ce 0x00 0x00 0x00 0x00 0x15 0x7f 0x00 0x2cf 0x00 0x00 0x00 0x00 0x16 0x7f 0x00 0x2d0 0x00 0x00 0x00 0x00 0x17 0x7f 0x00 0x2d1 0x00 0x00 0x00 0x00 0x18 0x7f 0x00 0x2d2 0x00 0x00 0x00 0x00 0x19 0x7f 0x00 0x2d3 0x00 0x00 0x00 0x00 0x1a 0x7f 0x00 0x2d4 0x00 0x00 0x00 0x00 0x1b 0x7f 0x00 0x2d5 0x00 0x00 0x00 0x00 0x1c 0x7f 0x00 0x2d6 0x00 0x00 0x00 0x00 0x1d 0x7f 0x00 0x2d7 0x00 0x00 0x00 0x00 0x1e 0x7f 0x00 0x2d8 0x00 0x00 0x00 0x00 0x1f 0x7f 0x00 0x2d9 0x00 0x00 0x00 0x00 0x20 0x7f 0x00 0x2da 0x00 0x00 0x00 0x00 0x21 0x7f 0x00 0x2db 0x00 0x00 0x00 0x00 0x22 0x7f 0x00 0x2dc 0x00 0x00 0x00 0x00 0x23 0x7f 0x00 0x2dd 0x00 0x00 0x00 0x00 0x24 0x7f 0x00 0x2de 0x00 0x00 0x00 0x00 0x25 0x7f 0x00 0x2df 0x00>; | |
| qcom,use-19p2mhz-aux-clk; | |
| #size-cells = <0x02>; | |
| vreg-1.8-supply = <0x2e>; | |
| phandle = <0x266>; | |
| qcom,phy-status-offset = <0x1aac>; | |
| wake-gpio = <0x34 0x0b 0x00>; | |
| qcom,vreg-1.8-voltage-level = <0x124f80 0x124f80 0x5dc0>; | |
| qcom,aux-clk-sync; | |
| reg = <0x1c08000 0x2000 0x1c0a000 0x2000 0x40000000 0xf1d 0x40000f20 0xa8 0x40100000 0x100000 0x40200000 0x100000 0x40300000 0x1fd00000>; | |
| pinctrl-0 = <0x267 0x268 0x269>; | |
| max-clock-frequency-hz = <0x00 0x00 0x124f800 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x5f5e100 0x00>; | |
| qcom,msi-gicm-addr = <0x17a00040>; | |
| qcom,l1-supported; | |
| reset-names = "pcie_1_core_reset\0pcie_1_phy_reset"; | |
| qcom,phy-sequence = <0x1804 0x03 0x00 0xdc 0x27 0x00 0x14 0x01 0x00 0x20 0x31 0x00 0x24 0x01 0x00 0x28 0xde 0x00 0x2c 0x07 0x00 0x34 0x4c 0x00 0x38 0x06 0x00 0x54 0x18 0x00 0x58 0xb0 0x00 0x6c 0x8c 0x00 0x70 0x20 0x00 0x78 0x14 0x00 0x7c 0x34 0x00 0xb4 0x06 0x00 0xb8 0x06 0x00 0xc0 0x16 0x00 0xc4 0x16 0x00 0xcc 0x36 0x00 0xd0 0x36 0x00 0xf0 0x05 0x00 0xf8 0x42 0x00 0x100 0x82 0x00 0x108 0x68 0x00 0x11c 0x55 0x00 0x120 0x55 0x00 0x124 0x03 0x00 0x128 0xab 0x00 0x12c 0xaa 0x00 0x130 0x02 0x00 0x150 0x3f 0x00 0x158 0x3f 0x00 0x178 0x10 0x00 0x1cc 0x04 0x00 0x1d0 0x30 0x00 0x1e0 0x04 0x00 0x1e8 0x73 0x00 0x1f0 0x1c 0x00 0x1fc 0x15 0x00 0x21c 0x04 0x00 0x224 0x01 0x00 0x228 0x22 0x00 0x22c 0x00 0x00 0x98 0x05 0x00 0x80c 0x00 0x00 0x818 0x0d 0x00 0x860 0x01 0x00 0x864 0x3a 0x00 0x87c 0x2f 0x00 0x8c0 0x09 0x00 0x8c4 0x09 0x00 0x8c8 0x1a 0x00 0x8d0 0x01 0x00 0x8d4 0x07 0x00 0x8d8 0x31 0x00 0x8dc 0x31 0x00 0x8e0 0x03 0x00 0x8fc 0x02 0x00 0x900 0x01 0x00 0x908 0x12 0x00 0x914 0x25 0x00 0x918 0x00 0x00 0x91c 0x05 0x00 0x920 0x01 0x00 0x924 0x26 0x00 0x928 0x12 0x00 0x930 0x04 0x00 0x934 0x04 0x00 0x938 0x09 0x00 0x954 0x15 0x00 0x960 0x32 0x00 0x968 0x7f 0x00 0x96c 0x07 0x00 0x978 0x04 0x00 0x980 0x70 0x00 0x984 0x8b 0x00 0x988 0x08 0x00 0x98c 0x09 0x00 0x990 0x03 0x00 0x994 0x04 0x00 0x998 0x02 0x00 0x99c 0x0c 0x00 0x9a4 0x02 0x00 0x9c0 0x5c 0x00 0x9c4 0x3e 0x00 0x9c8 0x3f 0x00 0xa30 0x01 0x00 0xa34 0xa0 0x00 0xa38 0x08 0x00 0xaa4 0x01 0x00 0xaac 0xc3 0x00 0xab0 0x00 0x00 0xab8 0x8c 0x00 0xac0 0x7f 0x00 0xac4 0x2a 0x00 0x810 0x0c 0x00 0x814 0x00 0x00 0xacc 0x04 0x00 0x93c 0x20 0x00 0x100c 0x00 0x00 0x1018 0x0d 0x00 0x1060 0x01 0x00 0x1064 0x3a 0x00 0x107c 0x2f 0x00 0x10c0 0x09 0x00 0x10c4 0x09 0x00 0x10c8 0x1a 0x00 0x10d0 0x01 0x00 0x10d4 0x07 0x00 0x10d8 0x31 0x00 0x10dc 0x31 0x00 0x10e0 0x03 0x00 0x10fc 0x02 0x00 0x1100 0x01 0x00 0x1108 0x12 0x00 0x1114 0x25 0x00 0x1118 0x00 0x00 0x111c 0x05 0x00 0x1120 0x01 0x00 0x1124 0x26 0x00 0x1128 0x12 0x00 0x1130 0x04 0x00 0x1134 0x04 0x00 0x1138 0x09 0x00 0x1154 0x15 0x00 0x1160 0x32 0x00 0x1168 0x7f 0x00 0x116c 0x07 0x00 0x1178 0x04 0x00 0x1180 0x70 0x00 0x1184 0x8b 0x00 0x1188 0x08 0x00 0x118c 0x09 0x00 0x1190 0x03 0x00 0x1194 0x04 0x00 0x1198 0x02 0x00 0x119c 0x0c 0x00 0x11a4 0x02 0x00 0x11c0 0x5c 0x00 0x11c4 0x3e 0x00 0x11c8 0x3f 0x00 0x1230 0x01 0x00 0x1234 0xa0 0x00 0x1238 0x08 0x00 0x12a4 0x01 0x00 0x12ac 0xc3 0x00 0x12b0 0x00 0x00 0x12b8 0x8c 0x00 0x12c0 0x7f 0x00 0x12c4 0x2a 0x00 0x1010 0x0c 0x00 0x1014 0x0f 0x00 0x12cc 0x04 0x00 0x113c 0x20 0x00 0x195c 0x3f 0x00 0x1974 0x50 0x00 0x196c 0x9f 0x00 0x182c 0x19 0x00 0x1840 0x07 0x00 0x1854 0x17 0x00 0x1868 0x09 0x00 0x1800 0x00 0x00 0xaa8 0x01 0x00 0x12a8 0x01 0x00 0x1808 0x01 0x00>; | |
| interrupt-names = "int_msi\0int_a\0int_b\0int_c\0int_d\0int_global_int\0msi_0\0msi_1\0msi_2\0msi_3\0msi_4\0msi_5\0msi_6\0msi_7\0msi_8\0msi_9\0msi_10\0msi_11\0msi_12\0msi_13\0msi_14\0msi_15\0msi_16\0msi_17\0msi_18\0msi_19\0msi_20\0msi_21\0msi_22\0msi_23\0msi_24\0msi_25\0msi_26\0msi_27\0msi_28\0msi_29\0msi_30\0msi_31"; | |
| qcom,max-link-speed = <0x03>; | |
| qcom,smmu-sid-base = <0x1c00>; | |
| pinctrl-names = "default"; | |
| cell-index = <0x01>; | |
| }; | |
| qcom,smp2pgpio-ipa-1-out { | |
| compatible = "qcom,smp2pgpio"; | |
| gpio-controller; | |
| #interrupt-cells = <0x02>; | |
| phandle = <0xe7>; | |
| qcom,entry-name = "ipa"; | |
| #gpio-cells = <0x02>; | |
| qcom,remote-pid = <0x01>; | |
| interrupt-controller; | |
| }; | |
| qcom,cpu-bwmon { | |
| compatible = "qcom,bimc-bwmon4"; | |
| reg-names = "base\0global_base"; | |
| qcom,count-unit = <0x10000>; | |
| interrupts = <0x00 0x245 0x04>; | |
| qcom,mport = <0x00>; | |
| qcom,hw-timer-hz = <0x124f800>; | |
| phandle = <0x30a>; | |
| qcom,target-dev = <0x82>; | |
| reg = <0x1436400 0x300 0x1436300 0x200>; | |
| }; | |
| qcom,mdss_rotator@ae00000 { | |
| qcom,mdss-default-ot-rd-limit = <0x20>; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,msm-bus,num-cases = <0x03>; | |
| cache-slices = <0x2d 0x04>; | |
| power-domains = <0x2c>; | |
| compatible = "qcom,sde_rotator"; | |
| clocks = <0x22 0x1b 0x22 0x1c 0x20 0x00 0x20 0x20 0x20 0x01>; | |
| qcom,mdss-default-ot-wr-limit = <0x20>; | |
| qcom,msm-bus,vectors-KBps = <0x19 0x200 0x00 0x00 0x19 0x200 0x00 0x61a800 0x19 0x200 0x00 0x61a800>; | |
| reg-names = "mdp_phys\0rot_vbif_phys"; | |
| rot-vdd-supply = <0x19>; | |
| qcom,mdss-rot-safe-lut = <0xffff 0xffff>; | |
| qcom,mdss-rot-mode = <0x01>; | |
| qcom,mdss-rot-qos-lut = <0x00 0x00 0x00 0x00>; | |
| clock-names = "gcc_iface\0gcc_bus\0iface_clk\0rot_clk\0axi_clk"; | |
| qcom,mdss-rot-vbif-qos-setting = <0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03>; | |
| qcom,supply-names = "rot-vdd"; | |
| qcom,mdss-rot-vbif-memtype = <0x03 0x03>; | |
| qcom,msm-bus,name = "mdss_rotator"; | |
| qcom,mdss-inline-rot-danger-lut = <0x55aaff 0xffff>; | |
| interrupt-parent = <0x2c>; | |
| interrupts = <0x02 0x00>; | |
| qcom,mdss-highest-bank-bit = <0x02>; | |
| phandle = <0x2a>; | |
| qcom,mdss-inline-rot-safe-lut = <0xf000 0xff00>; | |
| cache-slice-names = "rotator"; | |
| reg = <0xae00000 0xac000 0xaeb8000 0x3000>; | |
| qcom,mdss-inline-rot-qos-lut = <0x44556677 0x112233 0x44556677 0x112233>; | |
| #list-cells = <0x01>; | |
| qcom,mdss-rot-danger-lut = <0x00 0x00>; | |
| qcom,mdss-rot-cdp-setting = <0x01 0x01>; | |
| qcom,mdss-sbuf-headroom = <0x14>; | |
| qcom,smmu_rot_sec_cb { | |
| compatible = "qcom,smmu_sde_rot_sec"; | |
| phandle = <0x2c2>; | |
| iommus = <0x29 0x1091 0x00>; | |
| }; | |
| qcom,rot-reg-bus { | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| qcom,msm-bus,vectors-KBps = <0x01 0x24e 0x00 0x00 0x01 0x24e 0x00 0x12c00>; | |
| qcom,msm-bus,name = "mdss_rot_reg"; | |
| phandle = <0x2c0>; | |
| qcom,msm-bus,active-only; | |
| }; | |
| qcom,smmu_rot_unsec_cb { | |
| compatible = "qcom,smmu_sde_rot_unsec"; | |
| phandle = <0x2c1>; | |
| iommus = <0x29 0x1090 0x00>; | |
| }; | |
| }; | |
| qcom,kgsl-iommu { | |
| compatible = "qcom,kgsl-smmu-v2"; | |
| clocks = <0x22 0x26 0x22 0x1a 0x22 0x29>; | |
| clock-names = "iface_clk\0mem_clk\0mem_iface_clk"; | |
| qcom,retention; | |
| qcom,micro-mmu-control = <0x6000>; | |
| phandle = <0x4ca>; | |
| qcom,protect = <0x40000 0xc000>; | |
| reg = <0x5040000 0x10000>; | |
| qcom,hyp_secure_alloc; | |
| qcom,secure_align_mask = <0xfff>; | |
| gfx3d_user { | |
| compatible = "qcom,smmu-kgsl-cb"; | |
| qcom,gpu-offset = <0x48000>; | |
| label = "gfx3d_user"; | |
| phandle = <0x4cb>; | |
| iommus = <0x1ab 0x00>; | |
| }; | |
| gfx3d_secure { | |
| compatible = "qcom,smmu-kgsl-cb"; | |
| phandle = <0x4cc>; | |
| iommus = <0x1ab 0x02 0x1ab 0x01>; | |
| }; | |
| }; | |
| qcom,spss@1880000 { | |
| qcom,proxy-timeout-ms = <0x2710>; | |
| compatible = "qcom,pil-tz-generic"; | |
| qcom,vdd_cx-uV-uA = <0x181 0x186a0>; | |
| clocks = <0x21 0x00>; | |
| qcom,proxy-clock-names = "xo"; | |
| reg-names = "sp2soc_irq_status\0sp2soc_irq_clr\0sp2soc_irq_mask\0rmb_err\0rmb_err_spare2"; | |
| qcom,firmware-name = "spss"; | |
| clock-names = "xo"; | |
| qcom,pas-id = <0x0e>; | |
| qcom,spss-scsr-bits = <0x18 0x19>; | |
| vdd_cx-supply = <0x1b>; | |
| vdd_mx-supply = <0x8c>; | |
| status = "ok"; | |
| interrupts = <0x00 0x160 0x01>; | |
| vdd_mx-uV = <0x181 0x186a0>; | |
| mbox-names = "spss-pil"; | |
| memory-region = <0xbb>; | |
| mboxes = <0x80 0x00>; | |
| qcom,proxy-reg-names = "vdd_cx"; | |
| reg = <0x188101c 0x04 0x1881024 0x04 0x1881028 0x04 0x188103c 0x04 0x1882014 0x04>; | |
| qcom,signal-aop; | |
| qcom,pil-generic-irq-handler; | |
| }; | |
| i2c@894000 { | |
| compatible = "qcom,i2c-geni"; | |
| clocks = <0x22 0x56 0x22 0x6c 0x22 0x6d>; | |
| qcom,wrapper-core = <0x35>; | |
| pinctrl-1 = <0x44>; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| status = "ok"; | |
| #address-cells = <0x01>; | |
| interrupts = <0x00 0x25e 0x00>; | |
| #size-cells = <0x00>; | |
| dma-names = "tx\0rx"; | |
| phandle = <0x2d0>; | |
| reg = <0x894000 0x4000>; | |
| pinctrl-0 = <0x43>; | |
| dmas = <0x38 0x00 0x05 0x03 0x40 0x00 0x38 0x01 0x05 0x03 0x40 0x00>; | |
| qcom,clk-freq-out = <0x61a80>; | |
| pinctrl-names = "default\0sleep"; | |
| synaptics@70 { | |
| synaptics,irq-gpio = <0x34 0x7d 0x2008>; | |
| synaptics,reset-delay-ms = <0xc8>; | |
| compatible = "synaptics,dsx-i2c"; | |
| vdd_ana-supply = <0x34a>; | |
| synaptics,irq-on-state = <0x00>; | |
| pinctrl-1 = <0x42e 0x42d>; | |
| synaptics,bus-reg-name = "vcc_i2c"; | |
| synaptics,ub-i2c-addr = <0x20>; | |
| interrupt-parent = <0x34>; | |
| interrupts = <0x7d 0x02>; | |
| synaptics,reset-on-state = <0x00>; | |
| vcc_i2c-supply = <0x120>; | |
| synaptics,reset-active-ms = <0x14>; | |
| reg = <0x70>; | |
| pinctrl-0 = <0x423 0x425>; | |
| synaptics,pwr-reg-name = "vdd_ana"; | |
| synaptics,x-flip = <0x01>; | |
| synaptics,power-delay-ms = <0xc8>; | |
| synaptics,reset-gpio = <0x34 0x68 0x00>; | |
| pinctrl-names = "pmx_ts_active\0pmx_ts_suspend"; | |
| }; | |
| }; | |
| etm@7240000 { | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| coresight-name = "coresight-etm2"; | |
| clock-names = "apb_pclk"; | |
| cpu = <0x13>; | |
| phandle = <0x3a4>; | |
| arm,primecell-periphid = <0xbb95d>; | |
| reg = <0x7240000 0x1000>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x194>; | |
| phandle = <0x19d>; | |
| }; | |
| }; | |
| }; | |
| qcom,dsi-display@10 { | |
| compatible = "qcom,dsi-display"; | |
| clocks = <0x2bc 0x06 0x2bc 0x09>; | |
| pinctrl-1 = <0x41c 0x41e>; | |
| clock-names = "mux_byte_clk\0mux_pixel_clk"; | |
| qcom,dsi-panel = <0x4ed>; | |
| label = "dsi_sim_cmd_display"; | |
| phandle = <0x54a>; | |
| qcom,dsi-ctrl = <0x2c3>; | |
| qcom,display-type = "primary"; | |
| pinctrl-0 = <0x41b 0x41d>; | |
| qcom,dsi-phy = <0x2c5>; | |
| pinctrl-names = "panel_active\0panel_suspend"; | |
| }; | |
| qcom,dsi-display@1 { | |
| compatible = "qcom,dsi-display"; | |
| clocks = <0x2bc 0x06 0x2bc 0x09>; | |
| lab-supply = <0x4e2>; | |
| pinctrl-1 = <0x41c 0x41e>; | |
| clock-names = "mux_byte_clk\0mux_pixel_clk"; | |
| vddio-supply = <0x120>; | |
| qcom,dsi-panel = <0x4e4>; | |
| label = "dsi_sharp_4k_dsc_cmd_display"; | |
| ibb-supply = <0x4e3>; | |
| phandle = <0x541>; | |
| qcom,dsi-ctrl = <0x2c3 0x2c4>; | |
| qcom,display-type = "primary"; | |
| qcom,panel-mode-gpio = <0x34 0x34 0x00>; | |
| pinctrl-0 = <0x41b 0x41d>; | |
| qcom,platform-te-gpio = <0x34 0x0a 0x00>; | |
| qcom,dsi-phy = <0x2c5 0x2c6>; | |
| qcom,platform-reset-gpio = <0x34 0x06 0x00>; | |
| pinctrl-names = "panel_active\0panel_suspend"; | |
| }; | |
| msm_cdc_pinctrl@49 { | |
| compatible = "qcom,msm-cdc-pinctrl"; | |
| pinctrl-1 = <0x40e>; | |
| phandle = <0x531>; | |
| pinctrl-0 = <0x40f>; | |
| pinctrl-names = "aud_active\0aud_sleep"; | |
| }; | |
| spi@894000 { | |
| compatible = "qcom,spi-geni"; | |
| clocks = <0x22 0x56 0x22 0x6c 0x22 0x6d>; | |
| qcom,wrapper-core = <0x35>; | |
| reg-names = "se_phys"; | |
| pinctrl-1 = <0x54>; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| status = "disabled"; | |
| #address-cells = <0x01>; | |
| interrupts = <0x00 0x25e 0x00>; | |
| #size-cells = <0x00>; | |
| dma-names = "tx\0rx"; | |
| phandle = <0x2d8>; | |
| reg = <0x894000 0x4000>; | |
| pinctrl-0 = <0x53>; | |
| dmas = <0x38 0x00 0x05 0x01 0x40 0x00 0x38 0x01 0x05 0x01 0x40 0x00>; | |
| spi-max-frequency = <0x2faf080>; | |
| pinctrl-names = "default\0sleep"; | |
| }; | |
| qcom,llccbw { | |
| compatible = "qcom,devbw"; | |
| qcom,active-only; | |
| qcom,src-dst-ports = <0x81 0x200>; | |
| governor = "performance"; | |
| qcom,bw-tbl = <0x2fa 0x478 0x6b8 0x826 0xa25 0xb71 0xf27 0x134f 0x172b 0x1ae1>; | |
| phandle = <0x83>; | |
| }; | |
| rpmh-regulator-smpa7 { | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "smpa7"; | |
| mboxes = <0x8a 0x00>; | |
| regulator-s7 { | |
| phandle = <0xa2>; | |
| qcom,init-voltage = <0xdbba0>; | |
| regulator-min-microvolt = <0xdbba0>; | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0xfafa0>; | |
| regulator-name = "pm8998_s7"; | |
| }; | |
| }; | |
| jtagmm@7040000 { | |
| compatible = "qcom,jtagv8-mm"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "etm-base"; | |
| clock-names = "core_clk"; | |
| phandle = <0x2ee>; | |
| reg = <0x7040000 0x1000>; | |
| qcom,coresight-jtagmm-cpu = <0x11>; | |
| }; | |
| cti@69e4000 { | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti-ddr_dl_1_cti0"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x381>; | |
| arm,primecell-periphid = <0x3b966>; | |
| reg = <0x69e4000 0x1000>; | |
| }; | |
| i2c@a98000 { | |
| compatible = "qcom,i2c-geni"; | |
| clocks = <0x22 0x68 0x22 0x6e 0x22 0x6f>; | |
| qcom,wrapper-core = <0x5b>; | |
| pinctrl-1 = <0x6c>; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| status = "disabled"; | |
| #address-cells = <0x01>; | |
| interrupts = <0x00 0x167 0x00>; | |
| #size-cells = <0x00>; | |
| dma-names = "tx\0rx"; | |
| phandle = <0x2e4>; | |
| reg = <0xa98000 0x4000>; | |
| pinctrl-0 = <0x6b>; | |
| dmas = <0x5e 0x00 0x06 0x03 0x40 0x00 0x5e 0x01 0x06 0x03 0x40 0x00>; | |
| pinctrl-names = "default\0sleep"; | |
| }; | |
| qcom,smp2pgpio-ipa-1-in { | |
| compatible = "qcom,smp2pgpio"; | |
| gpio-controller; | |
| #interrupt-cells = <0x02>; | |
| phandle = <0xe8>; | |
| qcom,entry-name = "ipa"; | |
| #gpio-cells = <0x02>; | |
| qcom,is-inbound; | |
| qcom,remote-pid = <0x01>; | |
| interrupt-controller; | |
| }; | |
| restart@10ac000 { | |
| compatible = "qcom,pshold"; | |
| reg-names = "pshold-base\0tcsr-boot-misc-detect"; | |
| reg = <0xc264000 0x04 0x1fd3000 0x04>; | |
| }; | |
| timer@0x17C90000 { | |
| compatible = "arm,armv7-timer-mem"; | |
| ranges; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| reg = <0x17c90000 0x1000>; | |
| clock-frequency = <0x124f800>; | |
| frame@17cc0000 { | |
| frame-number = <0x01>; | |
| status = "disabled"; | |
| interrupts = <0x00 0x08 0x04>; | |
| reg = <0x17cc0000 0x1000>; | |
| }; | |
| frame@17cd0000 { | |
| frame-number = <0x02>; | |
| status = "disabled"; | |
| interrupts = <0x00 0x09 0x04>; | |
| reg = <0x17cd0000 0x1000>; | |
| }; | |
| frame@0x17CA0000 { | |
| frame-number = <0x00>; | |
| interrupts = <0x00 0x07 0x04 0x00 0x06 0x04>; | |
| reg = <0x17ca0000 0x1000 0x17cb0000 0x1000>; | |
| }; | |
| frame@17ce0000 { | |
| frame-number = <0x03>; | |
| status = "disabled"; | |
| interrupts = <0x00 0x0a 0x04>; | |
| reg = <0x17ce0000 0x1000>; | |
| }; | |
| frame@17d00000 { | |
| frame-number = <0x05>; | |
| status = "disabled"; | |
| interrupts = <0x00 0x0c 0x04>; | |
| reg = <0x17d00000 0x1000>; | |
| }; | |
| frame@17cf0000 { | |
| frame-number = <0x04>; | |
| status = "disabled"; | |
| interrupts = <0x00 0x0b 0x04>; | |
| reg = <0x17cf0000 0x1000>; | |
| }; | |
| frame@17d10000 { | |
| frame-number = <0x06>; | |
| status = "disabled"; | |
| interrupts = <0x00 0x0d 0x04>; | |
| reg = <0x17d10000 0x1000>; | |
| }; | |
| }; | |
| cti@601f000 { | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti15"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x395>; | |
| arm,primecell-periphid = <0x3b966>; | |
| reg = <0x601f000 0x1000>; | |
| }; | |
| spi@a98000 { | |
| compatible = "qcom,spi-geni"; | |
| clocks = <0x22 0x68 0x22 0x6e 0x22 0x6f>; | |
| qcom,wrapper-core = <0x5b>; | |
| reg-names = "se_phys"; | |
| pinctrl-1 = <0x7b>; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| status = "disabled"; | |
| #address-cells = <0x01>; | |
| interrupts = <0x00 0x167 0x00>; | |
| #size-cells = <0x00>; | |
| dma-names = "tx\0rx"; | |
| phandle = <0x2ec>; | |
| reg = <0xa98000 0x4000>; | |
| pinctrl-0 = <0x7a>; | |
| dmas = <0x5e 0x00 0x06 0x01 0x40 0x00 0x5e 0x01 0x06 0x01 0x40 0x00>; | |
| spi-max-frequency = <0x2faf080>; | |
| pinctrl-names = "default\0sleep"; | |
| }; | |
| qcom,msm-dai-tdm-quat-rx { | |
| compatible = "qcom,msm-dai-tdm"; | |
| qcom,msm-cpudai-tdm-group-port-id = <0x9030 0x9032>; | |
| qcom,msm-cpudai-tdm-clk-internal = <0x01>; | |
| qcom,msm-cpudai-tdm-sync-mode = <0x01>; | |
| qcom,msm-cpudai-tdm-clk-rate = <0x177000>; | |
| qcom,msm-cpudai-tdm-data-out = <0x00>; | |
| phandle = <0x4c5>; | |
| qcom,msm-cpudai-tdm-data-delay = <0x01>; | |
| qcom,msm-cpudai-tdm-group-id = <0x9130>; | |
| qcom,msm-cpudai-tdm-invert-sync = <0x01>; | |
| qcom,msm-cpudai-tdm-group-num-ports = <0x02>; | |
| qcom,msm-cpudai-tdm-sync-src = <0x01>; | |
| qcom,msm-dai-q6-tdm-quat-rx-0 { | |
| compatible = "qcom,msm-dai-q6-tdm"; | |
| qcom,msm-cpudai-tdm-dev-id = <0x9030>; | |
| phandle = <0x2a8>; | |
| qcom,msm-cpudai-tdm-data-align = <0x00>; | |
| }; | |
| qcom,msm-dai-q6-tdm-quat-rx-1 { | |
| compatible = "qcom,msm-dai-q6-tdm"; | |
| qcom,msm-cpudai-tdm-dev-id = <0x9032>; | |
| phandle = <0x2aa>; | |
| qcom,msm-cpudai-tdm-data-align = <0x00>; | |
| }; | |
| }; | |
| qcom,smp2pgpio-rdbg-5-in { | |
| compatible = "qcom,smp2pgpio"; | |
| gpio-controller; | |
| #interrupt-cells = <0x02>; | |
| phandle = <0x27>; | |
| qcom,entry-name = "rdbg"; | |
| #gpio-cells = <0x02>; | |
| qcom,is-inbound; | |
| qcom,remote-pid = <0x05>; | |
| interrupt-controller; | |
| }; | |
| cti@69e1000 { | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti-ddr_dl_0_cti"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x380>; | |
| arm,primecell-periphid = <0x3b966>; | |
| reg = <0x69e1000 0x1000>; | |
| }; | |
| qcom,msm-pcm { | |
| compatible = "qcom,msm-pcm-dsp"; | |
| qcom,msm-pcm-dsp-id = <0x00>; | |
| phandle = <0x271>; | |
| }; | |
| rpmh-regulator-ldoa1 { | |
| qcom,supported-modes = <0x02 0x04>; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "ldoa1"; | |
| proxy-supply = <0x2f>; | |
| mboxes = <0x8a 0x00>; | |
| qcom,regulator-type = "pmic4-ldo"; | |
| qcom,mode-threshold-currents = <0x00 0x01>; | |
| regulator-l1-so { | |
| qcom,init-mode = <0x02>; | |
| qcom,init-enable = <0x00>; | |
| qcom,init-voltage = <0xd6d80>; | |
| regulator-min-microvolt = <0xd6d80>; | |
| qcom,set = <0x02>; | |
| regulator-max-microvolt = <0xd6d80>; | |
| regulator-name = "pm8998_l1_so"; | |
| }; | |
| regulator-l1-ao { | |
| qcom,init-mode = <0x02>; | |
| phandle = <0xa0>; | |
| qcom,init-voltage = <0xd6d80>; | |
| regulator-min-microvolt = <0xd6d80>; | |
| qcom,set = <0x01>; | |
| regulator-max-microvolt = <0xd6d80>; | |
| regulator-name = "pm8998_l1_ao"; | |
| }; | |
| regulator-l1 { | |
| qcom,proxy-consumer-enable; | |
| qcom,init-mode = <0x02>; | |
| phandle = <0x2f>; | |
| qcom,init-voltage = <0xd6d80>; | |
| regulator-min-microvolt = <0xd6d80>; | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0xd6d80>; | |
| regulator-name = "pm8998_l1"; | |
| qcom,proxy-consumer-current = <0x11940>; | |
| }; | |
| }; | |
| rpmh-regulator-ldoa28 { | |
| qcom,supported-modes = <0x02 0x04>; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "ldoa28"; | |
| mboxes = <0x8a 0x00>; | |
| qcom,regulator-type = "pmic4-ldo"; | |
| qcom,mode-threshold-currents = <0x00 0x01>; | |
| regulator-l28 { | |
| qcom,init-mode = <0x02>; | |
| phandle = <0x34a>; | |
| qcom,init-voltage = <0x2b9440>; | |
| regulator-min-microvolt = <0x2b9440>; | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x2de600>; | |
| regulator-name = "pm8998_l28"; | |
| }; | |
| }; | |
| qcom,cpubw { | |
| compatible = "qcom,devbw"; | |
| qcom,active-only; | |
| qcom,src-dst-ports = <0x01 0x302>; | |
| governor = "performance"; | |
| qcom,bw-tbl = <0x8f0 0x11e1 0x1964 0x1fc4 0x23c3 0x300a 0x379c>; | |
| phandle = <0x82>; | |
| }; | |
| cti@601c000 { | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti12"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x392>; | |
| arm,primecell-periphid = <0x3b966>; | |
| reg = <0x601c000 0x1000>; | |
| }; | |
| qcom,rpmhclk { | |
| compatible = "qcom,rpmh-clk-sdm845"; | |
| mbox-names = "apps"; | |
| mboxes = <0x8a 0x00>; | |
| #clock-cells = <0x01>; | |
| phandle = <0x21>; | |
| }; | |
| qcom,smp2pgpio-rdbg-2-in { | |
| compatible = "qcom,smp2pgpio"; | |
| gpio-controller; | |
| #interrupt-cells = <0x02>; | |
| phandle = <0x23>; | |
| qcom,entry-name = "rdbg"; | |
| #gpio-cells = <0x02>; | |
| qcom,is-inbound; | |
| qcom,remote-pid = <0x02>; | |
| interrupt-controller; | |
| }; | |
| qcom,msm-dai-fe { | |
| compatible = "qcom,msm-dai-fe"; | |
| }; | |
| qcom,smp2pgpio-rdbg-1-out { | |
| compatible = "qcom,smp2pgpio"; | |
| gpio-controller; | |
| #interrupt-cells = <0x02>; | |
| phandle = <0x26>; | |
| qcom,entry-name = "rdbg"; | |
| #gpio-cells = <0x02>; | |
| qcom,remote-pid = <0x01>; | |
| interrupt-controller; | |
| }; | |
| qcom,cpu0-l3lat-mon { | |
| compatible = "qcom,arm-memlat-mon"; | |
| qcom,cachemiss-ev = <0x17>; | |
| phandle = <0x30f>; | |
| qcom,target-dev = <0x87>; | |
| qcom,core-dev-table = <0x493e0 0x11e1a300 0x75300 0x18085800 0x9f600 0x1c9c3800 0xb6d00 0x22551000 0xdc500 0x26e8f000 0xef100 0x2ca1c800 0x114900 0x325aa000 0x12c000 0x38137800 0x143700 0x3dcc5000 0x15ae00 0x43852800 0x172500 0x48190800 0x19c800 0x4dd1e000 0x1af400 0x538ab800>; | |
| qcom,cpulist = <0x11 0x12 0x13 0x14>; | |
| }; | |
| qcom,spss_utils { | |
| compatible = "qcom,spss-utils"; | |
| qcom,spss-fuse2-addr = <0x7841c4>; | |
| qcom,spss-test-firmware-name = "spss2t"; | |
| qcom,spss-dev-firmware-name = "spss2d"; | |
| qcom,spss-fuse1-addr = <0x7841c4>; | |
| qcom,spss-debug-reg-addr = <0x1886020>; | |
| status = "ok"; | |
| qcom,spss-fuse1-bit = <0x1b>; | |
| phandle = <0x322>; | |
| qcom,spss-prod-firmware-name = "spss2p"; | |
| qcom,spss-fuse2-bit = <0x1a>; | |
| }; | |
| qcom,smp2p-adsp@1799000c { | |
| compatible = "qcom,smp2p"; | |
| interrupts = <0x00 0x9e 0x01>; | |
| reg = <0x1799000c 0x04>; | |
| qcom,remote-pid = <0x02>; | |
| qcom,irq-bitmask = <0x400>; | |
| }; | |
| qcom,qup_uart@0xa88000 { | |
| compatible = "qcom,msm-geni-console"; | |
| clocks = <0x22 0x60 0x22 0x6e 0x22 0x6f>; | |
| qcom,wrapper-core = <0x5b>; | |
| reg-names = "se_phys"; | |
| pinctrl-1 = <0x5d>; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| status = "disabled"; | |
| interrupts = <0x00 0x163 0x00>; | |
| phandle = <0x2dd>; | |
| reg = <0xa88000 0x4000>; | |
| pinctrl-0 = <0x5c>; | |
| pinctrl-names = "default\0sleep"; | |
| }; | |
| cti@7520000 { | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti-cpu5"; | |
| clock-names = "apb_pclk"; | |
| cpu = <0x16>; | |
| phandle = <0x39b>; | |
| arm,primecell-periphid = <0x3b966>; | |
| reg = <0x7520000 0x1000>; | |
| }; | |
| qcom,wb-display@0 { | |
| compatible = "qcom,wb-display"; | |
| label = "wb_display"; | |
| phandle = <0x4fa>; | |
| cell-index = <0x00>; | |
| }; | |
| qcom,smp2pgpio-ssr-smp2p-1-out { | |
| compatible = "qcom,smp2pgpio"; | |
| gpio-controller; | |
| #interrupt-cells = <0x02>; | |
| phandle = <0xb0>; | |
| qcom,entry-name = "master-kernel"; | |
| #gpio-cells = <0x02>; | |
| qcom,remote-pid = <0x01>; | |
| interrupt-controller; | |
| }; | |
| qcom,dsi-display@19 { | |
| compatible = "qcom,dsi-display"; | |
| clocks = <0x2bd 0x18 0x2bd 0x1b>; | |
| pinctrl-1 = <0x407>; | |
| clock-names = "mux_byte_clk\0mux_pixel_clk"; | |
| vddio-supply = <0x120>; | |
| qcom,dsi-panel = <0x4f6>; | |
| label = "dsi_lt8912_1080_dsi1_video_display"; | |
| phandle = <0x553>; | |
| qcom,dsi-ctrl = <0x2c4>; | |
| qcom,display-type = "secondary"; | |
| pinctrl-0 = <0x406>; | |
| qcom,dsi-phy = <0x2c6>; | |
| pinctrl-names = "panel_active\0panel_suspend"; | |
| }; | |
| rpmh-regulator-ldoa18 { | |
| qcom,supported-modes = <0x02 0x04>; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "ldoa18"; | |
| mboxes = <0x8a 0x00>; | |
| qcom,regulator-type = "pmic4-ldo"; | |
| qcom,mode-threshold-currents = <0x00 0x01>; | |
| regulator-l18 { | |
| qcom,init-mode = <0x02>; | |
| phandle = <0x344>; | |
| qcom,init-voltage = <0x294280>; | |
| regulator-min-microvolt = <0x294280>; | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x2d2a80>; | |
| regulator-name = "pm8998_l18"; | |
| }; | |
| }; | |
| ufsphy_mem@1d87000 { | |
| vdda-phy-supply = <0x2f>; | |
| compatible = "qcom,ufs-phy-qmp-v3"; | |
| clocks = <0x21 0x00 0x22 0x88 0x22 0xb9>; | |
| reg-names = "phy_mem"; | |
| lanes-per-direction = <0x02>; | |
| clock-names = "ref_clk_src\0ref_clk\0ref_aux_clk"; | |
| vdda-phy-max-microamp = <0xf5b4>; | |
| vdda-pll-max-microamp = <0x477c>; | |
| status = "ok"; | |
| phandle = <0xa9>; | |
| vdda-pll-supply = <0x2e>; | |
| reg = <0x1d87000 0xda8>; | |
| #phy-cells = <0x00>; | |
| }; | |
| qcom,gdsc@0x509100c { | |
| compatible = "qcom,gdsc"; | |
| clocks = <0x1c 0x02>; | |
| clock-names = "core_root_clk"; | |
| sw-reset = <0x1f>; | |
| status = "ok"; | |
| parent-supply = <0x1d>; | |
| qcom,force-enable-root-clk; | |
| phandle = <0x2ad>; | |
| reg = <0x509100c 0x04>; | |
| qcom,reset-aon-logic; | |
| regulator-name = "gpu_gx_gdsc"; | |
| qcom,poll-cfg-gdscr; | |
| domain-addr = <0x1e>; | |
| }; | |
| hwevent@0x014066f0 { | |
| compatible = "qcom,coresight-hwevent"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "ddr-ch0-cfg\0ddr-ch23-cfg\0ddr-ch0-ctrl\0ddr-ch23-ctrl"; | |
| coresight-name = "coresight-hwevent"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x35c>; | |
| reg = <0x14066f0 0x04 0x14166f0 0x04 0x1406038 0x04 0x1416038 0x04>; | |
| coresight-csr = <0x128>; | |
| }; | |
| tmc@6047000 { | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "tmc-base"; | |
| coresight-name = "coresight-tmc-etf"; | |
| clock-names = "apb_pclk"; | |
| arm,default-sink; | |
| phandle = <0x359>; | |
| arm,primecell-periphid = <0x3b961>; | |
| reg = <0x6047000 0x1000>; | |
| coresight-ctis = <0x133 0x134>; | |
| coresight-csr = <0x128>; | |
| ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@1 { | |
| reg = <0x01>; | |
| endpoint { | |
| remote-endpoint = <0x137>; | |
| phandle = <0x138>; | |
| slave-mode; | |
| }; | |
| }; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x136>; | |
| phandle = <0x124>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,glink-ssr-modem { | |
| compatible = "qcom,glink_ssr"; | |
| qcom,xprt = "smem"; | |
| qcom,notify-edges = <0xe1 0xe2 0xe3 0xe4>; | |
| label = "modem"; | |
| qcom,edge = "mpss"; | |
| phandle = <0xe5>; | |
| }; | |
| tpdm@6a24000 { | |
| qcom,msr-fix-req; | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "tpdm-base"; | |
| coresight-name = "coresight-tpdm-north"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x368>; | |
| arm,primecell-periphid = <0x3b968>; | |
| reg = <0x6a24000 0x1000>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x15f>; | |
| phandle = <0x152>; | |
| }; | |
| }; | |
| }; | |
| qcom,gpubw { | |
| compatible = "qcom,devbw"; | |
| qcom,src-dst-ports = <0x1a 0x200>; | |
| governor = "bw_vbif"; | |
| qcom,bw-tbl = <0x00 0x17d 0x23c 0x2fa 0x478 0x623 0x826 0xa25 0xb71 0xf27 0x134f 0x172b 0x1ae1>; | |
| phandle = <0x2ac>; | |
| }; | |
| devfreq-cpufreq { | |
| phandle = <0x312>; | |
| mincpubw-cpufreq { | |
| cpu-to-dev-map-4 = <0x1cb600 0x2fa 0x249f00 0xf27>; | |
| target-dev = <0x89>; | |
| cpu-to-dev-map-0 = <0x1a1300 0x2fa>; | |
| }; | |
| }; | |
| qcom,msm-stub-codec { | |
| compatible = "qcom,msm-stub-codec"; | |
| phandle = <0x4b4>; | |
| }; | |
| csr@6001000 { | |
| compatible = "qcom,coresight-csr"; | |
| reg-names = "csr-base"; | |
| coresight-name = "coresight-csr"; | |
| qcom,hwctrl-set-support; | |
| qcom,usb-bam-support; | |
| qcom,set-byte-cntr-support; | |
| phandle = <0x128>; | |
| qcom,blk-size = <0x01>; | |
| reg = <0x6001000 0x1000>; | |
| }; | |
| qcom,spmi@c440000 { | |
| compatible = "qcom,spmi-pmic-arb"; | |
| reg-names = "core\0chnls\0obsrvr\0intr\0cnfg"; | |
| qcom,channel = <0x00>; | |
| #interrupt-cells = <0x04>; | |
| #address-cells = <0x02>; | |
| interrupts = <0x00 0x1e1 0x00>; | |
| #size-cells = <0x00>; | |
| phandle = <0x2f6>; | |
| qcom,ee = <0x00>; | |
| reg = <0xc440000 0x1100 0xc600000 0x2000000 0xe600000 0x100000 0xe700000 0xa0000 0xc40a000 0x26000>; | |
| interrupt-names = "periph_irq"; | |
| cell-index = <0x00>; | |
| interrupt-controller; | |
| qcom,pm8005@5 { | |
| compatible = "qcom,spmi-pmic"; | |
| #address-cells = <0x02>; | |
| #size-cells = <0x00>; | |
| reg = <0x05 0x00>; | |
| regulator@1a00 { | |
| compatible = "qcom,qpnp-regulator"; | |
| status = "disabled"; | |
| reg = <0x1a00 0x100>; | |
| regulator-name = "pm8005_s3"; | |
| }; | |
| regulator@1d00 { | |
| compatible = "qcom,qpnp-regulator"; | |
| status = "disabled"; | |
| reg = <0x1d00 0x100>; | |
| regulator-name = "pm8005_s4"; | |
| }; | |
| regulator@1400 { | |
| compatible = "qcom,qpnp-regulator"; | |
| status = "disabled"; | |
| reg = <0x1400 0x100>; | |
| regulator-name = "pm8005_s1"; | |
| }; | |
| regulator@1700 { | |
| compatible = "qcom,qpnp-regulator"; | |
| status = "disabled"; | |
| reg = <0x1700 0x100>; | |
| regulator-name = "pm8005_s2"; | |
| }; | |
| }; | |
| qcom,pm8998@0 { | |
| compatible = "qcom,spmi-pmic"; | |
| #address-cells = <0x02>; | |
| #size-cells = <0x00>; | |
| reg = <0x00 0x00>; | |
| qcom,clkdiv@5d00 { | |
| compatible = "qcom,qpnp-clkdiv"; | |
| qcom,clkdiv-id = <0x03>; | |
| #clock-cells = <0x01>; | |
| phandle = <0x306>; | |
| reg = <0x5d00 0x100>; | |
| qcom,cxo-freq = <0x124f800>; | |
| qcom,clkdiv-init-freq = <0x124f800>; | |
| }; | |
| qcom,pm8998_rtc { | |
| qcom,qpnp-rtc-alarm-pwrup = <0x00>; | |
| compatible = "qcom,qpnp-rtc"; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| phandle = <0x302>; | |
| qcom,qpnp-rtc-write = <0x00>; | |
| qcom,pm8998_rtc_alarm@6100 { | |
| interrupts = <0x00 0x61 0x01 0x00>; | |
| reg = <0x6100 0x100>; | |
| }; | |
| qcom,pm8998_rtc_rw@6000 { | |
| reg = <0x6000 0x100>; | |
| }; | |
| }; | |
| qcom,revid@100 { | |
| compatible = "qcom,qpnp-revid"; | |
| phandle = <0x2f7>; | |
| reg = <0x100 0x100>; | |
| }; | |
| qcom,power-on@800 { | |
| qcom,system-reset; | |
| compatible = "qcom,qpnp-power-on"; | |
| qcom,pon-dbc-delay = <0x3d09>; | |
| interrupts = <0x00 0x08 0x00 0x00 0x00 0x08 0x01 0x00 0x00 0x08 0x04 0x00 0x00 0x08 0x05 0x00>; | |
| qcom,kpdpwr-sw-debounce; | |
| reg = <0x800 0x100>; | |
| interrupt-names = "kpdpwr\0resin\0resin-bark\0kpdpwr-resin-bark"; | |
| qcom,store-hard-reset-reason; | |
| qcom,pon_1 { | |
| qcom,s2-type = <0x04>; | |
| qcom,s1-timer = <0x1a40>; | |
| qcom,support-reset = <0x01>; | |
| qcom,pull-up = <0x01>; | |
| qcom,s2-timer = <0x7d0>; | |
| qcom,pon-type = <0x00>; | |
| linux,code = <0x74>; | |
| }; | |
| qcom,pon_2 { | |
| qcom,pull-up = <0x01>; | |
| qcom,pon-type = <0x01>; | |
| linux,code = <0x72>; | |
| }; | |
| qcom,pon_3 { | |
| qcom,s2-type = <0x08>; | |
| qcom,use-bark; | |
| qcom,s1-timer = <0x1a40>; | |
| qcom,support-reset = <0x01>; | |
| qcom,pull-up = <0x01>; | |
| qcom,s2-timer = <0x7d0>; | |
| qcom,pon-type = <0x03>; | |
| }; | |
| }; | |
| vadc@3100 { | |
| qcom,adc-vdd-reference = <0x753>; | |
| compatible = "qcom,qpnp-vadc-hc"; | |
| #address-cells = <0x01>; | |
| interrupts = <0x00 0x31 0x00 0x01>; | |
| #size-cells = <0x00>; | |
| phandle = <0x81>; | |
| reg = <0x3100 0x100>; | |
| interrupt-names = "eoc-int-en-set"; | |
| chan@4f { | |
| qcom,decimation = <0x02>; | |
| qcom,calibration-type = "ratiometric"; | |
| qcom,hw-settle-time = <0x02>; | |
| qcom,fast-avg-setup = <0x00>; | |
| qcom,pre-div-channel-scaling = <0x00>; | |
| label = "pa_therm1"; | |
| reg = <0x4f>; | |
| qcom,scale-function = <0x02>; | |
| }; | |
| chan@4d { | |
| qcom,decimation = <0x02>; | |
| qcom,calibration-type = "ratiometric"; | |
| qcom,hw-settle-time = <0x02>; | |
| qcom,fast-avg-setup = <0x00>; | |
| qcom,pre-div-channel-scaling = <0x00>; | |
| label = "msm_therm"; | |
| reg = <0x4d>; | |
| qcom,scale-function = <0x02>; | |
| }; | |
| chan@16 { | |
| qcom,decimation = <0x00>; | |
| qcom,calibration-type = "absolute"; | |
| qcom,hw-settle-time = <0x00>; | |
| qcom,fast-avg-setup = <0x00>; | |
| qcom,pre-div-channel-scaling = <0x00>; | |
| label = "gpio12_adc0"; | |
| reg = <0x16>; | |
| qcom,scale-function = <0x00>; | |
| }; | |
| chan@1 { | |
| qcom,decimation = <0x02>; | |
| qcom,calibration-type = "absolute"; | |
| qcom,hw-settle-time = <0x00>; | |
| qcom,fast-avg-setup = <0x00>; | |
| qcom,pre-div-channel-scaling = <0x00>; | |
| label = "ref_1250v"; | |
| reg = <0x01>; | |
| qcom,cal-val = <0x00>; | |
| qcom,scale-function = <0x00>; | |
| }; | |
| chan@14 { | |
| qcom,decimation = <0x00>; | |
| qcom,calibration-type = "absolute"; | |
| qcom,hw-settle-time = <0x00>; | |
| qcom,fast-avg-setup = <0x00>; | |
| qcom,pre-div-channel-scaling = <0x00>; | |
| label = "gpio10_adc0"; | |
| reg = <0x14>; | |
| qcom,scale-function = <0x00>; | |
| }; | |
| chan@12 { | |
| qcom,decimation = <0x00>; | |
| qcom,calibration-type = "absolute"; | |
| qcom,hw-settle-time = <0x00>; | |
| qcom,fast-avg-setup = <0x00>; | |
| qcom,pre-div-channel-scaling = <0x00>; | |
| label = "gpio8_adc0"; | |
| reg = <0x12>; | |
| qcom,scale-function = <0x00>; | |
| }; | |
| chan@97 { | |
| qcom,decimation = <0x00>; | |
| qcom,calibration-type = "absolute"; | |
| qcom,hw-settle-time = <0x00>; | |
| qcom,fast-avg-setup = <0x00>; | |
| qcom,pre-div-channel-scaling = <0x01>; | |
| label = "gpio21_adc1"; | |
| reg = <0x97>; | |
| qcom,scale-function = <0x00>; | |
| }; | |
| chan@6 { | |
| qcom,decimation = <0x02>; | |
| qcom,calibration-type = "absolute"; | |
| qcom,hw-settle-time = <0x00>; | |
| qcom,fast-avg-setup = <0x00>; | |
| qcom,pre-div-channel-scaling = <0x00>; | |
| label = "die_temp"; | |
| reg = <0x06>; | |
| qcom,cal-val = <0x00>; | |
| qcom,scale-function = <0x03>; | |
| }; | |
| chan@85 { | |
| qcom,decimation = <0x02>; | |
| qcom,calibration-type = "absolute"; | |
| qcom,hw-settle-time = <0x00>; | |
| qcom,fast-avg-setup = <0x00>; | |
| qcom,pre-div-channel-scaling = <0x01>; | |
| label = "vcoin"; | |
| reg = <0x85>; | |
| qcom,scale-function = <0x00>; | |
| }; | |
| chan@83 { | |
| qcom,decimation = <0x02>; | |
| qcom,calibration-type = "absolute"; | |
| qcom,hw-settle-time = <0x00>; | |
| qcom,fast-avg-setup = <0x00>; | |
| qcom,pre-div-channel-scaling = <0x01>; | |
| label = "vph_pwr"; | |
| reg = <0x83>; | |
| qcom,scale-function = <0x00>; | |
| }; | |
| chan@4c { | |
| qcom,decimation = <0x02>; | |
| qcom,calibration-type = "ratiometric"; | |
| qcom,hw-settle-time = <0x02>; | |
| qcom,fast-avg-setup = <0x00>; | |
| qcom,pre-div-channel-scaling = <0x00>; | |
| label = "xo_therm"; | |
| reg = <0x4c>; | |
| qcom,scale-function = <0x04>; | |
| }; | |
| chan@15 { | |
| qcom,decimation = <0x00>; | |
| qcom,calibration-type = "absolute"; | |
| qcom,hw-settle-time = <0x00>; | |
| qcom,fast-avg-setup = <0x00>; | |
| qcom,pre-div-channel-scaling = <0x00>; | |
| label = "gpio11_adc0"; | |
| reg = <0x15>; | |
| qcom,scale-function = <0x00>; | |
| }; | |
| chan@0 { | |
| qcom,decimation = <0x02>; | |
| qcom,calibration-type = "absolute"; | |
| qcom,hw-settle-time = <0x00>; | |
| qcom,fast-avg-setup = <0x00>; | |
| qcom,pre-div-channel-scaling = <0x00>; | |
| label = "ref_gnd"; | |
| reg = <0x00>; | |
| qcom,cal-val = <0x00>; | |
| qcom,scale-function = <0x00>; | |
| }; | |
| chan@51 { | |
| qcom,decimation = <0x02>; | |
| qcom,calibration-type = "ratiometric"; | |
| qcom,hw-settle-time = <0x02>; | |
| qcom,fast-avg-setup = <0x00>; | |
| qcom,pre-div-channel-scaling = <0x00>; | |
| label = "quiet_therm"; | |
| reg = <0x51>; | |
| qcom,scale-function = <0x02>; | |
| }; | |
| chan@13 { | |
| qcom,decimation = <0x00>; | |
| qcom,calibration-type = "absolute"; | |
| qcom,hw-settle-time = <0x00>; | |
| qcom,fast-avg-setup = <0x00>; | |
| qcom,pre-div-channel-scaling = <0x00>; | |
| label = "gpio9_adc0"; | |
| reg = <0x13>; | |
| qcom,scale-function = <0x00>; | |
| }; | |
| }; | |
| vadc@3400 { | |
| qcom,adc-vdd-reference = <0x753>; | |
| compatible = "qcom,qpnp-adc-tm-hc"; | |
| qcom,decimation = <0x00>; | |
| #thermal-sensor-cells = <0x01>; | |
| qcom,fast-avg-setup = <0x00>; | |
| qcom,adc_tm-vadc = <0x81>; | |
| #address-cells = <0x01>; | |
| interrupts = <0x00 0x34 0x00 0x01>; | |
| #size-cells = <0x00>; | |
| phandle = <0x303>; | |
| reg = <0x3400 0x100>; | |
| interrupt-names = "eoc-int-en-set"; | |
| chan@4f { | |
| qcom,thermal-node; | |
| qcom,btm-channel-number = <0x78>; | |
| qcom,calibration-type = "ratiometric"; | |
| qcom,hw-settle-time = <0x02>; | |
| qcom,pre-div-channel-scaling = <0x00>; | |
| label = "pa_therm1"; | |
| reg = <0x4f>; | |
| qcom,scale-function = <0x02>; | |
| }; | |
| chan@4d { | |
| qcom,thermal-node; | |
| qcom,btm-channel-number = <0x70>; | |
| qcom,calibration-type = "ratiometric"; | |
| qcom,hw-settle-time = <0x02>; | |
| qcom,pre-div-channel-scaling = <0x00>; | |
| label = "msm_therm"; | |
| reg = <0x4d>; | |
| qcom,scale-function = <0x02>; | |
| }; | |
| chan@83 { | |
| qcom,btm-channel-number = <0x60>; | |
| qcom,calibration-type = "absolute"; | |
| qcom,hw-settle-time = <0x00>; | |
| qcom,pre-div-channel-scaling = <0x01>; | |
| label = "vph_pwr"; | |
| reg = <0x83>; | |
| qcom,scale-function = <0x00>; | |
| }; | |
| chan@4c { | |
| qcom,thermal-node; | |
| qcom,btm-channel-number = <0x68>; | |
| qcom,calibration-type = "ratiometric"; | |
| qcom,hw-settle-time = <0x02>; | |
| qcom,pre-div-channel-scaling = <0x00>; | |
| label = "xo_therm"; | |
| reg = <0x4c>; | |
| qcom,scale-function = <0x04>; | |
| }; | |
| chan@51 { | |
| qcom,thermal-node; | |
| qcom,btm-channel-number = <0x80>; | |
| qcom,calibration-type = "ratiometric"; | |
| qcom,hw-settle-time = <0x02>; | |
| qcom,pre-div-channel-scaling = <0x00>; | |
| label = "quiet_therm"; | |
| reg = <0x51>; | |
| qcom,scale-function = <0x02>; | |
| }; | |
| }; | |
| qcom,clkdiv@5c00 { | |
| compatible = "qcom,qpnp-clkdiv"; | |
| qcom,clkdiv-id = <0x02>; | |
| #clock-cells = <0x01>; | |
| phandle = <0x305>; | |
| reg = <0x5c00 0x100>; | |
| qcom,cxo-freq = <0x124f800>; | |
| qcom,clkdiv-init-freq = <0x124f800>; | |
| }; | |
| qcom,coincell@2800 { | |
| compatible = "qcom,qpnp-coincell"; | |
| phandle = <0x301>; | |
| reg = <0x2800 0x100>; | |
| }; | |
| qcom,clkdiv@5b00 { | |
| compatible = "qcom,qpnp-clkdiv"; | |
| qcom,clkdiv-id = <0x01>; | |
| #clock-cells = <0x01>; | |
| phandle = <0x304>; | |
| reg = <0x5b00 0x100>; | |
| qcom,cxo-freq = <0x124f800>; | |
| qcom,clkdiv-init-freq = <0x124f800>; | |
| }; | |
| pinctrl@c000 { | |
| compatible = "qcom,spmi-gpio"; | |
| gpio-controller; | |
| qcom,gpios-disallowed = <0x03 0x0f 0x14 0x16 0x18 0x19 0x1a>; | |
| interrupts = <0x00 0xc0 0x00 0x00 0x00 0xc1 0x00 0x00 0x00 0xc3 0x00 0x00 0x00 0xc4 0x00 0x00 0x00 0xc5 0x00 0x00 0x00 0xc6 0x00 0x00 0x00 0xc7 0x00 0x00 0x00 0xc8 0x00 0x00 0x00 0xc9 0x00 0x00 0x00 0xca 0x00 0x00 0x00 0xcb 0x00 0x00 0x00 0xcc 0x00 0x00 0x00 0xcd 0x00 0x00 0x00 0xcf 0x00 0x00 0x00 0xd0 0x00 0x00 0x00 0xd1 0x00 0x00 0x00 0xd2 0x00 0x00 0x00 0xd4 0x00 0x00 0x00 0xd6 0x00 0x00>; | |
| phandle = <0xe6>; | |
| reg = <0xc000 0x1a00>; | |
| #gpio-cells = <0x02>; | |
| pinctrl-0 = <0x50d 0x50e>; | |
| interrupt-names = "pm8998_gpio1\0pm8998_gpio2\0pm8998_gpio4\0pm8998_gpio5\0pm8998_gpio6\0pm8998_gpio7\0pm8998_gpio8\0pm8998_gpio9\0pm8998_gpio10\0pm8998_gpio11\0pm8998_gpio12\0pm8998_gpio13\0pm8998_gpio14\0pm8998_gpio16\0pm8998_gpio17\0pm8998_gpio18\0pm8998_gpio19\0pm8998_gpio21\0pm8998_gpio23"; | |
| pinctrl-names = "default"; | |
| nfc_clk { | |
| nfc_clk_default { | |
| phandle = <0x300>; | |
| }; | |
| }; | |
| camera_rear_avdd_en { | |
| camera_rear_avdd_en_default { | |
| phandle = <0x2fe>; | |
| }; | |
| }; | |
| camera_rear_dvdd_en { | |
| camera_rear_dvdd_en_default { | |
| phandle = <0x2ff>; | |
| }; | |
| }; | |
| camera_dvdd_en { | |
| }; | |
| key_cam_focus { | |
| key_cam_focus_default { | |
| phandle = <0x2fc>; | |
| }; | |
| }; | |
| gpio8_adc0 { | |
| gpio8_adc0_default { | |
| pins = "gpio8"; | |
| phandle = <0x50d>; | |
| bias-high-impedance; | |
| }; | |
| }; | |
| key_home { | |
| key_home_default { | |
| pins = "gpio5"; | |
| phandle = <0x2f8>; | |
| function = "normal"; | |
| power-source = <0x00>; | |
| input-enable; | |
| bias-pull-up; | |
| }; | |
| }; | |
| key_cam_snapshot { | |
| key_cam_snapshot_default { | |
| phandle = <0x2fb>; | |
| function = "normal"; | |
| power-source = <0x00>; | |
| input-enable; | |
| bias-pull-up; | |
| }; | |
| }; | |
| gpio21_adc1 { | |
| gpio21_adc1_default { | |
| pins = "gpio21"; | |
| phandle = <0x50e>; | |
| bias-high-impedance; | |
| }; | |
| }; | |
| led_wifi { | |
| led_wifi_default { | |
| phandle = <0x2fd>; | |
| }; | |
| }; | |
| key_vol_up { | |
| key_vol_up_default { | |
| pins = "gpio6"; | |
| phandle = <0x2fa>; | |
| function = "normal"; | |
| power-source = <0x00>; | |
| input-enable; | |
| bias-pull-up; | |
| }; | |
| }; | |
| led_bt { | |
| led_bt_default { | |
| output-low; | |
| pins = "gpio5"; | |
| phandle = <0x2f9>; | |
| function = "normal"; | |
| power-source = <0x00>; | |
| }; | |
| }; | |
| }; | |
| qcom,temp-alarm@2400 { | |
| qcom,temp_alarm-vadc = <0x81>; | |
| compatible = "qcom,qpnp-temp-alarm"; | |
| #thermal-sensor-cells = <0x00>; | |
| qcom,channel-num = <0x06>; | |
| interrupts = <0x00 0x24 0x00 0x01>; | |
| label = "pm8998_tz"; | |
| phandle = <0xfb>; | |
| reg = <0x2400 0x100>; | |
| }; | |
| }; | |
| qcom,pmi8998@3 { | |
| compatible = "qcom,spmi-pmic"; | |
| #address-cells = <0x02>; | |
| #size-cells = <0x00>; | |
| phandle = <0x55e>; | |
| reg = <0x03 0x00>; | |
| pwm@b300 { | |
| compatible = "qcom,qpnp-pwm"; | |
| reg-names = "qpnp-lpg-channel-base\0qpnp-lpg-lut-base"; | |
| qcom,channel-id = <0x03>; | |
| qcom,lpg-lut-size = <0x7e>; | |
| phandle = <0x503>; | |
| reg = <0xb300 0x100 0xb042 0x7e>; | |
| qcom,supported-sizes = <0x06 0x09>; | |
| qcom,ramp-index = <0x02>; | |
| #pwm-cells = <0x02>; | |
| }; | |
| pwm@b600 { | |
| compatible = "qcom,qpnp-pwm"; | |
| reg-names = "qpnp-lpg-channel-base\0qpnp-lpg-lut-base"; | |
| qcom,channel-id = <0x06>; | |
| qcom,lpg-lut-size = <0x7e>; | |
| status = "disabled"; | |
| phandle = <0x560>; | |
| reg = <0xb600 0x100 0xb042 0x7e>; | |
| qcom,supported-sizes = <0x06 0x09>; | |
| qcom,ramp-index = <0x05>; | |
| #pwm-cells = <0x02>; | |
| }; | |
| pwm@b200 { | |
| compatible = "qcom,qpnp-pwm"; | |
| reg-names = "qpnp-lpg-channel-base\0qpnp-lpg-lut-base"; | |
| qcom,channel-id = <0x02>; | |
| qcom,lpg-lut-size = <0x7e>; | |
| status = "okay"; | |
| phandle = <0x51e>; | |
| reg = <0xb200 0x100 0xb042 0x7e>; | |
| qcom,supported-sizes = <0x06 0x09>; | |
| qcom,ramp-index = <0x01>; | |
| #pwm-cells = <0x02>; | |
| }; | |
| qcom,leds@d800 { | |
| qcom,boost-duty-ns = <0x1a>; | |
| qcom,hyb-thres = <0x271>; | |
| compatible = "qcom,qpnp-wled"; | |
| qcom,loop-auto-gm-en; | |
| qcom,sync-dly-us = <0x320>; | |
| linux,name = "wled"; | |
| reg-names = "qpnp-wled-ctrl-base\0qpnp-wled-sink-base"; | |
| qcom,pmic-revid = <0x4fc>; | |
| qcom,cons-sync-write-delay-us = <0x3e8>; | |
| qcom,ovp-mv = <0x73a0>; | |
| qcom,auto-calibration-enable; | |
| qcom,en-ext-pfet-sc-pro; | |
| qcom,led-strings-list = [00 01]; | |
| status = "okay"; | |
| interrupts = <0x03 0xd8 0x01 0x01 0x03 0xd8 0x02 0x01>; | |
| qcom,fs-curr-ua = <0x57e4>; | |
| qcom,fdbk-output = "auto"; | |
| qcom,ilim-ma = <0x3ca>; | |
| phandle = <0x565>; | |
| qcom,mod-freq-khz = <0x2580>; | |
| qcom,dim-mode = "hybrid"; | |
| reg = <0xd800 0x100 0xd900 0x100>; | |
| qcom,vref-uv = <0x1f20c>; | |
| interrupt-names = "ovp-irq\0sc-irq"; | |
| qcom,switch-freq-khz = <0x320>; | |
| linux,default-trigger = "bkl-trigger"; | |
| }; | |
| pwm@b500 { | |
| compatible = "qcom,qpnp-pwm"; | |
| reg-names = "qpnp-lpg-channel-base\0qpnp-lpg-lut-base"; | |
| qcom,channel-id = <0x05>; | |
| qcom,lpg-lut-size = <0x7e>; | |
| phandle = <0x501>; | |
| reg = <0xb500 0x100 0xb042 0x7e>; | |
| qcom,supported-sizes = <0x06 0x09>; | |
| qcom,ramp-index = <0x04>; | |
| #pwm-cells = <0x02>; | |
| }; | |
| qcom,haptics@c000 { | |
| qcom,lra-auto-res-mode = "qwd"; | |
| compatible = "qcom,qpnp-haptics"; | |
| qcom,pmic-misc = <0x504>; | |
| qcom,en-brake; | |
| qcom,pmic-revid = <0x4fc>; | |
| qcom,sc-dbc-cycles = <0x08>; | |
| qcom,play-mode = "direct"; | |
| qcom,wave-play-rate-us = <0x1a0b>; | |
| status = "okay"; | |
| interrupts = <0x03 0xc0 0x00 0x03 0x03 0xc0 0x01 0x03>; | |
| qcom,ilim-ma = <0x320>; | |
| phandle = <0x567>; | |
| qcom,misc-clk-trim-error-reg = <0xf3>; | |
| qcom,lra-res-cal-period = <0x04>; | |
| qcom,lra-high-z = "opt1"; | |
| reg = <0xc000 0x100>; | |
| qcom,vmax-mv = <0xe0c>; | |
| qcom,actuator-type = <0x01>; | |
| interrupt-names = "hap-sc-irq\0hap-play-irq"; | |
| }; | |
| qpnp-labibb-regulator { | |
| compatible = "qcom,qpnp-labibb-regulator"; | |
| qcom,pmic-revid = <0x4fc>; | |
| status = "ok"; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| phandle = <0x564>; | |
| qcom,qpnp-labibb-mode = "lcd"; | |
| qcom,lab@de00 { | |
| qcom,qpnp-lab-init-amoled-voltage = <0x4630c0>; | |
| qcom,qpnp-lab-step-size = <0x186a0>; | |
| qcom,qpnp-lab-use-default-voltage; | |
| reg-names = "lab"; | |
| qcom,qpnp-lab-limit-max-current-enable; | |
| qcom,qpnp-lab-pull-down-enable; | |
| qcom,qpnp-lab-pfet-size = <0x64>; | |
| qcom,qpnp-lab-min-voltage = <0x4630c0>; | |
| qcom,qpnp-lab-limit-maximum-current = <0x640>; | |
| qcom,qpnp-lab-ps-threshold = <0x46>; | |
| qcom,qpnp-lab-init-lcd-voltage = <0x53ec60>; | |
| interrupts = <0x03 0xde 0x00 0x01 0x03 0xde 0x01 0x01>; | |
| qcom,qpnp-lab-nfet-size = <0x64>; | |
| qcom,qpnp-lab-soft-start = <0x320>; | |
| qcom,qpnp-lab-init-voltage = <0x53ec60>; | |
| phandle = <0x4e2>; | |
| regulator-min-microvolt = <0x4630c0>; | |
| qcom,qpnp-lab-slew-rate = <0x1388>; | |
| reg = <0xde00 0x100>; | |
| regulator-max-microvolt = <0x5b8d80>; | |
| qcom,qpnp-lab-max-precharge-time = <0x1f4>; | |
| qcom,qpnp-lab-full-pull-down; | |
| qcom,qpnp-lab-ps-enable; | |
| regulator-name = "lab_reg"; | |
| interrupt-names = "lab-vreg-ok\0lab-sc-err"; | |
| qcom,qpnp-lab-switching-clock-frequency = <0x640>; | |
| }; | |
| qcom,ibb@dc00 { | |
| qcom,qpnp-ibb-init-voltage = <0x53ec60>; | |
| qcom,qpnp-ibb-init-amoled-voltage = "\0=\t"; | |
| qcom,qpnp-ibb-soft-start = <0x3e8>; | |
| qcom,qpnp-ibb-use-default-voltage; | |
| qcom,qpnp-ibb-init-lcd-voltage = <0x53ec60>; | |
| reg-names = "ibb_reg"; | |
| qcom,qpnp-ibb-slew-rate = <0x1e8480>; | |
| qcom,qpnp-ibb-en-discharge; | |
| qcom,qpnp-ibb-ps-enable; | |
| qcom,qpnp-ibb-limit-max-current-enable; | |
| interrupts = <0x03 0xdc 0x02 0x01>; | |
| qcom,qpnp-ibb-lab-pwrup-delay = <0x1f40>; | |
| phandle = <0x4e3>; | |
| qcom,qpnp-ibb-debounce-cycle = <0x10>; | |
| regulator-min-microvolt = <0x4630c0>; | |
| qcom,qpnp-ibb-limit-maximum-current = <0x60e>; | |
| reg = <0xdc00 0x100>; | |
| regulator-max-microvolt = <0x5b8d80>; | |
| qcom,qpnp-ibb-step-size = <0x186a0>; | |
| qcom,qpnp-ibb-full-pull-down; | |
| qcom,qpnp-ibb-switching-clock-frequency = <0x5c8>; | |
| regulator-name = "ibb_reg"; | |
| interrupt-names = "ibb-sc-err"; | |
| qcom,qpnp-ibb-min-voltage = <0x155cc0>; | |
| qcom,qpnp-ibb-pull-down-enable; | |
| qcom,qpnp-ibb-lab-pwrdn-delay = <0x1f40>; | |
| }; | |
| }; | |
| pwm@b100 { | |
| compatible = "qcom,qpnp-pwm"; | |
| reg-names = "qpnp-lpg-channel-base\0qpnp-lpg-lut-base"; | |
| qcom,channel-id = <0x01>; | |
| qcom,lpg-lut-size = <0x7e>; | |
| status = "disabled"; | |
| phandle = <0x55f>; | |
| reg = <0xb100 0x100 0xb042 0x7e>; | |
| qcom,supported-sizes = <0x06 0x09>; | |
| qcom,ramp-index = <0x00>; | |
| #pwm-cells = <0x02>; | |
| }; | |
| pwm@b400 { | |
| compatible = "qcom,qpnp-pwm"; | |
| reg-names = "qpnp-lpg-channel-base\0qpnp-lpg-lut-base"; | |
| qcom,channel-id = <0x04>; | |
| qcom,lpg-lut-size = <0x7e>; | |
| phandle = <0x502>; | |
| reg = <0xb400 0x100 0xb042 0x7e>; | |
| qcom,supported-sizes = <0x06 0x09>; | |
| qcom,ramp-index = <0x03>; | |
| #pwm-cells = <0x02>; | |
| }; | |
| qcom,leds@d000 { | |
| compatible = "qcom,leds-qpnp"; | |
| status = "okay"; | |
| label = "rgb"; | |
| reg = <0xd000 0x100>; | |
| qcom,rgb_2 { | |
| qcom,default-state = "off"; | |
| qcom,id = <0x05>; | |
| linux,name = "blue"; | |
| label = "rgb"; | |
| qcom,mode = "pwm"; | |
| qcom,max-current = <0x0c>; | |
| phandle = <0x563>; | |
| qcom,pwm-us = <0x3e8>; | |
| pwms = <0x503 0x00 0x00>; | |
| }; | |
| qcom,rgb_0 { | |
| qcom,default-state = "off"; | |
| qcom,id = <0x03>; | |
| linux,name = "red"; | |
| label = "rgb"; | |
| qcom,mode = "pwm"; | |
| qcom,max-current = <0x0c>; | |
| phandle = <0x561>; | |
| qcom,pwm-us = <0x3e8>; | |
| pwms = <0x501 0x00 0x00>; | |
| }; | |
| qcom,rgb_1 { | |
| qcom,default-state = "off"; | |
| qcom,id = <0x04>; | |
| linux,name = "green"; | |
| label = "rgb"; | |
| qcom,mode = "pwm"; | |
| qcom,max-current = <0x0c>; | |
| phandle = <0x562>; | |
| qcom,pwm-us = <0x3e8>; | |
| pwms = <0x502 0x00 0x00>; | |
| }; | |
| }; | |
| qcom,leds@d300 { | |
| qcom,vph-droop-det; | |
| compatible = "qcom,qpnp-flash-led-v2"; | |
| qcom,thermal-derate-current = <0xc8 0x1f4 0x3e8>; | |
| qcom,open-circuit-det; | |
| qcom,pmic-revid = <0x4fc>; | |
| qcom,isc-delay = <0xc0>; | |
| qcom,short-circuit-det; | |
| status = "okay"; | |
| interrupts = <0x03 0xd3 0x00 0x01 0x03 0xd3 0x03 0x01 0x03 0xd3 0x04 0x01>; | |
| label = "flash"; | |
| qcom,thermal-derate-en; | |
| phandle = <0x566>; | |
| qcom,hdrm-auto-mode; | |
| reg = <0xd300 0x100>; | |
| interrupt-names = "led-fault-irq\0all-ramp-down-done-irq\0all-ramp-up-done-irq"; | |
| qcom,torch_1 { | |
| qcom,led-name = "led:torch_1"; | |
| qcom,id = <0x01>; | |
| qcom,hdrm-voltage-mv = <0x145>; | |
| qcom,default-led-trigger = "torch1_trigger"; | |
| label = "torch"; | |
| qcom,hdrm-vol-hi-lo-win-mv = <0x64>; | |
| qcom,max-current = <0x1f4>; | |
| phandle = <0x512>; | |
| qcom,ires-ua = <0x30d4>; | |
| qcom,current-ma = <0x12c>; | |
| }; | |
| qcom,flash_0 { | |
| qcom,led-name = "led:flash_0"; | |
| qcom,id = <0x00>; | |
| qcom,hdrm-voltage-mv = <0x145>; | |
| qcom,duration-ms = <0x500>; | |
| qcom,default-led-trigger = "flash0_trigger"; | |
| label = "flash"; | |
| qcom,hdrm-vol-hi-lo-win-mv = <0x64>; | |
| qcom,max-current = <0x5dc>; | |
| phandle = <0x50f>; | |
| qcom,ires-ua = <0x30d4>; | |
| qcom,current-ma = <0x3e8>; | |
| }; | |
| qcom,led_switch_1 { | |
| qcom,led-name = "led:switch_1"; | |
| pinctrl-1 = <0x3ed>; | |
| qcom,led-mask = <0x04>; | |
| qcom,default-led-trigger = "switch1_trigger"; | |
| label = "switch"; | |
| phandle = <0x516>; | |
| pinctrl-0 = <0x3ec>; | |
| pinctrl-names = "led_enable\0led_disable"; | |
| }; | |
| qcom,torch_2 { | |
| qcom,led-name = "led:torch_2"; | |
| qcom,id = <0x02>; | |
| qcom,hdrm-voltage-mv = <0x145>; | |
| qcom,default-led-trigger = "torch2_trigger"; | |
| label = "torch"; | |
| qcom,hdrm-vol-hi-lo-win-mv = <0x64>; | |
| qcom,max-current = <0x1f4>; | |
| phandle = <0x515>; | |
| qcom,ires-ua = <0x30d4>; | |
| qcom,current-ma = <0x12c>; | |
| }; | |
| qcom,flash_1 { | |
| qcom,led-name = "led:flash_1"; | |
| qcom,id = <0x01>; | |
| qcom,hdrm-voltage-mv = <0x145>; | |
| qcom,duration-ms = <0x500>; | |
| qcom,default-led-trigger = "flash1_trigger"; | |
| label = "flash"; | |
| qcom,hdrm-vol-hi-lo-win-mv = <0x64>; | |
| qcom,max-current = <0x5dc>; | |
| phandle = <0x510>; | |
| qcom,ires-ua = <0x30d4>; | |
| qcom,current-ma = <0x3e8>; | |
| }; | |
| qcom,led_switch_2 { | |
| qcom,led-name = "led:switch_2"; | |
| pinctrl-1 = <0x3ef>; | |
| qcom,led-mask = <0x04>; | |
| qcom,default-led-trigger = "switch2_trigger"; | |
| label = "switch"; | |
| phandle = <0x517>; | |
| pinctrl-0 = <0x3ee>; | |
| pinctrl-names = "led_enable\0led_disable"; | |
| }; | |
| qcom,torch_0 { | |
| qcom,led-name = "led:torch_0"; | |
| qcom,id = <0x00>; | |
| qcom,hdrm-voltage-mv = <0x145>; | |
| qcom,default-led-trigger = "torch0_trigger"; | |
| label = "torch"; | |
| qcom,hdrm-vol-hi-lo-win-mv = <0x64>; | |
| qcom,max-current = <0x1f4>; | |
| phandle = <0x511>; | |
| qcom,ires-ua = <0x30d4>; | |
| qcom,current-ma = <0x12c>; | |
| }; | |
| qcom,led_switch_0 { | |
| qcom,led-name = "led:switch_0"; | |
| qcom,led-mask = <0x03>; | |
| qcom,default-led-trigger = "switch0_trigger"; | |
| label = "switch"; | |
| phandle = <0x513>; | |
| }; | |
| qcom,flash_2 { | |
| qcom,led-name = "led:flash_2"; | |
| qcom,id = <0x02>; | |
| qcom,hdrm-voltage-mv = <0x145>; | |
| qcom,duration-ms = <0x500>; | |
| qcom,default-led-trigger = "flash2_trigger"; | |
| label = "flash"; | |
| qcom,hdrm-vol-hi-lo-win-mv = <0x64>; | |
| qcom,max-current = <0x2ee>; | |
| phandle = <0x514>; | |
| qcom,ires-ua = <0x30d4>; | |
| qcom,current-ma = <0x1f4>; | |
| }; | |
| }; | |
| }; | |
| qcom,pm8005@4 { | |
| compatible = "qcom,spmi-pmic"; | |
| #address-cells = <0x02>; | |
| #size-cells = <0x00>; | |
| reg = <0x04 0x00>; | |
| qcom,revid@100 { | |
| compatible = "qcom,qpnp-revid"; | |
| phandle = <0x307>; | |
| reg = <0x100 0x100>; | |
| }; | |
| pinctrl@c000 { | |
| compatible = "qcom,spmi-gpio"; | |
| gpio-controller; | |
| qcom,gpios-disallowed = <0x03 0x04>; | |
| interrupts = <0x04 0xc0 0x00 0x00 0x04 0xc1 0x00 0x00>; | |
| phandle = <0x308>; | |
| reg = <0xc000 0x400>; | |
| #gpio-cells = <0x02>; | |
| interrupt-names = "pm8005_gpio1\0pm8005_gpio2"; | |
| }; | |
| qcom,temp-alarm@2400 { | |
| compatible = "qcom,qpnp-temp-alarm"; | |
| #thermal-sensor-cells = <0x00>; | |
| interrupts = <0x04 0x24 0x00 0x01>; | |
| label = "pm8005_tz"; | |
| phandle = <0xfe>; | |
| reg = <0x2400 0x100>; | |
| }; | |
| }; | |
| qcom,pm8998@1 { | |
| compatible = "qcom,spmi-pmic"; | |
| #address-cells = <0x02>; | |
| #size-cells = <0x00>; | |
| reg = <0x01 0x00>; | |
| }; | |
| qcom,pmi8998@2 { | |
| compatible = "qcom,spmi-pmic"; | |
| #address-cells = <0x02>; | |
| #size-cells = <0x00>; | |
| phandle = <0x557>; | |
| reg = <0x02 0x00>; | |
| qcom,qpnp-qnovo@1500 { | |
| compatible = "qcom,qpnp-qnovo"; | |
| qcom,pmic-revid = <0x4fc>; | |
| interrupts = <0x02 0x15 0x00 0x00>; | |
| phandle = <0x55b>; | |
| reg = <0x1500 0x100>; | |
| pinctrl-0 = <0x4fd>; | |
| interrupt-names = "ptrain-done"; | |
| pinctrl-names = "default"; | |
| }; | |
| qcom,revid@100 { | |
| compatible = "qcom,qpnp-revid"; | |
| qcom,fab-id-valid; | |
| phandle = <0x4fc>; | |
| reg = <0x100 0x100>; | |
| }; | |
| qcom,power-on@800 { | |
| compatible = "qcom,qpnp-power-on"; | |
| reg = <0x800 0x100>; | |
| }; | |
| qpnp,fg { | |
| qcom,hold-soc-while-full; | |
| qcom,battery-data = <0x500>; | |
| io-channels = <0x4fb 0x00>; | |
| compatible = "qcom,fg-gen3"; | |
| qcom,pmic-revid = <0x4fc>; | |
| io-channel-names = "rradc_batt_id"; | |
| status = "okay"; | |
| #address-cells = <0x01>; | |
| qcom,fg-esr-timer-charging = <0x00 0x60>; | |
| qcom,fg-recharge-soc-thr = <0x62>; | |
| #size-cells = <0x01>; | |
| phandle = <0x55d>; | |
| qcom,fg-esr-timer-asleep = <0x100 0x100>; | |
| qcom,fg-esr-timer-awake = <0x60 0x60>; | |
| qcom,rradc-base = <0x4500>; | |
| qcom,fg-force-load-profile; | |
| qcom,fg-auto-recharge-soc; | |
| qcom,cycle-counter-en; | |
| qcom,fg-batt-info@4100 { | |
| status = "okay"; | |
| interrupts = <0x02 0x41 0x00 0x03 0x02 0x41 0x01 0x03 0x02 0x41 0x02 0x03 0x02 0x41 0x03 0x03 0x02 0x41 0x06 0x03>; | |
| reg = <0x4100 0x100>; | |
| interrupt-names = "vbatt-pred-delta\0vbatt-low\0esr-delta\0batt-missing\0batt-temp-delta"; | |
| }; | |
| qcom,fg-batt-soc@4000 { | |
| status = "okay"; | |
| interrupts = <0x02 0x40 0x00 0x03 0x02 0x40 0x01 0x03 0x02 0x40 0x02 0x01 0x02 0x40 0x03 0x01 0x02 0x40 0x04 0x03 0x02 0x40 0x05 0x01 0x02 0x40 0x06 0x03 0x02 0x40 0x07 0x03>; | |
| reg = <0x4000 0x100>; | |
| interrupt-names = "soc-update\0soc-ready\0bsoc-delta\0msoc-delta\0msoc-low\0msoc-empty\0msoc-high\0msoc-full"; | |
| }; | |
| qcom,fg-memif@4400 { | |
| status = "okay"; | |
| interrupts = <0x02 0x44 0x00 0x03 0x02 0x44 0x01 0x03 0x02 0x44 0x02 0x01>; | |
| reg = <0x4400 0x100>; | |
| interrupt-names = "ima-rdy\0mem-xcp\0dma-grant"; | |
| }; | |
| }; | |
| qcom,misc@900 { | |
| compatible = "qcom,qpnp-misc"; | |
| phandle = <0x504>; | |
| reg = <0x900 0x100>; | |
| }; | |
| qcom,usb-pdphy@1700 { | |
| vbus-supply = <0x4fe>; | |
| compatible = "qcom,qpnp-pdphy"; | |
| qcom,default-sink-caps = <0x1388 0xbb8 0x2328 0xbb8 0x2ee0 0x8ca>; | |
| interrupts = <0x02 0x17 0x00 0x01 0x02 0x17 0x01 0x01 0x02 0x17 0x02 0x01 0x02 0x17 0x03 0x01 0x02 0x17 0x04 0x01 0x02 0x17 0x05 0x01 0x02 0x17 0x06 0x01>; | |
| vdd-pdphy-supply = <0xba>; | |
| phandle = <0x4f8>; | |
| reg = <0x1700 0x100>; | |
| interrupt-names = "sig-tx\0sig-rx\0msg-tx\0msg-rx\0msg-tx-failed\0msg-tx-discarded\0msg-rx-discarded"; | |
| vconn-supply = <0x4ff>; | |
| }; | |
| qcom,qpnp-smb2 { | |
| qcom,thermal-mitigation = <0x2dc6c0 0x16e360 0xf4240 0x7a120>; | |
| io-channels = <0x4fb 0x08 0x4fb 0x0a 0x4fb 0x03 0x4fb 0x04>; | |
| compatible = "qcom,qpnp-smb2"; | |
| qcom,auto-recharge-soc; | |
| qcom,pmic-revid = <0x4fc>; | |
| io-channel-names = "charger_temp\0charger_temp_max\0usbin_i\0usbin_v"; | |
| qcom,boost-threshold-ua = <0x186a0>; | |
| qcom,fcc-max-ua = <0x2625a0>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| phandle = <0x55c>; | |
| dpdm-supply = <0x2b3>; | |
| qcom,suspend-input-on-debug-batt; | |
| qcom,wipower-max-uw = <0x4c4b40>; | |
| #cooling-cells = <0x02>; | |
| qcom,dc-chgpth@1400 { | |
| interrupts = <0x02 0x14 0x00 0x03 0x02 0x14 0x01 0x03 0x02 0x14 0x02 0x03 0x02 0x14 0x03 0x03 0x02 0x14 0x04 0x03 0x02 0x14 0x05 0x03 0x02 0x14 0x06 0x01>; | |
| reg = <0x1400 0x100>; | |
| interrupt-names = "dcin-collapse\0dcin-lt-3p6v\0dcin-uv\0dcin-ov\0dcin-plugin\0div2-en-dg\0dcin-icl-change"; | |
| }; | |
| qcom,chgr@1000 { | |
| interrupts = <0x02 0x10 0x00 0x01 0x02 0x10 0x01 0x01 0x02 0x10 0x02 0x01 0x02 0x10 0x03 0x01 0x02 0x10 0x04 0x01>; | |
| reg = <0x1000 0x100>; | |
| interrupt-names = "chg-error\0chg-state-change\0step-chg-state-change\0step-chg-soc-update-fail\0step-chg-soc-update-request"; | |
| }; | |
| qcom,chgr-misc@1600 { | |
| interrupts = <0x02 0x16 0x00 0x01 0x02 0x16 0x01 0x01 0x02 0x16 0x02 0x03 0x02 0x16 0x03 0x03 0x02 0x16 0x04 0x03 0x02 0x16 0x05 0x03 0x02 0x16 0x06 0x02 0x02 0x16 0x07 0x03>; | |
| reg = <0x1600 0x100>; | |
| interrupt-names = "wdog-snarl\0wdog-bark\0aicl-fail\0aicl-done\0high-duty-cycle\0input-current-limiting\0temperature-change\0switcher-power-ok"; | |
| }; | |
| qcom,otg@1100 { | |
| interrupts = <0x02 0x11 0x00 0x03 0x02 0x11 0x01 0x03 0x02 0x11 0x02 0x03 0x02 0x11 0x03 0x03>; | |
| reg = <0x1100 0x100>; | |
| interrupt-names = "otg-fail\0otg-overcurrent\0otg-oc-dis-sw-sts\0testmode-change-detect"; | |
| }; | |
| qcom,usb-chgpth@1300 { | |
| interrupts = <0x02 0x13 0x00 0x03 0x02 0x13 0x01 0x03 0x02 0x13 0x02 0x03 0x02 0x13 0x03 0x03 0x02 0x13 0x04 0x03 0x02 0x13 0x05 0x01 0x02 0x13 0x06 0x01 0x02 0x13 0x07 0x01>; | |
| reg = <0x1300 0x100>; | |
| interrupt-names = "usbin-collapse\0usbin-lt-3p6v\0usbin-uv\0usbin-ov\0usbin-plugin\0usbin-src-change\0usbin-icl-change\0type-c-change"; | |
| }; | |
| qcom,smb2-vconn { | |
| phandle = <0x4ff>; | |
| regulator-name = "smb2-vconn"; | |
| }; | |
| qcom,bat-if@1200 { | |
| interrupts = <0x02 0x12 0x00 0x01 0x02 0x12 0x01 0x03 0x02 0x12 0x02 0x03 0x02 0x12 0x03 0x03 0x02 0x12 0x04 0x03 0x02 0x12 0x05 0x03>; | |
| reg = <0x1200 0x100>; | |
| interrupt-names = "bat-temp\0bat-ocp\0bat-ov\0bat-low\0bat-therm-or-id-missing\0bat-terminal-missing"; | |
| }; | |
| qcom,smb2-vbus { | |
| phandle = <0x4fe>; | |
| regulator-name = "smb2-vbus"; | |
| }; | |
| }; | |
| bcl@4200 { | |
| compatible = "qcom,msm-bcl-lmh"; | |
| reg-names = "fg_user_adc\0fg_lmh"; | |
| #thermal-sensor-cells = <0x01>; | |
| interrupts = <0x02 0x42 0x00 0x00 0x02 0x42 0x01 0x00 0x02 0x42 0x02 0x00 0x02 0x42 0x03 0x00 0x02 0x42 0x04 0x00>; | |
| phandle = <0x505>; | |
| reg = <0x4200 0xff 0x4300 0xff>; | |
| interrupt-names = "bcl-high-ibat\0bcl-very-high-ibat\0bcl-low-vbat\0bcl-very-low-vbat\0bcl-crit-low-vbat"; | |
| }; | |
| rradc@4500 { | |
| compatible = "qcom,rradc"; | |
| qcom,pmic-revid = <0x4fc>; | |
| #io-channel-cells = <0x01>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| phandle = <0x4fb>; | |
| reg = <0x4500 0x100>; | |
| }; | |
| pinctrl@c000 { | |
| compatible = "qcom,spmi-gpio"; | |
| gpio-controller; | |
| qcom,gpios-disallowed = <0x04 0x07 0x0d>; | |
| interrupts = <0x02 0xc0 0x00 0x00 0x02 0xc1 0x00 0x00 0x02 0xc2 0x00 0x00 0x02 0xc4 0x00 0x00 0x02 0xc5 0x00 0x00 0x02 0xc7 0x00 0x00 0x02 0xc8 0x00 0x00 0x02 0xc9 0x00 0x00 0x02 0xca 0x00 0x00 0x02 0xcb 0x00 0x00 0x02 0xcd 0x00 0x00>; | |
| phandle = <0x509>; | |
| reg = <0xc000 0xe00>; | |
| #gpio-cells = <0x02>; | |
| interrupt-names = "pmi8998_gpio1\0pmi8998_gpio2\0pmi8998_gpio3\0pmi8998_gpio5\0pmi8998_gpio6\0pmi8998_gpio8\0pmi8998_gpio9\0pmi8998_gpio10\0pmi8998_gpio11\0pmi8998_gpio12\0pmi8998_gpio14"; | |
| pwm_out { | |
| pwm_out_default { | |
| output-low; | |
| pins = "gpio5"; | |
| bias-disable; | |
| phandle = <0x51f>; | |
| function = "func1"; | |
| power-source = <0x00>; | |
| drive-push-pull; | |
| qcom,drive-strength = <0x03>; | |
| }; | |
| }; | |
| usb2_ext_5v_boost { | |
| usb2_ext_5v_boost_default { | |
| output-low; | |
| pins = "gpio10"; | |
| phandle = <0x55a>; | |
| function = "normal"; | |
| power-source = <0x00>; | |
| }; | |
| }; | |
| usb2_id_det { | |
| usb2_id_det_default { | |
| pins = "gpio9"; | |
| phandle = <0x559>; | |
| function = "normal"; | |
| power-source = <0x00>; | |
| input-enable; | |
| bias-pull-up; | |
| }; | |
| }; | |
| qnovo_fet_ctrl { | |
| qnovo_fet_ctrl_default { | |
| output-low; | |
| pins = "gpio6"; | |
| bias-disable; | |
| phandle = <0x4fd>; | |
| function = "func1"; | |
| power-source = <0x00>; | |
| input-disable; | |
| qcom,drive-strength = <0x01>; | |
| }; | |
| }; | |
| usb2_vbus_det { | |
| usb2_vbus_det_default { | |
| pins = "gpio8"; | |
| phandle = <0x520>; | |
| function = "normal"; | |
| bias-pull-down; | |
| power-source = <0x01>; | |
| input-enable; | |
| }; | |
| }; | |
| usb2_vbus_boost { | |
| usb2_vbus_boost_default { | |
| output-low; | |
| pins = "gpio2"; | |
| phandle = <0x558>; | |
| function = "normal"; | |
| power-source = <0x00>; | |
| }; | |
| }; | |
| }; | |
| qcom,temp-alarm@2400 { | |
| io-channels = <0x4fb 0x07>; | |
| compatible = "qcom,spmi-temp-alarm"; | |
| io-channel-names = "thermal"; | |
| #thermal-sensor-cells = <0x00>; | |
| interrupts = <0x02 0x24 0x00 0x01>; | |
| phandle = <0x508>; | |
| reg = <0x2400 0x100>; | |
| }; | |
| }; | |
| }; | |
| qcom,l3-cdsp { | |
| compatible = "devfreq-simple-dev"; | |
| clocks = <0x86 0x0d>; | |
| clock-names = "devfreq_clk"; | |
| governor = "powersave"; | |
| phandle = <0x9f>; | |
| }; | |
| qcom,smp2pgpio-rdbg-5-out { | |
| compatible = "qcom,smp2pgpio"; | |
| gpio-controller; | |
| #interrupt-cells = <0x02>; | |
| phandle = <0x28>; | |
| qcom,entry-name = "rdbg"; | |
| #gpio-cells = <0x02>; | |
| qcom,remote-pid = <0x05>; | |
| interrupt-controller; | |
| }; | |
| tpdm@6b02000 { | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "tpdm-base"; | |
| coresight-name = "coresight-tpdm-swao-0"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x356>; | |
| arm,primecell-periphid = <0x3b968>; | |
| reg = <0x6b02000 0x1000>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x131>; | |
| phandle = <0x12f>; | |
| }; | |
| }; | |
| }; | |
| ssusb@a600000 { | |
| qcom,use-pdc-interrupts; | |
| qcom,msm-bus,num-paths = <0x03>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| qcom,core-clk-rate = <0x7f28155>; | |
| compatible = "qcom,dwc-usb3-msm"; | |
| clocks = <0x22 0x95 0x22 0x12 0x22 0x09 0x22 0x97 0x22 0x99 0x22 0xa9 0x22 0x9f>; | |
| qcom,msm-bus,vectors-KBps = <0x3d 0x200 0x00 0x00 0x3d 0x2a4 0x00 0x00 0x01 0x247 0x00 0x00 0x3d 0x200 0x3a980 0xaae60 0x3d 0x2a4 0x00 0x960 0x01 0x247 0x00 0x9c40>; | |
| qcom,usb-dbm = <0x2b1>; | |
| resets = <0x22 0x0f>; | |
| extcon = <0x4f8 0x4f8 0x2b2>; | |
| qcom,smmu-s1-bypass; | |
| reg-names = "core_base\0ahb2phy_base"; | |
| clock-names = "core_clk\0iface_clk\0bus_aggr_clk\0utmi_clk\0sleep_clk\0cfg_ahb_clk\0xo"; | |
| qcom,core-clk-rate-hs = <0x3f940ab>; | |
| qcom,msm-bus,name = "usb0"; | |
| ranges; | |
| USB3_GDSC-supply = <0x2b0>; | |
| #address-cells = <0x01>; | |
| interrupts = <0x00 0x1e9 0x00 0x00 0x82 0x00 0x00 0x1e6 0x00 0x00 0x1e8 0x00>; | |
| qcom,num-gsi-evt-buffs = <0x03>; | |
| #size-cells = <0x01>; | |
| phandle = <0x4cf>; | |
| reg = <0xa600000 0xf8c00 0x88ee000 0x400>; | |
| iommus = <0x29 0x740 0x00>; | |
| reset-names = "core_reset"; | |
| qcom,pm-qos-latency = <0x2c>; | |
| interrupt-names = "dp_hs_phy_irq\0pwr_event_irq\0ss_phy_irq\0dm_hs_phy_irq"; | |
| qcom,dwc-usb3-msm-tx-fifo-size = <0x5328>; | |
| dwc3@a600000 { | |
| usb-phy = <0x2b3 0x2b4>; | |
| compatible = "snps,dwc3"; | |
| snps,disable-clk-gating; | |
| snps,usb3_lpm_capable; | |
| linux,sysdev_is_parent; | |
| tx-fifo-resize; | |
| interrupts = <0x00 0x85 0x00>; | |
| snps,has-lpm-erratum; | |
| reg = <0xa600000 0xcd00>; | |
| snps,hird-threshold = [10]; | |
| usb-core-id = <0x00>; | |
| }; | |
| qcom,usbbam@a704000 { | |
| compatible = "qcom,usb-bam-msm"; | |
| qcom,usb-bam-override-threshold = <0x4001>; | |
| qcom,usb-bam-max-mbps-superspeed = <0xe10>; | |
| qcom,ignore-core-reset-ack; | |
| qcom,bam-type = <0x00>; | |
| qcom,usb-bam-fifo-baseaddr = <0x146bb000>; | |
| interrupts = <0x00 0x84 0x00>; | |
| reg = <0xa704000 0x17000>; | |
| qcom,usb-bam-max-mbps-highspeed = <0x190>; | |
| qcom,disable-clk-gating; | |
| qcom,reset-bam-on-connect; | |
| qcom,usb-bam-num-pipes = <0x08>; | |
| qcom,pipe0 { | |
| qcom,descriptor-fifo-offset = <0x1800>; | |
| qcom,data-fifo-offset = <0x00>; | |
| qcom,src-bam-pipe-index = <0x00>; | |
| qcom,data-fifo-size = <0x1800>; | |
| qcom,pipe-num = <0x00>; | |
| qcom,dir = <0x01>; | |
| qcom,dst-bam-pipe-index = <0x00>; | |
| label = "ssusb-qdss-in-0"; | |
| qcom,peer-bam = <0x00>; | |
| qcom,usb-bam-mem-type = <0x02>; | |
| qcom,descriptor-fifo-size = <0x800>; | |
| qcom,peer-bam-physical-address = <0x6064000>; | |
| }; | |
| }; | |
| }; | |
| gpio-regulator@3 { | |
| regulator-enable-ramp-delay = <0x64>; | |
| compatible = "regulator-fixed"; | |
| enable-active-high; | |
| gpio = <0x34 0x5e 0x00>; | |
| phandle = <0x519>; | |
| regulator-min-microvolt = <0x2ab980>; | |
| reg = <0x03 0x00>; | |
| regulator-max-microvolt = <0x2ab980>; | |
| regulator-name = "actuator_regulator_front"; | |
| }; | |
| mem_dump { | |
| compatible = "qcom,mem-dump"; | |
| memory-region = <0x11b>; | |
| tmc_etr_reg { | |
| qcom,dump-size = <0x1000>; | |
| qcom,dump-id = <0x100>; | |
| }; | |
| tpdm_swao { | |
| qcom,dump-size = <0x512>; | |
| qcom,dump-id = <0xf2>; | |
| }; | |
| rpm_sw { | |
| qcom,dump-size = <0x28000>; | |
| qcom,dump-id = <0xea>; | |
| }; | |
| fcm { | |
| qcom,dump-size = <0x8400>; | |
| qcom,dump-id = <0xee>; | |
| }; | |
| tmc_etf { | |
| qcom,dump-size = <0x10000>; | |
| qcom,dump-id = <0xf0>; | |
| }; | |
| etfswao_reg { | |
| qcom,dump-size = <0x1000>; | |
| qcom,dump-id = <0x102>; | |
| }; | |
| pmic { | |
| qcom,dump-size = <0x10000>; | |
| qcom,dump-id = <0xe4>; | |
| }; | |
| tmc_etfswao { | |
| qcom,dump-size = <0x8400>; | |
| qcom,dump-id = <0xf1>; | |
| }; | |
| tmc_etf_reg { | |
| qcom,dump-size = <0x1000>; | |
| qcom,dump-id = <0x101>; | |
| }; | |
| rpmh { | |
| qcom,dump-size = <0x2000000>; | |
| qcom,dump-id = <0xec>; | |
| }; | |
| misc_data { | |
| qcom,dump-size = <0x1000>; | |
| qcom,dump-id = <0xe8>; | |
| }; | |
| }; | |
| tpdm@6860000 { | |
| qcom,msr-fix-req; | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "tpdm-base"; | |
| coresight-name = "coresight-tpdm-turing"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x374>; | |
| arm,primecell-periphid = <0x3b968>; | |
| reg = <0x6860000 0x1000>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x171>; | |
| phandle = <0x16e>; | |
| }; | |
| }; | |
| }; | |
| i2c@880000 { | |
| compatible = "qcom,i2c-geni"; | |
| clocks = <0x22 0x4c 0x22 0x6c 0x22 0x6d>; | |
| qcom,wrapper-core = <0x35>; | |
| pinctrl-1 = <0x3a>; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| status = "disabled"; | |
| #address-cells = <0x01>; | |
| interrupts = <0x00 0x259 0x00>; | |
| #size-cells = <0x00>; | |
| dma-names = "tx\0rx"; | |
| phandle = <0x2cb>; | |
| reg = <0x880000 0x4000>; | |
| pinctrl-0 = <0x39>; | |
| dmas = <0x38 0x00 0x00 0x03 0x40 0x00 0x38 0x01 0x00 0x03 0x40 0x00>; | |
| pinctrl-names = "default\0sleep"; | |
| }; | |
| rpmh-regulator-vsa1 { | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "vsa1"; | |
| mboxes = <0x8a 0x00>; | |
| regulator-lvs1 { | |
| phandle = <0x34b>; | |
| regulator-min-microvolt = <0x1b7740>; | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x1b7740>; | |
| regulator-name = "pm8998_lvs1"; | |
| }; | |
| }; | |
| qcom,msm-dai-q6-dp { | |
| compatible = "qcom,msm-dai-q6-hdmi"; | |
| phandle = <0x27f>; | |
| qcom,msm-dai-q6-dev-id = <0x6020>; | |
| }; | |
| funnel@0x6043000 { | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "funnel-base"; | |
| coresight-name = "coresight-funnel-in2"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x35e>; | |
| arm,primecell-periphid = <0x3b908>; | |
| reg = <0x6043000 0x1000>; | |
| ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@5 { | |
| reg = <0x06>; | |
| endpoint { | |
| remote-endpoint = <0x145>; | |
| phandle = <0x146>; | |
| slave-mode; | |
| }; | |
| }; | |
| port@3 { | |
| reg = <0x02>; | |
| endpoint { | |
| remote-endpoint = <0x143>; | |
| phandle = <0x154>; | |
| slave-mode; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x141>; | |
| phandle = <0x189>; | |
| slave-mode; | |
| }; | |
| }; | |
| port@4 { | |
| reg = <0x05>; | |
| endpoint { | |
| remote-endpoint = <0x144>; | |
| phandle = <0x18c>; | |
| slave-mode; | |
| }; | |
| }; | |
| port@2 { | |
| reg = <0x01>; | |
| endpoint { | |
| remote-endpoint = <0x142>; | |
| phandle = <0x127>; | |
| slave-mode; | |
| }; | |
| }; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x140>; | |
| phandle = <0x13a>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,smp2pgpio-ssr-smp2p-5-out { | |
| compatible = "qcom,smp2pgpio"; | |
| gpio-controller; | |
| #interrupt-cells = <0x02>; | |
| phandle = <0xbe>; | |
| qcom,entry-name = "master-kernel"; | |
| #gpio-cells = <0x02>; | |
| qcom,remote-pid = <0x05>; | |
| interrupt-controller; | |
| }; | |
| spi@880000 { | |
| compatible = "qcom,spi-geni"; | |
| clocks = <0x22 0x4c 0x22 0x6c 0x22 0x6d>; | |
| qcom,wrapper-core = <0x35>; | |
| reg-names = "se_phys"; | |
| pinctrl-1 = <0x4a>; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| status = "ok"; | |
| #address-cells = <0x01>; | |
| interrupts = <0x00 0x259 0x00>; | |
| #size-cells = <0x00>; | |
| dma-names = "tx\0rx"; | |
| phandle = <0x2d3>; | |
| reg = <0x880000 0x4000>; | |
| pinctrl-0 = <0x49>; | |
| dmas = <0x38 0x00 0x00 0x01 0x40 0x00 0x38 0x01 0x00 0x01 0x40 0x00>; | |
| spi-max-frequency = <0x2faf080>; | |
| pinctrl-names = "default\0sleep"; | |
| can@0 { | |
| compatible = "microchip,mcp2517fd"; | |
| clocks = <0x316>; | |
| gpio-controller; | |
| status = "okay"; | |
| interrupt-parent = <0x34>; | |
| interrupts = <0x22 0x00>; | |
| reg = <0x00>; | |
| interrupt-names = "can_irq"; | |
| spi-max-frequency = <0x989680>; | |
| }; | |
| }; | |
| rpmh-regulator-smpa5 { | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "smpa5"; | |
| mboxes = <0x8a 0x00>; | |
| regulator-s5 { | |
| phandle = <0xa3>; | |
| qcom,init-voltage = <0x1d0d80>; | |
| regulator-min-microvolt = <0x1d0d80>; | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x1f20c0>; | |
| regulator-name = "pm8998_s5"; | |
| }; | |
| }; | |
| qcom,msm-pcm-afe { | |
| compatible = "qcom,msm-pcm-afe"; | |
| phandle = <0x279>; | |
| }; | |
| jtagmm@7640000 { | |
| compatible = "qcom,jtagv8-mm"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "etm-base"; | |
| clock-names = "core_clk"; | |
| phandle = <0x2f4>; | |
| reg = <0x7640000 0x1000>; | |
| qcom,coresight-jtagmm-cpu = <0x17>; | |
| }; | |
| system_pm { | |
| compatible = "qcom,system-pm"; | |
| mboxes = <0x8a 0x00>; | |
| }; | |
| qcom,sps { | |
| compatible = "qcom,msm_sps_4k"; | |
| qcom,pipe-attr-ee; | |
| }; | |
| i2c@a84000 { | |
| compatible = "qcom,i2c-geni"; | |
| clocks = <0x22 0x5e 0x22 0x6e 0x22 0x6f>; | |
| qcom,wrapper-core = <0x5b>; | |
| pinctrl-1 = <0x62>; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| status = "disabled"; | |
| #address-cells = <0x01>; | |
| interrupts = <0x00 0x162 0x00>; | |
| #size-cells = <0x00>; | |
| dma-names = "tx\0rx"; | |
| phandle = <0x2df>; | |
| reg = <0xa84000 0x4000>; | |
| pinctrl-0 = <0x61>; | |
| dmas = <0x5e 0x00 0x01 0x03 0x40 0x00 0x5e 0x01 0x01 0x03 0x40 0x00>; | |
| pinctrl-names = "default\0sleep"; | |
| }; | |
| spi@a84000 { | |
| compatible = "qcom,spi-geni"; | |
| clocks = <0x22 0x5e 0x22 0x6e 0x22 0x6f>; | |
| qcom,wrapper-core = <0x5b>; | |
| reg-names = "se_phys"; | |
| pinctrl-1 = <0x71>; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| status = "disabled"; | |
| #address-cells = <0x01>; | |
| interrupts = <0x00 0x162 0x00>; | |
| #size-cells = <0x00>; | |
| dma-names = "tx\0rx"; | |
| phandle = <0x2e7>; | |
| reg = <0xa84000 0x4000>; | |
| pinctrl-0 = <0x70>; | |
| dmas = <0x5e 0x00 0x01 0x01 0x40 0x00 0x5e 0x01 0x01 0x01 0x40 0x00>; | |
| spi-max-frequency = <0x2faf080>; | |
| pinctrl-names = "default\0sleep"; | |
| }; | |
| qcom,gdsc@0x17d048 { | |
| compatible = "qcom,gdsc"; | |
| status = "ok"; | |
| phandle = <0x1a7>; | |
| reg = <0x17d048 0x04>; | |
| qcom,no-status-check-on-disable; | |
| qcom,gds-timeout = <0x1f4>; | |
| regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc"; | |
| }; | |
| cti@78f0000 { | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti-apss_cti1"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x386>; | |
| arm,primecell-periphid = <0x3b966>; | |
| reg = <0x78f0000 0x1000>; | |
| }; | |
| rpmh-regulator-ldoa26 { | |
| qcom,supported-modes = <0x02 0x04>; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "ldoa26"; | |
| proxy-supply = <0x2e>; | |
| mboxes = <0x8a 0x00>; | |
| qcom,regulator-type = "pmic4-ldo"; | |
| qcom,mode-threshold-currents = <0x00 0x01>; | |
| regulator-l26 { | |
| qcom,proxy-consumer-enable; | |
| qcom,init-mode = <0x02>; | |
| phandle = <0x2e>; | |
| qcom,init-voltage = <0x124f80>; | |
| regulator-min-microvolt = <0x124f80>; | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x124f80>; | |
| regulator-name = "pm8998_l26"; | |
| qcom,proxy-consumer-current = <0xaa50>; | |
| }; | |
| }; | |
| qcom,csiphy@ac68000 { | |
| phandle = <0x9b>; | |
| }; | |
| qcom,smp2pgpio-smp2p-1-out { | |
| compatible = "qcom,smp2pgpio"; | |
| gpio-controller; | |
| #interrupt-cells = <0x02>; | |
| phandle = <0x1b3>; | |
| qcom,entry-name = "smp2p"; | |
| #gpio-cells = <0x02>; | |
| qcom,remote-pid = <0x01>; | |
| interrupt-controller; | |
| }; | |
| wcd9xxx-irq { | |
| compatible = "qcom,wcd9xxx-irq"; | |
| status = "ok"; | |
| #interrupt-cells = <0x01>; | |
| interrupt-parent = <0x34>; | |
| qcom,gpio-connect = <0x34 0x36 0x00>; | |
| phandle = <0x538>; | |
| pinctrl-0 = <0x3f0>; | |
| pinctrl-names = "default"; | |
| interrupt-controller; | |
| }; | |
| qcom,sde_rscc@af20000 { | |
| compatible = "qcom,sde-rsc"; | |
| clocks = <0x20 0x23 0x20 0x22>; | |
| reg-names = "drv\0wrapper"; | |
| qcom,sde-dram-channels = <0x02>; | |
| clock-names = "vsync_clk\0iface_clk"; | |
| mbox-names = "disp_rsc"; | |
| clock-rate = <0x00 0x00>; | |
| mboxes = <0x2b 0x00>; | |
| phandle = <0x2bf>; | |
| vdd-supply = <0x19>; | |
| reg = <0xaf20000 0x1c44 0xaf30000 0x3fd4>; | |
| qcom,sde-rsc-version = <0x01>; | |
| cell-index = <0x00>; | |
| qcom,sde-data-bus { | |
| qcom,msm-bus,num-paths = <0x02>; | |
| qcom,msm-bus,num-cases = <0x03>; | |
| qcom,msm-bus,vectors-KBps = <0x4e23 0x5023 0x00 0x00 0x4e24 0x5023 0x00 0x00 0x4e23 0x5023 0x00 0x61a800 0x4e24 0x5023 0x00 0x61a800 0x4e23 0x5023 0x00 0x61a800 0x4e24 0x5023 0x00 0x61a800>; | |
| qcom,msm-bus,name = "disp_rsc_mnoc"; | |
| qcom,msm-bus,active-only; | |
| }; | |
| qcom,sde-ebi-bus { | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,msm-bus,num-cases = <0x03>; | |
| qcom,msm-bus,vectors-KBps = <0x4e20 0x5020 0x00 0x00 0x4e20 0x5020 0x00 0x61a800 0x4e20 0x5020 0x00 0x61a800>; | |
| qcom,msm-bus,name = "disp_rsc_ebi"; | |
| qcom,msm-bus,active-only; | |
| }; | |
| qcom,sde-llcc-bus { | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,msm-bus,num-cases = <0x03>; | |
| qcom,msm-bus,vectors-KBps = <0x4e21 0x5021 0x00 0x00 0x4e21 0x5021 0x00 0x61a800 0x4e21 0x5021 0x00 0x61a800>; | |
| qcom,msm-bus,name = "disp_rsc_llcc"; | |
| qcom,msm-bus,active-only; | |
| }; | |
| }; | |
| cti@6019000 { | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti9"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x38f>; | |
| arm,primecell-periphid = <0x3b966>; | |
| reg = <0x6019000 0x1000>; | |
| }; | |
| qcom,gdsc@0xad0a004 { | |
| compatible = "qcom,gdsc"; | |
| status = "ok"; | |
| phandle = <0x1c2>; | |
| reg = <0xad0a004 0x04>; | |
| regulator-name = "ife_1_gdsc"; | |
| qcom,poll-cfg-gdscr; | |
| }; | |
| qcom,glink-smem-native-xprt-dsps@86000000 { | |
| compatible = "qcom,glink-smem-native-xprt"; | |
| reg-names = "smem\0irq-reg-base"; | |
| interrupts = <0x00 0xaa 0x01>; | |
| label = "dsps"; | |
| qcom,irq-mask = <0x1000000>; | |
| reg = <0x86000000 0x200000 0x1799000c 0x04>; | |
| }; | |
| qcom,llcc-bwmon { | |
| compatible = "qcom,bimc-bwmon5"; | |
| qcom,byte-mid-match = <0xe000>; | |
| reg-names = "base"; | |
| qcom,count-unit = <0x400000>; | |
| interrupts = <0x00 0x244 0x04>; | |
| qcom,hw-timer-hz = <0x124f800>; | |
| phandle = <0x30b>; | |
| qcom,target-dev = <0x83>; | |
| reg = <0x114a000 0x1000>; | |
| qcom,byte-mid-mask = <0xe000>; | |
| }; | |
| etm@7140000 { | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| coresight-name = "coresight-etm1"; | |
| clock-names = "apb_pclk"; | |
| cpu = <0x12>; | |
| phandle = <0x3a3>; | |
| arm,primecell-periphid = <0xbb95d>; | |
| reg = <0x7140000 0x1000>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x193>; | |
| phandle = <0x19c>; | |
| }; | |
| }; | |
| }; | |
| rpmh-regulator-smpc3 { | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "smpc3"; | |
| mboxes = <0x8a 0x00>; | |
| regulator-s3 { | |
| phandle = <0x34f>; | |
| qcom,init-voltage = <0x927c0>; | |
| regulator-min-microvolt = <0x927c0>; | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x927c0>; | |
| regulator-name = "pm8005_s3"; | |
| }; | |
| }; | |
| qcom,cam-isp { | |
| compatible = "qcom,cam-isp"; | |
| status = "ok"; | |
| arch-compat = "ife"; | |
| }; | |
| qcom,mdss_dsi_ctrl0@ae94000 { | |
| compatible = "qcom,dsi-ctrl-hw-v2.2"; | |
| clocks = <0x20 0x02 0x20 0x03 0x20 0x04 0x20 0x1a 0x20 0x1b 0x20 0x13>; | |
| reg-names = "dsi_ctrl\0disp_cc_base"; | |
| clock-names = "byte_clk\0byte_clk_rcg\0byte_intf_clk\0pixel_clk\0pixel_clk_rcg\0esc_clk"; | |
| vdda-1p2-supply = <0x2e>; | |
| interrupt-parent = <0x2c>; | |
| interrupts = <0x04 0x00>; | |
| label = "dsi-ctrl-0"; | |
| phandle = <0x2c3>; | |
| reg = <0xae94000 0x400 0xaf08000 0x04>; | |
| qcom,null-insertion-enabled; | |
| cell-index = <0x00>; | |
| qcom,core-supply-entries { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| qcom,core-supply-entry@0 { | |
| qcom,supply-name = "refgen"; | |
| qcom,supply-disable-load = <0x00>; | |
| qcom,supply-max-voltage = <0x00>; | |
| qcom,supply-enable-load = <0x00>; | |
| qcom,supply-min-voltage = <0x00>; | |
| reg = <0x00>; | |
| }; | |
| }; | |
| qcom,ctrl-supply-entries { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| qcom,ctrl-supply-entry@0 { | |
| qcom,supply-name = "vdda-1p2"; | |
| qcom,supply-disable-load = <0x04>; | |
| qcom,supply-max-voltage = <0x124f80>; | |
| qcom,supply-enable-load = <0x5528>; | |
| qcom,supply-min-voltage = <0x124f80>; | |
| reg = <0x00>; | |
| }; | |
| }; | |
| }; | |
| tpda@7862000 { | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "tpda-base"; | |
| coresight-name = "coresight-tpda-apss"; | |
| clock-names = "apb_pclk"; | |
| qcom,dsb-elem-size = <0x00 0x20>; | |
| phandle = <0x36a>; | |
| arm,primecell-periphid = <0x3b969>; | |
| reg = <0x7862000 0x1000>; | |
| qcom,tpda-atid = <0x42>; | |
| ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@1 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x162>; | |
| phandle = <0x163>; | |
| slave-mode; | |
| }; | |
| }; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x161>; | |
| phandle = <0x18f>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,cam-icp { | |
| compatible = "qcom,cam-icp"; | |
| num-bps = <0x01>; | |
| num-ipe = <0x02>; | |
| num-a5 = <0x01>; | |
| compat-hw-name = "qcom,a5\0qcom,ipe0\0qcom,ipe1\0qcom,bps"; | |
| status = "ok"; | |
| }; | |
| qcom,msm-pcm-low-latency { | |
| compatible = "qcom,msm-pcm-dsp"; | |
| qcom,latency-level = "regular"; | |
| qcom,msm-pcm-low-latency; | |
| qcom,msm-pcm-dsp-id = <0x01>; | |
| phandle = <0x272>; | |
| }; | |
| qcom,gdsc@0x17d038 { | |
| compatible = "qcom,gdsc"; | |
| status = "ok"; | |
| phandle = <0x1a5>; | |
| reg = <0x17d038 0x04>; | |
| qcom,no-status-check-on-disable; | |
| qcom,gds-timeout = <0x1f4>; | |
| regulator-name = "hlos1_vote_aggre_noc_mmu_tbu2_gdsc"; | |
| }; | |
| qcom,msm-dai-q6-hdmi { | |
| compatible = "qcom,msm-dai-q6-hdmi"; | |
| phandle = <0x27e>; | |
| qcom,msm-dai-q6-dev-id = <0x08>; | |
| }; | |
| qcom,kgsl-busmon { | |
| compatible = "qcom,kgsl-busmon"; | |
| label = "kgsl-busmon"; | |
| phandle = <0x4c9>; | |
| }; | |
| qcom,csiphy@ac65000 { | |
| phandle = <0x8d>; | |
| }; | |
| qcom,dsi-display@17 { | |
| compatible = "qcom,dsi-display"; | |
| clocks = <0x2bc 0x06 0x2bc 0x09>; | |
| lab-supply = <0x4e2>; | |
| pinctrl-1 = <0x41c 0x41e>; | |
| clock-names = "mux_byte_clk\0mux_pixel_clk"; | |
| vddio-supply = <0x120>; | |
| qcom,dsi-panel = <0x4f4>; | |
| label = "dsi_dual_test_cmd"; | |
| ibb-supply = <0x4e3>; | |
| phandle = <0x551>; | |
| qcom,dsi-ctrl = <0x2c3 0x2c4>; | |
| qcom,display-type = "primary"; | |
| qcom,panel-mode-gpio = <0x34 0x34 0x00>; | |
| oled-vdda-supply = <0x348>; | |
| pinctrl-0 = <0x41b 0x41d>; | |
| qcom,platform-te-gpio = <0x34 0x0a 0x00>; | |
| qcom,dsi-phy = <0x2c5 0x2c6>; | |
| qcom,platform-reset-gpio = <0x34 0x06 0x00>; | |
| pinctrl-names = "panel_active\0panel_suspend"; | |
| }; | |
| qcom,dsi-display@8 { | |
| compatible = "qcom,dsi-display"; | |
| clocks = <0x2bc 0x06 0x2bc 0x09>; | |
| pinctrl-1 = <0x41c 0x41e>; | |
| clock-names = "mux_byte_clk\0mux_pixel_clk"; | |
| qcom,dsi-panel = <0x4eb>; | |
| label = "dsi_sim_vid_display"; | |
| phandle = <0x548>; | |
| qcom,dsi-ctrl = <0x2c3>; | |
| qcom,display-type = "primary"; | |
| pinctrl-0 = <0x41b 0x41d>; | |
| qcom,dsi-phy = <0x2c5>; | |
| pinctrl-names = "panel_active\0panel_suspend"; | |
| }; | |
| qcom,msm-quat-auxpcm { | |
| qcom,msm-auxpcm-interface = "quaternary"; | |
| compatible = "qcom,msm-auxpcm-dev"; | |
| qcom,msm-cpudai-auxpcm-sync = <0x01 0x01>; | |
| qcom,msm-cpudai-auxpcm-frame = <0x05 0x04>; | |
| qcom,msm-cpudai-auxpcm-quant = <0x02 0x02>; | |
| qcom,msm-cpudai-afe-clk-ver = <0x02>; | |
| qcom,msm-cpudai-auxpcm-slot-mapping = <0x01 0x01>; | |
| qcom,msm-cpudai-auxpcm-num-slots = <0x01 0x01>; | |
| qcom,msm-cpudai-auxpcm-data = <0x00 0x00>; | |
| qcom,msm-cpudai-auxpcm-pcm-clk-rate = <0x1f4000 0x1f4000>; | |
| phandle = <0x287>; | |
| qcom,msm-cpudai-auxpcm-mode = <0x00 0x00>; | |
| }; | |
| cti@6016000 { | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti6"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x38d>; | |
| arm,primecell-periphid = <0x3b966>; | |
| reg = <0x6016000 0x1000>; | |
| }; | |
| slim@171c0000 { | |
| compatible = "qcom,slim-ngd"; | |
| qcom,iommu-s1-bypass; | |
| reg-names = "slimbus_physical\0slimbus_bam_physical"; | |
| qcom,apps-ch-pipes = <0x780000>; | |
| interrupts = <0x00 0xa3 0x00 0x00 0xa4 0x00>; | |
| phandle = <0x31a>; | |
| qcom,ea-pc = <0x270>; | |
| reg = <0x171c0000 0x2c000 0x17184000 0x2a000>; | |
| interrupt-names = "slimbus_irq\0slimbus_bam_irq"; | |
| cell-index = <0x01>; | |
| tavil_codec { | |
| qcom,cdc-vddpx-1-voltage = <0x1b7740 0x1b7740>; | |
| qcom,cdc-dmic-sample-rate = "\0I>"; | |
| compatible = "qcom,tavil-slim-pgd"; | |
| clocks = <0x53a 0x00>; | |
| cdc-buck-sido-supply = <0x4dd>; | |
| cdc-vddpx-1-supply = <0x4dd>; | |
| qcom,cdc-micbias3-mv = <0x708>; | |
| qcom,cdc-buck-sido-current = <0x3d090>; | |
| cdc-vdd-buck-supply = <0x4dd>; | |
| qcom,wdsp-cmpnt-dev-name = "tavil_codec"; | |
| qcom,cdc-vdd-rx-h-voltage = <0x1b7740 0x1b7740>; | |
| clock-names = "wcd_clk"; | |
| qcom,wcd-rst-gpio-node = <0x539>; | |
| qcom,cdc-slim-ifd = "tavil-slim-ifd"; | |
| qcom,cdc-static-supplies = "cdc-vdd-buck\0cdc-buck-sido\0cdc-vdd-tx-h\0cdc-vdd-rx-h\0cdc-vddpx-1"; | |
| qcom,cdc-vdd-tx-h-current = <0x61a8>; | |
| qcom,cdc-buck-sido-voltage = <0x1b7740 0x1b7740>; | |
| qcom,cdc-micbias2-mv = <0x708>; | |
| status = "okay"; | |
| interrupt-parent = <0x538>; | |
| qcom,cdc-vdd-buck-current = <0x9eb10>; | |
| interrupts = <0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f>; | |
| qcom,cdc-mclk-clk-rate = <0x927c00>; | |
| qcom,cdc-slim-ifd-elemental-addr = [00 00 50 02 17 02]; | |
| phandle = <0x536>; | |
| qcom,cdc-vdd-tx-h-voltage = <0x1b7740 0x1b7740>; | |
| cdc-vdd-tx-h-supply = <0x4dd>; | |
| elemental-addr = [00 01 50 02 17 02]; | |
| qcom,cdc-vddpx-1-current = <0x2710>; | |
| qcom,cdc-micbias4-mv = <0x708>; | |
| qcom,cdc-vdd-buck-voltage = <0x1b7740 0x1b7740>; | |
| qcom,cdc-micbias1-mv = <0x708>; | |
| qcom,cdc-mad-dmic-rate = <0x927c0>; | |
| cdc-vdd-rx-h-supply = <0x4dd>; | |
| qcom,cdc-vdd-rx-h-current = <0x61a8>; | |
| msm_cdc_pinctrl_hph_en0 { | |
| compatible = "qcom,msm-cdc-pinctrl"; | |
| pinctrl-1 = <0x529>; | |
| phandle = <0x52e>; | |
| pinctrl-0 = <0x528>; | |
| pinctrl-names = "aud_active\0aud_sleep"; | |
| }; | |
| msm_cdc_pinctrl_us_euro_sw { | |
| compatible = "qcom,msm-cdc-pinctrl"; | |
| pinctrl-1 = <0x527>; | |
| phandle = <0x57f>; | |
| pinctrl-0 = <0x526>; | |
| pinctrl-names = "aud_active\0aud_sleep"; | |
| }; | |
| wcd_spi { | |
| compatible = "qcom,wcd-spi-v2"; | |
| qcom,master-bus-num = <0x00>; | |
| qcom,max-frequency = <0x16e3600>; | |
| qcom,chip-select = <0x00>; | |
| phandle = <0x537>; | |
| qcom,mem-base-addr = <0x100000>; | |
| }; | |
| msm_cdc_pinctrl_hph_en1 { | |
| compatible = "qcom,msm-cdc-pinctrl"; | |
| pinctrl-1 = <0x52b>; | |
| phandle = <0x52f>; | |
| pinctrl-0 = <0x52a>; | |
| pinctrl-names = "aud_active\0aud_sleep"; | |
| }; | |
| wcd_pinctrl@5 { | |
| compatible = "qcom,wcd-pinctrl"; | |
| gpio-controller; | |
| qcom,num-gpios = <0x05>; | |
| phandle = <0x57e>; | |
| #gpio-cells = <0x02>; | |
| us_euro_sw_wcd_sleep { | |
| phandle = <0x527>; | |
| config { | |
| output-low; | |
| pins = "gpio1"; | |
| }; | |
| mux { | |
| pins = "gpio1"; | |
| }; | |
| }; | |
| hph_en0_wcd_sleep { | |
| phandle = <0x529>; | |
| config { | |
| output-low; | |
| pins = "gpio4"; | |
| }; | |
| mux { | |
| pins = "gpio4"; | |
| }; | |
| }; | |
| us_euro_sw_wcd_active { | |
| phandle = <0x526>; | |
| config { | |
| pins = "gpio1"; | |
| output-high; | |
| }; | |
| mux { | |
| pins = "gpio1"; | |
| }; | |
| }; | |
| spkr_2_sd_n_active { | |
| phandle = <0x524>; | |
| config { | |
| pins = "gpio3"; | |
| output-high; | |
| }; | |
| mux { | |
| pins = "gpio3"; | |
| }; | |
| }; | |
| hph_en0_wcd_active { | |
| phandle = <0x528>; | |
| config { | |
| pins = "gpio4"; | |
| output-high; | |
| }; | |
| mux { | |
| pins = "gpio4"; | |
| }; | |
| }; | |
| hph_en1_wcd_active { | |
| phandle = <0x52a>; | |
| config { | |
| pins = "gpio5"; | |
| output-high; | |
| }; | |
| mux { | |
| pins = "gpio5"; | |
| }; | |
| }; | |
| spkr_1_wcd_en_sleep { | |
| phandle = <0x523>; | |
| config { | |
| pins = "gpio2"; | |
| input-enable; | |
| }; | |
| mux { | |
| pins = "gpio2"; | |
| }; | |
| }; | |
| spkr_2_sd_n_sleep { | |
| phandle = <0x525>; | |
| config { | |
| pins = "gpio3"; | |
| input-enable; | |
| }; | |
| mux { | |
| pins = "gpio3"; | |
| }; | |
| }; | |
| hph_en1_wcd_sleep { | |
| phandle = <0x52b>; | |
| config { | |
| output-low; | |
| pins = "gpio5"; | |
| }; | |
| mux { | |
| pins = "gpio5"; | |
| }; | |
| }; | |
| spkr_1_wcd_en_active { | |
| phandle = <0x522>; | |
| config { | |
| pins = "gpio2"; | |
| output-high; | |
| }; | |
| mux { | |
| pins = "gpio2"; | |
| }; | |
| }; | |
| }; | |
| msm_cdc_pinctrll { | |
| compatible = "qcom,msm-cdc-pinctrl"; | |
| pinctrl-1 = <0x523>; | |
| status = "okay"; | |
| phandle = <0x52d>; | |
| pinctrl-0 = <0x522>; | |
| pinctrl-names = "aud_active\0aud_sleep"; | |
| }; | |
| msm_cdc_pinctrlr { | |
| compatible = "qcom,msm-cdc-pinctrl"; | |
| pinctrl-1 = <0x525>; | |
| status = "okay"; | |
| phandle = <0x52c>; | |
| pinctrl-0 = <0x524>; | |
| pinctrl-names = "aud_active\0aud_sleep"; | |
| }; | |
| swr_master { | |
| compatible = "qcom,swr-wcd"; | |
| #address-cells = <0x02>; | |
| #size-cells = <0x00>; | |
| wsa881x@20170212 { | |
| compatible = "qcom,wsa881x"; | |
| qcom,spkr-sd-n-node = <0x52c>; | |
| phandle = <0x533>; | |
| reg = <0x00 0x20170212>; | |
| }; | |
| wsa881x@21170214 { | |
| compatible = "qcom,wsa881x"; | |
| qcom,spkr-sd-n-node = <0x52d>; | |
| phandle = <0x535>; | |
| reg = <0x00 0x21170214>; | |
| }; | |
| wsa881x@20170211 { | |
| compatible = "qcom,wsa881x"; | |
| qcom,spkr-sd-n-node = <0x52c>; | |
| phandle = <0x532>; | |
| reg = <0x00 0x20170211>; | |
| }; | |
| wsa881x@21170213 { | |
| compatible = "qcom,wsa881x"; | |
| qcom,spkr-sd-n-node = <0x52d>; | |
| phandle = <0x534>; | |
| reg = <0x00 0x21170213>; | |
| }; | |
| }; | |
| }; | |
| msm_dai_slim { | |
| compatible = "qcom,msm-dai-slim"; | |
| status = "okay"; | |
| elemental-addr = [ff ff ff fe 17 02]; | |
| }; | |
| qcom,iommu_slim_ctrl_cb { | |
| compatible = "qcom,iommu-slim-ctrl-cb"; | |
| phandle = <0x31b>; | |
| iommus = <0x29 0x1806 0x00 0x29 0x180d 0x00 0x29 0x180e 0x01 0x29 0x1810 0x01>; | |
| }; | |
| }; | |
| qcom,smp2pgpio-ssr-smp2p-3-in { | |
| compatible = "qcom,smp2pgpio"; | |
| gpio-controller; | |
| #interrupt-cells = <0x02>; | |
| phandle = <0xb8>; | |
| qcom,entry-name = "slave-kernel"; | |
| #gpio-cells = <0x02>; | |
| qcom,is-inbound; | |
| qcom,remote-pid = <0x03>; | |
| interrupt-controller; | |
| }; | |
| rpmh-regulator-ldoa16 { | |
| qcom,supported-modes = <0x02 0x04>; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "ldoa16"; | |
| mboxes = <0x8a 0x00>; | |
| qcom,regulator-type = "pmic4-ldo"; | |
| qcom,mode-threshold-currents = <0x00 0x01>; | |
| regulator-l16 { | |
| qcom,init-mode = <0x02>; | |
| phandle = <0x343>; | |
| qcom,init-voltage = <0x294280>; | |
| regulator-min-microvolt = <0x294280>; | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x294280>; | |
| regulator-name = "pm8998_l16"; | |
| }; | |
| }; | |
| tpdm@69e0000 { | |
| qcom,msr-fix-req; | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "tpdm-base"; | |
| coresight-name = "coresight-tpdm-ddr"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x376>; | |
| arm,primecell-periphid = <0x3b968>; | |
| reg = <0x69e0000 0x1000>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x174>; | |
| phandle = <0x173>; | |
| }; | |
| }; | |
| }; | |
| qcom,cam-jpeg { | |
| compatible = "qcom,cam-jpeg"; | |
| num-jpeg-dma = <0x01>; | |
| compat-hw-name = "qcom,jpegenc\0qcom,jpegdma"; | |
| status = "ok"; | |
| num-jpeg-enc = <0x01>; | |
| }; | |
| qcom,venus@aae0000 { | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| qcom,proxy-timeout-ms = <0x64>; | |
| compatible = "qcom,pil-tz-generic"; | |
| clocks = <0xa4 0x0b 0xa4 0x08 0xa4 0x0a>; | |
| qcom,msm-bus,vectors-KBps = <0x3f 0x200 0x00 0x00 0x3f 0x200 0x00 0x4a380>; | |
| qcom,proxy-clock-names = "core_clk\0iface_clk\0bus_clk"; | |
| qcom,firmware-name = "venus"; | |
| clock-names = "core_clk\0iface_clk\0bus_clk"; | |
| qcom,pas-id = <0x09>; | |
| qcom,msm-bus,name = "pil-venus"; | |
| status = "ok"; | |
| memory-region = <0xc1>; | |
| qcom,proxy-reg-names = "vdd"; | |
| vdd-supply = <0xc0>; | |
| reg = <0xaae0000 0x4000>; | |
| }; | |
| qcom,cci@ac4a000 { | |
| gpios = <0x34 0x11 0x00 0x34 0x12 0x00 0x34 0x13 0x00 0x34 0x14 0x00>; | |
| clock-rates = <0x00 0x00 0x00 0x00 0x00 0x23c3460>; | |
| compatible = "qcom,cci"; | |
| clocks = <0xa5 0x06 0xa5 0x55 0xa5 0x54 0xa5 0x09 0xa5 0x07 0xa5 0x08>; | |
| gpio-req-tbl-label = "CCI_I2C_DATA0\0CCI_I2C_CLK0\0CCI_I2C_DATA1\0CCI_I2C_CLK1"; | |
| reg-names = "cci"; | |
| pinctrl-1 = <0x1be 0x1bf>; | |
| clock-names = "camnoc_axi_clk\0soc_ahb_clk\0slow_ahb_src_clk\0cpas_ahb_clk\0cci_clk\0cci_clk_src"; | |
| regulator-names = "gdscr"; | |
| status = "ok"; | |
| #address-cells = <0x01>; | |
| interrupts = <0x00 0x1cc 0x00>; | |
| #size-cells = <0x00>; | |
| gpio-req-tbl-num = <0x00 0x01 0x02 0x03>; | |
| phandle = <0x90>; | |
| gpio-req-tbl-flags = <0x01 0x01 0x01 0x01>; | |
| reg = <0xac4a000 0x4000>; | |
| pinctrl-0 = <0x1bc 0x1bd>; | |
| src-clock-name = "cci_clk_src"; | |
| interrupt-names = "cci"; | |
| reg-cam-base = <0x4a000>; | |
| gdscr-supply = <0x1bb>; | |
| pinctrl-names = "cam_default\0cam_suspend"; | |
| cell-index = <0x00>; | |
| clock-cntl-level = "lowsvs"; | |
| qcom,cam-sensor@3 { | |
| }; | |
| qcom,actuator@1 { | |
| compatible = "qcom,actuator"; | |
| cci-master = <0x01>; | |
| rgltr-max-voltage = <0x2ab980>; | |
| regulator-names = "cam_vaf"; | |
| rgltr-load-current = <0x00>; | |
| rgltr-cntrl-support; | |
| phandle = <0x574>; | |
| rgltr-min-voltage = <0x2ab980>; | |
| reg = <0x01>; | |
| cam_vaf-supply = <0x519>; | |
| cell-index = <0x01>; | |
| }; | |
| qcom,ois@0 { | |
| compatible = "qcom,ois"; | |
| cci-master = <0x00>; | |
| rgltr-max-voltage = <0x2ab980>; | |
| regulator-names = "cam_vaf"; | |
| rgltr-load-current = <0x00>; | |
| status = "ok"; | |
| rgltr-cntrl-support; | |
| phandle = <0x576>; | |
| rgltr-min-voltage = <0x2ab980>; | |
| reg = <0x00>; | |
| cam_vaf-supply = <0x518>; | |
| cell-index = <0x00>; | |
| }; | |
| qcom,i2c_standard_mode { | |
| hw-trdhld = <0x06>; | |
| hw-tbuf = <0xe3>; | |
| hw-tsp = <0x03>; | |
| hw-thd-dat = <0x16>; | |
| hw-thigh = <0xc9>; | |
| hw-tsu-sta = <0xe7>; | |
| hw-thd-sta = <0xa2>; | |
| status = "ok"; | |
| phandle = <0x3b4>; | |
| cci-clk-src = <0x23c3460>; | |
| hw-tsu-sto = <0xcc>; | |
| hw-scl-stretch-en = <0x00>; | |
| hw-tlow = <0xae>; | |
| }; | |
| qcom,cam-sensor@1 { | |
| }; | |
| qcom,eeprom@1 { | |
| phandle = <0x578>; | |
| }; | |
| qcom,actuator@2 { | |
| compatible = "qcom,actuator"; | |
| cci-master = <0x01>; | |
| rgltr-max-voltage = <0x2ab980>; | |
| regulator-names = "cam_vaf"; | |
| rgltr-load-current = <0x00>; | |
| rgltr-cntrl-support; | |
| phandle = <0x575>; | |
| rgltr-min-voltage = <0x2ab980>; | |
| reg = <0x02>; | |
| cam_vaf-supply = <0x518>; | |
| cell-index = <0x02>; | |
| }; | |
| qcom,cam-sensor@2 { | |
| }; | |
| qcom,actuator@0 { | |
| compatible = "qcom,actuator"; | |
| cci-master = <0x00>; | |
| rgltr-max-voltage = <0x2ab980>; | |
| regulator-names = "cam_vaf"; | |
| rgltr-load-current = <0x00>; | |
| rgltr-cntrl-support; | |
| phandle = <0x573>; | |
| rgltr-min-voltage = <0x2ab980>; | |
| reg = <0x00>; | |
| cam_vaf-supply = <0x518>; | |
| cell-index = <0x00>; | |
| }; | |
| qcom,eeprom@2 { | |
| phandle = <0x579>; | |
| }; | |
| qcom,cam-sensor@0 { | |
| }; | |
| qcom,i2c_custom_mode { | |
| hw-trdhld = <0x06>; | |
| hw-tbuf = <0x3e>; | |
| hw-tsp = <0x03>; | |
| hw-thd-dat = <0x16>; | |
| hw-thigh = <0x26>; | |
| hw-tsu-sta = <0x28>; | |
| hw-thd-sta = <0x23>; | |
| status = "ok"; | |
| phandle = <0x3b6>; | |
| cci-clk-src = <0x23c3460>; | |
| hw-tsu-sto = <0x28>; | |
| hw-scl-stretch-en = <0x01>; | |
| hw-tlow = <0x38>; | |
| }; | |
| qcom,i2c_fast_plus_mode { | |
| hw-trdhld = <0x03>; | |
| hw-tbuf = <0x18>; | |
| hw-tsp = <0x03>; | |
| hw-thd-dat = <0x10>; | |
| hw-thigh = <0x10>; | |
| hw-tsu-sta = <0x12>; | |
| hw-thd-sta = <0x0f>; | |
| status = "ok"; | |
| phandle = <0x3b7>; | |
| cci-clk-src = <0x23c3460>; | |
| hw-tsu-sto = <0x11>; | |
| hw-scl-stretch-en = <0x00>; | |
| hw-tlow = <0x16>; | |
| }; | |
| qcom,eeprom@0 { | |
| phandle = <0x577>; | |
| }; | |
| qcom,cam-res-mgr { | |
| compatible = "qcom,cam-res-mgr"; | |
| status = "ok"; | |
| }; | |
| qcom,i2c_fast_mode { | |
| hw-trdhld = <0x06>; | |
| hw-tbuf = <0x3e>; | |
| hw-tsp = <0x03>; | |
| hw-thd-dat = <0x16>; | |
| hw-thigh = <0x26>; | |
| hw-tsu-sta = <0x28>; | |
| hw-thd-sta = <0x23>; | |
| status = "ok"; | |
| phandle = <0x3b5>; | |
| cci-clk-src = <0x23c3460>; | |
| hw-tsu-sto = <0x28>; | |
| hw-scl-stretch-en = <0x00>; | |
| hw-tlow = <0x38>; | |
| }; | |
| }; | |
| qcom,smp2pgpio-smp2p-3-in { | |
| compatible = "qcom,smp2pgpio"; | |
| gpio-controller; | |
| #interrupt-cells = <0x02>; | |
| phandle = <0x1b6>; | |
| qcom,entry-name = "smp2p"; | |
| #gpio-cells = <0x02>; | |
| qcom,is-inbound; | |
| qcom,remote-pid = <0x03>; | |
| interrupt-controller; | |
| }; | |
| qcom,smp2pgpio_test_smp2p_15_out { | |
| gpios = <0x1b1 0x00 0x00>; | |
| compatible = "qcom,smp2pgpio_test_smp2p_15_out"; | |
| }; | |
| qcom,glink-mailbox-xprt-spss@1885008 { | |
| compatible = "qcom,glink-mailbox-xprt"; | |
| reg-names = "mbox-loc-addr\0mbox-loc-size\0irq-reg-base\0irq-rx-reset"; | |
| qcom,rx-ring-size = <0x400>; | |
| interrupts = <0x00 0x15c 0x04>; | |
| label = "spss"; | |
| qcom,irq-mask = <0x01>; | |
| reg = <0x1885008 0x08 0x1885010 0x04 0x188501c 0x04 0x1886008 0x04>; | |
| qcom,tx-ring-size = <0x400>; | |
| }; | |
| qcom,smp2pgpio-smp2p-5-out { | |
| compatible = "qcom,smp2pgpio"; | |
| gpio-controller; | |
| #interrupt-cells = <0x02>; | |
| phandle = <0x1b9>; | |
| qcom,entry-name = "smp2p"; | |
| #gpio-cells = <0x02>; | |
| qcom,remote-pid = <0x05>; | |
| interrupt-controller; | |
| }; | |
| qcom,smp2pgpio_test_smp2p_1_out { | |
| gpios = <0x1b3 0x00 0x00>; | |
| compatible = "qcom,smp2pgpio_test_smp2p_1_out"; | |
| }; | |
| cti@6013000 { | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti3"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x38a>; | |
| arm,primecell-periphid = <0x3b966>; | |
| reg = <0x6013000 0x1000>; | |
| }; | |
| usb_audio_qmi_dev { | |
| compatible = "qcom,usb-audio-qmi-dev"; | |
| qcom,usb-audio-intr-num = <0x02>; | |
| qcom,usb-audio-stream-id = <0x0c>; | |
| iommus = <0x29 0x182c 0x00>; | |
| }; | |
| quec_gpios { | |
| gpios = <0x34 0x00 0x00 0x34 0x03 0x00 0x34 0x07 0x01 0x34 0x16 0x00 0x34 0x18 0x00 0x34 0x19 0x01 0x34 0x1a 0x00 0x34 0x28 0x00 0x34 0x29 0x00 0x34 0x31 0x00 0x34 0x34 0x00 0x34 0x57 0x01 0x34 0x5b 0x00 0x34 0x5c 0x00 0x34 0x5f 0x00 0x34 0x60 0x00 0x34 0x74 0x00 0x34 0x7a 0x00 0x34 0x7c 0x00 0x34 0x80 0x00 0x34 0x81 0x01>; | |
| compatible = "quec,gpios"; | |
| pinctrl-0 = <0x4b2 0x4b3>; | |
| pinctrl-names = "default"; | |
| }; | |
| gpio-regulator@1 { | |
| regulator-enable-ramp-delay = <0x87>; | |
| compatible = "regulator-fixed"; | |
| enable-active-high; | |
| phandle = <0x571>; | |
| reg = <0x01 0x00>; | |
| regulator-name = "camera_rear_ldo"; | |
| }; | |
| i2c@89c000 { | |
| compatible = "qcom,i2c-geni"; | |
| clocks = <0x22 0x5a 0x22 0x6c 0x22 0x6d>; | |
| qcom,wrapper-core = <0x35>; | |
| pinctrl-1 = <0x48>; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| status = "disabled"; | |
| #address-cells = <0x01>; | |
| interrupts = <0x00 0x260 0x00>; | |
| #size-cells = <0x00>; | |
| dma-names = "tx\0rx"; | |
| phandle = <0x2d2>; | |
| reg = <0x89c000 0x4000>; | |
| pinctrl-0 = <0x47>; | |
| dmas = <0x38 0x00 0x07 0x03 0x40 0x00 0x38 0x01 0x07 0x03 0x40 0x00>; | |
| pinctrl-names = "default\0sleep"; | |
| }; | |
| qcom,glink_pkt { | |
| compatible = "qcom,glinkpkt"; | |
| qcom,glinkpkt-at-mdm0 { | |
| qcom,glinkpkt-ch-name = "DS"; | |
| qcom,glinkpkt-transport = "smem"; | |
| qcom,glinkpkt-edge = "mpss"; | |
| qcom,glinkpkt-dev-name = "at_mdm0"; | |
| }; | |
| qcom,glinkpkt-data40-cntl { | |
| qcom,glinkpkt-ch-name = "DATA40_CNTL"; | |
| qcom,glinkpkt-transport = "smem"; | |
| qcom,glinkpkt-edge = "mpss"; | |
| qcom,glinkpkt-dev-name = "smdcntl8"; | |
| }; | |
| qcom,glinkpkt-loopback_data { | |
| qcom,glinkpkt-ch-name = "glink_pkt_lloop_CLNT"; | |
| qcom,glinkpkt-transport = "lloop"; | |
| qcom,glinkpkt-edge = "local"; | |
| qcom,glinkpkt-dev-name = "glink_pkt_loopback"; | |
| }; | |
| qcom,glinkpkt-apr-apps2 { | |
| qcom,glinkpkt-ch-name = "apr_apps2"; | |
| qcom,glinkpkt-transport = "smem"; | |
| qcom,glinkpkt-edge = "adsp"; | |
| qcom,glinkpkt-dev-name = "apr_apps2"; | |
| }; | |
| qcom,glinkpkt-data4 { | |
| qcom,glinkpkt-ch-name = "DATA4"; | |
| qcom,glinkpkt-transport = "smem"; | |
| qcom,glinkpkt-edge = "mpss"; | |
| qcom,glinkpkt-dev-name = "smd8"; | |
| }; | |
| qcom,glinkpkt-loopback_cntl { | |
| qcom,glinkpkt-ch-name = "LOCAL_LOOPBACK_CLNT"; | |
| qcom,glinkpkt-transport = "lloop"; | |
| qcom,glinkpkt-edge = "local"; | |
| qcom,glinkpkt-dev-name = "glink_pkt_loopback_ctrl"; | |
| }; | |
| qcom,glinkpkt-data1 { | |
| qcom,glinkpkt-ch-name = "DATA1"; | |
| qcom,glinkpkt-transport = "smem"; | |
| qcom,glinkpkt-edge = "mpss"; | |
| qcom,glinkpkt-dev-name = "smd7"; | |
| }; | |
| qcom,glinkpkt-data11 { | |
| qcom,glinkpkt-ch-name = "DATA11"; | |
| qcom,glinkpkt-transport = "smem"; | |
| qcom,glinkpkt-edge = "mpss"; | |
| qcom,glinkpkt-dev-name = "smd11"; | |
| }; | |
| }; | |
| qcom,vfe1@acb6000 { | |
| clock-rates = <0x00 0x00 0x00 0x00 0x00 0x00 0x18148d00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x23c34600 0x00 0x00>; | |
| compatible = "qcom,vfe170"; | |
| clocks = <0x22 0x0c 0x22 0x0d 0xa5 0x55 0xa5 0x09 0xa5 0x54 0xa5 0x29 0xa5 0x2a 0xa5 0x06 0xa5 0x28>; | |
| reg-names = "ife"; | |
| clocks-option = <0xa5 0x2e>; | |
| clock-names-option = "ife_dsp_clk"; | |
| clock-control-debugfs = "true"; | |
| clock-rates-option = <0x23c34600>; | |
| clock-names = "camera_ahb\0camera_axi\0soc_ahb_clk\0cpas_ahb_clk\0slow_ahb_clk_src\0ife_clk\0ife_clk_src\0camnoc_axi_clk\0ife_axi_clk"; | |
| regulator-names = "camss\0ife1"; | |
| status = "ok"; | |
| interrupts = <0x00 0x1d3 0x00>; | |
| ife1-supply = <0x1c2>; | |
| phandle = <0x94>; | |
| reg = <0xacb6000 0x4000>; | |
| src-clock-name = "ife_clk_src"; | |
| interrupt-names = "ife"; | |
| reg-cam-base = "\0\v`"; | |
| cell-index = <0x01>; | |
| camss-supply = <0x1bb>; | |
| clock-cntl-level = "svs\0svs_l1\0turbo"; | |
| }; | |
| qcom,cpas-cdm0@ac48000 { | |
| clock-rates = <0x00 0x00 0x00 0x00 0x00>; | |
| compatible = "qcom,cam170-cpas-cdm0"; | |
| clocks = <0x22 0x0c 0x22 0x0d 0xa5 0x55 0xa5 0x09 0xa5 0x06>; | |
| reg-names = "cpas-cdm"; | |
| clock-names = "gcc_camera_ahb\0gcc_camera_axi\0cam_cc_soc_ahb_clk\0cam_cc_cpas_ahb_clk\0cam_cc_camnoc_axi_clk"; | |
| regulator-names = "camss"; | |
| cdm-client-names = "ife"; | |
| status = "ok"; | |
| interrupts = <0x00 0x1cd 0x00>; | |
| label = "cpas-cdm"; | |
| reg = <0xac48000 0x1000>; | |
| interrupt-names = "cpas-cdm"; | |
| reg-cam-base = <0x48000>; | |
| cell-index = <0x00>; | |
| camss-supply = <0x1bb>; | |
| clock-cntl-level = "svs"; | |
| }; | |
| syscon@0x5091008 { | |
| compatible = "syscon"; | |
| phandle = <0x1f>; | |
| reg = <0x5091008 0x04>; | |
| }; | |
| rpmh-regulator-smpa3 { | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "smpa3"; | |
| mboxes = <0x8a 0x00>; | |
| regulator-s3 { | |
| phandle = <0x339>; | |
| qcom,init-voltage = <0x14a140>; | |
| regulator-min-microvolt = <0x14a140>; | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x14a140>; | |
| regulator-name = "pm8998_s3"; | |
| }; | |
| }; | |
| cti@6010000 { | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti0"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x133>; | |
| arm,primecell-periphid = <0x3b966>; | |
| reg = <0x6010000 0x1000>; | |
| }; | |
| rpmh-regulator-ldoa8 { | |
| qcom,supported-modes = <0x02 0x04>; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "ldoa8"; | |
| mboxes = <0x8a 0x00>; | |
| qcom,regulator-type = "pmic4-ldo"; | |
| qcom,mode-threshold-currents = <0x00 0x01>; | |
| regulator-l8 { | |
| qcom,init-mode = <0x02>; | |
| phandle = <0x33d>; | |
| qcom,init-voltage = <0x124f80>; | |
| regulator-min-microvolt = <0x124f80>; | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x130b00>; | |
| regulator-name = "pm8998_l8"; | |
| }; | |
| }; | |
| qcom,gpi-dma@0x800000 { | |
| #dma-cells = <0x05>; | |
| compatible = "qcom,gpi-dma"; | |
| qcom,iova-range = <0x00 0x100000 0x00 0x100000>; | |
| reg-names = "gpi-top"; | |
| qcom,smmu-cfg = <0x01>; | |
| status = "ok"; | |
| interrupts = <0x00 0xf4 0x00 0x00 0xf5 0x00 0x00 0xf6 0x00 0x00 0xf7 0x00 0x00 0xf8 0x00 0x00 0xf9 0x00 0x00 0xfa 0x00 0x00 0xfb 0x00 0x00 0xfc 0x00 0x00 0xfd 0x00 0x00 0xfe 0x00 0x00 0xff 0x00 0x00 0x100 0x00>; | |
| qcom,gpii-mask = <0xfa>; | |
| phandle = <0x38>; | |
| qcom,max-num-gpii = <0x0d>; | |
| reg = <0x800000 0x60000>; | |
| iommus = <0x29 0x16 0x00>; | |
| qcom,ev-factor = <0x02>; | |
| }; | |
| spi@89c000 { | |
| compatible = "qcom,spi-geni"; | |
| clocks = <0x22 0x5a 0x22 0x6c 0x22 0x6d>; | |
| qcom,wrapper-core = <0x35>; | |
| reg-names = "se_phys"; | |
| pinctrl-1 = <0x58>; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| status = "disabled"; | |
| #address-cells = <0x01>; | |
| interrupts = <0x00 0x260 0x00>; | |
| #size-cells = <0x00>; | |
| dma-names = "tx\0rx"; | |
| phandle = <0x2da>; | |
| reg = <0x89c000 0x4000>; | |
| pinctrl-0 = <0x57>; | |
| dmas = <0x38 0x00 0x07 0x01 0x40 0x00 0x38 0x01 0x07 0x01 0x40 0x00>; | |
| spi-max-frequency = <0x2faf080>; | |
| pinctrl-names = "default\0sleep"; | |
| }; | |
| cti@7420000 { | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti-cpu4"; | |
| clock-names = "apb_pclk"; | |
| cpu = <0x15>; | |
| phandle = <0x39a>; | |
| arm,primecell-periphid = <0x3b966>; | |
| reg = <0x7420000 0x1000>; | |
| }; | |
| tpdm@6844000 { | |
| qcom,msr-fix-req; | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "tpdm-base"; | |
| coresight-name = "coresight-tpdm-lpass"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x366>; | |
| arm,primecell-periphid = <0x3b968>; | |
| reg = <0x6844000 0x1000>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x15d>; | |
| phandle = <0x15a>; | |
| }; | |
| }; | |
| }; | |
| qcom,mincpubw { | |
| compatible = "qcom,devbw"; | |
| qcom,active-only; | |
| qcom,src-dst-ports = <0x01 0x200>; | |
| governor = "powersave"; | |
| qcom,bw-tbl = <0x2fa 0x478 0x6b8 0x826 0xa25 0xb71 0xf27 0x134f 0x172b 0x1ae1>; | |
| phandle = <0x89>; | |
| }; | |
| qcom,spmi-debug@6b22000 { | |
| compatible = "qcom,spmi-pmic-arb-debug"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "core\0fuse"; | |
| clock-names = "core_clk"; | |
| #address-cells = <0x02>; | |
| #size-cells = <0x00>; | |
| phandle = <0x309>; | |
| qcom,fuse-disable-bit = <0x0c>; | |
| reg = <0x6b22000 0x60 0x7820a8 0x04>; | |
| qcom,pm8998-debug@0 { | |
| compatible = "qcom,spmi-pmic"; | |
| qcom,can-sleep; | |
| #address-cells = <0x02>; | |
| #size-cells = <0x00>; | |
| reg = <0x00 0x00>; | |
| }; | |
| qcom,pmi8998-debug@2 { | |
| compatible = "qcom,spmi-pmic"; | |
| qcom,can-sleep; | |
| #address-cells = <0x02>; | |
| #size-cells = <0x00>; | |
| reg = <0x02 0x00>; | |
| }; | |
| qcom,pm8005-debug@5 { | |
| compatible = "qcom,spmi-pmic"; | |
| qcom,can-sleep; | |
| #address-cells = <0x02>; | |
| #size-cells = <0x00>; | |
| reg = <0x05 0x00>; | |
| }; | |
| qcom,pm8998-debug@1 { | |
| compatible = "qcom,spmi-pmic"; | |
| qcom,can-sleep; | |
| #address-cells = <0x02>; | |
| #size-cells = <0x00>; | |
| reg = <0x01 0x00>; | |
| }; | |
| qcom,pmi8998-debug@3 { | |
| compatible = "qcom,spmi-pmic"; | |
| qcom,can-sleep; | |
| #address-cells = <0x02>; | |
| #size-cells = <0x00>; | |
| reg = <0x03 0x00>; | |
| }; | |
| qcom,pm8005-debug@4 { | |
| compatible = "qcom,spmi-pmic"; | |
| qcom,can-sleep; | |
| #address-cells = <0x02>; | |
| #size-cells = <0x00>; | |
| reg = <0x04 0x00>; | |
| }; | |
| }; | |
| rpmh-regulator-gfxlvl { | |
| compatible = "qcom,rpmh-arc-regulator"; | |
| qcom,resource-name = "gfx.lvl"; | |
| mboxes = <0x8a 0x00>; | |
| regulator-s1-level { | |
| qcom,init-voltage-level = <0x31>; | |
| phandle = <0x1d>; | |
| regulator-min-microvolt = <0x31>; | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x10000>; | |
| regulator-name = "pm8005_s1_level"; | |
| }; | |
| }; | |
| qcom,smp2pgpio_test_smp2p_5_out { | |
| gpios = <0x1b9 0x00 0x00>; | |
| compatible = "qcom,smp2pgpio_test_smp2p_5_out"; | |
| }; | |
| qcom,chd_sliver { | |
| compatible = "qcom,core-hang-detect"; | |
| qcom,threshold-arr = <0x17e00058 0x17e10058 0x17e20058 0x17e30058>; | |
| label = "silver"; | |
| qcom,config-arr = <0x17e00060 0x17e10060 0x17e20060 0x17e30060>; | |
| }; | |
| qcom,cpucc@0x17d41000 { | |
| qcom,mx-turbo-freq = <0x581e9800 0x64b54000 0xc4b20101>; | |
| compatible = "qcom,clk-cpu-osm-v2"; | |
| clocks = <0x21 0x01>; | |
| l3-devs = <0x87 0x88 0x9f 0x9d>; | |
| reg-names = "osm_l3_base\0osm_pwrcl_base\0osm_perfcl_base"; | |
| clock-names = "xo_ao"; | |
| #clock-cells = <0x01>; | |
| phandle = <0x86>; | |
| reg = <0x17d41000 0x1400 0x17d43000 0x1400 0x17d45800 0x1400>; | |
| vdd_l3_mx_ao-supply = <0x9e>; | |
| vdd_pwrcl_mx_ao-supply = <0x9e>; | |
| qcom,limits-dcvs@0 { | |
| compatible = "qcom,msm-hw-limits"; | |
| #thermal-sensor-cells = <0x00>; | |
| interrupts = <0x00 0x20 0x04>; | |
| phandle = <0x02>; | |
| qcom,affinity = <0x00>; | |
| }; | |
| qcom,wil6210 { | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| qcom,keep-radio-on-during-sleep; | |
| clocks = <0x21 0x0a 0x21 0x0b>; | |
| qcom,use-ext-clocks; | |
| qcom,msm-bus,vectors-KBps = <0x2d 0x200 0x00 0x00 0x2d 0x200 0x927c0 0xc3500>; | |
| qcom,use-ext-supply; | |
| clock-names = "rf_clk3_clk\0rf_clk3_pin_clk"; | |
| vddio-supply = <0xa3>; | |
| qcom,smmu-s1-en; | |
| qcom,msm-bus,name = "wil6210"; | |
| status = "disabled"; | |
| phandle = <0x314>; | |
| qcom,smmu-mapping = <0x20000000 0xe0000000>; | |
| qcom,smmu-support; | |
| vdd-supply = <0xa2>; | |
| qcom,pcie-parent = <0xa1>; | |
| qcom,wigig-en = <0x34 0x27 0x00>; | |
| qcom,smmu-coherent; | |
| qcom,smmu-fast-map; | |
| }; | |
| qcom,limits-dcvs@1 { | |
| compatible = "qcom,msm-hw-limits"; | |
| #thermal-sensor-cells = <0x00>; | |
| isens_vref-supply = <0xa0>; | |
| interrupts = <0x00 0x21 0x04>; | |
| phandle = <0x0a>; | |
| qcom,affinity = <0x01>; | |
| isens-vref-settings = <0xd6d80 0xd6d80 0x4e20>; | |
| }; | |
| }; | |
| qcom,mdss_dsi_phy0@ae96400 { | |
| compatible = "qcom,dsi-phy-v3.0"; | |
| reg-names = "dsi_phy"; | |
| qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; | |
| qcom,platform-strength-ctrl = [55 03 55 03 55 03 55 03 55 00]; | |
| gdsc-supply = <0x19>; | |
| label = "dsi-phy-1"; | |
| phandle = <0x2c6>; | |
| reg = <0xae96400 0x7c0>; | |
| vdda-0p9-supply = <0x2f>; | |
| cell-index = <0x01>; | |
| qcom,platform-lane-config = <0x00 0x00 0x00 0x00 0x80>; | |
| qcom,phy-supply-entries { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| qcom,phy-supply-entry@0 { | |
| qcom,supply-name = "vdda-0p9"; | |
| qcom,supply-disable-load = <0x20>; | |
| qcom,supply-max-voltage = <0xd6d80>; | |
| qcom,supply-enable-load = <0x8ca0>; | |
| qcom,supply-min-voltage = <0xd6d80>; | |
| reg = <0x00>; | |
| }; | |
| }; | |
| }; | |
| qcom,cam-fd { | |
| compatible = "qcom,cam-fd"; | |
| compat-hw-name = "qcom,fd"; | |
| status = "ok"; | |
| num-fd = <0x01>; | |
| }; | |
| qcom,smp2p-modem@1799000c { | |
| compatible = "qcom,smp2p"; | |
| interrupts = <0x00 0x1c3 0x01>; | |
| reg = <0x1799000c 0x04>; | |
| qcom,remote-pid = <0x01>; | |
| qcom,irq-bitmask = <0x4000>; | |
| }; | |
| qcom,gdsc@0x175004 { | |
| compatible = "qcom,gdsc"; | |
| status = "ok"; | |
| phandle = <0x2bb>; | |
| reg = <0x175004 0x04>; | |
| regulator-name = "ufs_card_gdsc"; | |
| qcom,poll-cfg-gdscr; | |
| }; | |
| rpmh-regulator-ldoa24 { | |
| qcom,supported-modes = <0x02 0x04>; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| pm8998_l24-parent-supply = <0x121>; | |
| qcom,resource-name = "ldoa24"; | |
| mboxes = <0x8a 0x00>; | |
| qcom,regulator-type = "pmic4-ldo"; | |
| qcom,mode-threshold-currents = <0x00 0x2710>; | |
| regulator-l24 { | |
| qcom,init-mode = <0x02>; | |
| phandle = <0xba>; | |
| qcom,init-voltage = <0x2f1e80>; | |
| regulator-min-microvolt = <0x2f1e80>; | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x2f1e80>; | |
| regulator-name = "pm8998_l24"; | |
| }; | |
| }; | |
| qcom,gdsc@0xad07004 { | |
| compatible = "qcom,gdsc"; | |
| qcom,support-hw-trigger; | |
| status = "ok"; | |
| phandle = <0x1c3>; | |
| reg = <0xad07004 0x04>; | |
| regulator-name = "ipe_0_gdsc"; | |
| qcom,poll-cfg-gdscr; | |
| }; | |
| can_clock { | |
| compatible = "fixed-clock"; | |
| #clock-cells = <0x00>; | |
| phandle = <0x316>; | |
| clock-frequency = <0x2625a00>; | |
| }; | |
| tsens@c222000 { | |
| compatible = "qcom,sdm845-tsens"; | |
| reg-names = "tsens_srot_physical\0tsens_tm_physical"; | |
| #thermal-sensor-cells = <0x01>; | |
| interrupts = <0x00 0x1fa 0x00 0x00 0x1fc 0x00>; | |
| phandle = <0xef>; | |
| reg = <0xc222000 0x04 0xc263000 0x1ff>; | |
| interrupt-names = "tsens-upper-lower\0tsens-critical"; | |
| }; | |
| qcom,avtimer@170f7000 { | |
| compatible = "qcom,avtimer"; | |
| qcom,clk-mult = <0x0a>; | |
| reg-names = "avtimer_lsb_addr\0avtimer_msb_addr"; | |
| qcom,clk-div = <0xc0>; | |
| reg = <0x170f700c 0x04 0x170f7010 0x04>; | |
| }; | |
| etm@7740000 { | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| coresight-name = "coresight-etm7"; | |
| clock-names = "apb_pclk"; | |
| cpu = <0x18>; | |
| phandle = <0x3a9>; | |
| arm,primecell-periphid = <0xbb95d>; | |
| reg = <0x7740000 0x1000>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x199>; | |
| phandle = <0x1a2>; | |
| }; | |
| }; | |
| }; | |
| qcom,msm-dai-tdm-pri-tx { | |
| compatible = "qcom,msm-dai-tdm"; | |
| qcom,msm-cpudai-tdm-group-port-id = <0x9001>; | |
| qcom,msm-cpudai-tdm-clk-internal = <0x01>; | |
| qcom,msm-cpudai-tdm-sync-mode = <0x01>; | |
| qcom,msm-cpudai-tdm-clk-rate = <0x177000>; | |
| qcom,msm-cpudai-tdm-data-out = <0x00>; | |
| qcom,msm-cpudai-tdm-data-delay = <0x01>; | |
| qcom,msm-cpudai-tdm-group-id = <0x9101>; | |
| qcom,msm-cpudai-tdm-invert-sync = <0x01>; | |
| qcom,msm-cpudai-tdm-group-num-ports = <0x01>; | |
| qcom,msm-cpudai-tdm-sync-src = <0x01>; | |
| qcom,msm-dai-q6-tdm-pri-tx-0 { | |
| compatible = "qcom,msm-dai-q6-tdm"; | |
| qcom,msm-cpudai-tdm-dev-id = <0x9001>; | |
| phandle = <0x2a3>; | |
| qcom,msm-cpudai-tdm-data-align = <0x00>; | |
| }; | |
| }; | |
| qcom,smp2pgpio-wlan-1-in { | |
| compatible = "qcom,smp2pgpio"; | |
| gpio-controller; | |
| #interrupt-cells = <0x02>; | |
| phandle = <0xea>; | |
| qcom,entry-name = "wlan"; | |
| #gpio-cells = <0x02>; | |
| qcom,is-inbound; | |
| qcom,remote-pid = <0x01>; | |
| interrupt-controller; | |
| }; | |
| qcom,dsi-display@15 { | |
| compatible = "qcom,dsi-display"; | |
| clocks = <0x2bc 0x06 0x2bc 0x09>; | |
| lab-supply = <0x4e2>; | |
| pinctrl-1 = <0x41c 0x41e>; | |
| clock-names = "mux_byte_clk\0mux_pixel_clk"; | |
| vddio-supply = <0x120>; | |
| qcom,dsi-panel = <0x4f2>; | |
| label = "dsi_dual_nt35597_cmd_display"; | |
| ibb-supply = <0x4e3>; | |
| phandle = <0x54f>; | |
| qcom,dsi-ctrl = <0x2c3 0x2c4>; | |
| qcom,display-type = "primary"; | |
| qcom,panel-mode-gpio = <0x34 0x34 0x00>; | |
| pinctrl-0 = <0x41b 0x41d>; | |
| qcom,platform-te-gpio = <0x34 0x0a 0x00>; | |
| qcom,dsi-phy = <0x2c5 0x2c6>; | |
| qcom,platform-reset-gpio = <0x34 0x06 0x00>; | |
| pinctrl-names = "panel_active\0panel_suspend"; | |
| }; | |
| qcom,snoc_cnoc_keepalive { | |
| compatible = "qcom,devbw"; | |
| qcom,active-only; | |
| qcom,src-dst-ports = <0x8b 0x273>; | |
| governor = "powersave"; | |
| qcom,bw-tbl = <0x01>; | |
| status = "ok"; | |
| phandle = <0x30c>; | |
| }; | |
| qcom,dsi-display@6 { | |
| compatible = "qcom,dsi-display"; | |
| clocks = <0x2bd 0x18 0x2bd 0x1b>; | |
| lab-supply = <0x4e2>; | |
| pinctrl-1 = <0x41c 0x41e>; | |
| clock-names = "mux_byte_clk\0mux_pixel_clk"; | |
| vddio-supply = <0x120>; | |
| qcom,dsi-panel = <0x4e9>; | |
| label = "dsi_nt35597_truly_dsc_cmd_display"; | |
| ibb-supply = <0x4e3>; | |
| phandle = <0x546>; | |
| qcom,dsi-ctrl = <0x2c4>; | |
| qcom,display-type = "primary"; | |
| qcom,panel-mode-gpio = <0x34 0x34 0x00>; | |
| pinctrl-0 = <0x41b 0x41d>; | |
| qcom,platform-te-gpio = <0x34 0x0a 0x00>; | |
| qcom,dsi-phy = <0x2c6>; | |
| qcom,platform-reset-gpio = <0x34 0x06 0x00>; | |
| pinctrl-names = "panel_active\0panel_suspend"; | |
| }; | |
| rpmh-regulator-ldoa14 { | |
| qcom,supported-modes = <0x02 0x04>; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "ldoa14"; | |
| proxy-supply = <0x120>; | |
| mboxes = <0x8a 0x00>; | |
| qcom,regulator-type = "pmic4-ldo"; | |
| qcom,mode-threshold-currents = <0x00 0x2710>; | |
| regulator-l14 { | |
| qcom,proxy-consumer-enable; | |
| qcom,init-mode = <0x02>; | |
| phandle = <0x120>; | |
| qcom,init-voltage = <0x1c3a90>; | |
| regulator-min-microvolt = <0x1c3a90>; | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x1cafc0>; | |
| regulator-name = "pm8998_l14"; | |
| qcom,proxy-consumer-current = <0x1c138>; | |
| }; | |
| }; | |
| jtagmm@7540000 { | |
| compatible = "qcom,jtagv8-mm"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "etm-base"; | |
| clock-names = "core_clk"; | |
| phandle = <0x2f3>; | |
| reg = <0x7540000 0x1000>; | |
| qcom,coresight-jtagmm-cpu = <0x16>; | |
| }; | |
| qcom,qmp-aop@c300000 { | |
| compatible = "qcom,qmp-mbox"; | |
| reg-names = "msgram\0irq-reg-base"; | |
| mbox-desc-offset = <0x00>; | |
| #mbox-cells = <0x01>; | |
| interrupts = <0x00 0x185 0x01>; | |
| label = "aop"; | |
| qcom,irq-mask = <0x01>; | |
| phandle = <0x80>; | |
| reg = <0xc300000 0x100000 0x1799000c 0x04>; | |
| priority = <0x00>; | |
| }; | |
| thermal-zones { | |
| phandle = <0x333>; | |
| cpu0-silver-usr { | |
| thermal-sensors = <0xef 0x01>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-governor = "user_space"; | |
| wake-capable-sensor; | |
| trips { | |
| active-config0 { | |
| hysteresis = <0x3e8>; | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| compute-hvx-usr { | |
| thermal-sensors = <0xf0 0x04>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-governor = "user_space"; | |
| wake-capable-sensor; | |
| trips { | |
| active-config0 { | |
| hysteresis = <0x3e8>; | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| cpu1-gold-usr { | |
| thermal-sensors = <0xef 0x08>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-governor = "user_space"; | |
| wake-capable-sensor; | |
| trips { | |
| active-config0 { | |
| hysteresis = <0x3e8>; | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| cpu1-silver-step { | |
| thermal-sensors = <0xef 0x02>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x64>; | |
| thermal-governor = "step_wise"; | |
| wake-capable-sensor; | |
| trips { | |
| emerg-config1 { | |
| hysteresis = <0x2710>; | |
| temperature = <0x1adb0>; | |
| type = "passive"; | |
| phandle = <0xf4>; | |
| }; | |
| }; | |
| cooling-maps { | |
| emerg_cdev1 { | |
| trip = <0xf4>; | |
| cooling-device = <0x12 0xfffffffe 0xfffffffe>; | |
| }; | |
| }; | |
| }; | |
| pm8998_tz { | |
| thermal-sensors = <0xfb>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| phandle = <0x334>; | |
| thermal-governor = "step_wise"; | |
| wake-capable-sensor; | |
| trips { | |
| pm8998-trip1 { | |
| hysteresis = <0x00>; | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| phandle = <0xfd>; | |
| }; | |
| pm8998-trip2 { | |
| hysteresis = <0x00>; | |
| temperature = <0x23668>; | |
| type = "passive"; | |
| phandle = <0x335>; | |
| }; | |
| pm8998-trip0 { | |
| hysteresis = <0x00>; | |
| temperature = <0x19a28>; | |
| type = "passive"; | |
| phandle = <0xfc>; | |
| }; | |
| }; | |
| cooling-maps { | |
| trip0_cpu5 { | |
| trip = <0xfc>; | |
| cooling-device = <0x16 0xfffffffd 0xfffffffd>; | |
| }; | |
| trip1_cpu1 { | |
| trip = <0xfd>; | |
| cooling-device = <0x12 0xfffffffe 0xfffffffe>; | |
| }; | |
| trip0_cpu3 { | |
| trip = <0xfc>; | |
| cooling-device = <0x14 0xfffffffd 0xfffffffd>; | |
| }; | |
| trip0_cpu1 { | |
| trip = <0xfc>; | |
| cooling-device = <0x12 0xfffffffd 0xfffffffd>; | |
| }; | |
| trip1_cpu6 { | |
| trip = <0xfd>; | |
| cooling-device = <0x17 0xfffffffe 0xfffffffe>; | |
| }; | |
| trip1_cpu4 { | |
| trip = <0xfd>; | |
| cooling-device = <0x15 0xfffffffe 0xfffffffe>; | |
| }; | |
| trip0_cpu6 { | |
| trip = <0xfc>; | |
| cooling-device = <0x17 0xfffffffd 0xfffffffd>; | |
| }; | |
| trip1_cpu2 { | |
| trip = <0xfd>; | |
| cooling-device = <0x13 0xfffffffe 0xfffffffe>; | |
| }; | |
| trip0_cpu4 { | |
| trip = <0xfc>; | |
| cooling-device = <0x15 0xfffffffd 0xfffffffd>; | |
| }; | |
| trip0_cpu2 { | |
| trip = <0xfc>; | |
| cooling-device = <0x13 0xfffffffd 0xfffffffd>; | |
| }; | |
| trip0_cpu0 { | |
| trip = <0xfc>; | |
| cooling-device = <0x11 0xfffffffd 0xfffffffd>; | |
| }; | |
| trip1_cpu7 { | |
| trip = <0xfd>; | |
| cooling-device = <0x18 0xfffffffe 0xfffffffe>; | |
| }; | |
| trip1_cpu5 { | |
| trip = <0xfd>; | |
| cooling-device = <0x16 0xfffffffe 0xfffffffe>; | |
| }; | |
| trip0_cpu7 { | |
| trip = <0xfc>; | |
| cooling-device = <0x18 0xfffffffd 0xfffffffd>; | |
| }; | |
| trip1_cpu3 { | |
| trip = <0xfd>; | |
| cooling-device = <0x14 0xfffffffe 0xfffffffe>; | |
| }; | |
| }; | |
| }; | |
| cpu3-gold-step { | |
| thermal-sensors = <0xef 0x0a>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x64>; | |
| thermal-governor = "step_wise"; | |
| wake-capable-sensor; | |
| trips { | |
| emerg-config7 { | |
| hysteresis = <0x2710>; | |
| temperature = <0x1adb0>; | |
| type = "passive"; | |
| phandle = <0xfa>; | |
| }; | |
| }; | |
| cooling-maps { | |
| emerg_cdev7 { | |
| trip = <0xfa>; | |
| cooling-device = <0x18 0xfffffffe 0xfffffffe>; | |
| }; | |
| }; | |
| }; | |
| kryo-l3-1-lowf { | |
| thermal-sensors = <0xef 0x06>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-governor = "low_limits_floor"; | |
| tracks-low; | |
| wake-capable-sensor; | |
| trips { | |
| l3-1-trip { | |
| hysteresis = <0x1388>; | |
| temperature = <0x1388>; | |
| type = "passive"; | |
| phandle = <0x10c>; | |
| }; | |
| }; | |
| cooling-maps { | |
| cx_vdd_cdev { | |
| trip = <0x10c>; | |
| cooling-device = <0x100 0x00 0x00>; | |
| }; | |
| cpu4_vdd_cdev { | |
| trip = <0x10c>; | |
| cooling-device = <0x15 0x09 0x09>; | |
| }; | |
| adsp_vdd_cdev { | |
| trip = <0x10c>; | |
| cooling-device = <0x104 0x00 0x00>; | |
| }; | |
| modem_vdd_cdev { | |
| trip = <0x10c>; | |
| cooling-device = <0x103 0x00 0x00>; | |
| }; | |
| ebi_vdd_cdev { | |
| trip = <0x10c>; | |
| cooling-device = <0x102 0x00 0x00>; | |
| }; | |
| slpi_vdd_cdev { | |
| trip = <0x10c>; | |
| cooling-device = <0x106 0x00 0x00>; | |
| }; | |
| gpu_vdd_cdev { | |
| trip = <0x10c>; | |
| cooling-device = <0x9d 0x01 0x01>; | |
| }; | |
| cdsp_vdd_cdev { | |
| trip = <0x10c>; | |
| cooling-device = <0x105 0x00 0x00>; | |
| }; | |
| mx_vdd_cdev { | |
| trip = <0x10c>; | |
| cooling-device = <0x101 0x00 0x00>; | |
| }; | |
| cpu0_vdd_cdev { | |
| trip = <0x10c>; | |
| cooling-device = <0x11 0x04 0x04>; | |
| }; | |
| }; | |
| }; | |
| cpu2-gold-lowf { | |
| thermal-sensors = <0xef 0x09>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-governor = "low_limits_floor"; | |
| tracks-low; | |
| wake-capable-sensor; | |
| trips { | |
| cpug2-trip { | |
| hysteresis = <0x1388>; | |
| temperature = <0x1388>; | |
| type = "passive"; | |
| phandle = <0x10f>; | |
| }; | |
| }; | |
| cooling-maps { | |
| cx_vdd_cdev { | |
| trip = <0x10f>; | |
| cooling-device = <0x100 0x00 0x00>; | |
| }; | |
| cpu4_vdd_cdev { | |
| trip = <0x10f>; | |
| cooling-device = <0x15 0x09 0x09>; | |
| }; | |
| adsp_vdd_cdev { | |
| trip = <0x10f>; | |
| cooling-device = <0x104 0x00 0x00>; | |
| }; | |
| modem_vdd_cdev { | |
| trip = <0x10f>; | |
| cooling-device = <0x103 0x00 0x00>; | |
| }; | |
| ebi_vdd_cdev { | |
| trip = <0x10f>; | |
| cooling-device = <0x102 0x00 0x00>; | |
| }; | |
| slpi_vdd_cdev { | |
| trip = <0x10f>; | |
| cooling-device = <0x106 0x00 0x00>; | |
| }; | |
| gpu_vdd_cdev { | |
| trip = <0x10f>; | |
| cooling-device = <0x9d 0x01 0x01>; | |
| }; | |
| cdsp_vdd_cdev { | |
| trip = <0x10f>; | |
| cooling-device = <0x105 0x00 0x00>; | |
| }; | |
| mx_vdd_cdev { | |
| trip = <0x10f>; | |
| cooling-device = <0x101 0x00 0x00>; | |
| }; | |
| cpu0_vdd_cdev { | |
| trip = <0x10f>; | |
| cooling-device = <0x11 0x04 0x04>; | |
| }; | |
| }; | |
| }; | |
| mdm-core-lowf { | |
| thermal-sensors = <0xf0 0x07>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-governor = "low_limits_floor"; | |
| tracks-low; | |
| wake-capable-sensor; | |
| trips { | |
| mdm-trip { | |
| hysteresis = <0x1388>; | |
| temperature = <0x1388>; | |
| type = "passive"; | |
| phandle = <0x11a>; | |
| }; | |
| }; | |
| cooling-maps { | |
| cx_vdd_cdev { | |
| trip = <0x11a>; | |
| cooling-device = <0x100 0x00 0x00>; | |
| }; | |
| cpu4_vdd_cdev { | |
| trip = <0x11a>; | |
| cooling-device = <0x15 0x09 0x09>; | |
| }; | |
| adsp_vdd_cdev { | |
| trip = <0x11a>; | |
| cooling-device = <0x104 0x00 0x00>; | |
| }; | |
| modem_vdd_cdev { | |
| trip = <0x11a>; | |
| cooling-device = <0x103 0x00 0x00>; | |
| }; | |
| ebi_vdd_cdev { | |
| trip = <0x11a>; | |
| cooling-device = <0x102 0x00 0x00>; | |
| }; | |
| slpi_vdd_cdev { | |
| trip = <0x11a>; | |
| cooling-device = <0x106 0x00 0x00>; | |
| }; | |
| gpu_vdd_cdev { | |
| trip = <0x11a>; | |
| cooling-device = <0x9d 0x01 0x01>; | |
| }; | |
| cdsp_vdd_cdev { | |
| trip = <0x11a>; | |
| cooling-device = <0x105 0x00 0x00>; | |
| }; | |
| mx_vdd_cdev { | |
| trip = <0x11a>; | |
| cooling-device = <0x101 0x00 0x00>; | |
| }; | |
| cpu0_vdd_cdev { | |
| trip = <0x11a>; | |
| cooling-device = <0x11 0x04 0x04>; | |
| }; | |
| }; | |
| }; | |
| aoss0-lowf { | |
| thermal-sensors = <0xef 0x00>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-governor = "low_limits_floor"; | |
| tracks-low; | |
| wake-capable-sensor; | |
| trips { | |
| aoss0-trip { | |
| hysteresis = <0x1388>; | |
| temperature = <0x1388>; | |
| type = "passive"; | |
| phandle = <0xff>; | |
| }; | |
| }; | |
| cooling-maps { | |
| cx_vdd_cdev { | |
| trip = <0xff>; | |
| cooling-device = <0x100 0x00 0x00>; | |
| }; | |
| cpu4_vdd_cdev { | |
| trip = <0xff>; | |
| cooling-device = <0x15 0x09 0x09>; | |
| }; | |
| adsp_vdd_cdev { | |
| trip = <0xff>; | |
| cooling-device = <0x104 0x00 0x00>; | |
| }; | |
| modem_vdd_cdev { | |
| trip = <0xff>; | |
| cooling-device = <0x103 0x00 0x00>; | |
| }; | |
| ebi_vdd_cdev { | |
| trip = <0xff>; | |
| cooling-device = <0x102 0x00 0x00>; | |
| }; | |
| slpi_vdd_cdev { | |
| trip = <0xff>; | |
| cooling-device = <0x106 0x00 0x00>; | |
| }; | |
| gpu_vdd_cdev { | |
| trip = <0xff>; | |
| cooling-device = <0x9d 0x01 0x01>; | |
| }; | |
| cdsp_vdd_cdev { | |
| trip = <0xff>; | |
| cooling-device = <0x105 0x00 0x00>; | |
| }; | |
| mx_vdd_cdev { | |
| trip = <0xff>; | |
| cooling-device = <0x101 0x00 0x00>; | |
| }; | |
| cpu0_vdd_cdev { | |
| trip = <0xff>; | |
| cooling-device = <0x11 0x04 0x04>; | |
| }; | |
| }; | |
| }; | |
| pm8005_tz { | |
| thermal-sensors = <0xfe>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| trips { | |
| pm8005-trip2 { | |
| hysteresis = <0x00>; | |
| temperature = <0x23668>; | |
| type = "passive"; | |
| }; | |
| pm8005-trip0 { | |
| hysteresis = <0x00>; | |
| temperature = <0x19a28>; | |
| type = "passive"; | |
| }; | |
| pm8005-trip1 { | |
| hysteresis = <0x00>; | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| gpu1-usr { | |
| thermal-sensors = <0xef 0x0c>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-governor = "user_space"; | |
| wake-capable-sensor; | |
| trips { | |
| active-config0 { | |
| hysteresis = <0x3e8>; | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| pop-mem-step { | |
| thermal-sensors = <0xf0 0x02>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x0a>; | |
| thermal-governor = "step_wise"; | |
| wake-capable-sensor; | |
| trips { | |
| pop-trip { | |
| hysteresis = <0x00>; | |
| temperature = <0x17318>; | |
| type = "passive"; | |
| phandle = <0xf2>; | |
| }; | |
| }; | |
| cooling-maps { | |
| pop_cdev5 { | |
| trip = <0xf2>; | |
| cooling-device = <0x16 0xffffffff 0xfffffffd>; | |
| }; | |
| pop_cdev6 { | |
| trip = <0xf2>; | |
| cooling-device = <0x17 0xffffffff 0xfffffffd>; | |
| }; | |
| pop_cdev4 { | |
| trip = <0xf2>; | |
| cooling-device = <0x15 0xffffffff 0xfffffffd>; | |
| }; | |
| pop_cdev7 { | |
| trip = <0xf2>; | |
| cooling-device = <0x18 0xffffffff 0xfffffffd>; | |
| }; | |
| }; | |
| }; | |
| xo-therm-adc { | |
| thermal-sensors = <0x303 0x4c>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-governor = "user_space"; | |
| wake-capable-sensor; | |
| trips { | |
| active-config0 { | |
| hysteresis = <0x2710>; | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| vbat_too_low { | |
| thermal-sensors = <0x505 0x04>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-governor = "low_limits_cap"; | |
| tracks-low; | |
| wake-capable-sensor; | |
| trips { | |
| low-vbat { | |
| hysteresis = <0x00>; | |
| temperature = <0xa28>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| vbat { | |
| thermal-sensors = <0x505 0x02>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x64>; | |
| thermal-governor = "low_limits_cap"; | |
| tracks-low; | |
| wake-capable-sensor; | |
| trips { | |
| low-vbat { | |
| hysteresis = <0x64>; | |
| temperature = <0xc80>; | |
| type = "passive"; | |
| phandle = <0x506>; | |
| }; | |
| }; | |
| cooling-maps { | |
| vbat_map7 { | |
| trip = <0x506>; | |
| cooling-device = <0x18 0xfffffffe 0xfffffffe>; | |
| }; | |
| vbat_cpu4 { | |
| trip = <0x506>; | |
| cooling-device = <0x15 0xfffffffe 0xfffffffe>; | |
| }; | |
| vbat_map6 { | |
| trip = <0x506>; | |
| cooling-device = <0x17 0xfffffffe 0xfffffffe>; | |
| }; | |
| vbat_cpu5 { | |
| trip = <0x506>; | |
| cooling-device = <0x16 0xfffffffe 0xfffffffe>; | |
| }; | |
| }; | |
| }; | |
| kryo-l3-1-usr { | |
| thermal-sensors = <0xef 0x06>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-governor = "user_space"; | |
| wake-capable-sensor; | |
| trips { | |
| active-config0 { | |
| hysteresis = <0x3e8>; | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| mdm-core-usr { | |
| thermal-sensors = <0xf0 0x07>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-governor = "user_space"; | |
| wake-capable-sensor; | |
| trips { | |
| active-config0 { | |
| hysteresis = <0x3e8>; | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| pa-therm1-adc { | |
| thermal-sensors = <0x303 0x4f>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-governor = "user_space"; | |
| wake-capable-sensor; | |
| trips { | |
| active-config0 { | |
| hysteresis = <0x2710>; | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| gpu-virt-max-step { | |
| polling-delay = <0x64>; | |
| polling-delay-passive = <0x0a>; | |
| thermal-governor = "step_wise"; | |
| wake-capable-sensor; | |
| trips { | |
| gpu-trip0 { | |
| hysteresis = <0x00>; | |
| temperature = <0x17318>; | |
| type = "passive"; | |
| phandle = <0xf1>; | |
| }; | |
| }; | |
| cooling-maps { | |
| gpu_cdev0 { | |
| trip = <0xf1>; | |
| cooling-device = <0x9d 0x00 0xffffffff>; | |
| }; | |
| }; | |
| }; | |
| cpu1-silver-usr { | |
| thermal-sensors = <0xef 0x02>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-governor = "user_space"; | |
| wake-capable-sensor; | |
| trips { | |
| active-config0 { | |
| hysteresis = <0x3e8>; | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| kryo-l3-0-lowf { | |
| thermal-sensors = <0xef 0x05>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-governor = "low_limits_floor"; | |
| tracks-low; | |
| wake-capable-sensor; | |
| trips { | |
| l3-0-trip { | |
| hysteresis = <0x1388>; | |
| temperature = <0x1388>; | |
| type = "passive"; | |
| phandle = <0x10b>; | |
| }; | |
| }; | |
| cooling-maps { | |
| cx_vdd_cdev { | |
| trip = <0x10b>; | |
| cooling-device = <0x100 0x00 0x00>; | |
| }; | |
| cpu4_vdd_cdev { | |
| trip = <0x10b>; | |
| cooling-device = <0x15 0x09 0x09>; | |
| }; | |
| adsp_vdd_cdev { | |
| trip = <0x10b>; | |
| cooling-device = <0x104 0x00 0x00>; | |
| }; | |
| modem_vdd_cdev { | |
| trip = <0x10b>; | |
| cooling-device = <0x103 0x00 0x00>; | |
| }; | |
| ebi_vdd_cdev { | |
| trip = <0x10b>; | |
| cooling-device = <0x102 0x00 0x00>; | |
| }; | |
| slpi_vdd_cdev { | |
| trip = <0x10b>; | |
| cooling-device = <0x106 0x00 0x00>; | |
| }; | |
| gpu_vdd_cdev { | |
| trip = <0x10b>; | |
| cooling-device = <0x9d 0x01 0x01>; | |
| }; | |
| cdsp_vdd_cdev { | |
| trip = <0x10b>; | |
| cooling-device = <0x105 0x00 0x00>; | |
| }; | |
| mx_vdd_cdev { | |
| trip = <0x10b>; | |
| cooling-device = <0x101 0x00 0x00>; | |
| }; | |
| cpu0_vdd_cdev { | |
| trip = <0x10b>; | |
| cooling-device = <0x11 0x04 0x04>; | |
| }; | |
| }; | |
| }; | |
| cpu0-silver-lowf { | |
| thermal-sensors = <0xef 0x01>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-governor = "low_limits_floor"; | |
| tracks-low; | |
| wake-capable-sensor; | |
| trips { | |
| cpu0-trip { | |
| hysteresis = <0x1388>; | |
| temperature = <0x1388>; | |
| type = "passive"; | |
| phandle = <0x107>; | |
| }; | |
| }; | |
| cooling-maps { | |
| cx_vdd_cdev { | |
| trip = <0x107>; | |
| cooling-device = <0x100 0x00 0x00>; | |
| }; | |
| cpu4_vdd_cdev { | |
| trip = <0x107>; | |
| cooling-device = <0x15 0x09 0x09>; | |
| }; | |
| adsp_vdd_cdev { | |
| trip = <0x107>; | |
| cooling-device = <0x104 0x00 0x00>; | |
| }; | |
| modem_vdd_cdev { | |
| trip = <0x107>; | |
| cooling-device = <0x103 0x00 0x00>; | |
| }; | |
| ebi_vdd_cdev { | |
| trip = <0x107>; | |
| cooling-device = <0x102 0x00 0x00>; | |
| }; | |
| slpi_vdd_cdev { | |
| trip = <0x107>; | |
| cooling-device = <0x106 0x00 0x00>; | |
| }; | |
| gpu_vdd_cdev { | |
| trip = <0x107>; | |
| cooling-device = <0x9d 0x01 0x01>; | |
| }; | |
| cdsp_vdd_cdev { | |
| trip = <0x107>; | |
| cooling-device = <0x105 0x00 0x00>; | |
| }; | |
| mx_vdd_cdev { | |
| trip = <0x107>; | |
| cooling-device = <0x101 0x00 0x00>; | |
| }; | |
| cpu0_vdd_cdev { | |
| trip = <0x107>; | |
| cooling-device = <0x11 0x04 0x04>; | |
| }; | |
| }; | |
| }; | |
| silv-virt-max-step { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-governor = "step_wise"; | |
| wake-capable-sensor; | |
| trips { | |
| silver-trip { | |
| hysteresis = <0x00>; | |
| temperature = <0x1d4c0>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| cpu2-silver-step { | |
| thermal-sensors = <0xef 0x03>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x64>; | |
| thermal-governor = "step_wise"; | |
| wake-capable-sensor; | |
| trips { | |
| emerg-config2 { | |
| hysteresis = <0x2710>; | |
| temperature = <0x1adb0>; | |
| type = "passive"; | |
| phandle = <0xf5>; | |
| }; | |
| }; | |
| cooling-maps { | |
| emerg_cdev2 { | |
| trip = <0xf5>; | |
| cooling-device = <0x13 0xfffffffe 0xfffffffe>; | |
| }; | |
| }; | |
| }; | |
| cpu1-gold-step { | |
| thermal-sensors = <0xef 0x08>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x64>; | |
| thermal-governor = "step_wise"; | |
| wake-capable-sensor; | |
| trips { | |
| emerg-config5 { | |
| hysteresis = <0x2710>; | |
| temperature = <0x1adb0>; | |
| type = "passive"; | |
| phandle = <0xf8>; | |
| }; | |
| }; | |
| cooling-maps { | |
| emerg_cdev5 { | |
| trip = <0xf8>; | |
| cooling-device = <0x16 0xfffffffe 0xfffffffe>; | |
| }; | |
| }; | |
| }; | |
| cpu0-gold-lowf { | |
| thermal-sensors = <0xef 0x07>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-governor = "low_limits_floor"; | |
| tracks-low; | |
| wake-capable-sensor; | |
| trips { | |
| cpug0-trip { | |
| hysteresis = <0x1388>; | |
| temperature = <0x1388>; | |
| type = "passive"; | |
| phandle = <0x10d>; | |
| }; | |
| }; | |
| cooling-maps { | |
| cx_vdd_cdev { | |
| trip = <0x10d>; | |
| cooling-device = <0x100 0x00 0x00>; | |
| }; | |
| cpu4_vdd_cdev { | |
| trip = <0x10d>; | |
| cooling-device = <0x15 0x09 0x09>; | |
| }; | |
| adsp_vdd_cdev { | |
| trip = <0x10d>; | |
| cooling-device = <0x104 0x00 0x00>; | |
| }; | |
| modem_vdd_cdev { | |
| trip = <0x10d>; | |
| cooling-device = <0x103 0x00 0x00>; | |
| }; | |
| ebi_vdd_cdev { | |
| trip = <0x10d>; | |
| cooling-device = <0x102 0x00 0x00>; | |
| }; | |
| slpi_vdd_cdev { | |
| trip = <0x10d>; | |
| cooling-device = <0x106 0x00 0x00>; | |
| }; | |
| gpu_vdd_cdev { | |
| trip = <0x10d>; | |
| cooling-device = <0x9d 0x01 0x01>; | |
| }; | |
| cdsp_vdd_cdev { | |
| trip = <0x10d>; | |
| cooling-device = <0x105 0x00 0x00>; | |
| }; | |
| mx_vdd_cdev { | |
| trip = <0x10d>; | |
| cooling-device = <0x101 0x00 0x00>; | |
| }; | |
| cpu0_vdd_cdev { | |
| trip = <0x10d>; | |
| cooling-device = <0x11 0x04 0x04>; | |
| }; | |
| }; | |
| }; | |
| mmss-lowf { | |
| thermal-sensors = <0xf0 0x06>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-governor = "low_limits_floor"; | |
| tracks-low; | |
| wake-capable-sensor; | |
| trips { | |
| mmss-trip { | |
| hysteresis = <0x1388>; | |
| temperature = <0x1388>; | |
| type = "passive"; | |
| phandle = <0x119>; | |
| }; | |
| }; | |
| cooling-maps { | |
| cx_vdd_cdev { | |
| trip = <0x119>; | |
| cooling-device = <0x100 0x00 0x00>; | |
| }; | |
| cpu4_vdd_cdev { | |
| trip = <0x119>; | |
| cooling-device = <0x15 0x09 0x09>; | |
| }; | |
| adsp_vdd_cdev { | |
| trip = <0x119>; | |
| cooling-device = <0x104 0x00 0x00>; | |
| }; | |
| modem_vdd_cdev { | |
| trip = <0x119>; | |
| cooling-device = <0x103 0x00 0x00>; | |
| }; | |
| ebi_vdd_cdev { | |
| trip = <0x119>; | |
| cooling-device = <0x102 0x00 0x00>; | |
| }; | |
| slpi_vdd_cdev { | |
| trip = <0x119>; | |
| cooling-device = <0x106 0x00 0x00>; | |
| }; | |
| gpu_vdd_cdev { | |
| trip = <0x119>; | |
| cooling-device = <0x9d 0x01 0x01>; | |
| }; | |
| cdsp_vdd_cdev { | |
| trip = <0x119>; | |
| cooling-device = <0x105 0x00 0x00>; | |
| }; | |
| mx_vdd_cdev { | |
| trip = <0x119>; | |
| cooling-device = <0x101 0x00 0x00>; | |
| }; | |
| cpu0_vdd_cdev { | |
| trip = <0x119>; | |
| cooling-device = <0x11 0x04 0x04>; | |
| }; | |
| }; | |
| }; | |
| soc { | |
| thermal-sensors = <0x505 0x05>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x64>; | |
| thermal-governor = "low_limits_cap"; | |
| tracks-low; | |
| wake-capable-sensor; | |
| trips { | |
| low-soc { | |
| hysteresis = <0x00>; | |
| temperature = <0x0a>; | |
| type = "passive"; | |
| phandle = <0x507>; | |
| }; | |
| }; | |
| cooling-maps { | |
| soc_map7 { | |
| trip = <0x507>; | |
| cooling-device = <0x18 0xfffffffe 0xfffffffe>; | |
| }; | |
| soc_cpu4 { | |
| trip = <0x507>; | |
| cooling-device = <0x15 0xfffffffe 0xfffffffe>; | |
| }; | |
| soc_map6 { | |
| trip = <0x507>; | |
| cooling-device = <0x17 0xfffffffe 0xfffffffe>; | |
| }; | |
| soc_cpu5 { | |
| trip = <0x507>; | |
| cooling-device = <0x16 0xfffffffe 0xfffffffe>; | |
| }; | |
| }; | |
| }; | |
| cpu2-gold-usr { | |
| thermal-sensors = <0xef 0x09>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-governor = "user_space"; | |
| wake-capable-sensor; | |
| trips { | |
| active-config0 { | |
| hysteresis = <0x3e8>; | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| pmi8998_tz { | |
| thermal-sensors = <0x508>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| wake-capable-sensor; | |
| trips { | |
| pmi8998-trip2 { | |
| hysteresis = <0x00>; | |
| temperature = <0x23668>; | |
| type = "passive"; | |
| phandle = <0x56c>; | |
| }; | |
| pmi8998-trip0 { | |
| hysteresis = <0x00>; | |
| temperature = <0x19a28>; | |
| type = "passive"; | |
| phandle = <0x56a>; | |
| }; | |
| pmi8998-trip1 { | |
| hysteresis = <0x00>; | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| phandle = <0x56b>; | |
| }; | |
| }; | |
| }; | |
| cpu2-silver-usr { | |
| thermal-sensors = <0xef 0x03>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-governor = "user_space"; | |
| wake-capable-sensor; | |
| trips { | |
| active-config0 { | |
| hysteresis = <0x3e8>; | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| ddr-lowf { | |
| thermal-sensors = <0xf0 0x02>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-governor = "low_limits_floor"; | |
| tracks-low; | |
| wake-capable-sensor; | |
| trips { | |
| ddr-trip { | |
| hysteresis = <0x1388>; | |
| temperature = <0x1388>; | |
| type = "passive"; | |
| phandle = <0x115>; | |
| }; | |
| }; | |
| cooling-maps { | |
| cx_vdd_cdev { | |
| trip = <0x115>; | |
| cooling-device = <0x100 0x00 0x00>; | |
| }; | |
| cpu4_vdd_cdev { | |
| trip = <0x115>; | |
| cooling-device = <0x15 0x09 0x09>; | |
| }; | |
| adsp_vdd_cdev { | |
| trip = <0x115>; | |
| cooling-device = <0x104 0x00 0x00>; | |
| }; | |
| modem_vdd_cdev { | |
| trip = <0x115>; | |
| cooling-device = <0x103 0x00 0x00>; | |
| }; | |
| ebi_vdd_cdev { | |
| trip = <0x115>; | |
| cooling-device = <0x102 0x00 0x00>; | |
| }; | |
| slpi_vdd_cdev { | |
| trip = <0x115>; | |
| cooling-device = <0x106 0x00 0x00>; | |
| }; | |
| gpu_vdd_cdev { | |
| trip = <0x115>; | |
| cooling-device = <0x9d 0x01 0x01>; | |
| }; | |
| cdsp_vdd_cdev { | |
| trip = <0x115>; | |
| cooling-device = <0x105 0x00 0x00>; | |
| }; | |
| mx_vdd_cdev { | |
| trip = <0x115>; | |
| cooling-device = <0x101 0x00 0x00>; | |
| }; | |
| cpu0_vdd_cdev { | |
| trip = <0x115>; | |
| cooling-device = <0x11 0x04 0x04>; | |
| }; | |
| }; | |
| }; | |
| mdm-dsp-usr { | |
| thermal-sensors = <0xf0 0x01>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-governor = "user_space"; | |
| wake-capable-sensor; | |
| trips { | |
| active-config0 { | |
| hysteresis = <0x3e8>; | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| msm-therm-adc { | |
| thermal-sensors = <0x303 0x4d>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-governor = "user_space"; | |
| wake-capable-sensor; | |
| trips { | |
| active-config0 { | |
| hysteresis = <0x2710>; | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| cpu1-silver-lowf { | |
| thermal-sensors = <0xef 0x02>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-governor = "low_limits_floor"; | |
| tracks-low; | |
| wake-capable-sensor; | |
| trips { | |
| cpu1-trip { | |
| hysteresis = <0x1388>; | |
| temperature = <0x1388>; | |
| type = "passive"; | |
| phandle = <0x108>; | |
| }; | |
| }; | |
| cooling-maps { | |
| cx_vdd_cdev { | |
| trip = <0x108>; | |
| cooling-device = <0x100 0x00 0x00>; | |
| }; | |
| cpu4_vdd_cdev { | |
| trip = <0x108>; | |
| cooling-device = <0x15 0x09 0x09>; | |
| }; | |
| adsp_vdd_cdev { | |
| trip = <0x108>; | |
| cooling-device = <0x104 0x00 0x00>; | |
| }; | |
| modem_vdd_cdev { | |
| trip = <0x108>; | |
| cooling-device = <0x103 0x00 0x00>; | |
| }; | |
| ebi_vdd_cdev { | |
| trip = <0x108>; | |
| cooling-device = <0x102 0x00 0x00>; | |
| }; | |
| slpi_vdd_cdev { | |
| trip = <0x108>; | |
| cooling-device = <0x106 0x00 0x00>; | |
| }; | |
| gpu_vdd_cdev { | |
| trip = <0x108>; | |
| cooling-device = <0x9d 0x01 0x01>; | |
| }; | |
| cdsp_vdd_cdev { | |
| trip = <0x108>; | |
| cooling-device = <0x105 0x00 0x00>; | |
| }; | |
| mx_vdd_cdev { | |
| trip = <0x108>; | |
| cooling-device = <0x101 0x00 0x00>; | |
| }; | |
| cpu0_vdd_cdev { | |
| trip = <0x108>; | |
| cooling-device = <0x11 0x04 0x04>; | |
| }; | |
| }; | |
| }; | |
| cpu3-silver-step { | |
| thermal-sensors = <0xef 0x04>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x64>; | |
| thermal-governor = "step_wise"; | |
| wake-capable-sensor; | |
| trips { | |
| emerg-config3 { | |
| hysteresis = <0x2710>; | |
| temperature = <0x1adb0>; | |
| type = "passive"; | |
| phandle = <0xf6>; | |
| }; | |
| }; | |
| cooling-maps { | |
| emerg_cdev3 { | |
| trip = <0xf6>; | |
| cooling-device = <0x14 0xfffffffe 0xfffffffe>; | |
| }; | |
| }; | |
| }; | |
| lmh-dcvs-00 { | |
| thermal-sensors = <0x02>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-governor = "user_space"; | |
| wake-capable-sensor; | |
| trips { | |
| active-config { | |
| hysteresis = <0x7530>; | |
| temperature = <0x17318>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| cpu3-gold-lowf { | |
| thermal-sensors = <0xef 0x0a>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-governor = "low_limits_floor"; | |
| tracks-low; | |
| wake-capable-sensor; | |
| trips { | |
| cpug3-trip { | |
| hysteresis = <0x1388>; | |
| temperature = <0x1388>; | |
| type = "passive"; | |
| phandle = <0x110>; | |
| }; | |
| }; | |
| cooling-maps { | |
| cx_vdd_cdev { | |
| trip = <0x110>; | |
| cooling-device = <0x100 0x00 0x00>; | |
| }; | |
| cpu4_vdd_cdev { | |
| trip = <0x110>; | |
| cooling-device = <0x15 0x09 0x09>; | |
| }; | |
| adsp_vdd_cdev { | |
| trip = <0x110>; | |
| cooling-device = <0x104 0x00 0x00>; | |
| }; | |
| modem_vdd_cdev { | |
| trip = <0x110>; | |
| cooling-device = <0x103 0x00 0x00>; | |
| }; | |
| ebi_vdd_cdev { | |
| trip = <0x110>; | |
| cooling-device = <0x102 0x00 0x00>; | |
| }; | |
| slpi_vdd_cdev { | |
| trip = <0x110>; | |
| cooling-device = <0x106 0x00 0x00>; | |
| }; | |
| gpu_vdd_cdev { | |
| trip = <0x110>; | |
| cooling-device = <0x9d 0x01 0x01>; | |
| }; | |
| cdsp_vdd_cdev { | |
| trip = <0x110>; | |
| cooling-device = <0x105 0x00 0x00>; | |
| }; | |
| mx_vdd_cdev { | |
| trip = <0x110>; | |
| cooling-device = <0x101 0x00 0x00>; | |
| }; | |
| cpu0_vdd_cdev { | |
| trip = <0x110>; | |
| cooling-device = <0x11 0x04 0x04>; | |
| }; | |
| }; | |
| }; | |
| compute-hvx-lowf { | |
| thermal-sensors = <0xf0 0x04>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-governor = "low_limits_floor"; | |
| tracks-low; | |
| wake-capable-sensor; | |
| trips { | |
| hvx-trip { | |
| hysteresis = <0x1388>; | |
| temperature = <0x1388>; | |
| type = "passive"; | |
| phandle = <0x117>; | |
| }; | |
| }; | |
| cooling-maps { | |
| cx_vdd_cdev { | |
| trip = <0x117>; | |
| cooling-device = <0x100 0x00 0x00>; | |
| }; | |
| cpu4_vdd_cdev { | |
| trip = <0x117>; | |
| cooling-device = <0x15 0x09 0x09>; | |
| }; | |
| adsp_vdd_cdev { | |
| trip = <0x117>; | |
| cooling-device = <0x104 0x00 0x00>; | |
| }; | |
| modem_vdd_cdev { | |
| trip = <0x117>; | |
| cooling-device = <0x103 0x00 0x00>; | |
| }; | |
| ebi_vdd_cdev { | |
| trip = <0x117>; | |
| cooling-device = <0x102 0x00 0x00>; | |
| }; | |
| slpi_vdd_cdev { | |
| trip = <0x117>; | |
| cooling-device = <0x106 0x00 0x00>; | |
| }; | |
| gpu_vdd_cdev { | |
| trip = <0x117>; | |
| cooling-device = <0x9d 0x01 0x01>; | |
| }; | |
| cdsp_vdd_cdev { | |
| trip = <0x117>; | |
| cooling-device = <0x105 0x00 0x00>; | |
| }; | |
| mx_vdd_cdev { | |
| trip = <0x117>; | |
| cooling-device = <0x101 0x00 0x00>; | |
| }; | |
| cpu0_vdd_cdev { | |
| trip = <0x117>; | |
| cooling-device = <0x11 0x04 0x04>; | |
| }; | |
| }; | |
| }; | |
| gpu1-lowf { | |
| thermal-sensors = <0xef 0x0c>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-governor = "low_limits_floor"; | |
| tracks-low; | |
| wake-capable-sensor; | |
| trips { | |
| gpu1-trip_l { | |
| hysteresis = <0x1388>; | |
| temperature = <0x1388>; | |
| type = "passive"; | |
| phandle = <0x112>; | |
| }; | |
| }; | |
| cooling-maps { | |
| cx_vdd_cdev { | |
| trip = <0x112>; | |
| cooling-device = <0x100 0x00 0x00>; | |
| }; | |
| cpu4_vdd_cdev { | |
| trip = <0x112>; | |
| cooling-device = <0x15 0x09 0x09>; | |
| }; | |
| adsp_vdd_cdev { | |
| trip = <0x112>; | |
| cooling-device = <0x104 0x00 0x00>; | |
| }; | |
| modem_vdd_cdev { | |
| trip = <0x112>; | |
| cooling-device = <0x103 0x00 0x00>; | |
| }; | |
| ebi_vdd_cdev { | |
| trip = <0x112>; | |
| cooling-device = <0x102 0x00 0x00>; | |
| }; | |
| slpi_vdd_cdev { | |
| trip = <0x112>; | |
| cooling-device = <0x106 0x00 0x00>; | |
| }; | |
| gpu_vdd_cdev { | |
| trip = <0x112>; | |
| cooling-device = <0x9d 0x01 0x01>; | |
| }; | |
| cdsp_vdd_cdev { | |
| trip = <0x112>; | |
| cooling-device = <0x105 0x00 0x00>; | |
| }; | |
| mx_vdd_cdev { | |
| trip = <0x112>; | |
| cooling-device = <0x101 0x00 0x00>; | |
| }; | |
| cpu0_vdd_cdev { | |
| trip = <0x112>; | |
| cooling-device = <0x11 0x04 0x04>; | |
| }; | |
| }; | |
| }; | |
| ibat-high { | |
| thermal-sensors = <0x505 0x00>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-governor = "step_wise"; | |
| wake-capable-sensor; | |
| trips { | |
| low-ibat { | |
| hysteresis = <0xc8>; | |
| temperature = <0x1388>; | |
| type = "passive"; | |
| phandle = <0x568>; | |
| }; | |
| }; | |
| }; | |
| wlan-usr { | |
| thermal-sensors = <0xf0 0x03>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-governor = "user_space"; | |
| wake-capable-sensor; | |
| trips { | |
| active-config0 { | |
| hysteresis = <0x3e8>; | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| quiet-therm-adc { | |
| thermal-sensors = <0x303 0x51>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-governor = "user_space"; | |
| wake-capable-sensor; | |
| trips { | |
| active-config0 { | |
| hysteresis = <0x2710>; | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| ibat-vhigh { | |
| thermal-sensors = <0x505 0x01>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-governor = "step_wise"; | |
| wake-capable-sensor; | |
| trips { | |
| ibat_vhigh { | |
| hysteresis = <0x64>; | |
| temperature = <0x1770>; | |
| type = "passive"; | |
| phandle = <0x569>; | |
| }; | |
| }; | |
| }; | |
| cpu3-silver-usr { | |
| thermal-sensors = <0xef 0x04>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-governor = "user_space"; | |
| wake-capable-sensor; | |
| trips { | |
| active-config0 { | |
| hysteresis = <0x3e8>; | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| gold-virt-max-step { | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-governor = "step_wise"; | |
| wake-capable-sensor; | |
| trips { | |
| gold-trip { | |
| hysteresis = <0x00>; | |
| temperature = <0x1d4c0>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| aoss0-usr { | |
| thermal-sensors = <0xef 0x00>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-governor = "user_space"; | |
| wake-capable-sensor; | |
| trips { | |
| active-config0 { | |
| hysteresis = <0x3e8>; | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| cpu2-silver-lowf { | |
| thermal-sensors = <0xef 0x03>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-governor = "low_limits_floor"; | |
| tracks-low; | |
| wake-capable-sensor; | |
| trips { | |
| cpu2-trip { | |
| hysteresis = <0x1388>; | |
| temperature = <0x1388>; | |
| type = "passive"; | |
| phandle = <0x109>; | |
| }; | |
| }; | |
| cooling-maps { | |
| cx_vdd_cdev { | |
| trip = <0x109>; | |
| cooling-device = <0x100 0x00 0x00>; | |
| }; | |
| cpu4_vdd_cdev { | |
| trip = <0x109>; | |
| cooling-device = <0x15 0x09 0x09>; | |
| }; | |
| adsp_vdd_cdev { | |
| trip = <0x109>; | |
| cooling-device = <0x104 0x00 0x00>; | |
| }; | |
| modem_vdd_cdev { | |
| trip = <0x109>; | |
| cooling-device = <0x103 0x00 0x00>; | |
| }; | |
| ebi_vdd_cdev { | |
| trip = <0x109>; | |
| cooling-device = <0x102 0x00 0x00>; | |
| }; | |
| slpi_vdd_cdev { | |
| trip = <0x109>; | |
| cooling-device = <0x106 0x00 0x00>; | |
| }; | |
| gpu_vdd_cdev { | |
| trip = <0x109>; | |
| cooling-device = <0x9d 0x01 0x01>; | |
| }; | |
| cdsp_vdd_cdev { | |
| trip = <0x109>; | |
| cooling-device = <0x105 0x00 0x00>; | |
| }; | |
| mx_vdd_cdev { | |
| trip = <0x109>; | |
| cooling-device = <0x101 0x00 0x00>; | |
| }; | |
| cpu0_vdd_cdev { | |
| trip = <0x109>; | |
| cooling-device = <0x11 0x04 0x04>; | |
| }; | |
| }; | |
| }; | |
| mmss-usr { | |
| thermal-sensors = <0xf0 0x06>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-governor = "user_space"; | |
| wake-capable-sensor; | |
| trips { | |
| active-config0 { | |
| hysteresis = <0x3e8>; | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| gpu0-lowf { | |
| thermal-sensors = <0xef 0x0b>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-governor = "low_limits_floor"; | |
| tracks-low; | |
| wake-capable-sensor; | |
| trips { | |
| gpu0-trip { | |
| hysteresis = <0x1388>; | |
| temperature = <0x1388>; | |
| type = "passive"; | |
| phandle = <0x111>; | |
| }; | |
| }; | |
| cooling-maps { | |
| cx_vdd_cdev { | |
| trip = <0x111>; | |
| cooling-device = <0x100 0x00 0x00>; | |
| }; | |
| cpu4_vdd_cdev { | |
| trip = <0x111>; | |
| cooling-device = <0x15 0x09 0x09>; | |
| }; | |
| adsp_vdd_cdev { | |
| trip = <0x111>; | |
| cooling-device = <0x104 0x00 0x00>; | |
| }; | |
| modem_vdd_cdev { | |
| trip = <0x111>; | |
| cooling-device = <0x103 0x00 0x00>; | |
| }; | |
| ebi_vdd_cdev { | |
| trip = <0x111>; | |
| cooling-device = <0x102 0x00 0x00>; | |
| }; | |
| slpi_vdd_cdev { | |
| trip = <0x111>; | |
| cooling-device = <0x106 0x00 0x00>; | |
| }; | |
| gpu_vdd_cdev { | |
| trip = <0x111>; | |
| cooling-device = <0x9d 0x01 0x01>; | |
| }; | |
| cdsp_vdd_cdev { | |
| trip = <0x111>; | |
| cooling-device = <0x105 0x00 0x00>; | |
| }; | |
| mx_vdd_cdev { | |
| trip = <0x111>; | |
| cooling-device = <0x101 0x00 0x00>; | |
| }; | |
| cpu0_vdd_cdev { | |
| trip = <0x111>; | |
| cooling-device = <0x11 0x04 0x04>; | |
| }; | |
| }; | |
| }; | |
| cpu3-gold-usr { | |
| thermal-sensors = <0xef 0x0a>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-governor = "user_space"; | |
| wake-capable-sensor; | |
| trips { | |
| active-config0 { | |
| hysteresis = <0x3e8>; | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| mdm-dsp-lowf { | |
| thermal-sensors = <0xf0 0x01>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-governor = "low_limits_floor"; | |
| tracks-low; | |
| wake-capable-sensor; | |
| trips { | |
| dsp-trip { | |
| hysteresis = <0x1388>; | |
| temperature = <0x1388>; | |
| type = "passive"; | |
| phandle = <0x114>; | |
| }; | |
| }; | |
| cooling-maps { | |
| cx_vdd_cdev { | |
| trip = <0x114>; | |
| cooling-device = <0x100 0x00 0x00>; | |
| }; | |
| cpu4_vdd_cdev { | |
| trip = <0x114>; | |
| cooling-device = <0x15 0x09 0x09>; | |
| }; | |
| adsp_vdd_cdev { | |
| trip = <0x114>; | |
| cooling-device = <0x104 0x00 0x00>; | |
| }; | |
| modem_vdd_cdev { | |
| trip = <0x114>; | |
| cooling-device = <0x103 0x00 0x00>; | |
| }; | |
| ebi_vdd_cdev { | |
| trip = <0x114>; | |
| cooling-device = <0x102 0x00 0x00>; | |
| }; | |
| slpi_vdd_cdev { | |
| trip = <0x114>; | |
| cooling-device = <0x106 0x00 0x00>; | |
| }; | |
| gpu_vdd_cdev { | |
| trip = <0x114>; | |
| cooling-device = <0x9d 0x01 0x01>; | |
| }; | |
| cdsp_vdd_cdev { | |
| trip = <0x114>; | |
| cooling-device = <0x105 0x00 0x00>; | |
| }; | |
| mx_vdd_cdev { | |
| trip = <0x114>; | |
| cooling-device = <0x101 0x00 0x00>; | |
| }; | |
| cpu0_vdd_cdev { | |
| trip = <0x114>; | |
| cooling-device = <0x11 0x04 0x04>; | |
| }; | |
| }; | |
| }; | |
| cpu2-gold-step { | |
| thermal-sensors = <0xef 0x09>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x64>; | |
| thermal-governor = "step_wise"; | |
| wake-capable-sensor; | |
| trips { | |
| emerg-config6 { | |
| hysteresis = <0x2710>; | |
| temperature = <0x1adb0>; | |
| type = "passive"; | |
| phandle = <0xf9>; | |
| }; | |
| }; | |
| cooling-maps { | |
| emerg_cdev6 { | |
| trip = <0xf9>; | |
| cooling-device = <0x17 0xfffffffe 0xfffffffe>; | |
| }; | |
| }; | |
| }; | |
| cpu1-gold-lowf { | |
| thermal-sensors = <0xef 0x08>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-governor = "low_limits_floor"; | |
| tracks-low; | |
| wake-capable-sensor; | |
| trips { | |
| cpug1-trip { | |
| hysteresis = <0x1388>; | |
| temperature = <0x1388>; | |
| type = "passive"; | |
| phandle = <0x10e>; | |
| }; | |
| }; | |
| cooling-maps { | |
| cx_vdd_cdev { | |
| trip = <0x10e>; | |
| cooling-device = <0x100 0x00 0x00>; | |
| }; | |
| cpu4_vdd_cdev { | |
| trip = <0x10e>; | |
| cooling-device = <0x15 0x09 0x09>; | |
| }; | |
| adsp_vdd_cdev { | |
| trip = <0x10e>; | |
| cooling-device = <0x104 0x00 0x00>; | |
| }; | |
| modem_vdd_cdev { | |
| trip = <0x10e>; | |
| cooling-device = <0x103 0x00 0x00>; | |
| }; | |
| ebi_vdd_cdev { | |
| trip = <0x10e>; | |
| cooling-device = <0x102 0x00 0x00>; | |
| }; | |
| slpi_vdd_cdev { | |
| trip = <0x10e>; | |
| cooling-device = <0x106 0x00 0x00>; | |
| }; | |
| gpu_vdd_cdev { | |
| trip = <0x10e>; | |
| cooling-device = <0x9d 0x01 0x01>; | |
| }; | |
| cdsp_vdd_cdev { | |
| trip = <0x10e>; | |
| cooling-device = <0x105 0x00 0x00>; | |
| }; | |
| mx_vdd_cdev { | |
| trip = <0x10e>; | |
| cooling-device = <0x101 0x00 0x00>; | |
| }; | |
| cpu0_vdd_cdev { | |
| trip = <0x10e>; | |
| cooling-device = <0x11 0x04 0x04>; | |
| }; | |
| }; | |
| }; | |
| cpu0-gold-usr { | |
| thermal-sensors = <0xef 0x07>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-governor = "user_space"; | |
| wake-capable-sensor; | |
| trips { | |
| active-config0 { | |
| hysteresis = <0x3e8>; | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| camera-lowf { | |
| thermal-sensors = <0xf0 0x05>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-governor = "low_limits_floor"; | |
| tracks-low; | |
| wake-capable-sensor; | |
| trips { | |
| camera-trip { | |
| hysteresis = <0x1388>; | |
| temperature = <0x1388>; | |
| type = "passive"; | |
| phandle = <0x118>; | |
| }; | |
| }; | |
| cooling-maps { | |
| cx_vdd_cdev { | |
| trip = <0x118>; | |
| cooling-device = <0x100 0x00 0x00>; | |
| }; | |
| cpu4_vdd_cdev { | |
| trip = <0x118>; | |
| cooling-device = <0x15 0x09 0x09>; | |
| }; | |
| adsp_vdd_cdev { | |
| trip = <0x118>; | |
| cooling-device = <0x104 0x00 0x00>; | |
| }; | |
| modem_vdd_cdev { | |
| trip = <0x118>; | |
| cooling-device = <0x103 0x00 0x00>; | |
| }; | |
| ebi_vdd_cdev { | |
| trip = <0x118>; | |
| cooling-device = <0x102 0x00 0x00>; | |
| }; | |
| slpi_vdd_cdev { | |
| trip = <0x118>; | |
| cooling-device = <0x106 0x00 0x00>; | |
| }; | |
| gpu_vdd_cdev { | |
| trip = <0x118>; | |
| cooling-device = <0x9d 0x01 0x01>; | |
| }; | |
| cdsp_vdd_cdev { | |
| trip = <0x118>; | |
| cooling-device = <0x105 0x00 0x00>; | |
| }; | |
| mx_vdd_cdev { | |
| trip = <0x118>; | |
| cooling-device = <0x101 0x00 0x00>; | |
| }; | |
| cpu0_vdd_cdev { | |
| trip = <0x118>; | |
| cooling-device = <0x11 0x04 0x04>; | |
| }; | |
| }; | |
| }; | |
| camera-usr { | |
| thermal-sensors = <0xf0 0x05>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-governor = "user_space"; | |
| wake-capable-sensor; | |
| trips { | |
| active-config0 { | |
| hysteresis = <0x3e8>; | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| vbat_low { | |
| thermal-sensors = <0x505 0x03>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-governor = "low_limits_cap"; | |
| tracks-low; | |
| wake-capable-sensor; | |
| trips { | |
| low-vbat { | |
| hysteresis = <0x00>; | |
| temperature = <0xaf0>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| ddr-usr { | |
| thermal-sensors = <0xf0 0x02>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-governor = "user_space"; | |
| wake-capable-sensor; | |
| trips { | |
| active-config0 { | |
| hysteresis = <0x3e8>; | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| cpu3-silver-lowf { | |
| thermal-sensors = <0xef 0x04>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-governor = "low_limits_floor"; | |
| tracks-low; | |
| wake-capable-sensor; | |
| trips { | |
| cpu3-trip { | |
| hysteresis = <0x1388>; | |
| temperature = <0x1388>; | |
| type = "passive"; | |
| phandle = <0x10a>; | |
| }; | |
| }; | |
| cooling-maps { | |
| cx_vdd_cdev { | |
| trip = <0x10a>; | |
| cooling-device = <0x100 0x00 0x00>; | |
| }; | |
| cpu4_vdd_cdev { | |
| trip = <0x10a>; | |
| cooling-device = <0x15 0x09 0x09>; | |
| }; | |
| adsp_vdd_cdev { | |
| trip = <0x10a>; | |
| cooling-device = <0x104 0x00 0x00>; | |
| }; | |
| modem_vdd_cdev { | |
| trip = <0x10a>; | |
| cooling-device = <0x103 0x00 0x00>; | |
| }; | |
| ebi_vdd_cdev { | |
| trip = <0x10a>; | |
| cooling-device = <0x102 0x00 0x00>; | |
| }; | |
| slpi_vdd_cdev { | |
| trip = <0x10a>; | |
| cooling-device = <0x106 0x00 0x00>; | |
| }; | |
| gpu_vdd_cdev { | |
| trip = <0x10a>; | |
| cooling-device = <0x9d 0x01 0x01>; | |
| }; | |
| cdsp_vdd_cdev { | |
| trip = <0x10a>; | |
| cooling-device = <0x105 0x00 0x00>; | |
| }; | |
| mx_vdd_cdev { | |
| trip = <0x10a>; | |
| cooling-device = <0x101 0x00 0x00>; | |
| }; | |
| cpu0_vdd_cdev { | |
| trip = <0x10a>; | |
| cooling-device = <0x11 0x04 0x04>; | |
| }; | |
| }; | |
| }; | |
| cpu0-silver-step { | |
| thermal-sensors = <0xef 0x01>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x64>; | |
| thermal-governor = "step_wise"; | |
| wake-capable-sensor; | |
| trips { | |
| emerg-config0 { | |
| hysteresis = <0x2710>; | |
| temperature = <0x1adb0>; | |
| type = "passive"; | |
| phandle = <0xf3>; | |
| }; | |
| }; | |
| cooling-maps { | |
| emerg_cdev0 { | |
| trip = <0xf3>; | |
| cooling-device = <0x11 0xfffffffe 0xfffffffe>; | |
| }; | |
| }; | |
| }; | |
| gpu0-usr { | |
| thermal-sensors = <0xef 0x0b>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-governor = "user_space"; | |
| wake-capable-sensor; | |
| trips { | |
| active-config0 { | |
| hysteresis = <0x3e8>; | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| aoss1-usr { | |
| thermal-sensors = <0xf0 0x00>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-governor = "user_space"; | |
| wake-capable-sensor; | |
| trips { | |
| active-config0 { | |
| hysteresis = <0x3e8>; | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| wlan-lowf { | |
| thermal-sensors = <0xf0 0x03>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-governor = "low_limits_floor"; | |
| tracks-low; | |
| wake-capable-sensor; | |
| trips { | |
| wlan-trip { | |
| hysteresis = <0x1388>; | |
| temperature = <0x1388>; | |
| type = "passive"; | |
| phandle = <0x116>; | |
| }; | |
| }; | |
| cooling-maps { | |
| cx_vdd_cdev { | |
| trip = <0x116>; | |
| cooling-device = <0x100 0x00 0x00>; | |
| }; | |
| cpu4_vdd_cdev { | |
| trip = <0x116>; | |
| cooling-device = <0x15 0x09 0x09>; | |
| }; | |
| adsp_vdd_cdev { | |
| trip = <0x116>; | |
| cooling-device = <0x104 0x00 0x00>; | |
| }; | |
| modem_vdd_cdev { | |
| trip = <0x116>; | |
| cooling-device = <0x103 0x00 0x00>; | |
| }; | |
| ebi_vdd_cdev { | |
| trip = <0x116>; | |
| cooling-device = <0x102 0x00 0x00>; | |
| }; | |
| slpi_vdd_cdev { | |
| trip = <0x116>; | |
| cooling-device = <0x106 0x00 0x00>; | |
| }; | |
| gpu_vdd_cdev { | |
| trip = <0x116>; | |
| cooling-device = <0x9d 0x01 0x01>; | |
| }; | |
| cdsp_vdd_cdev { | |
| trip = <0x116>; | |
| cooling-device = <0x105 0x00 0x00>; | |
| }; | |
| mx_vdd_cdev { | |
| trip = <0x116>; | |
| cooling-device = <0x101 0x00 0x00>; | |
| }; | |
| cpu0_vdd_cdev { | |
| trip = <0x116>; | |
| cooling-device = <0x11 0x04 0x04>; | |
| }; | |
| }; | |
| }; | |
| lmh-dcvs-01 { | |
| thermal-sensors = <0x0a>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-governor = "user_space"; | |
| wake-capable-sensor; | |
| trips { | |
| active-config { | |
| hysteresis = <0x7530>; | |
| temperature = <0x17318>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| kryo-l3-0-usr { | |
| thermal-sensors = <0xef 0x05>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-governor = "user_space"; | |
| wake-capable-sensor; | |
| trips { | |
| active-config0 { | |
| hysteresis = <0x3e8>; | |
| temperature = <0x1e848>; | |
| type = "passive"; | |
| }; | |
| }; | |
| }; | |
| cpu0-gold-step { | |
| thermal-sensors = <0xef 0x07>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x64>; | |
| thermal-governor = "step_wise"; | |
| wake-capable-sensor; | |
| trips { | |
| emerg-config4 { | |
| hysteresis = <0x2710>; | |
| temperature = <0x1adb0>; | |
| type = "passive"; | |
| phandle = <0xf7>; | |
| }; | |
| }; | |
| cooling-maps { | |
| emerg_cdev4 { | |
| trip = <0xf7>; | |
| cooling-device = <0x15 0xfffffffe 0xfffffffe>; | |
| }; | |
| }; | |
| }; | |
| aoss1-lowf { | |
| thermal-sensors = <0xf0 0x00>; | |
| polling-delay = <0x00>; | |
| polling-delay-passive = <0x00>; | |
| thermal-governor = "low_limits_floor"; | |
| tracks-low; | |
| wake-capable-sensor; | |
| trips { | |
| aoss1-trip { | |
| hysteresis = <0x1388>; | |
| temperature = <0x1388>; | |
| type = "passive"; | |
| phandle = <0x113>; | |
| }; | |
| }; | |
| cooling-maps { | |
| cx_vdd_cdev { | |
| trip = <0x113>; | |
| cooling-device = <0x100 0x00 0x00>; | |
| }; | |
| cpu4_vdd_cdev { | |
| trip = <0x113>; | |
| cooling-device = <0x15 0x09 0x09>; | |
| }; | |
| adsp_vdd_cdev { | |
| trip = <0x113>; | |
| cooling-device = <0x104 0x00 0x00>; | |
| }; | |
| modem_vdd_cdev { | |
| trip = <0x113>; | |
| cooling-device = <0x103 0x00 0x00>; | |
| }; | |
| ebi_vdd_cdev { | |
| trip = <0x113>; | |
| cooling-device = <0x102 0x00 0x00>; | |
| }; | |
| slpi_vdd_cdev { | |
| trip = <0x113>; | |
| cooling-device = <0x106 0x00 0x00>; | |
| }; | |
| gpu_vdd_cdev { | |
| trip = <0x113>; | |
| cooling-device = <0x9d 0x01 0x01>; | |
| }; | |
| cdsp_vdd_cdev { | |
| trip = <0x113>; | |
| cooling-device = <0x105 0x00 0x00>; | |
| }; | |
| mx_vdd_cdev { | |
| trip = <0x113>; | |
| cooling-device = <0x101 0x00 0x00>; | |
| }; | |
| cpu0_vdd_cdev { | |
| trip = <0x113>; | |
| cooling-device = <0x11 0x04 0x04>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,wcd-dsp-mgr { | |
| compatible = "qcom,wcd-dsp-mgr"; | |
| qcom,img-filename = "cpe_9340"; | |
| qcom,wdsp-components = <0x536 0x00 0x537 0x01 0x321 0x02>; | |
| }; | |
| qcom,qupv3_1_geni_se@ac0000 { | |
| compatible = "qcom,qupv3-geni-se"; | |
| qcom,iommu-s1-bypass; | |
| phandle = <0x5b>; | |
| qcom,bus-mas-id = <0x54>; | |
| reg = <0xac0000 0x6000>; | |
| qcom,bus-slv-id = <0x200>; | |
| qcom,iommu_qupv3_1_geni_se_cb { | |
| compatible = "qcom,qupv3-geni-se-cb"; | |
| phandle = <0x2db>; | |
| iommus = <0x29 0x6c3 0x00>; | |
| }; | |
| }; | |
| qcom,jpegenc@ac4e000 { | |
| clock-rates = <0x00 0x00 0x00 0x00 0x00 0x23c34600 0x00>; | |
| compatible = "qcom,cam_jpeg_enc"; | |
| clocks = <0x22 0x0c 0x22 0x0d 0xa5 0x55 0xa5 0x09 0xa5 0x06 0xa5 0x3f 0xa5 0x3e>; | |
| reg-names = "jpege_hw"; | |
| clock-names = "camera_ahb\0camera_axi\0soc_ahb_clk\0cpas_ahb_clk\0camnoc_axi_clk\0jpegenc_clk_src\0jpegenc_clk"; | |
| regulator-names = "camss-vdd"; | |
| status = "ok"; | |
| interrupts = <0x00 0x1da 0x00>; | |
| camss-vdd-supply = <0x1bb>; | |
| phandle = <0x3be>; | |
| reg = <0xac4e000 0x4000>; | |
| src-clock-name = "jpegenc_clk_src"; | |
| interrupt-names = "jpeg"; | |
| reg-cam-base = <0x4e000>; | |
| cell-index = <0x00>; | |
| clock-cntl-level = "nominal"; | |
| }; | |
| funnel@69e2000 { | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "funnel-base"; | |
| coresight-name = "coresight-funnel-ddr-0"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x375>; | |
| arm,primecell-periphid = <0x3b908>; | |
| reg = <0x69e2000 0x1000>; | |
| ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@1 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x173>; | |
| phandle = <0x174>; | |
| slave-mode; | |
| }; | |
| }; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x172>; | |
| phandle = <0x14c>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,qupv3_0_geni_se@8c0000 { | |
| compatible = "qcom,qupv3-geni-se"; | |
| qcom,iommu-s1-bypass; | |
| phandle = <0x35>; | |
| qcom,bus-mas-id = <0x56>; | |
| reg = <0x8c0000 0x6000>; | |
| qcom,bus-slv-id = <0x200>; | |
| qcom,iommu_qupv3_0_geni_se_cb { | |
| compatible = "qcom,qupv3-geni-se-cb"; | |
| phandle = <0x2c8>; | |
| iommus = <0x29 0x03 0x00>; | |
| }; | |
| }; | |
| qcom,msm-pcm-hostless { | |
| compatible = "qcom,msm-pcm-hostless"; | |
| phandle = <0x278>; | |
| }; | |
| rpmh-regulator-lmxlvl { | |
| compatible = "qcom,rpmh-arc-regulator"; | |
| qcom,resource-name = "lmx.lvl"; | |
| mboxes = <0x8a 0x00>; | |
| regulator-l4-level { | |
| phandle = <0xb6>; | |
| regulator-min-microvolt = <0x01>; | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x10000>; | |
| regulator-name = "pm8998_l4_level"; | |
| }; | |
| }; | |
| rpmh-regulator-cxlvl { | |
| compatible = "qcom,rpmh-arc-regulator"; | |
| pm8998_s9_level-parent-supply = <0x8c>; | |
| qcom,resource-name = "cx.lvl"; | |
| mboxes = <0x8a 0x00>; | |
| pm8998_s9_level_ao-parent-supply = <0x9e>; | |
| regulator-cdev { | |
| compatible = "qcom,rpmh-reg-cdev"; | |
| mboxes = <0x80 0x00>; | |
| phandle = <0x100>; | |
| qcom,reg-resource-name = "cx"; | |
| #cooling-cells = <0x02>; | |
| }; | |
| regulator-s9-level-ao { | |
| phandle = <0x8b>; | |
| regulator-min-microvolt = <0x11>; | |
| qcom,set = <0x01>; | |
| regulator-max-microvolt = <0x10000>; | |
| regulator-name = "pm8998_s9_level_ao"; | |
| qcom,min-dropout-voltage-level = <0xffffffff>; | |
| }; | |
| regulator-s9-level { | |
| phandle = <0x1b>; | |
| regulator-min-microvolt = <0x11>; | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x10000>; | |
| regulator-name = "pm8998_s9_level"; | |
| qcom,min-dropout-voltage-level = <0xffffffff>; | |
| }; | |
| }; | |
| qcom,ipc_router_modem_xprt { | |
| compatible = "qcom,ipc_router_glink_xprt"; | |
| qcom,ch-name = "IPCRTR"; | |
| qcom,glink-xprt = "smem"; | |
| qcom,xprt-remote = "mpss"; | |
| qcom,xprt-linkid = <0x01>; | |
| qcom,fragmented-data; | |
| qcom,xprt-version = <0x01>; | |
| }; | |
| qcom,ion { | |
| compatible = "qcom,msm-ion"; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| qcom,ion-heap@22 { | |
| qcom,ion-heap-type = "DMA"; | |
| memory-region = <0xbf>; | |
| reg = <0x16>; | |
| }; | |
| qcom,ion-heap@10 { | |
| qcom,ion-heap-type = "HYP_CMA"; | |
| memory-region = <0x1af>; | |
| reg = <0x0a>; | |
| }; | |
| qcom,ion-heap@19 { | |
| qcom,ion-heap-type = "DMA"; | |
| memory-region = <0x1ad>; | |
| reg = <0x13>; | |
| }; | |
| qcom,ion-heap@27 { | |
| qcom,ion-heap-type = "DMA"; | |
| memory-region = <0x1ac>; | |
| reg = <0x1b>; | |
| }; | |
| qcom,ion-heap@25 { | |
| qcom,ion-heap-type = "SYSTEM"; | |
| phandle = <0x3b3>; | |
| reg = <0x19>; | |
| }; | |
| qcom,ion-heap@13 { | |
| qcom,ion-heap-type = "HYP_CMA"; | |
| memory-region = <0x1ae>; | |
| reg = <0x0d>; | |
| }; | |
| qcom,ion-heap@9 { | |
| qcom,ion-heap-type = "SYSTEM_SECURE"; | |
| reg = <0x09>; | |
| }; | |
| }; | |
| etm@7040000 { | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| coresight-name = "coresight-etm0"; | |
| clock-names = "apb_pclk"; | |
| cpu = <0x11>; | |
| phandle = <0x3a2>; | |
| arm,primecell-periphid = <0xbb95d>; | |
| reg = <0x7040000 0x1000>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x192>; | |
| phandle = <0x19b>; | |
| }; | |
| }; | |
| }; | |
| qcom,gdsc@0xab00874 { | |
| compatible = "qcom,gdsc"; | |
| qcom,support-hw-trigger; | |
| status = "ok"; | |
| phandle = <0x260>; | |
| reg = <0xab00874 0x04>; | |
| regulator-name = "vcodec0_gdsc"; | |
| qcom,poll-cfg-gdscr; | |
| }; | |
| qcom,glink-ssr-adsp { | |
| compatible = "qcom,glink_ssr"; | |
| qcom,xprt = "smem"; | |
| qcom,notify-edges = <0xe5 0xe2 0xe3>; | |
| label = "adsp"; | |
| qcom,edge = "lpass"; | |
| phandle = <0xe1>; | |
| }; | |
| qcom,llcc@1100000 { | |
| compatible = "qcom,llcc-core\0syscon\0simple-mfd"; | |
| reg-names = "llcc_base"; | |
| reg = <0x1100000 0x250000>; | |
| qcom,llcc-banks-off = <0x00 0x80000 0x100000 0x180000>; | |
| qcom,llcc-broadcast-off = <0x200000>; | |
| llcc_1_dcache { | |
| phandle = <0xd2>; | |
| qcom,dump-size = <0x1141c0>; | |
| }; | |
| qcom,sdm845-llcc { | |
| compatible = "qcom,sdm845-llcc"; | |
| max-slices = <0x20>; | |
| phandle = <0x2d>; | |
| #cache-cells = <0x01>; | |
| }; | |
| qcom,llcc-amon { | |
| compatible = "qcom,llcc-amon"; | |
| }; | |
| qcom,llcc-erp { | |
| compatible = "qcom,llcc-erp"; | |
| interrupts = <0x00 0x246 0x04>; | |
| interrupt-names = "ecc_irq"; | |
| }; | |
| llcc_4_dcache { | |
| phandle = <0xd5>; | |
| qcom,dump-size = <0x1141c0>; | |
| }; | |
| qcom,llcc-perfmon { | |
| compatible = "qcom,llcc-perfmon"; | |
| }; | |
| llcc_3_dcache { | |
| phandle = <0xd4>; | |
| qcom,dump-size = <0x1141c0>; | |
| }; | |
| llcc_2_dcache { | |
| phandle = <0xd3>; | |
| qcom,dump-size = <0x1141c0>; | |
| }; | |
| }; | |
| qcom,msm-adsprpc-mem { | |
| compatible = "qcom,msm-adsprpc-mem-region"; | |
| memory-region = <0xbf>; | |
| }; | |
| qcom,dp_display@0 { | |
| qcom,aux-cfg1-settings = <0x2413231d>; | |
| compatible = "qcom,dp-display"; | |
| clocks = <0x20 0x08 0x21 0x00 0x22 0x9f 0x22 0xa9 0x22 0xa3 0x20 0x0c 0x20 0x0e 0x20 0x11 0x20 0x0a 0x20 0x12 0x30 0x05>; | |
| qcom,ext-disp = <0x4f9>; | |
| reg-names = "dp_ahb\0dp_aux\0dp_link\0dp_p0\0dp_phy\0dp_ln_tx0\0dp_ln_tx1\0dp_mmss_cc\0qfprom_physical\0dp_pll\0usb3_dp_com\0hdcp_physical"; | |
| qcom,aux-cfg8-settings = [40 bb]; | |
| pinctrl-1 = <0x420 0x422>; | |
| qcom,aux-cfg5-settings = [34 26]; | |
| clock-names = "core_aux_clk\0core_usb_ref_clk_src\0core_usb_ref_clk\0core_usb_cfg_ahb_clk\0core_usb_pipe_clk\0ctrl_link_clk\0ctrl_link_iface_clk\0ctrl_pixel_clk\0crypto_clk\0pixel_clk_rcg\0pixel_parent"; | |
| vdda-1p2-supply = <0x2e>; | |
| qcom,aux-cfg2-settings = [28 24]; | |
| gdsc-supply = <0x19>; | |
| qcom,usbplug-cc-gpio = <0x34 0x26 0x00>; | |
| qcom,aux-cfg9-settings = [44 03]; | |
| interrupt-parent = <0x2c>; | |
| interrupts = <0x0c 0x00>; | |
| qcom,aux-cfg6-settings = [38 0a]; | |
| qcom,aux-en-gpio = <0x34 0x2b 0x00>; | |
| phandle = <0x2c7>; | |
| qcom,aux-cfg3-settings = ","; | |
| reg = <0xae90000 0xdc 0xae90200 0xc0 0xae90400 0x508 0xae90a00 0x94 0x88eaa00 0x200 0x88ea200 0x200 0x88ea600 0x200 0xaf02000 0x1a0 0x780000 0x621c 0x88ea030 0x10 0x88e8000 0x20 0xaee1000 0x34>; | |
| qcom,dp-usbpd-detection = <0x4f8>; | |
| qcom,aux-cfg0-settings = " "; | |
| pinctrl-0 = <0x41f 0x421>; | |
| qcom,aux-sel-gpio = <0x34 0x33 0x00>; | |
| qcom,aux-cfg7-settings = [3c 03]; | |
| vdda-0p9-supply = <0x2f>; | |
| pinctrl-names = "mdss_dp_active\0mdss_dp_sleep"; | |
| cell-index = <0x00>; | |
| qcom,max-pclk-frequency-khz = <0xa4cb8>; | |
| qcom,aux-cfg4-settings = [30 0a]; | |
| qcom,core-supply-entries { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| qcom,core-supply-entry@0 { | |
| qcom,supply-name = "refgen"; | |
| qcom,supply-disable-load = <0x00>; | |
| qcom,supply-max-voltage = <0x00>; | |
| qcom,supply-enable-load = <0x00>; | |
| qcom,supply-min-voltage = <0x00>; | |
| reg = <0x00>; | |
| }; | |
| }; | |
| qcom,ctrl-supply-entries { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| qcom,ctrl-supply-entry@0 { | |
| qcom,supply-name = "vdda-1p2"; | |
| qcom,supply-disable-load = <0x04>; | |
| qcom,supply-max-voltage = <0x124f80>; | |
| qcom,supply-enable-load = <0x5528>; | |
| qcom,supply-min-voltage = <0x124f80>; | |
| reg = <0x00>; | |
| }; | |
| }; | |
| qcom,phy-supply-entries { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| qcom,phy-supply-entry@0 { | |
| qcom,supply-name = "vdda-0p9"; | |
| qcom,supply-disable-load = <0x20>; | |
| qcom,supply-max-voltage = <0xd6d80>; | |
| qcom,supply-enable-load = <0x8ca0>; | |
| qcom,supply-min-voltage = <0xd6d80>; | |
| reg = <0x00>; | |
| }; | |
| }; | |
| }; | |
| rpmh-regulator-ldoa6 { | |
| qcom,supported-modes = <0x02 0x04>; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "ldoa6"; | |
| mboxes = <0x8a 0x00>; | |
| qcom,regulator-type = "pmic4-ldo"; | |
| qcom,mode-threshold-currents = <0x00 0x01>; | |
| regulator-l6 { | |
| qcom,init-mode = <0x02>; | |
| phandle = <0x33c>; | |
| qcom,init-voltage = <0x1c5200>; | |
| regulator-min-microvolt = <0x1c5200>; | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x1c5200>; | |
| regulator-name = "pm8998_l6"; | |
| }; | |
| }; | |
| dcc_v2@10a2000 { | |
| compatible = "qcom,dcc-v2"; | |
| reg-names = "dcc-base\0dcc-ram-base"; | |
| qcom,link-list = <0x00 0x1740300 0x06 0x00 0x00 0x1620500 0x04 0x00 0x00 0x7840000 0x01 0x00 0x00 0x7841010 0x0c 0x00 0x00 0x7842000 0x10 0x00 0x00 0x7842500 0x02 0x00 0x02 0x07 0x00 0x00 0x00 0x7841000 0x01 0x00 0x02 0x01 0x00 0x00 0x02 0xa5 0x00 0x00 0x00 0x7841008 0x02 0x00 0x02 0x01 0x00 0x00 0x00 0x17dc3a84 0x02 0x00 0x00 0x17db3a84 0x01 0x00 0x00 0x1301000 0x02 0x00 0x00 0x17990044 0x01 0x00 0x00 0x17d45f00 0x01 0x00 0x00 0x17d45f08 0x06 0x00 0x00 0x17d45f80 0x01 0x00 0x00 0x17d47418 0x01 0x00 0x00 0x17d47570 0x01 0x00 0x00 0x17d47588 0x01 0x00 0x00 0x17d43700 0x01 0x00 0x00 0x17d43708 0x06 0x00 0x00 0x17d43780 0x01 0x00 0x00 0x17d44c18 0x01 0x00 0x00 0x17d44d70 0x01 0x00 0x00 0x17d44d88 0x01 0x00 0x00 0x17d41700 0x01 0x00 0x00 0x17d41708 0x06 0x00 0x00 0x17d41780 0x01 0x00 0x00 0x17d42c18 0x01 0x00 0x00 0x17d42d70 0x01 0x00 0x00 0x17d42d88 0x01 0x00 0x01 0x69ea00c 0x600007 0x01 0x01 0x69ea01c 0x136800 0x01 0x00 0x69ea014 0x01 0x01 0x01 0x69ea01c 0x136810 0x01 0x00 0x69ea014 0x01 0x01 0x01 0x69ea01c 0x136820 0x01 0x00 0x69ea014 0x01 0x01 0x01 0x69ea01c 0x136830 0x01 0x00 0x69ea014 0x01 0x01 0x01 0x69ea01c 0x136840 0x01 0x00 0x69ea014 0x01 0x01 0x01 0x69ea01c 0x136850 0x01 0x00 0x69ea014 0x01 0x01 0x01 0x69ea01c 0x136860 0x01 0x00 0x69ea014 0x01 0x01 0x01 0x69ea01c 0x136870 0x01 0x00 0x69ea014 0x01 0x01 0x01 0x69ea01c 0x3e9a0 0x01 0x01 0x69ea01c 0x1368a0 0x01 0x00 0x69ea014 0x01 0x01 0x01 0x69ea01c 0x3c0a0 0x01 0x01 0x69ea01c 0x1368a0 0x01 0x00 0x69ea014 0x01 0x01 0x01 0x69ea01c 0x3d1a0 0x01 0x01 0x69ea01c 0x1368a0 0x01 0x00 0x69ea014 0x01 0x01 0x01 0x69ea01c 0x3d2a0 0x01 0x01 0x69ea01c 0x1368a0 0x01 0x00 0x69ea014 0x01 0x01 0x01 0x69ea01c 0x3d5a0 0x01 0x01 0x69ea01c 0x1368a0 0x01 0x00 0x69ea014 0x01 0x01 0x01 0x69ea01c 0x3d6a0 0x01 0x01 0x69ea01c 0x1368a0 0x01 0x00 0x69ea014 0x01 0x01 0x01 0x69ea01c 0x1368a0 0x01 0x01 0x69ea01c 0x1368a0 0x01 0x00 0x69ea014 0x01 0x01 0x01 0x69ea01c 0x3b1a0 0x01 0x01 0x69ea01c 0x1368a0 0x01 0x00 0x69ea014 0x01 0x01 0x01 0x69ea01c 0x3b2a0 0x01 0x01 0x69ea01c 0x1368a0 0x01 0x00 0x69ea014 0x01 0x01 0x01 0x69ea01c 0x3b5a0 0x01 0x01 0x69ea01c 0x1368a0 0x01 0x00 0x69ea014 0x01 0x01 0x01 0x69ea01c 0x3b6a0 0x01 0x01 0x69ea01c 0x1368a0 0x01 0x00 0x69ea014 0x01 0x01 0x01 0x69ea01c 0x3c2a0 0x01 0x01 0x69ea01c 0x1368a0 0x01 0x00 0x69ea014 0x01 0x01 0x01 0x69ea01c 0x3c5a0 0x01 0x01 0x69ea01c 0x1368a0 0x01 0x00 0x69ea014 0x01 0x01 0x01 0x69ea01c 0x3c6a0 0x01 0x01 0x69ea01c 0x1368a0 0x01 0x00 0x69ea014 0x01 0x01 0x01 0x69ea01c 0xf1e000 0x01 0x01 0x69ea008 0x07 0x01 0x00 0x13e7e00 0x1f 0x00 0x00 0x1132100 0x01 0x00 0x00 0x1136044 0x04 0x00 0x00 0x11360b0 0x01 0x00 0x00 0x113e030 0x02 0x00 0x00 0x1141000 0x01 0x00 0x00 0x1148058 0x04 0x00 0x00 0x1160410 0x03 0x00 0x00 0x11604a0 0x01 0x00 0x00 0x11604b8 0x01 0x00 0x00 0x1165804 0x01 0x00 0x00 0x1166418 0x01 0x00 0x00 0x11b2100 0x01 0x00 0x00 0x11b6044 0x04 0x00 0x00 0x11be030 0x02 0x00 0x00 0x11c1000 0x01 0x00 0x00 0x11c8058 0x04 0x00 0x00 0x11e0410 0x03 0x00 0x00 0x11e04a0 0x01 0x00 0x00 0x11e04b8 0x01 0x00 0x00 0x11e5804 0x01 0x00 0x00 0x11e6418 0x01 0x00 0x00 0x1232100 0x01 0x00 0x00 0x1236044 0x04 0x00 0x00 0x12360b0 0x01 0x00 0x00 0x123e030 0x02 0x00 0x00 0x1241000 0x01 0x00 0x00 0x1248058 0x04 0x00 0x00 0x1260410 0x03 0x00 0x00 0x12604a0 0x01 0x00 0x00 0x12604b8 0x01 0x00 0x00 0x1265804 0x01 0x00 0x00 0x1266418 0x01 0x00 0x00 0x12b2100 0x01 0x00 0x00 0x12b6044 0x03 0x00 0x00 0x12b6050 0x01 0x00 0x00 0x12b60b0 0x01 0x00 0x00 0x12be030 0x02 0x00 0x00 0x12c1000 0x01 0x00 0x00 0x12c8058 0x04 0x00 0x00 0x12e0410 0x03 0x00 0x00 0x12e04a0 0x01 0x00 0x00 0x12e04b8 0x01 0x00 0x00 0x12e5804 0x01 0x00 0x00 0x12e6418 0x01 0x00 0x00 0x1380900 0x08 0x00 0x00 0x1380d00 0x05 0x00 0x00 0x1430280 0x01 0x00 0x00 0x1430288 0x01 0x00 0x00 0x143028c 0x07 0x00 0x00 0x1132100 0x01 0x00 0x00 0x1136044 0x04 0x00 0x00 0x11360b0 0x01 0x00 0x00 0x113e030 0x02 0x00 0x00 0x1141000 0x01 0x00 0x00 0x1148058 0x04 0x00 0x00 0x1160410 0x03 0x00 0x00 0x11604a0 0x01 0x00 0x00 0x11604b8 0x01 0x00 0x00 0x1165804 0x01 0x00 0x00 0x1166418 0x01 0x00 0x00 0x11b2100 0x01 0x00 0x00 0x11b6044 0x04 0x00 0x00 0x11be030 0x02 0x00 0x00 0x11c1000 0x01 0x00 0x00 0x11c8058 0x04 0x00 0x00 0x11e0410 0x03 0x00 0x00 0x11e04a0 0x01 0x00 0x00 0x11e04b8 0x01 0x00 0x00 0x11e5804 0x01 0x00 0x00 0x11e6418 0x01 0x00 0x00 0x1232100 0x01 0x00 0x00 0x1236044 0x04 0x00 0x00 0x12360b0 0x01 0x00 0x00 0x123e030 0x02 0x00 0x00 0x1241000 0x01 0x00 0x00 0x1248058 0x04 0x00 0x00 0x1260410 0x03 0x00 0x00 0x12604a0 0x01 0x00 0x00 0x12604b8 0x01 0x00 0x00 0x1265804 0x01 0x00 0x00 0x1266418 0x01 0x00 0x00 0x12b2100 0x01 0x00 0x00 0x12b6044 0x03 0x00 0x00 0x12b6050 0x01 0x00 0x00 0x12b60b0 0x01 0x00 0x00 0x12be030 0x02 0x00 0x00 0x12c1000 0x01 0x00 0x00 0x12c8058 0x04 0x00 0x00 0x12e0410 0x03 0x00 0x00 0x12e04a0 0x01 0x00 0x00 0x12e04b8 0x01 0x00 0x00 0x12e5804 0x01 0x00 0x00 0x12e6418 0x01 0x00 0x00 0x1380900 0x08 0x00 0x00 0x1380d00 0x05 0x00 0x00 0x1430280 0x01 0x00 0x00 0x1430288 0x01 0x00 0x00 0x143028c 0x07 0x00 0x00 0xc201244 0x01 0x00 0x00 0xc202244 0x01 0x00>; | |
| qcom,curr-link-list = <0x02>; | |
| phandle = <0x32e>; | |
| reg = <0x10a2000 0x1000 0x10ae000 0x2000>; | |
| dcc-ram-offset = <0x6000>; | |
| }; | |
| qcom,msm-cdsp-loader { | |
| compatible = "qcom,cdsp-loader"; | |
| qcom,proc-img-to-load = "cdsp"; | |
| }; | |
| qcom,msm-ssc-sensors { | |
| compatible = "qcom,msm-ssc-sensors"; | |
| qcom,firmware-name = "slpi"; | |
| status = "ok"; | |
| phandle = <0x320>; | |
| }; | |
| tz-log@146bf720 { | |
| hyplog-size-offset = <0x414>; | |
| compatible = "qcom,tz-log"; | |
| phandle = <0x325>; | |
| reg = <0x146bf720 0x3000>; | |
| qcom,hyplog-enabled; | |
| hyplog-address-offset = <0x410>; | |
| }; | |
| qcom,smp2pgpio_client_rdbg_1_out { | |
| gpios = <0x26 0x00 0x00>; | |
| compatible = "qcom,smp2pgpio_client_rdbg_1_out"; | |
| }; | |
| qcom,ssc@5c00000 { | |
| qcom,proxy-timeout-ms = <0x2710>; | |
| compatible = "qcom,pil-tz-generic"; | |
| qcom,vdd_cx-uV-uA = <0x181 0x00>; | |
| clocks = <0x21 0x00>; | |
| qcom,proxy-clock-names = "xo"; | |
| qcom,firmware-name = "slpi"; | |
| qcom,gpio-proxy-unvote = <0xb8 0x02 0x00>; | |
| qcom,gpio-stop-ack = <0xb8 0x03 0x00>; | |
| clock-names = "xo"; | |
| qcom,gpio-err-ready = <0xb8 0x01 0x00>; | |
| qcom,smem-id = <0x1a8>; | |
| qcom,pas-id = <0x0c>; | |
| qcom,gpio-err-fatal = <0xb8 0x00 0x00>; | |
| vdd_cx-supply = <0xb5>; | |
| vdd_mx-supply = <0xb6>; | |
| status = "ok"; | |
| interrupts = <0x00 0x1ee 0x01>; | |
| qcom,vdd_mx-uV-uA = <0x181 0x00>; | |
| mbox-names = "slpi-pil"; | |
| memory-region = <0xb7>; | |
| mboxes = <0x80 0x00>; | |
| qcom,proxy-reg-names = "vdd_cx\0vdd_mx"; | |
| qcom,ssctl-instance-id = <0x16>; | |
| reg = <0x5c00000 0x4000>; | |
| qcom,signal-aop; | |
| qcom,gpio-force-stop = <0xb9 0x00 0x00>; | |
| qcom,sysmon-id = <0x03>; | |
| qcom,keep-proxy-regs-on; | |
| }; | |
| qcom,msm-dai-tdm-pri-rx { | |
| compatible = "qcom,msm-dai-tdm"; | |
| qcom,msm-cpudai-tdm-group-port-id = <0x9000>; | |
| qcom,msm-cpudai-tdm-clk-internal = <0x01>; | |
| qcom,msm-cpudai-tdm-sync-mode = <0x01>; | |
| qcom,msm-cpudai-tdm-clk-rate = <0x177000>; | |
| qcom,msm-cpudai-tdm-data-out = <0x00>; | |
| qcom,msm-cpudai-tdm-data-delay = <0x01>; | |
| qcom,msm-cpudai-tdm-group-id = <0x9100>; | |
| qcom,msm-cpudai-tdm-invert-sync = <0x01>; | |
| qcom,msm-cpudai-tdm-group-num-ports = <0x01>; | |
| qcom,msm-cpudai-tdm-sync-src = <0x01>; | |
| qcom,msm-dai-q6-tdm-pri-rx-0 { | |
| compatible = "qcom,msm-dai-q6-tdm"; | |
| qcom,msm-cpudai-tdm-dev-id = <0x9000>; | |
| phandle = <0x2a2>; | |
| qcom,msm-cpudai-tdm-data-align = <0x00>; | |
| }; | |
| }; | |
| qcom,smp2pgpio_test_smp2p_1_in { | |
| gpios = <0x1b2 0x00 0x00>; | |
| compatible = "qcom,smp2pgpio_test_smp2p_1_in"; | |
| }; | |
| qcom,camera-flash@2 { | |
| compatible = "qcom,camera-flash"; | |
| flash-source = <0x514>; | |
| status = "ok"; | |
| torch-source = <0x515>; | |
| phandle = <0x56f>; | |
| reg = <0x02 0x00>; | |
| switch-source = <0x516>; | |
| cell-index = <0x02>; | |
| }; | |
| qcom,smp2pgpio-rdbg-2-out { | |
| compatible = "qcom,smp2pgpio"; | |
| gpio-controller; | |
| #interrupt-cells = <0x02>; | |
| phandle = <0x24>; | |
| qcom,entry-name = "rdbg"; | |
| #gpio-cells = <0x02>; | |
| qcom,remote-pid = <0x02>; | |
| interrupt-controller; | |
| }; | |
| tpdm@6830000 { | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "tpdm-base"; | |
| coresight-name = "coresight-tpdm-modem"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x363>; | |
| arm,primecell-periphid = <0x3b968>; | |
| reg = <0x6830000 0x1000>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x158>; | |
| phandle = <0x157>; | |
| }; | |
| }; | |
| }; | |
| i2c@a8c000 { | |
| compatible = "qcom,i2c-geni"; | |
| clocks = <0x22 0x62 0x22 0x6e 0x22 0x6f>; | |
| qcom,wrapper-core = <0x5b>; | |
| pinctrl-1 = <0x66>; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| status = "disabled"; | |
| #address-cells = <0x01>; | |
| interrupts = <0x00 0x164 0x00>; | |
| #size-cells = <0x00>; | |
| dma-names = "tx\0rx"; | |
| phandle = <0x2e1>; | |
| reg = <0xa8c000 0x4000>; | |
| pinctrl-0 = <0x65>; | |
| dmas = <0x5e 0x00 0x03 0x03 0x40 0x00 0x5e 0x01 0x03 0x03 0x40 0x00>; | |
| pinctrl-names = "default\0sleep"; | |
| }; | |
| tpda@6882000 { | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "tpda-base"; | |
| coresight-name = "coresight-tpda-spss"; | |
| clock-names = "apb_pclk"; | |
| qcom,dsb-elem-size = <0x00 0x20>; | |
| phandle = <0x37c>; | |
| arm,primecell-periphid = <0x3b969>; | |
| reg = <0x6882000 0x1000>; | |
| qcom,tpda-atid = <0x46>; | |
| ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@1 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x17c>; | |
| phandle = <0x17d>; | |
| slave-mode; | |
| }; | |
| }; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x17b>; | |
| phandle = <0x17f>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,gdsc@0x17d044 { | |
| compatible = "qcom,gdsc"; | |
| status = "ok"; | |
| phandle = <0x1a8>; | |
| reg = <0x17d044 0x04>; | |
| qcom,no-status-check-on-disable; | |
| qcom,gds-timeout = <0x1f4>; | |
| regulator-name = "hlos1_vote_mmnoc_mmu_tbu_sf_gdsc"; | |
| }; | |
| qcom,mdss_mdp@ae00000 { | |
| qcom,sde-reg-dma-off = <0x00>; | |
| sde-vdd-supply = <0x19>; | |
| qcom,sde-sspp-xin-id = <0x00 0x04 0x08 0x0c 0x01 0x05 0x09 0x0d>; | |
| qcom,sde-vbif-memtype-0 = <0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03>; | |
| qcom,sde-smart-panel-align-mode = <0x0c>; | |
| qcom,sde-mixer-blendstages = <0x0b>; | |
| qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98 0xb0 0xc8 0xe0 0xf8 0x110>; | |
| compatible = "qcom,sde-kms"; | |
| qcom,sde-has-dim-layer; | |
| qcom,sde-dest-scaler-size = <0x800>; | |
| qcom,sde-dest-scaler-top-off = <0x61000>; | |
| clocks = <0x22 0x1b 0x22 0x1c 0x20 0x00 0x20 0x01 0x20 0x17 0x20 0x24>; | |
| qcom,sde-ubwc-version = <0x200>; | |
| qcom,sde-dither-off = <0x30e0 0x30e0 0x30e0 0x30e0 0x00>; | |
| qcom,sde-pp-off = <0x71000 0x71800 0x72000 0x72800 0x73000>; | |
| qcom,sde-wb-xin-id = <0x06>; | |
| qcom,sde-ctl-size = <0xe4>; | |
| qcom,sde-ctl-display-pref = "primary\0none\0none\0none\0none"; | |
| qcom,sde-sspp-excl-rect = <0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01>; | |
| qcom,sde-cdm-off = <0x7a200>; | |
| qcom,sde-mixer-pair-mask = <0x02 0x01 0x06 0x00 0x00 0x03>; | |
| reg-names = "mdp_phys\0vbif_phys\0regdma_phys"; | |
| qcom,sde-len = <0x45c>; | |
| qcom,sde-wb-linewidth = <0x1000>; | |
| qcom,sde-panic-per-pipe; | |
| qcom,sde-qos-lut-nrt = <0x00 0x00 0x00>; | |
| qcom,sde-min-core-ib-kbps = "\0I>"; | |
| qcom,sde-dram-channels = <0x02>; | |
| connectors = <0x2bf 0x4fa 0x2c7>; | |
| qcom,sde-mixer-off = <0x45000 0x46000 0x47000 0x00 0x00 0x4a000>; | |
| qcom,sde-wb-clk-ctrl = <0x3b8 0x18>; | |
| qcom,sde-has-idle-pc; | |
| clock-names = "gcc_iface\0gcc_bus\0iface_clk\0bus_clk\0core_clk\0vsync_clk"; | |
| qcom,sde-dest-scaler-top-size = <0x0c>; | |
| qcom,sde-danger-lut = <0x0f 0xffff 0x00 0x00>; | |
| qcom,sde-dspp-top-size = <0x0c>; | |
| qcom,sde-sspp-csc-off = <0x1a00>; | |
| qcom,sde-safe-lut-cwb = <0x00 0xffff>; | |
| qcom,sde-wb-off = <0x66000>; | |
| qcom,sde-inline-rot-xin = <0x0a 0x0b>; | |
| qcom,sde-pp-slave = <0x00 0x00 0x00 0x00 0x01>; | |
| qcom,sde-cdm-size = <0x224>; | |
| qcom,sde-max-bw-low-kbps = <0x927c00>; | |
| qcom,sde-dspp-size = <0x17e0>; | |
| qcom,sde-vbif-id = <0x00>; | |
| qcom,sde-max-dest-scaler-output-linewidth = <0xa00>; | |
| qcom,sde-dither-size = <0x20>; | |
| qcom,sde-vbif-memtype-1 = <0x03 0x03 0x03 0x03 0x03 0x03>; | |
| qcom,sde-pp-size = <0xd4>; | |
| #interrupt-cells = <0x01>; | |
| qcom,sde-max-dest-scaler-input-linewidth = <0x800>; | |
| interrupt-parent = <0x01>; | |
| #address-cells = <0x01>; | |
| qcom,sde-mixer-linewidth = <0xa00>; | |
| qcom,sde-sspp-src-size = <0x1c8>; | |
| qcom,sde-safe-lut-linear = <0x04 0xfff8 0x00 0xfff0>; | |
| interrupts = <0x00 0x53 0x00>; | |
| qcom,sde-dspp-off = <0x55000 0x57000 0x59000 0x5b000>; | |
| qcom,sde-mixer-size = <0x320>; | |
| clock-rate = <0x00 0x00 0x00 0x00 0x11e1a300 0x124f800 0x00>; | |
| qcom,sde-has-cdp; | |
| qcom,sde-highest-bank-bit = <0x02>; | |
| qcom,sde-sspp-smart-dma-priority = <0x05 0x06 0x07 0x08 0x01 0x02 0x03 0x04>; | |
| #size-cells = <0x00>; | |
| qcom,sde-reg-dma-trigger-off = <0x119c>; | |
| qcom,sde-te2-off = <0x2000 0x2000 0x00 0x00 0x00>; | |
| qcom,sde-smart-dma-rev = "smart_dma_v2"; | |
| qcom,sde-qos-cpu-dma-latency = <0x12c>; | |
| phandle = <0x2c>; | |
| qcom,sde-off = <0x1000>; | |
| qcom,sde-sspp-qseed-off = <0xa00>; | |
| qcom,sde-vbif-off = <0x00>; | |
| qcom,sde-safe-lut-macrotile = <0x0a 0xfe00 0x0b 0xfc00 0x0c 0xf800 0x00 0xf000>; | |
| qcom,sde-ctl-off = <0x2000 0x2200 0x2400 0x2600 0x2800>; | |
| qcom,sde-wb-id = <0x02>; | |
| qcom,sde-vbif-qos-rt-remap = <0x03 0x03 0x04 0x04 0x05 0x05 0x06 0x06>; | |
| qcom,sde-has-src-split; | |
| qcom,sde-safe-lut-nrt = <0x00 0xffff>; | |
| qcom,sde-sspp-clk-ctrl = <0x2ac 0x00 0x2b4 0x00 0x2bc 0x00 0x2c4 0x00 0x2ac 0x08 0x2b4 0x08 0x2bc 0x08 0x2c4 0x08>; | |
| qcom,sde-min-dram-ib-kbps = "\0\f5"; | |
| qcom,sde-qos-lut-linear = <0x04 0x00 0x357 0x05 0x00 0x3357 0x06 0x00 0x23357 0x07 0x00 0x223357 0x08 0x00 0x2223357 0x09 0x00 0x22223357 0x0a 0x02 0x22223357 0x0b 0x22 0x22223357 0x0c 0x222 0x22223357 0x0d 0x2222 0x22223357 0x0e 0x12222 0x22223357 0x00 0x112222 0x22223357>; | |
| qcom,sde-dspp-ad-off = <0x28000 0x27000>; | |
| reg = <0xae00000 0x81d40 0xaeb0000 0x2008 0xaeac000 0xf0>; | |
| qcom,sde-qos-cpu-mask = <0x03>; | |
| qcom,sde-inline-rot-clk-ctrl = <0x2bc 0x08 0x2bc 0x0c>; | |
| iommus = <0x29 0x880 0x08 0x29 0xc80 0x08>; | |
| qcom,sde-intf-type = "dp\0dsi\0dsi\0dp"; | |
| qcom,sde-sspp-off = <0x5000 0x7000 0x9000 0xb000 0x25000 0x27000 0x29000 0x2b000>; | |
| qcom,sde-dspp-ad-version = <0x40000>; | |
| qcom,sde-min-llcc-ib-kbps = "\0\f5"; | |
| qcom,sde-cdp-setting = <0x01 0x01 0x01 0x00>; | |
| qcom,sde-vbif-qos-nrt-remap = <0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03>; | |
| qcom,sde-dither-version = <0x10000>; | |
| #cooling-cells = <0x02>; | |
| qcom,sde-intf-off = <0x6b000 0x6b800 0x6c000 0x6c800>; | |
| qcom,sde-max-bw-high-kbps = <0x927c00>; | |
| qcom,sde-num-nrt-paths = <0x00>; | |
| qcom,sde-dsc-off = <0x81000 0x81400 0x81800 0x81c00>; | |
| qcom,sde-has-dest-scaler; | |
| qcom,sde-wb-size = <0x2c8>; | |
| qcom,sde-inline-rot-xin-type = "sspp\0wb"; | |
| qcom,sde-intf-size = <0x280>; | |
| qcom,sde-inline-rotator = <0x2a 0x00>; | |
| qcom,sde-dspp-top-off = <0x1300>; | |
| qcom,sde-qos-lut-cwb = <0x00 0x75300000 0x00>; | |
| qcom,sde-sspp-type = "vig\0vig\0vig\0vig\0dma\0dma\0dma\0dma"; | |
| qcom,sde-vbif-size = <0x1040>; | |
| qcom,sde-qseed-type = "qseedv3"; | |
| #power-domain-cells = <0x00>; | |
| qcom,sde-dest-scaler-off = <0x800 0x1000>; | |
| qcom,sde-qos-lut-macrotile = <0x0a 0x03 0x44556677 0x0b 0x33 0x44556677 0x0c 0x233 0x44556677 0x0d 0x2233 0x44556677 0x0e 0x12233 0x44556677 0x00 0x112233 0x44556677>; | |
| qcom,sde-dsc-size = <0x140>; | |
| qcom,sde-sspp-linewidth = <0xa00>; | |
| interrupt-controller; | |
| clock-max-rate = <0x00 0x00 0x00 0x00 0x19a14780 0x124f800 0x00>; | |
| qcom,sde-mixer-display-pref = "primary\0none\0none\0none\0none\0none"; | |
| qcom,sde-reg-dma-version = <0x01>; | |
| qcom,sde-csc-type = "csc-10bit"; | |
| qcom,sde-data-bus { | |
| qcom,msm-bus,num-paths = <0x02>; | |
| qcom,msm-bus,num-cases = <0x03>; | |
| qcom,msm-bus,vectors-KBps = <0x16 0x200 0x00 0x00 0x17 0x200 0x00 0x00 0x16 0x200 0x00 0x61a800 0x17 0x200 0x00 0x61a800 0x16 0x200 0x00 0x61a800 0x17 0x200 0x00 0x61a800>; | |
| qcom,msm-bus,name = "mdss_sde"; | |
| }; | |
| qcom,mdss_dsi_nt35597_truly_wqxga_cmd { | |
| qcom,esd-check-enabled; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-color-order = "rgb_swap_rgb"; | |
| qcom,mdss-dsi-t-clk-pre = <0x2d>; | |
| qcom,mdss-dsi-bl-min-level = <0x01>; | |
| qcom,mdss-dsi-panel-name = "Dual nt35597 cmd mode dsi truly panel without DSC"; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-panel-status-check-mode = "reg_read"; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; | |
| qcom,mdss-dsi-te-check-enable; | |
| qcom,mdss-dsi-te-pin-select = <0x01>; | |
| qcom,mdss-dsi-te-using-te-pin; | |
| qcom,mdss-dsi-panel-hdr-enabled; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,ulps-enabled; | |
| qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; | |
| qcom,mdss-dsi-te-dcs-command = <0x01>; | |
| qcom,mdss-dsi-mode-sel-gpio-state = "dual_port"; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-panel-peak-brightness = <0x401640>; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-panel-status-read-length = <0x01>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-pan-physical-width-dimension = <0x4a>; | |
| qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| phandle = <0x4e8>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
| qcom,mdss-dsi-panel-status-value = <0x9c>; | |
| qcom,mdss-pan-physical-height-dimension = <0x83>; | |
| qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; | |
| qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
| qcom,mdss-dsi-panel-blackness-level = <0xc9e>; | |
| qcom,mdss-dsi-bl-max-level = <0xfff>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,platform-te-gpio = <0x34 0x0a 0x00>; | |
| qcom,panel-supply-entries = <0x4de>; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,mdss-dsi-panel-on-check-value = <0x9c>; | |
| qcom,platform-reset-gpio = <0x34 0x06 0x00>; | |
| qcom,adjust-timer-wakeup-ms = <0x01>; | |
| qcom,mdss-dsi-t-clk-post = <0x0d>; | |
| qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@0 { | |
| qcom,mdss-dsi-on-command = [15 01 00 00 00 00 02 ff 20 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 01 15 01 00 00 00 00 02 01 55 15 01 00 00 00 00 02 02 45 15 01 00 00 00 00 02 05 40 15 01 00 00 00 00 02 06 19 15 01 00 00 00 00 02 07 1e 15 01 00 00 00 00 02 0b 73 15 01 00 00 00 00 02 0c 73 15 01 00 00 00 00 02 0e b0 15 01 00 00 00 00 02 0f ae 15 01 00 00 00 00 02 11 b8 15 01 00 00 00 00 02 13 00 15 01 00 00 00 00 02 58 80 15 01 00 00 00 00 02 59 01 15 01 00 00 00 00 02 5a 00 15 01 00 00 00 00 02 5b 01 15 01 00 00 00 00 02 5c 80 15 01 00 00 00 00 02 5d 81 15 01 00 00 00 00 02 5e 00 15 01 00 00 00 00 02 5f 01 15 01 00 00 00 00 02 72 11 15 01 00 00 00 00 02 68 03 15 01 00 00 00 00 02 ff 24 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 1c 15 01 00 00 00 00 02 01 0b 15 01 00 00 00 00 02 02 0c 15 01 00 00 00 00 02 03 01 15 01 00 00 00 00 02 04 0f 15 01 00 00 00 00 02 05 10 15 01 00 00 00 00 02 06 10 15 01 00 00 00 00 02 07 10 15 01 00 00 00 00 02 08 89 15 01 00 00 00 00 02 09 8a 15 01 00 00 00 00 02 0a 13 15 01 00 00 00 00 02 0b 13 15 01 00 00 00 00 02 0c 15 15 01 00 00 00 00 02 0d 15 15 01 00 00 00 00 02 0e 17 15 01 00 00 00 00 02 0f 17 15 01 00 00 00 00 02 10 1c 15 01 00 00 00 00 02 11 0b 15 01 00 00 00 00 02 12 0c 15 01 00 00 00 00 02 13 01 15 01 00 00 00 00 02 14 0f 15 01 00 00 00 00 02 15 10 15 01 00 00 00 00 02 16 10 15 01 00 00 00 00 02 17 10 15 01 00 00 00 00 02 18 89 15 01 00 00 00 00 02 19 8a 15 01 00 00 00 00 02 1a 13 15 01 00 00 00 00 02 1b 13 15 01 00 00 00 00 02 1c 15 15 01 00 00 00 00 02 1d 15 15 01 00 00 00 00 02 1e 17 15 01 00 00 00 00 02 1f 17 15 01 00 00 00 00 02 20 40 15 01 00 00 00 00 02 21 01 15 01 00 00 00 00 02 22 00 15 01 00 00 00 00 02 23 40 15 01 00 00 00 00 02 24 40 15 01 00 00 00 00 02 25 6d 15 01 00 00 00 00 02 26 40 15 01 00 00 00 00 02 27 40 15 01 00 00 00 00 02 e0 00 15 01 00 00 00 00 02 dc 21 15 01 00 00 00 00 02 dd 22 15 01 00 00 00 00 02 de 07 15 01 00 00 00 00 02 df 07 15 01 00 00 00 00 02 e3 6d 15 01 00 00 00 00 02 e1 07 15 01 00 00 00 00 02 e2 07 15 01 00 00 00 00 02 29 d8 15 01 00 00 00 00 02 2a 2a 15 01 00 00 00 00 02 4b 03 15 01 00 00 00 00 02 4c 11 15 01 00 00 00 00 02 4d 10 15 01 00 00 00 00 02 4e 01 15 01 00 00 00 00 02 4f 01 15 01 00 00 00 00 02 50 10 15 01 00 00 00 00 02 51 00 15 01 00 00 00 00 02 52 80 15 01 00 00 00 00 02 53 00 15 01 00 00 00 00 02 56 00 15 01 00 00 00 00 02 54 07 15 01 00 00 00 00 02 58 07 15 01 00 00 00 00 02 55 25 15 01 00 00 00 00 02 5b 43 15 01 00 00 00 00 02 5c 00 15 01 00 00 00 00 02 5f 73 15 01 00 00 00 00 02 60 73 15 01 00 00 00 00 02 63 22 15 01 00 00 00 00 02 64 00 15 01 00 00 00 00 02 67 08 15 01 00 00 00 00 02 68 04 15 01 00 00 00 00 02 72 02 15 01 00 00 00 00 02 7a 80 15 01 00 00 00 00 02 7b 91 15 01 00 00 00 00 02 7c d8 15 01 00 00 00 00 02 7d 60 15 01 00 00 00 00 02 7f 15 15 01 00 00 00 00 02 75 15 15 01 00 00 00 00 02 b3 c0 15 01 00 00 00 00 02 b4 00 15 01 00 00 00 00 02 b5 00 15 01 00 00 00 00 02 78 00 15 01 00 00 00 00 02 79 00 15 01 00 00 00 00 02 80 00 15 01 00 00 00 00 02 83 00 15 01 00 00 00 00 02 93 0a 15 01 00 00 00 00 02 94 0a 15 01 00 00 00 00 02 8a 00 15 01 00 00 00 00 02 9b ff 15 01 00 00 00 00 02 9d b0 15 01 00 00 00 00 02 9f 63 15 01 00 00 00 00 02 98 10 15 01 00 00 00 00 02 ec 00 15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 04 3b 03 0a 0a 15 01 00 00 00 00 02 35 00 15 01 00 00 00 00 02 e5 01 15 01 00 00 00 00 02 bb 10 15 01 00 00 00 00 02 c0 00 29 01 00 00 00 00 0c c9 01 01 70 00 0a 06 67 04 c5 12 18 15 01 00 00 00 00 02 fb 01 05 01 00 00 78 00 02 11 00 05 01 00 00 78 00 02 29 00]; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-h-back-porch = <0x20>; | |
| qcom,mdss-dsi-v-back-porch = <0x07>; | |
| qcom,mdss-dsi-panel-jitter = <0x01 0x01>; | |
| qcom,mdss-dsi-panel-width = <0x2d0>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-h-front-porch = <0x64>; | |
| qcom,partial-update-enabled = "single_roi"; | |
| qcom,mdss-dsi-v-front-porch = <0x08>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsi-panel-height = <0xa00>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,display-topology = <0x02 0x00 0x02 0x01 0x00 0x02>; | |
| qcom,panel-roi-alignment = <0x2d0 0x80 0x2d0 0x80 0x5a0 0x80>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = <0x1c0707 0x23210707 0x5030400>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x10>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| }; | |
| }; | |
| }; | |
| qcom,platform-supply-entries { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| qcom,platform-supply-entry@0 { | |
| qcom,supply-name = "sde-vdd"; | |
| qcom,supply-disable-load = <0x00>; | |
| qcom,supply-max-voltage = <0x00>; | |
| qcom,supply-enable-load = <0x00>; | |
| qcom,supply-min-voltage = <0x00>; | |
| reg = <0x00>; | |
| }; | |
| }; | |
| qcom,mdss_dsi_nt35597_dsc_cmd_truly { | |
| qcom,esd-check-enabled; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-color-order = "rgb_swap_rgb"; | |
| qcom,mdss-dsi-t-clk-pre = <0x23>; | |
| qcom,mdss-dsi-bl-min-level = <0x01>; | |
| qcom,mdss-dsi-panel-name = "nt35597 cmd mode dsi truly panel with DSC"; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-panel-status-check-mode = "reg_read"; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; | |
| qcom,mdss-dsi-te-check-enable; | |
| qcom,mdss-dsi-te-pin-select = <0x01>; | |
| qcom,mdss-dsi-te-using-te-pin; | |
| qcom,mdss-dsi-panel-hdr-enabled; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,ulps-enabled; | |
| qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; | |
| qcom,mdss-dsi-te-dcs-command = <0x01>; | |
| qcom,mdss-dsi-mode-sel-gpio-state = "single_port"; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-panel-peak-brightness = <0x401640>; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-panel-status-read-length = <0x01>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-pan-physical-width-dimension = <0x4a>; | |
| qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| phandle = <0x4e9>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
| qcom,mdss-dsi-panel-status-value = <0x9c>; | |
| qcom,mdss-pan-physical-height-dimension = <0x83>; | |
| qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; | |
| qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
| qcom,mdss-dsi-panel-blackness-level = <0xc9e>; | |
| qcom,mdss-dsi-bl-max-level = <0xfff>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,platform-te-gpio = <0x34 0x0a 0x00>; | |
| qcom,panel-supply-entries = <0x4de>; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,mdss-dsi-panel-on-check-value = <0x9c>; | |
| qcom,platform-reset-gpio = <0x34 0x06 0x00>; | |
| qcom,adjust-timer-wakeup-ms = <0x01>; | |
| qcom,mdss-dsi-t-clk-post = <0x0b>; | |
| qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@0 { | |
| qcom,mdss-dsi-on-command = <0x15010000 0x2ff 0x20150100 0x02 0xfb011501 0x00 0x2000115 0x1000000 0x20155 0x15010000 0x202 0x45150100 0x02 0x5401501 0x00 0x2061915 0x1000000 0x2071e 0x15010000 0x20b 0x73150100 0x02 0xc731501 0x00 0x20eb015 0x1000000 0x20fae 0x15010000 0x211 0xb8150100 0x02 0x13001501 0x00 0x2588015 0x1000000 0x25901 0x15010000 0x25a 0x150100 0x02 0x5b011501 0x00 0x25c8015 0x1000000 0x25d81 0x15010000 0x25e 0x150100 0x02 0x5f011501 0x00 0x2721115 0x1000000 0x26803 0x15010000 0x2ff 0x24150100 0x02 0xfb011501 0x00 0x2001c15 0x1000000 0x2010b 0x15010000 0x202 0xc150100 0x02 0x3011501 0x00 0x2040f15 0x1000000 0x20510 0x15010000 0x206 0x10150100 0x02 0x7101501 0x00 0x2088915 0x1000000 0x2098a 0x15010000 0x20a 0x13150100 0x02 0xb131501 0x00 0x20c1515 0x1000000 0x20d15 0x15010000 0x20e 0x17150100 0x02 0xf171501 0x00 0x2101c15 0x1000000 0x2110b 0x15010000 0x212 0xc150100 0x02 0x13011501 0x00 0x2140f15 0x1000000 0x21510 0x15010000 0x216 0x10150100 0x02 0x17101501 0x00 0x2188915 0x1000000 0x2198a 0x15010000 0x21a 0x13150100 0x02 0x1b131501 0x00 0x21c1515 0x1000000 0x21d15 0x15010000 0x21e 0x17150100 0x02 0x1f171501 0x00 0x2204015 0x1000000 0x22101 0x15010000 0x222 0x150100 0x02 0x23401501 0x00 0x2244015 0x1000000 0x2256d 0x15010000 0x226 0x40150100 0x02 0x27401501 0x00 0x2e00015 0x1000000 0x2dc21 0x15010000 0x2dd 0x22150100 0x02 0xde071501 0x00 0x2df0715 0x1000000 0x2e36d 0x15010000 0x2e1 0x7150100 0x02 0xe2071501 0x00 0x229d815 0x1000000 0x22a2a 0x15010000 0x24b 0x3150100 0x02 0x4c111501 0x00 0x24d1015 0x1000000 0x24e01 0x15010000 0x24f 0x1150100 0x02 0x50101501 0x00 0x2510015 0x1000000 0x25280 0x15010000 0x253 0x150100 0x02 0x56001501 0x00 0x2540715 0x1000000 0x25807 0x15010000 0x255 0x25150100 0x02 0x5b431501 0x00 0x25c0015 0x1000000 0x25f73 0x15010000 0x260 0x73150100 0x02 0x63221501 0x00 0x2640015 0x1000000 0x26708 0x15010000 0x268 0x4150100 0x02 0x72021501 0x00 0x27a8015 0x1000000 0x27b91 0x15010000 0x27c 0xd8150100 0x02 0x7d601501 0x00 0x27f1515 0x1000000 0x27515 0x15010000 0x2b3 0xc0150100 0x02 0xb4001501 0x00 0x2b50015 0x1000000 0x27800 0x15010000 0x279 0x150100 0x02 0x80001501 0x00 0x2830015 0x1000000 0x2930a 0x15010000 0x294 0xa150100 0x02 0x8a001501 0x00 0x29bff15 0x1000000 0x29db0 0x15010000 0x29f 0x63150100 0x02 0x98101501 0x00 0x2ec0015 0x1000000 0x2ff10 0x39010000 0x11c1 0x9200010 0x2000268 0x1bb000a 0x66704c5 0x39010000 0x3c2 0x10f01501 0x00 0x2c00315 0x1000000 0x43b03 0xa0a1501 0x00 0x2350015 0x1000000 0x2e501 0x15010000 0x2bb 0x10150100 0x02 0xfb010501 0x7800 0x2110005 0x1000078 0x22900>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,mdss-dsi-on-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-h-back-porch = <0x20>; | |
| qcom,mdss-dsi-v-back-porch = <0x08>; | |
| qcom,mdss-dsi-panel-jitter = <0x01 0x01>; | |
| qcom,mdss-dsi-panel-width = <0x5a0>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-h-front-porch = <0x64>; | |
| qcom,mdss-dsi-v-front-porch = <0x0a>; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x02>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsi-panel-height = <0xa00>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,display-topology = <0x01 0x01 0x01 0x02 0x02 0x01 0x02 0x01 0x01>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = <0x150505 0x201f0505 0x3030400>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x10>; | |
| qcom,mdss-dsi-v-pulse-width = <0x02>; | |
| qcom,mdss-dsc-slice-width = <0x2d0>; | |
| qcom,default-topology-index = <0x01>; | |
| qcom,mdss-dsc-slice-height = <0x10>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_nt35597_dsc_video_truly { | |
| qcom,esd-check-enabled; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-t-clk-pre = <0x23>; | |
| qcom,mdss-dsi-bl-min-level = <0x01>; | |
| qcom,mdss-dsi-panel-name = "nt35597 video mode dsi truly panel with DSC"; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-panel-status-check-mode = "reg_read"; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; | |
| qcom,mdss-dsi-pan-enable-dynamic-fps; | |
| qcom,mdss-dsi-panel-hdr-enabled; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; | |
| qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; | |
| qcom,mdss-dsi-dma-schedule-line = <0x05>; | |
| qcom,mdss-dsi-mode-sel-gpio-state = "single_port"; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-panel-peak-brightness = <0x401640>; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-panel-status-read-length = <0x01>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-pan-physical-width-dimension = <0x4a>; | |
| qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| phandle = <0x4ea>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
| qcom,mdss-dsi-panel-status-value = <0x9c>; | |
| qcom,mdss-pan-physical-height-dimension = <0x83>; | |
| qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; | |
| qcom,mdss-dsi-panel-blackness-level = <0xc9e>; | |
| qcom,mdss-dsi-bl-max-level = <0xfff>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,panel-supply-entries = <0x4de>; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,mdss-dsi-panel-on-check-value = <0x9c>; | |
| qcom,platform-reset-gpio = <0x34 0x06 0x00>; | |
| qcom,mdss-dsi-t-clk-post = <0x0b>; | |
| qcom,dsi-supported-dfps-list = <0x3c 0x37 0x35>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@0 { | |
| qcom,mdss-dsi-on-command = <0x15010000 0x2ff 0x20150100 0x02 0xfb011501 0x00 0x2000115 0x1000000 0x20155 0x15010000 0x202 0x45150100 0x02 0x5401501 0x00 0x2061915 0x1000000 0x2071e 0x15010000 0x20b 0x73150100 0x02 0xc731501 0x00 0x20eb015 0x1000000 0x20fae 0x15010000 0x211 0xb8150100 0x02 0x13001501 0x00 0x2588015 0x1000000 0x25901 0x15010000 0x25a 0x150100 0x02 0x5b011501 0x00 0x25c8015 0x1000000 0x25d81 0x15010000 0x25e 0x150100 0x02 0x5f011501 0x00 0x2721115 0x1000000 0x26803 0x15010000 0x2ff 0x24150100 0x02 0xfb011501 0x00 0x2001c15 0x1000000 0x2010b 0x15010000 0x202 0xc150100 0x02 0x3011501 0x00 0x2040f15 0x1000000 0x20510 0x15010000 0x206 0x10150100 0x02 0x7101501 0x00 0x2088915 0x1000000 0x2098a 0x15010000 0x20a 0x13150100 0x02 0xb131501 0x00 0x20c1515 0x1000000 0x20d15 0x15010000 0x20e 0x17150100 0x02 0xf171501 0x00 0x2101c15 0x1000000 0x2110b 0x15010000 0x212 0xc150100 0x02 0x13011501 0x00 0x2140f15 0x1000000 0x21510 0x15010000 0x216 0x10150100 0x02 0x17101501 0x00 0x2188915 0x1000000 0x2198a 0x15010000 0x21a 0x13150100 0x02 0x1b131501 0x00 0x21c1515 0x1000000 0x21d15 0x15010000 0x21e 0x17150100 0x02 0x1f171501 0x00 0x2204015 0x1000000 0x22101 0x15010000 0x222 0x150100 0x02 0x23401501 0x00 0x2244015 0x1000000 0x2256d 0x15010000 0x226 0x40150100 0x02 0x27401501 0x00 0x2e00015 0x1000000 0x2dc21 0x15010000 0x2dd 0x22150100 0x02 0xde071501 0x00 0x2df0715 0x1000000 0x2e36d 0x15010000 0x2e1 0x7150100 0x02 0xe2071501 0x00 0x229d815 0x1000000 0x22a2a 0x15010000 0x24b 0x3150100 0x02 0x4c111501 0x00 0x24d1015 0x1000000 0x24e01 0x15010000 0x24f 0x1150100 0x02 0x50101501 0x00 0x2510015 0x1000000 0x25280 0x15010000 0x253 0x150100 0x02 0x56001501 0x00 0x2540715 0x1000000 0x25807 0x15010000 0x255 0x25150100 0x02 0x5b431501 0x00 0x25c0015 0x1000000 0x25f73 0x15010000 0x260 0x73150100 0x02 0x63221501 0x00 0x2640015 0x1000000 0x26708 0x15010000 0x268 0x4150100 0x02 0x72021501 0x00 0x27a8015 0x1000000 0x27b91 0x15010000 0x27c 0xd8150100 0x02 0x7d601501 0x00 0x27f1515 0x1000000 0x27515 0x15010000 0x2b3 0xc0150100 0x02 0xb4001501 0x00 0x2b50015 0x1000000 0x27800 0x15010000 0x279 0x150100 0x02 0x80001501 0x00 0x2830015 0x1000000 0x2930a 0x15010000 0x294 0xa150100 0x02 0x8a001501 0x00 0x29bff15 0x1000000 0x29db0 0x15010000 0x29f 0x63150100 0x02 0x98101501 0x00 0x2ec0015 0x1000000 0x2ff10 0x39010000 0x11c1 0x9200010 0x2000268 0x1bb000a 0x66704c5 0x39010000 0x3c2 0x10f01501 0x00 0x2c00339 0x1000000 0x43b03 0xa0a1501 0x00 0x2350015 0x1000000 0x2e501 0x15010000 0x2bb 0x3150100 0x02 0xfb010501 0x7800 0x2110005 0x1000078 0x22900>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-h-back-porch = <0x20>; | |
| qcom,mdss-dsi-v-back-porch = <0x08>; | |
| qcom,mdss-dsi-panel-width = <0x5a0>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-h-front-porch = <0x64>; | |
| qcom,mdss-dsi-v-front-porch = <0x0a>; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x02>; | |
| qcom,mdss-dsi-panel-height = <0xa00>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,display-topology = <0x01 0x01 0x01 0x02 0x02 0x01 0x02 0x01 0x01>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = <0x150505 0x201f0504 0x3030400>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x10>; | |
| qcom,mdss-dsi-v-pulse-width = <0x02>; | |
| qcom,mdss-dsc-slice-width = <0x2d0>; | |
| qcom,default-topology-index = <0x01>; | |
| qcom,mdss-dsc-slice-height = <0x10>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| }; | |
| }; | |
| }; | |
| qcom,smmu_sde_sec_cb { | |
| compatible = "qcom,smmu_sde_sec"; | |
| phandle = <0x2be>; | |
| iommus = <0x29 0x881 0x08 0x29 0xc81 0x08>; | |
| }; | |
| qcom,mdss_dsi_nt36850_truly_wqhd_cmd { | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-color-order = "rgb_swap_rgb"; | |
| qcom,mdss-dsi-t-clk-pre = <0x30>; | |
| qcom,mdss-dsi-bl-min-level = <0x01>; | |
| qcom,mdss-dsi-panel-name = "Dual nt36850 cmd mode dsi truly panel without DSC"; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-lp11-init; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x32>; | |
| qcom,mdss-dsi-te-check-enable; | |
| qcom,mdss-dsi-tx-eot-append; | |
| qcom,mdss-dsi-te-pin-select = <0x01>; | |
| qcom,mdss-dsi-te-using-te-pin; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-te-dcs-command = <0x01>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| phandle = <0x4f3>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
| qcom,mdss-dsi-lane-map = "lane_map_0123"; | |
| qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
| qcom,mdss-dsi-bl-max-level = <0xfff>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,mdss-dsi-t-clk-post = <0x0e>; | |
| qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@0 { | |
| qcom,mdss-dsi-on-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 36 00 15 01 00 00 00 00 02 35 00 39 01 00 00 00 00 03 44 03 e8 15 01 00 00 00 00 02 51 ff 15 01 00 00 00 00 02 53 2c 15 01 00 00 00 00 02 55 01 05 01 00 00 0a 00 02 20 00 15 01 00 00 00 00 02 bb 10 05 01 00 00 78 00 02 11 00 05 01 00 00 78 00 02 29 00]; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-h-back-porch = <0x8c>; | |
| qcom,mdss-dsi-v-back-porch = <0x14>; | |
| qcom,mdss-dsi-panel-width = <0x2d0>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-h-front-porch = <0x78>; | |
| qcom,mdss-dsi-v-front-porch = <0x08>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsi-panel-height = <0xa00>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,display-topology = <0x02 0x00 0x02 0x01 0x00 0x02>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = <0x1f0808 0x24230808 0x5030400>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x14>; | |
| qcom,mdss-dsi-v-pulse-width = <0x04>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_sim_dsc_375_cmd { | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-color-order = "rgb_swap_rgb"; | |
| qcom,mdss-dsi-t-clk-pre = <0x2d>; | |
| qcom,mdss-dsi-panel-name = "Simulator cmd mode DSC 3.75:1 dsi panel"; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; | |
| qcom,mdss-dsi-te-check-enable; | |
| qcom,mdss-dsi-te-using-wd; | |
| qcom,mdss-dsi-te-pin-select = <0x01>; | |
| qcom,mdss-dsi-te-using-te-pin; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-te-dcs-command = <0x01>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| phandle = <0x4ef>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
| qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
| qcom,mdss-dsi-bl-max-level = <0xfff>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,panel-supply-entries = <0x4de>; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,platform-reset-gpio = <0x34 0x06 0x00>; | |
| qcom,adjust-timer-wakeup-ms = <0x01>; | |
| qcom,mdss-dsi-t-clk-post = <0x0d>; | |
| qcom,panel-ack-disabled; | |
| qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@1 { | |
| qcom,mdss-dsi-on-command = <0x15010000 0x2bb 0x10150100 0x02 0xb0030501 0x7800 0x1111501 0x00 0x251ff15 0x1000000 0x25324 0x15010000 0x2ff 0x23150100 0x02 0x8051501 0x00 0x2469015 0x1000000 0x2ff10 0x15010000 0x2ff 0xf0150100 0x02 0x92011501 0x00 0x2ff1015 0x1000000 0x23500 0x5010000 0x28000129>; | |
| qcom,mdss-dsi-off-command = <0x5010000 0x10000128 0x5010000 0x40000110>; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-h-back-porch = <0x00>; | |
| qcom,mdss-dsi-v-back-porch = <0x00>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-h-front-porch = <0x00>; | |
| qcom,mdss-dsi-v-front-porch = <0x00>; | |
| qcom,mdss-dsc-bit-per-component = <0x0a>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x02>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsi-panel-height = <0x780>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,display-topology = <0x01 0x01 0x01 0x02 0x02 0x01 0x02 0x01 0x01>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = <0x150505 0x201f0505 0x3030400>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x00>; | |
| qcom,mdss-dsi-v-pulse-width = <0x00>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsc-slice-height = <0x10>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| }; | |
| timing@0 { | |
| qcom,mdss-dsi-on-command = <0x15010000 0x2ff 0x20150100 0x02 0xfb011501 0x00 0x2000115 0x1000000 0x20155 0x15010000 0x202 0x45150100 0x02 0x5401501 0x00 0x2061915 0x1000000 0x2071e 0x15010000 0x20b 0x73150100 0x02 0xc731501 0x00 0x20eb015 0x1000000 0x20fae 0x15010000 0x211 0xb8150100 0x02 0x13001501 0x00 0x2588015 0x1000000 0x25901 0x15010000 0x25a 0x150100 0x02 0x5b011501 0x00 0x25c8015 0x1000000 0x25d81 0x15010000 0x25e 0x150100 0x02 0x5f011501 0x00 0x2723115 0x1000000 0x26803 0x15010000 0x2ff 0x24150100 0x02 0xfb011501 0x00 0x2001c15 0x1000000 0x2010b 0x15010000 0x202 0xc150100 0x02 0x3011501 0x00 0x2040f15 0x1000000 0x20510 0x15010000 0x206 0x10150100 0x02 0x7101501 0x00 0x2088915 0x1000000 0x2098a 0x15010000 0x20a 0x13150100 0x02 0xb131501 0x00 0x20c1515 0x1000000 0x20d15 0x15010000 0x20e 0x17150100 0x02 0xf171501 0x00 0x2101c15 0x1000000 0x2110b 0x15010000 0x212 0xc150100 0x02 0x13011501 0x00 0x2140f15 0x1000000 0x21510 0x15010000 0x216 0x10150100 0x02 0x17101501 0x00 0x2188915 0x1000000 0x2198a 0x15010000 0x21a 0x13150100 0x02 0x1b131501 0x00 0x21c1515 0x1000000 0x21d15 0x15010000 0x21e 0x17150100 0x02 0x1f171501 0x00 0x2204015 0x1000000 0x22101 0x15010000 0x222 0x150100 0x02 0x23401501 0x00 0x2244015 0x1000000 0x2256d 0x15010000 0x226 0x40150100 0x02 0x27401501 0x00 0x2e00015 0x1000000 0x2dc21 0x15010000 0x2dd 0x22150100 0x02 0xde071501 0x00 0x2df0715 0x1000000 0x2e36d 0x15010000 0x2e1 0x7150100 0x02 0xe2071501 0x00 0x229d815 0x1000000 0x22a2a 0x15010000 0x24b 0x3150100 0x02 0x4c111501 0x00 0x24d1015 0x1000000 0x24e01 0x15010000 0x24f 0x1150100 0x02 0x50101501 0x00 0x2510015 0x1000000 0x25280 0x15010000 0x253 0x150100 0x02 0x56001501 0x00 0x2540715 0x1000000 0x25807 0x15010000 0x255 0x25150100 0x02 0x5b431501 0x00 0x25c0015 0x1000000 0x25f73 0x15010000 0x260 0x73150100 0x02 0x63221501 0x00 0x2640015 0x1000000 0x26708 0x15010000 0x268 0x4150100 0x02 0x72021501 0x00 0x27a8015 0x1000000 0x27b91 0x15010000 0x27c 0xd8150100 0x02 0x7d601501 0x00 0x27f1515 0x1000000 0x27515 0x15010000 0x2b3 0xc0150100 0x02 0xb4001501 0x00 0x2b50015 0x1000000 0x27800 0x15010000 0x279 0x150100 0x02 0x80001501 0x00 0x2830015 0x1000000 0x2930a 0x15010000 0x294 0xa150100 0x02 0x8a001501 0x00 0x29bff15 0x1000000 0x29db0 0x15010000 0x29f 0x63150100 0x02 0x98101501 0x00 0x2ec0015 0x1000000 0x2ff10 0x39010000 0x11c1 0x9200010 0x2000268 0x1bb000a 0x66704c5 0x39010000 0x3c2 0x10f01501 0x00 0x2c00315 0x1000000 0x43b03 0xa0a1501 0x00 0x2350015 0x1000000 0x2e501 0x15010000 0x2bb 0x10150100 0x02 0xfb010501 0x7800 0x2110005 0x1000078 0x22900>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,mdss-dsi-on-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-h-back-porch = <0x20>; | |
| qcom,mdss-dsi-v-back-porch = <0x08>; | |
| qcom,mdss-dsi-panel-width = <0x5a0>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-h-front-porch = <0x64>; | |
| qcom,mdss-dsi-v-front-porch = <0x0a>; | |
| qcom,mdss-dsc-bit-per-component = <0x0a>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x02>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsi-panel-height = <0xa00>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,display-topology = <0x01 0x01 0x01>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = <0x1a0606 0x22200707 0x4030400>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x10>; | |
| qcom,mdss-dsi-v-pulse-width = <0x02>; | |
| qcom,mdss-dsc-slice-width = <0x2d0>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsc-slice-height = <0x10>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| }; | |
| }; | |
| }; | |
| qcom,sde-sspp-vig-blocks { | |
| qcom,sde-vig-csc-off = <0x1a00>; | |
| qcom,sde-vig-qseed-size = <0xa0>; | |
| qcom,sde-vig-qseed-off = <0xa00>; | |
| }; | |
| qcom,mdss_dsi_sharp_1080p_cmd { | |
| qcom,esd-check-enabled; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-t-clk-pre = <0x29>; | |
| qcom,mdss-dsi-panel-name = "sharp 1080p cmd mode dsi panel"; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-panel-clockrate = <0x32a9f880>; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-panel-status-check-mode = "reg_read"; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; | |
| qcom,mdss-dsi-te-check-enable; | |
| qcom,mdss-dsi-te-pin-select = <0x01>; | |
| qcom,mdss-dsi-te-using-te-pin; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-panel-destination = "display_1"; | |
| qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; | |
| qcom,mdss-dsi-te-dcs-command = <0x01>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-panel-status-read-length = <0x01>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-pan-physical-width-dimension = <0x40>; | |
| qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| phandle = <0x4e5>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
| qcom,mdss-dsi-panel-status-value = <0x9c>; | |
| qcom,mdss-pan-physical-height-dimension = <0x75>; | |
| qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-traffic-mode = "burst_mode"; | |
| qcom,mdss-dsi-panel-on-check-value = <0x9c>; | |
| qcom,mdss-dsi-t-clk-post = <0x0c>; | |
| qcom,mdss-dsi-panel-controller = <0x2c3>; | |
| qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@0 { | |
| qcom,mdss-dsi-on-command = <0x15010000 0x2bb 0x10150100 0x02 0xb0030501 0x7800 0x1111501 0x00 0x251ff15 0x1000000 0x25324 0x15010000 0x2ff 0x23150100 0x02 0x8051501 0x00 0x2469015 0x1000000 0x2ff10 0x15010000 0x2ff 0xf0150100 0x02 0x92011501 0x00 0x2ff1015 0x1000000 0x23500 0x5010000 0x28000129>; | |
| qcom,mdss-dsi-off-command = <0x5010000 0x10000128 0x5010000 0x40000110>; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-h-back-porch = <0x00>; | |
| qcom,mdss-dsi-v-back-porch = <0x00>; | |
| qcom,mdss-dsi-panel-clockrate = <0x35a4e900>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-h-front-porch = <0x00>; | |
| qcom,mdss-dsi-v-front-porch = <0x00>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsi-panel-height = <0x780>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,display-topology = <0x01 0x00 0x01>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = <0x1e0808 0x24220808 0x5030400>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x00>; | |
| qcom,mdss-dsi-v-pulse-width = <0x00>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_sim_video { | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-t-clk-pre = <0x2d>; | |
| qcom,mdss-dsi-panel-name = "Simulator video mode dsi panel"; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x00 0x00 0x00 0x01 0x00>; | |
| qcom,mdss-dsi-panel-hdr-enabled; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-panel-peak-brightness = <0x401640>; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| phandle = <0x4eb>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
| qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; | |
| qcom,mdss-dsi-panel-blackness-level = <0xc9e>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,panel-supply-entries = <0x4de>; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,platform-reset-gpio = <0x34 0x06 0x00>; | |
| qcom,mdss-dsi-t-clk-post = <0x0d>; | |
| qcom,panel-ack-disabled; | |
| qcom,mdss-dsi-display-timings { | |
| timing@0 { | |
| qcom,mdss-dsi-on-command = [32 01 00 00 00 00 02 00 00]; | |
| qcom,mdss-dsi-off-command = [22 01 00 00 00 00 02 00 00]; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-h-back-porch = <0x08>; | |
| qcom,mdss-dsi-v-back-porch = <0x06>; | |
| qcom,mdss-dsi-panel-width = <0x280>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-h-front-porch = <0x08>; | |
| qcom,mdss-dsi-v-front-porch = <0x06>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsi-panel-height = <0x1e0>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,display-topology = <0x01 0x00 0x01 0x02 0x00 0x01>; | |
| qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = <0x1c0707 0x23210707 0x5030400>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x08>; | |
| qcom,mdss-dsi-v-pulse-width = <0x02>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsi-panel-timings = <0x00 0x00 0x00>; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_nt35597_wqxga_cmd { | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-color-order = "rgb_swap_rgb"; | |
| qcom,mdss-dsi-t-clk-pre = <0x2d>; | |
| qcom,mdss-dsi-bl-min-level = <0x01>; | |
| qcom,mdss-dsi-panel-name = "Dual nt35597 cmd mode dsi panel without DSC"; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; | |
| qcom,mdss-dsi-te-check-enable; | |
| qcom,mdss-dsi-te-pin-select = <0x01>; | |
| qcom,mdss-dsi-te-using-te-pin; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,ulps-enabled; | |
| qcom,mdss-dsi-te-dcs-command = <0x01>; | |
| qcom,mdss-dsi-mode-sel-gpio-state = "dual_port"; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-pan-physical-width-dimension = <0x4a>; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| phandle = <0x4f2>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
| qcom,mdss-pan-physical-height-dimension = <0x83>; | |
| qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
| qcom,mdss-dsi-bl-max-level = <0xfff>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,platform-te-gpio = <0x34 0x0a 0x00>; | |
| qcom,panel-supply-entries = <0x4de>; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,platform-reset-gpio = <0x34 0x06 0x00>; | |
| qcom,adjust-timer-wakeup-ms = <0x01>; | |
| qcom,mdss-dsi-t-clk-post = <0x0d>; | |
| qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@0 { | |
| qcom,mdss-dsi-on-command = <0x15010000 0x100002ff 0x10150100 0x100002 0xfb011501 0x1000 0x2ba0315 0x1000010 0x2e501 0x15010000 0x10000235 0x150100 0x100002 0xbb101501 0x1000 0x2b00315 0x1000010 0x2ffe0 0x15010000 0x100002fb 0x1150100 0x100002 0x6b3d1501 0x1000 0x26c3d15 0x1000010 0x26d3d 0x15010000 0x1000026e 0x3d150100 0x100002 0x6f3d1501 0x1000 0x2350215 0x1000010 0x23672 0x15010000 0x10000237 0x10150100 0x100002 0x8c01501 0x1000 0x2ff2415 0x1000010 0x2fb01 0x15010000 0x100002c6 0x6150100 0x100002 0xff100501 0xa000 0x2110005 0x10000a0 0x22900>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 0a 00 02 28 00 05 01 00 00 3c 00 02 10 00]; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-h-back-porch = <0x20>; | |
| qcom,mdss-dsi-v-back-porch = <0x07>; | |
| qcom,mdss-dsi-panel-width = <0x2d0>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-h-front-porch = <0x64>; | |
| qcom,partial-update-enabled = "single_roi"; | |
| qcom,mdss-dsi-v-front-porch = <0x08>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsi-panel-height = <0xa00>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,display-topology = <0x02 0x00 0x02 0x01 0x00 0x02>; | |
| qcom,panel-roi-alignment = <0x2d0 0x80 0x2d0 0x80 0x5a0 0x80>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,config-select = <0x4e0>; | |
| qcom,mdss-dsi-h-pulse-width = <0x10>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsi-panel-timings = <0x1c0807 0x23220707 0x5030400>; | |
| config1 { | |
| qcom,split-mode = "pingpong-split"; | |
| phandle = <0x53d>; | |
| }; | |
| config0 { | |
| qcom,split-mode = "dualctl-split"; | |
| phandle = <0x4e0>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_sim_cmd { | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-color-order = "rgb_swap_rgb"; | |
| qcom,mdss-dsi-t-clk-pre = <0x29>; | |
| qcom,mdss-dsi-panel-name = "Simulator cmd mode dsi panel"; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; | |
| qcom,mdss-dsi-te-check-enable; | |
| qcom,mdss-dsi-te-using-wd; | |
| qcom,mdss-dsi-te-pin-select = <0x01>; | |
| qcom,mdss-dsi-te-using-te-pin; | |
| qcom,mdss-dsi-panel-hdr-enabled; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,ulps-enabled; | |
| qcom,mdss-dsi-te-dcs-command = <0x01>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-panel-peak-brightness = <0x401640>; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| phandle = <0x4ed>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
| qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; | |
| qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
| qcom,mdss-dsi-panel-blackness-level = <0xc9e>; | |
| qcom,mdss-dsi-bl-max-level = <0xfff>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,panel-supply-entries = <0x4de>; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,platform-reset-gpio = <0x34 0x06 0x00>; | |
| qcom,mdss-dsi-t-clk-post = <0x0c>; | |
| qcom,panel-ack-disabled; | |
| qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@1 { | |
| qcom,mdss-dsi-on-command = <0x29010000 0x2b0 0x3050100 0xa0001 0x150100 0xa0002 0x3a773901 0xa00 0x52a0000 0x4ff3901 0xa00 0x52b0000 0x59f1501 0xa00 0x2350039 0x100000a 0x34400 0x150100 0xa0002 0x51ff1501 0xa00 0x2532415 0x100000a 0x25500 0x5010000 0x78000111 0x5010000 0x10000129>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-h-back-porch = <0x1cc>; | |
| qcom,mdss-dsi-v-back-porch = <0x64>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-h-front-porch = <0x78>; | |
| qcom,partial-update-enabled = "single_roi"; | |
| qcom,mdss-dsi-v-front-porch = <0x2e4>; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsi-panel-height = <0x780>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,display-topology = <0x01 0x00 0x01 0x02 0x02 0x01>; | |
| qcom,panel-roi-alignment = <0x21c 0x28 0x21c 0x28 0x21c 0x28>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = <0x1a0606 0x22200707 0x4030400>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x28>; | |
| qcom,mdss-dsi-v-pulse-width = <0x28>; | |
| qcom,mdss-dsc-slice-width = <0x21c>; | |
| qcom,default-topology-index = <0x01>; | |
| qcom,mdss-dsc-slice-height = <0x28>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsi-panel-timings = <0x210909 0x24230808 0x8030400>; | |
| }; | |
| timing@2 { | |
| qcom,mdss-dsi-on-command = <0x29010000 0x2b0 0x3050100 0xa0001 0x150100 0xa0002 0x3a773901 0xa00 0x52a0000 0x4ff3901 0xa00 0x52b0000 0x59f1501 0xa00 0x2350039 0x100000a 0x34400 0x150100 0xa0002 0x51ff1501 0xa00 0x2532415 0x100000a 0x25500 0x5010000 0x78000111 0x5010000 0x10000129>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-h-back-porch = <0x348>; | |
| qcom,mdss-dsi-v-back-porch = <0x64>; | |
| qcom,mdss-dsi-panel-width = <0x2d0>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-h-front-porch = <0x64>; | |
| qcom,partial-update-enabled = "single_roi"; | |
| qcom,mdss-dsi-v-front-porch = <0x564>; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsi-panel-height = <0x500>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,display-topology = <0x01 0x00 0x01 0x02 0x02 0x01>; | |
| qcom,panel-roi-alignment = <0x168 0x28 0x168 0x28 0x168 0x28>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = <0x1a0606 0x22200707 0x4030400>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x28>; | |
| qcom,mdss-dsi-v-pulse-width = <0x28>; | |
| qcom,mdss-dsc-slice-width = <0x168>; | |
| qcom,default-topology-index = <0x01>; | |
| qcom,mdss-dsc-slice-height = <0x28>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsi-panel-timings = <0x210909 0x24230808 0x8030400>; | |
| }; | |
| timing@0 { | |
| qcom,mdss-dsi-on-command = <0x29010000 0x2b0 0x3050100 0xa0001 0x150100 0xa0002 0x3a773901 0xa00 0x52a0000 0x4ff3901 0xa00 0x52b0000 0x59f1501 0xa00 0x2350039 0x100000a 0x34400 0x150100 0xa0002 0x51ff1501 0xa00 0x2532415 0x100000a 0x25500 0x5010000 0x78000111 0x5010000 0x10000129>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-h-back-porch = <0x64>; | |
| qcom,mdss-dsi-v-back-porch = <0x64>; | |
| qcom,mdss-dsi-panel-width = <0x5a0>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-h-front-porch = <0x78>; | |
| qcom,partial-update-enabled = "single_roi"; | |
| qcom,mdss-dsi-v-front-porch = <0x64>; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsi-panel-height = <0xa00>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,display-topology = <0x01 0x00 0x01 0x02 0x02 0x01>; | |
| qcom,panel-roi-alignment = <0x2d0 0x28 0x2d0 0x28 0x2d0 0x28>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = <0x1a0606 0x22200707 0x4030400>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x28>; | |
| qcom,mdss-dsi-v-pulse-width = <0x28>; | |
| qcom,mdss-dsc-slice-width = <0x2d0>; | |
| qcom,default-topology-index = <0x01>; | |
| qcom,mdss-dsc-slice-height = <0x28>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| qcom,mdss-dsi-panel-timings = <0x210909 0x24230808 0x8030400>; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_lt8912_1080p_dsi1_video { | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-color-order = "rgb_swap_rgb"; | |
| qcom,mdss-dsi-t-clk-pre = <0x32>; | |
| qcom,mdss-dsi-panel-name = "lt8912 1080p video mode dsi1 panel"; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x14 0x00 0x02 0x01 0x14>; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-pan-physical-width-dimension = <0xd0>; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| phandle = <0x4f6>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
| qcom,mdss-dsi-lane-map = "lane_map_0123"; | |
| qcom,mdss-pan-physical-height-dimension = <0x75>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-force-clock-lane-hs = <0x01>; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,mdss-dsi-t-clk-post = <0x0d>; | |
| qcom,mdss-dsi-post-init-delay = <0x01>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@0 { | |
| qcom,mdss-dsi-on-command; | |
| qcom,mdss-dsi-off-command; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,mdss-dsi-on-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-h-back-porch = <0x94>; | |
| qcom,mdss-dsi-v-back-porch = <0x24>; | |
| qcom,mdss-dsi-panel-clockrate = <0x353fd600>; | |
| qcom,mdss-dsi-panel-width = <0x780>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-h-front-porch = <0x58>; | |
| qcom,mdss-dsi-v-front-porch = <0x04>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsi-panel-height = <0x438>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,display-topology = <0x01 0x00 0x01>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = <0x1e0808 0x24220808 0x8020400>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x2c>; | |
| qcom,mdss-dsi-v-pulse-width = <0x05>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_innolux_td4328_1080p_cmd { | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-t-clk-pre = <0x36>; | |
| qcom,mdss-dsi-bl-min-level = <0x01>; | |
| qcom,mdss-dsi-panel-orientation = "180"; | |
| qcom,mdss-dsi-panel-name = "TD4328 cmd mode dsi panel without DSC"; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x50>; | |
| qcom,mdss-dsi-te-check-enable; | |
| qcom,mdss-dsi-te-pin-select = <0x01>; | |
| qcom,mdss-dsi-te-using-te-pin; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-te-dcs-command = <0x01>; | |
| qcom,mdss-dsi-mode-sel-gpio-state = "single_port"; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-pan-physical-width-dimension = <0x4b>; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,5v-boost-gpio = <0x34 0x78 0x00>; | |
| phandle = <0x4f7>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
| qcom,mdss-pan-physical-height-dimension = <0x84>; | |
| qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
| qcom,mdss-dsi-bl-max-level = <0xfff>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,platform-te-gpio = <0x34 0x0a 0x00>; | |
| qcom,panel-supply-entries = <0x4de>; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,platform-reset-gpio = <0x34 0x06 0x00>; | |
| qcom,mdss-dsi-t-clk-post = <0x0e>; | |
| qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@0 { | |
| qcom,mdss-dsi-on-command = [29 01 00 00 00 00 02 b0 00 29 01 00 00 00 00 18 c2 01 f7 80 04 68 08 09 10 00 08 30 00 00 00 00 00 00 00 02 80 00 00 00 29 01 00 00 00 00 02 d6 01 29 01 00 00 00 00 02 b0 03 39 01 00 00 00 00 05 2a 00 00 04 37 39 01 00 00 00 00 05 2b 00 00 07 7f 05 01 00 00 00 00 02 35 00 05 01 00 00 96 00 01 11 05 01 00 00 32 00 01 29]; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 05 00 02 28 00 05 01 00 00 53 00 02 10 00]; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-h-back-porch = <0x3c>; | |
| qcom,mdss-dsi-v-back-porch = <0x14>; | |
| qcom,mdss-dsi-panel-clockrate = <0x390ed9c0>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-h-front-porch = <0x3c>; | |
| qcom,mdss-dsi-v-front-porch = <0x14>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsi-panel-height = <0x780>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,display-topology = <0x01 0x00 0x01 0x02 0x00 0x01>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = <0x210808 0x25230808 0x9020400>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x0a>; | |
| qcom,mdss-dsi-v-pulse-width = <0x08>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dual_sharp_1080p_120hz_cmd { | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-t-clk-pre = <0x36>; | |
| qcom,cmd-sync-wait-trigger; | |
| qcom,mdss-dsi-panel-name = "sharp 1080p 120hz dual dsi cmd mode panel"; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x14 0x00 0x01 0x01 0x0a>; | |
| qcom,mdss-dsi-te-check-enable; | |
| qcom,mdss-dsi-te-pin-select = <0x01>; | |
| qcom,mdss-dsi-te-using-te-pin; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-te-dcs-command = <0x01>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,cmd-sync-wait-broadcast; | |
| phandle = <0x4e6>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
| qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-traffic-mode = "burst_mode"; | |
| qcom,mdss-tear-check-frame-rate = <0x2ee0>; | |
| qcom,mdss-dsi-t-clk-post = <0x0f>; | |
| qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@0 { | |
| qcom,mdss-dsi-on-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 ba 07 15 01 00 00 00 00 02 c0 00 15 01 00 00 00 00 02 bb 10 15 01 00 00 00 00 02 d9 00 15 01 00 00 00 00 02 ef 70 15 01 00 00 00 00 02 f7 80 39 01 00 00 00 00 06 3b 03 0e 0c 08 1c 15 01 00 00 00 00 02 e9 0e 15 01 00 00 00 00 02 ea 0c 15 01 00 00 00 00 02 35 00 15 01 00 00 00 00 02 c0 00 15 01 00 00 00 00 02 ff 20 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 59 6a 15 01 00 00 00 00 02 0b 1b 15 01 00 00 00 00 02 61 f7 15 01 00 00 00 00 02 62 6c 15 01 00 00 00 00 02 00 01 15 01 00 00 00 00 02 01 55 15 01 00 00 00 00 02 04 c8 15 01 00 00 00 00 02 05 1a 15 01 00 00 00 00 02 0d 93 15 01 00 00 00 00 02 0e 93 15 01 00 00 00 00 02 0f 7e 15 01 00 00 00 00 02 06 69 15 01 00 00 00 00 02 07 bc 15 01 00 00 00 00 02 10 03 15 01 00 00 00 00 02 11 64 15 01 00 00 00 00 02 12 5a 15 01 00 00 00 00 02 13 40 15 01 00 00 00 00 02 14 40 15 01 00 00 00 00 02 15 00 15 01 00 00 00 00 02 33 13 15 01 00 00 00 00 02 5a 40 15 01 00 00 00 00 02 5b 40 15 01 00 00 00 00 02 5e 80 15 01 00 00 00 00 02 ff 24 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 80 15 01 00 00 00 00 02 14 80 15 01 00 00 00 00 02 01 80 15 01 00 00 00 00 02 15 80 15 01 00 00 00 00 02 02 80 15 01 00 00 00 00 02 16 80 15 01 00 00 00 00 02 03 0a 15 01 00 00 00 00 02 17 0c 15 01 00 00 00 00 02 04 06 15 01 00 00 00 00 02 18 08 15 01 00 00 00 00 02 05 80 15 01 00 00 00 00 02 19 80 15 01 00 00 00 00 02 06 80 15 01 00 00 00 00 02 1a 80 15 01 00 00 00 00 02 07 80 15 01 00 00 00 00 02 1b 80 15 01 00 00 00 00 02 08 80 15 01 00 00 00 00 02 1c 80 15 01 00 00 00 00 02 09 80 15 01 00 00 00 00 02 1d 80 15 01 00 00 00 00 02 0a 80 15 01 00 00 00 00 02 1e 80 15 01 00 00 00 00 02 0b 1a 15 01 00 00 00 00 02 1f 1b 15 01 00 00 00 00 02 0c 16 15 01 00 00 00 00 02 20 17 15 01 00 00 00 00 02 0d 1c 15 01 00 00 00 00 02 21 1d 15 01 00 00 00 00 02 0e 18 15 01 00 00 00 00 02 22 19 15 01 00 00 00 00 02 0f 0e 15 01 00 00 00 00 02 23 10 15 01 00 00 00 00 02 10 80 15 01 00 00 00 00 02 24 80 15 01 00 00 00 00 02 11 80 15 01 00 00 00 00 02 25 80 15 01 00 00 00 00 02 12 80 15 01 00 00 00 00 02 26 80 15 01 00 00 00 00 02 13 80 15 01 00 00 00 00 02 27 80 15 01 00 00 00 00 02 74 ff 15 01 00 00 00 00 02 75 ff 15 01 00 00 00 00 02 8d 00 15 01 00 00 00 00 02 8e 00 15 01 00 00 00 00 02 8f 9c 15 01 00 00 00 00 02 90 0c 15 01 00 00 00 00 02 91 0e 15 01 00 00 00 00 02 d6 00 15 01 00 00 00 00 02 d7 20 15 01 00 00 00 00 02 d8 00 15 01 00 00 00 00 02 d9 88 15 01 00 00 00 00 02 e5 05 15 01 00 00 00 00 02 e6 10 15 01 00 00 00 00 02 54 06 15 01 00 00 00 00 02 55 05 15 01 00 00 00 00 02 56 04 15 01 00 00 00 00 02 58 03 15 01 00 00 00 00 02 59 33 15 01 00 00 00 00 02 5a 33 15 01 00 00 00 00 02 5b 01 15 01 00 00 00 00 02 5c 00 15 01 00 00 00 00 02 5d 01 15 01 00 00 00 00 02 5e 0a 15 01 00 00 00 00 02 5f 0a 15 01 00 00 00 00 02 60 0a 15 01 00 00 00 00 02 61 0a 15 01 00 00 00 00 02 62 10 15 01 00 00 00 00 02 63 01 15 01 00 00 00 00 02 64 00 15 01 00 00 00 00 02 65 00 15 01 00 00 00 00 02 ef 00 15 01 00 00 00 00 02 f0 00 15 01 00 00 00 00 02 6d 20 15 01 00 00 00 00 02 66 44 15 01 00 00 00 00 02 68 01 15 01 00 00 00 00 02 69 00 15 01 00 00 00 00 02 67 11 15 01 00 00 00 00 02 6a 06 15 01 00 00 00 00 02 6b 31 15 01 00 00 00 00 02 6c 90 15 01 00 00 00 00 02 ab c3 15 01 00 00 00 00 02 b1 49 15 01 00 00 00 00 02 aa 80 15 01 00 00 00 00 02 b0 90 15 01 00 00 00 00 02 b2 a4 15 01 00 00 00 00 02 b3 00 15 01 00 00 00 00 02 b4 23 15 01 00 00 00 00 02 b5 00 15 01 00 00 00 00 02 b6 00 15 01 00 00 00 00 02 b7 00 15 01 00 00 00 00 02 b8 00 15 01 00 00 00 00 02 b9 00 15 01 00 00 00 00 02 ba 00 15 01 00 00 00 00 02 bb 00 15 01 00 00 00 00 02 bc 00 15 01 00 00 00 00 02 bd 00 15 01 00 00 00 00 02 be 00 15 01 00 00 00 00 02 bf 00 15 01 00 00 00 00 02 c0 00 15 01 00 00 00 00 02 c7 40 15 01 00 00 00 00 02 c9 00 15 01 00 00 00 00 02 c1 2a 15 01 00 00 00 00 02 c2 2a 15 01 00 00 00 00 02 c3 00 15 01 00 00 00 00 02 c4 00 15 01 00 00 00 00 02 c5 00 15 01 00 00 00 00 02 c6 00 15 01 00 00 00 00 02 c8 ab 15 01 00 00 00 00 02 ca 00 15 01 00 00 00 00 02 cb 00 15 01 00 00 00 00 02 cc 20 15 01 00 00 00 00 02 cd 40 15 01 00 00 00 00 02 ce a8 15 01 00 00 00 00 02 cf a8 15 01 00 00 00 00 02 d0 00 15 01 00 00 00 00 02 d1 00 15 01 00 00 00 00 02 d2 00 15 01 00 00 00 00 02 d3 00 15 01 00 00 00 00 02 af 01 15 01 00 00 00 00 02 a4 1e 15 01 00 00 00 00 02 95 41 15 01 00 00 00 00 02 96 03 15 01 00 00 00 00 02 98 00 15 01 00 00 00 00 02 9a 9a 15 01 00 00 00 00 02 9b 03 15 01 00 00 00 00 02 9d 80 15 01 00 00 00 00 02 ff 26 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 fa d0 15 01 00 00 00 00 02 6b 80 15 01 00 00 00 00 02 6c 5c 15 01 00 00 00 00 02 6d 0c 15 01 00 00 00 00 02 6e 0e 15 01 00 00 00 00 02 58 01 15 01 00 00 00 00 02 59 15 15 01 00 00 00 00 02 5a 01 15 01 00 00 00 00 02 5b 00 15 01 00 00 00 00 02 5c 01 15 01 00 00 00 00 02 5d 2b 15 01 00 00 00 00 02 74 00 15 01 00 00 00 00 02 75 ba 15 01 00 00 00 00 02 81 0a 15 01 00 00 00 00 02 4e 81 15 01 00 00 00 00 02 4f 83 15 01 00 00 00 00 02 51 00 15 01 00 00 00 00 02 53 4d 15 01 00 00 00 00 02 54 03 15 01 00 00 00 00 02 ff e0 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 b2 81 15 01 00 00 00 00 02 62 28 15 01 00 00 00 00 02 a2 09 15 01 00 00 00 00 02 b3 01 15 01 00 00 00 00 02 ed 00 15 01 00 00 00 00 02 ff 10 05 01 00 00 78 00 01 11 15 01 00 00 00 00 02 ff 20 15 01 00 00 00 00 02 75 00 15 01 00 00 00 00 02 76 71 15 01 00 00 00 00 02 77 00 15 01 00 00 00 00 02 78 84 15 01 00 00 00 00 02 79 00 15 01 00 00 00 00 02 7a a5 15 01 00 00 00 00 02 7b 00 15 01 00 00 00 00 02 7c bb 15 01 00 00 00 00 02 7d 00 15 01 00 00 00 00 02 7e ce 15 01 00 00 00 00 02 7f 00 15 01 00 00 00 00 02 80 e0 15 01 00 00 00 00 02 81 00 15 01 00 00 00 00 02 82 ef 15 01 00 00 00 00 02 83 00 15 01 00 00 00 00 02 84 ff 15 01 00 00 00 00 02 85 01 15 01 00 00 00 00 02 86 0b 15 01 00 00 00 00 02 87 01 15 01 00 00 00 00 02 88 38 15 01 00 00 00 00 02 89 01 15 01 00 00 00 00 02 8a 5b 15 01 00 00 00 00 02 8b 01 15 01 00 00 00 00 02 8c 95 15 01 00 00 00 00 02 8d 01 15 01 00 00 00 00 02 8e c4 15 01 00 00 00 00 02 8f 02 15 01 00 00 00 00 02 90 0d 15 01 00 00 00 00 02 91 02 15 01 00 00 00 00 02 92 4a 15 01 00 00 00 00 02 93 02 15 01 00 00 00 00 02 94 4c 15 01 00 00 00 00 02 95 02 15 01 00 00 00 00 02 96 85 15 01 00 00 00 00 02 97 02 15 01 00 00 00 00 02 98 c3 15 01 00 00 00 00 02 99 02 15 01 00 00 00 00 02 9a e9 15 01 00 00 00 00 02 9b 03 15 01 00 00 00 00 02 9c 16 15 01 00 00 00 00 02 9d 03 15 01 00 00 00 00 02 9e 34 15 01 00 00 00 00 02 9f 03 15 01 00 00 00 00 02 a0 56 15 01 00 00 00 00 02 a2 03 15 01 00 00 00 00 02 a3 62 15 01 00 00 00 00 02 a4 03 15 01 00 00 00 00 02 a5 6c 15 01 00 00 00 00 02 a6 03 15 01 00 00 00 00 02 a7 74 15 01 00 00 00 00 02 a9 03 15 01 00 00 00 00 02 aa 80 15 01 00 00 00 00 02 ab 03 15 01 00 00 00 00 02 ac 89 15 01 00 00 00 00 02 ad 03 15 01 00 00 00 00 02 ae 8b 15 01 00 00 00 00 02 af 03 15 01 00 00 00 00 02 b0 8d 15 01 00 00 00 00 02 b1 03 15 01 00 00 00 00 02 b2 8e 15 01 00 00 00 00 02 b3 00 15 01 00 00 00 00 02 b4 71 15 01 00 00 00 00 02 b5 00 15 01 00 00 00 00 02 b6 84 15 01 00 00 00 00 02 b7 00 15 01 00 00 00 00 02 b8 a5 15 01 00 00 00 00 02 b9 00 15 01 00 00 00 00 02 ba bb 15 01 00 00 00 00 02 bb 00 15 01 00 00 00 00 02 bc ce 15 01 00 00 00 00 02 bd 00 15 01 00 00 00 00 02 be e0 15 01 00 00 00 00 02 bf 00 15 01 00 00 00 00 02 c0 ef 15 01 00 00 00 00 02 c1 00 15 01 00 00 00 00 02 c2 ff 15 01 00 00 00 00 02 c3 01 15 01 00 00 00 00 02 c4 0b 15 01 00 00 00 00 02 c5 01 15 01 00 00 00 00 02 c6 38 15 01 00 00 00 00 02 c7 01 15 01 00 00 00 00 02 c8 5b 15 01 00 00 00 00 02 c9 01 15 01 00 00 00 00 02 ca 95 15 01 00 00 00 00 02 cb 01 15 01 00 00 00 00 02 cc c4 15 01 00 00 00 00 02 cd 02 15 01 00 00 00 00 02 ce 0d 15 01 00 00 00 00 02 cf 02 15 01 00 00 00 00 02 d0 4a 15 01 00 00 00 00 02 d1 02 15 01 00 00 00 00 02 d2 4c 15 01 00 00 00 00 02 d3 02 15 01 00 00 00 00 02 d4 85 15 01 00 00 00 00 02 d5 02 15 01 00 00 00 00 02 d6 c3 15 01 00 00 00 00 02 d7 02 15 01 00 00 00 00 02 d8 e9 15 01 00 00 00 00 02 d9 03 15 01 00 00 00 00 02 da 16 15 01 00 00 00 00 02 db 03 15 01 00 00 00 00 02 dc 34 15 01 00 00 00 00 02 dd 03 15 01 00 00 00 00 02 de 56 15 01 00 00 00 00 02 df 03 15 01 00 00 00 00 02 e0 62 15 01 00 00 00 00 02 e1 03 15 01 00 00 00 00 02 e2 6c 15 01 00 00 00 00 02 e3 03 15 01 00 00 00 00 02 e4 74 15 01 00 00 00 00 02 e5 03 15 01 00 00 00 00 02 e6 80 15 01 00 00 00 00 02 e7 03 15 01 00 00 00 00 02 e8 89 15 01 00 00 00 00 02 e9 03 15 01 00 00 00 00 02 ea 8b 15 01 00 00 00 00 02 eb 03 15 01 00 00 00 00 02 ec 8d 15 01 00 00 00 00 02 ed 03 15 01 00 00 00 00 02 ee 8e 15 01 00 00 00 00 02 ef 00 15 01 00 00 00 00 02 f0 71 15 01 00 00 00 00 02 f1 00 15 01 00 00 00 00 02 f2 84 15 01 00 00 00 00 02 f3 00 15 01 00 00 00 00 02 f4 a5 15 01 00 00 00 00 02 f5 00 15 01 00 00 00 00 02 f6 bb 15 01 00 00 00 00 02 f7 00 15 01 00 00 00 00 02 f8 ce 15 01 00 00 00 00 02 f9 00 15 01 00 00 00 00 02 fa e0 15 01 00 00 00 00 02 ff 21 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 00 15 01 00 00 00 00 02 01 ef 15 01 00 00 00 00 02 02 00 15 01 00 00 00 00 02 03 ff 15 01 00 00 00 00 02 04 01 15 01 00 00 00 00 02 05 0b 15 01 00 00 00 00 02 06 01 15 01 00 00 00 00 02 07 38 15 01 00 00 00 00 02 08 01 15 01 00 00 00 00 02 09 5b 15 01 00 00 00 00 02 0a 01 15 01 00 00 00 00 02 0b 95 15 01 00 00 00 00 02 0c 01 15 01 00 00 00 00 02 0d c4 15 01 00 00 00 00 02 0e 02 15 01 00 00 00 00 02 0f 0d 15 01 00 00 00 00 02 10 02 15 01 00 00 00 00 02 11 4a 15 01 00 00 00 00 02 12 02 15 01 00 00 00 00 02 13 4c 15 01 00 00 00 00 02 14 02 15 01 00 00 00 00 02 15 85 15 01 00 00 00 00 02 16 02 15 01 00 00 00 00 02 17 c3 15 01 00 00 00 00 02 18 02 15 01 00 00 00 00 02 19 e9 15 01 00 00 00 00 02 1a 03 15 01 00 00 00 00 02 1b 16 15 01 00 00 00 00 02 1c 03 15 01 00 00 00 00 02 1d 34 15 01 00 00 00 00 02 1e 03 15 01 00 00 00 00 02 1f 56 15 01 00 00 00 00 02 20 03 15 01 00 00 00 00 02 21 62 15 01 00 00 00 00 02 22 03 15 01 00 00 00 00 02 23 6c 15 01 00 00 00 00 02 24 03 15 01 00 00 00 00 02 25 74 15 01 00 00 00 00 02 26 03 15 01 00 00 00 00 02 27 80 15 01 00 00 00 00 02 28 03 15 01 00 00 00 00 02 29 89 15 01 00 00 00 00 02 2a 03 15 01 00 00 00 00 02 2b 8b 15 01 00 00 00 00 02 2d 03 15 01 00 00 00 00 02 2f 8d 15 01 00 00 00 00 02 30 03 15 01 00 00 00 00 02 31 8e 15 01 00 00 00 00 02 32 00 15 01 00 00 00 00 02 33 71 15 01 00 00 00 00 02 34 00 15 01 00 00 00 00 02 35 84 15 01 00 00 00 00 02 36 00 15 01 00 00 00 00 02 37 a5 15 01 00 00 00 00 02 38 00 15 01 00 00 00 00 02 39 bb 15 01 00 00 00 00 02 3a 00 15 01 00 00 00 00 02 3b ce 15 01 00 00 00 00 02 3d 00 15 01 00 00 00 00 02 3f e0 15 01 00 00 00 00 02 40 00 15 01 00 00 00 00 02 41 ef 15 01 00 00 00 00 02 42 00 15 01 00 00 00 00 02 43 ff 15 01 00 00 00 00 02 44 01 15 01 00 00 00 00 02 45 0b 15 01 00 00 00 00 02 46 01 15 01 00 00 00 00 02 47 38 15 01 00 00 00 00 02 48 01 15 01 00 00 00 00 02 49 5b 15 01 00 00 00 00 02 4a 01 15 01 00 00 00 00 02 4b 95 15 01 00 00 00 00 02 4c 01 15 01 00 00 00 00 02 4d c4 15 01 00 00 00 00 02 4e 02 15 01 00 00 00 00 02 4f 0d 15 01 00 00 00 00 02 50 02 15 01 00 00 00 00 02 51 4a 15 01 00 00 00 00 02 52 02 15 01 00 00 00 00 02 53 4c 15 01 00 00 00 00 02 54 02 15 01 00 00 00 00 02 55 85 15 01 00 00 00 00 02 56 02 15 01 00 00 00 00 02 58 c3 15 01 00 00 00 00 02 59 02 15 01 00 00 00 00 02 5a e9 15 01 00 00 00 00 02 5b 03 15 01 00 00 00 00 02 5c 16 15 01 00 00 00 00 02 5d 03 15 01 00 00 00 00 02 5e 34 15 01 00 00 00 00 02 5f 03 15 01 00 00 00 00 02 60 56 15 01 00 00 00 00 02 61 03 15 01 00 00 00 00 02 62 62 15 01 00 00 00 00 02 63 03 15 01 00 00 00 00 02 64 6c 15 01 00 00 00 00 02 65 03 15 01 00 00 00 00 02 66 74 15 01 00 00 00 00 02 67 03 15 01 00 00 00 00 02 68 80 15 01 00 00 00 00 02 69 03 15 01 00 00 00 00 02 6a 89 15 01 00 00 00 00 02 6b 03 15 01 00 00 00 00 02 6c 8b 15 01 00 00 00 00 02 6d 03 15 01 00 00 00 00 02 6e 8d 15 01 00 00 00 00 02 6f 03 15 01 00 00 00 00 02 70 8e 15 01 00 00 00 00 02 71 00 15 01 00 00 00 00 02 72 71 15 01 00 00 00 00 02 73 00 15 01 00 00 00 00 02 74 84 15 01 00 00 00 00 02 75 00 15 01 00 00 00 00 02 76 a5 15 01 00 00 00 00 02 77 00 15 01 00 00 00 00 02 78 bb 15 01 00 00 00 00 02 79 00 15 01 00 00 00 00 02 7a ce 15 01 00 00 00 00 02 7b 00 15 01 00 00 00 00 02 7c e0 15 01 00 00 00 00 02 7d 00 15 01 00 00 00 00 02 7e ef 15 01 00 00 00 00 02 7f 00 15 01 00 00 00 00 02 80 ff 15 01 00 00 00 00 02 81 01 15 01 00 00 00 00 02 82 0b 15 01 00 00 00 00 02 83 01 15 01 00 00 00 00 02 84 38 15 01 00 00 00 00 02 85 01 15 01 00 00 00 00 02 86 5b 15 01 00 00 00 00 02 87 01 15 01 00 00 00 00 02 88 95 15 01 00 00 00 00 02 89 01 15 01 00 00 00 00 02 8a c4 15 01 00 00 00 00 02 8b 02 15 01 00 00 00 00 02 8c 0d 15 01 00 00 00 00 02 8d 02 15 01 00 00 00 00 02 8e 4a 15 01 00 00 00 00 02 8f 02 15 01 00 00 00 00 02 90 4c 15 01 00 00 00 00 02 91 02 15 01 00 00 00 00 02 92 85 15 01 00 00 00 00 02 93 02 15 01 00 00 00 00 02 94 c3 15 01 00 00 00 00 02 95 02 15 01 00 00 00 00 02 96 e9 15 01 00 00 00 00 02 97 03 15 01 00 00 00 00 02 98 16 15 01 00 00 00 00 02 99 03 15 01 00 00 00 00 02 9a 34 15 01 00 00 00 00 02 9b 03 15 01 00 00 00 00 02 9c 56 15 01 00 00 00 00 02 9d 03 15 01 00 00 00 00 02 9e 62 15 01 00 00 00 00 02 9f 03 15 01 00 00 00 00 02 a0 6c 15 01 00 00 00 00 02 a2 03 15 01 00 00 00 00 02 a3 74 15 01 00 00 00 00 02 a4 03 15 01 00 00 00 00 02 a5 80 15 01 00 00 00 00 02 a6 03 15 01 00 00 00 00 02 a7 89 15 01 00 00 00 00 02 a9 03 15 01 00 00 00 00 02 aa 8b 15 01 00 00 00 00 02 ab 03 15 01 00 00 00 00 02 ac 8d 15 01 00 00 00 00 02 ad 03 15 01 00 00 00 00 02 ae 8e 15 01 00 00 00 00 02 af 00 15 01 00 00 00 00 02 b0 71 15 01 00 00 00 00 02 b1 00 15 01 00 00 00 00 02 b2 84 15 01 00 00 00 00 02 b3 00 15 01 00 00 00 00 02 b4 a5 15 01 00 00 00 00 02 b5 00 15 01 00 00 00 00 02 b6 bb 15 01 00 00 00 00 02 b7 00 15 01 00 00 00 00 02 b8 ce 15 01 00 00 00 00 02 b9 00 15 01 00 00 00 00 02 ba e0 15 01 00 00 00 00 02 bb 00 15 01 00 00 00 00 02 bc ef 15 01 00 00 00 00 02 bd 00 15 01 00 00 00 00 02 be ff 15 01 00 00 00 00 02 bf 01 15 01 00 00 00 00 02 c0 0b 15 01 00 00 00 00 02 c1 01 15 01 00 00 00 00 02 c2 38 15 01 00 00 00 00 02 c3 01 15 01 00 00 00 00 02 c4 5b 15 01 00 00 00 00 02 c5 01 15 01 00 00 00 00 02 c6 95 15 01 00 00 00 00 02 c7 01 15 01 00 00 00 00 02 c8 c4 15 01 00 00 00 00 02 c9 02 15 01 00 00 00 00 02 ca 0d 15 01 00 00 00 00 02 cb 02 15 01 00 00 00 00 02 cc 4a 15 01 00 00 00 00 02 cd 02 15 01 00 00 00 00 02 ce 4c 15 01 00 00 00 00 02 cf 02 15 01 00 00 00 00 02 d0 85 15 01 00 00 00 00 02 d1 02 15 01 00 00 00 00 02 d2 c3 15 01 00 00 00 00 02 d3 02 15 01 00 00 00 00 02 d4 e9 15 01 00 00 00 00 02 d5 03 15 01 00 00 00 00 02 d6 16 15 01 00 00 00 00 02 d7 03 15 01 00 00 00 00 02 d8 34 15 01 00 00 00 00 02 d9 03 15 01 00 00 00 00 02 da 56 15 01 00 00 00 00 02 db 03 15 01 00 00 00 00 02 dc 62 15 01 00 00 00 00 02 dd 03 15 01 00 00 00 00 02 de 6c 15 01 00 00 00 00 02 df 03 15 01 00 00 00 00 02 e0 74 15 01 00 00 00 00 02 e1 03 15 01 00 00 00 00 02 e2 80 15 01 00 00 00 00 02 e3 03 15 01 00 00 00 00 02 e4 89 15 01 00 00 00 00 02 e5 03 15 01 00 00 00 00 02 e6 8b 15 01 00 00 00 00 02 e7 03 15 01 00 00 00 00 02 e8 8d 15 01 00 00 00 00 02 e9 03 15 01 00 00 00 00 02 ea 8e 15 01 00 00 00 00 02 ff 10 05 01 00 00 00 00 01 29]; | |
| qcom,mdss-dsi-off-command = [15 01 00 00 00 00 02 ff 10 05 01 00 00 10 00 01 28 15 01 00 00 00 00 02 b0 00 05 01 00 00 40 00 01 10 15 01 00 00 00 00 02 4f 01]; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-h-back-porch = <0x04>; | |
| qcom,mdss-dsi-v-back-porch = <0x0c>; | |
| qcom,mdss-dsi-panel-width = <0x21c>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-h-front-porch = <0x1c>; | |
| qcom,mdss-dsi-v-front-porch = <0x0c>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsi-panel-height = <0x780>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,display-topology = <0x02 0x00 0x02 0x01 0x00 0x02>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = <0x240909 0x26240909 0x6030400>; | |
| qcom,mdss-dsi-panel-framerate = <0x78>; | |
| qcom,mdss-dsi-h-pulse-width = <0x04>; | |
| qcom,mdss-dsi-v-pulse-width = <0x02>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_nt35597_wqxga_video_truly { | |
| qcom,esd-check-enabled; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-t-clk-pre = <0x2d>; | |
| qcom,mdss-dsi-bl-min-level = <0x01>; | |
| qcom,mdss-dsi-panel-name = "Dual nt35597 video mode dsi truly panel without DSC"; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-panel-status-check-mode = "reg_read"; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x14 0x00 0x14 0x01 0x32>; | |
| qcom,mdss-dsi-pan-enable-dynamic-fps; | |
| qcom,mdss-dsi-tx-eot-append; | |
| qcom,mdss-dsi-panel-hdr-enabled; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; | |
| qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; | |
| qcom,mdss-dsi-mode-sel-gpio-state = "dual_port"; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-panel-peak-brightness = <0x401640>; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-underflow-color = <0x3ff>; | |
| qcom,mdss-dsi-panel-status-read-length = <0x01>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-pan-physical-width-dimension = <0x4a>; | |
| qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| phandle = <0x4e7>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
| qcom,mdss-dsi-panel-status-value = <0x9c>; | |
| qcom,mdss-pan-physical-height-dimension = <0x83>; | |
| qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; | |
| qcom,mdss-dsi-panel-blackness-level = <0xc9e>; | |
| qcom,mdss-dsi-bl-max-level = <0xfff>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,panel-supply-entries = <0x4de>; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,mdss-dsi-panel-on-check-value = <0x9c>; | |
| qcom,platform-reset-gpio = <0x34 0x06 0x00>; | |
| qcom,mdss-dsi-t-clk-post = <0x0d>; | |
| qcom,dsi-supported-dfps-list = <0x3c 0x37 0x35>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@0 { | |
| qcom,mdss-dsi-on-command = [15 01 00 00 00 00 02 ff 20 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 01 15 01 00 00 00 00 02 01 55 15 01 00 00 00 00 02 02 45 15 01 00 00 00 00 02 05 40 15 01 00 00 00 00 02 06 19 15 01 00 00 00 00 02 07 1e 15 01 00 00 00 00 02 0b 73 15 01 00 00 00 00 02 0c 73 15 01 00 00 00 00 02 0e b0 15 01 00 00 00 00 02 0f ae 15 01 00 00 00 00 02 11 b8 15 01 00 00 00 00 02 13 00 15 01 00 00 00 00 02 58 80 15 01 00 00 00 00 02 59 01 15 01 00 00 00 00 02 5a 00 15 01 00 00 00 00 02 5b 01 15 01 00 00 00 00 02 5c 80 15 01 00 00 00 00 02 5d 81 15 01 00 00 00 00 02 5e 00 15 01 00 00 00 00 02 5f 01 15 01 00 00 00 00 02 72 11 15 01 00 00 00 00 02 68 03 15 01 00 00 00 00 02 ff 24 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 1c 15 01 00 00 00 00 02 01 0b 15 01 00 00 00 00 02 02 0c 15 01 00 00 00 00 02 03 01 15 01 00 00 00 00 02 04 0f 15 01 00 00 00 00 02 05 10 15 01 00 00 00 00 02 06 10 15 01 00 00 00 00 02 07 10 15 01 00 00 00 00 02 08 89 15 01 00 00 00 00 02 09 8a 15 01 00 00 00 00 02 0a 13 15 01 00 00 00 00 02 0b 13 15 01 00 00 00 00 02 0c 15 15 01 00 00 00 00 02 0d 15 15 01 00 00 00 00 02 0e 17 15 01 00 00 00 00 02 0f 17 15 01 00 00 00 00 02 10 1c 15 01 00 00 00 00 02 11 0b 15 01 00 00 00 00 02 12 0c 15 01 00 00 00 00 02 13 01 15 01 00 00 00 00 02 14 0f 15 01 00 00 00 00 02 15 10 15 01 00 00 00 00 02 16 10 15 01 00 00 00 00 02 17 10 15 01 00 00 00 00 02 18 89 15 01 00 00 00 00 02 19 8a 15 01 00 00 00 00 02 1a 13 15 01 00 00 00 00 02 1b 13 15 01 00 00 00 00 02 1c 15 15 01 00 00 00 00 02 1d 15 15 01 00 00 00 00 02 1e 17 15 01 00 00 00 00 02 1f 17 15 01 00 00 00 00 02 20 40 15 01 00 00 00 00 02 21 01 15 01 00 00 00 00 02 22 00 15 01 00 00 00 00 02 23 40 15 01 00 00 00 00 02 24 40 15 01 00 00 00 00 02 25 6d 15 01 00 00 00 00 02 26 40 15 01 00 00 00 00 02 27 40 15 01 00 00 00 00 02 e0 00 15 01 00 00 00 00 02 dc 21 15 01 00 00 00 00 02 dd 22 15 01 00 00 00 00 02 de 07 15 01 00 00 00 00 02 df 07 15 01 00 00 00 00 02 e3 6d 15 01 00 00 00 00 02 e1 07 15 01 00 00 00 00 02 e2 07 15 01 00 00 00 00 02 29 d8 15 01 00 00 00 00 02 2a 2a 15 01 00 00 00 00 02 4b 03 15 01 00 00 00 00 02 4c 11 15 01 00 00 00 00 02 4d 10 15 01 00 00 00 00 02 4e 01 15 01 00 00 00 00 02 4f 01 15 01 00 00 00 00 02 50 10 15 01 00 00 00 00 02 51 00 15 01 00 00 00 00 02 52 80 15 01 00 00 00 00 02 53 00 15 01 00 00 00 00 02 56 00 15 01 00 00 00 00 02 54 07 15 01 00 00 00 00 02 58 07 15 01 00 00 00 00 02 55 25 15 01 00 00 00 00 02 5b 43 15 01 00 00 00 00 02 5c 00 15 01 00 00 00 00 02 5f 73 15 01 00 00 00 00 02 60 73 15 01 00 00 00 00 02 63 22 15 01 00 00 00 00 02 64 00 15 01 00 00 00 00 02 67 08 15 01 00 00 00 00 02 68 04 15 01 00 00 00 00 02 72 02 15 01 00 00 00 00 02 7a 80 15 01 00 00 00 00 02 7b 91 15 01 00 00 00 00 02 7c d8 15 01 00 00 00 00 02 7d 60 15 01 00 00 00 00 02 7f 15 15 01 00 00 00 00 02 75 15 15 01 00 00 00 00 02 b3 c0 15 01 00 00 00 00 02 b4 00 15 01 00 00 00 00 02 b5 00 15 01 00 00 00 00 02 78 00 15 01 00 00 00 00 02 79 00 15 01 00 00 00 00 02 80 00 15 01 00 00 00 00 02 83 00 15 01 00 00 00 00 02 93 0a 15 01 00 00 00 00 02 94 0a 15 01 00 00 00 00 02 8a 00 15 01 00 00 00 00 02 9b ff 15 01 00 00 00 00 02 9d b0 15 01 00 00 00 00 02 9f 63 15 01 00 00 00 00 02 98 10 15 01 00 00 00 00 02 ec 00 15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 04 3b 03 0a 0a 15 01 00 00 00 00 02 35 00 15 01 00 00 00 00 02 e5 01 15 01 00 00 00 00 02 bb 03 15 01 00 00 00 00 02 fb 01 05 01 00 00 78 00 02 11 00 05 01 00 00 78 00 02 29 00]; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-h-back-porch = <0x20>; | |
| qcom,mdss-dsi-v-back-porch = <0x07>; | |
| qcom,mdss-dsi-panel-width = <0x2d0>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-h-front-porch = <0x64>; | |
| qcom,mdss-dsi-v-front-porch = <0x08>; | |
| qcom,mdss-dsi-panel-height = <0xa00>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,display-topology = <0x02 0x00 0x02 0x01 0x00 0x02>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = <0x1c0707 0x23210707 0x5030400>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x10>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,default-topology-index = <0x00>; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_sharp_4k_dsc_cmd { | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-t-clk-pre = <0x27>; | |
| qcom,mdss-dsi-panel-name = "Sharp 4k cmd mode dsc dsi panel"; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0xc8 0x00 0xc8 0x01 0xc8>; | |
| qcom,mdss-dsi-te-check-enable; | |
| qcom,mdss-dsi-tx-eot-append; | |
| qcom,mdss-dsi-te-pin-select = <0x01>; | |
| qcom,mdss-dsi-te-using-te-pin; | |
| qcom,mdss-dsi-panel-hdr-enabled; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-te-dcs-command = <0x01>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-panel-peak-brightness = <0x401640>; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,dcs-cmd-by-left; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-pan-physical-width-dimension = <0x47>; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| phandle = <0x4e4>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
| qcom,mdss-pan-physical-height-dimension = <0x81>; | |
| qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; | |
| qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
| qcom,mdss-dsi-panel-blackness-level = <0xc9e>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-traffic-mode = "burst_mode"; | |
| qcom,adjust-timer-wakeup-ms = <0x01>; | |
| qcom,mdss-dsi-t-clk-post = <0x0c>; | |
| qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@0 { | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 11 91 09 20 00 20 02 00 03 1c 04 21 00 0f 03 19 01 97 39 01 00 00 00 00 03 92 10 f0 15 01 00 00 00 00 02 90 03 15 01 00 00 00 00 02 03 01 39 01 00 00 00 00 06 f0 55 aa 52 08 04 15 01 00 00 00 00 02 c0 03 39 01 00 00 00 00 06 f0 55 aa 52 08 07 15 01 00 00 00 00 02 ef 01 39 01 00 00 00 00 06 f0 55 aa 52 08 00 15 01 00 00 00 00 02 b4 01 15 01 00 00 00 00 02 35 00 39 01 00 00 00 00 06 f0 55 aa 52 08 01 39 01 00 00 00 00 05 ff aa 55 a5 80 15 01 00 00 00 00 02 6f 01 15 01 00 00 00 00 02 f3 10 39 01 00 00 00 00 05 ff aa 55 a5 00 05 01 00 00 78 00 01 11 05 01 00 00 78 00 01 29]; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-h-back-porch = <0x64>; | |
| qcom,mdss-dsi-v-back-porch = <0x07>; | |
| qcom,mdss-dsi-panel-jitter = <0x08 0x0a>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-h-front-porch = <0x1e>; | |
| qcom,mdss-dsi-v-front-porch = <0x08>; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-panel-height = <0xf00>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,display-topology = <0x02 0x02 0x02>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = <0x180606 0x21200606 0x4030400>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x04>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsc-slice-width = <0x438>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsc-slice-height = <0x20>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_dual_sim_cmd { | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-color-order = "rgb_swap_rgb"; | |
| qcom,mdss-dsi-t-clk-pre = <0x2d>; | |
| qcom,mdss-dsi-panel-name = "Sim dual cmd mode dsi panel"; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; | |
| qcom,mdss-dsi-te-check-enable; | |
| qcom,mdss-dsi-te-using-wd; | |
| qcom,mdss-dsi-te-pin-select = <0x01>; | |
| qcom,mdss-dsi-te-using-te-pin; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-te-dcs-command = <0x01>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,mdss-dsi-hor-line-idle = <0x00 0x28 0x100 0x28 0x78 0x80 0x78 0xf0 0x40>; | |
| qcom,cmd-sync-wait-broadcast; | |
| phandle = <0x4ee>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
| qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
| qcom,mdss-dsi-bl-max-level = <0xfff>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,panel-supply-entries = <0x4de>; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,platform-reset-gpio = <0x34 0x06 0x00>; | |
| qcom,mdss-dsi-t-clk-post = <0x0d>; | |
| qcom,panel-ack-disabled; | |
| qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@1 { | |
| qcom,mdss-dsi-on-command = <0x5010000 0x129>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 00 00 02 28 00 05 01 00 00 00 00 02 10 00]; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-h-back-porch = <0x20>; | |
| qcom,mdss-dsi-v-back-porch = <0x07>; | |
| qcom,mdss-dsi-panel-width = <0x2d0>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-h-front-porch = <0x64>; | |
| qcom,mdss-dsi-v-front-porch = <0x08>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsi-panel-height = <0xa00>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,display-topology = <0x02 0x00 0x02 0x01 0x00 0x02>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = <0x300c0d 0x2a270c0d 0x9030400>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x10>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| }; | |
| timing@2 { | |
| qcom,mdss-dsi-on-command = <0x5010000 0x129>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 00 00 02 28 00 05 01 00 00 00 00 02 10 00]; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-h-back-porch = <0x64>; | |
| qcom,mdss-dsi-v-back-porch = <0x07>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-h-front-porch = <0x1e>; | |
| qcom,mdss-dsi-v-front-porch = <0x08>; | |
| qcom,mdss-dsi-panel-height = <0xf00>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,display-topology = <0x02 0x00 0x02>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = <0x180606 0x21200606 0x4030400>; | |
| qcom,mdss-dsi-panel-framerate = <0x28>; | |
| qcom,mdss-dsi-h-pulse-width = <0x04>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,default-topology-index = <0x00>; | |
| }; | |
| timing@0 { | |
| qcom,mdss-dsi-on-command = <0x5010000 0x129>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 00 00 02 28 00 05 01 00 00 00 00 02 10 00]; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-h-back-porch = <0x04>; | |
| qcom,mdss-dsi-v-back-porch = <0x0c>; | |
| qcom,mdss-dsi-panel-width = <0x21c>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-h-front-porch = <0x1c>; | |
| qcom,mdss-dsi-v-front-porch = <0x0c>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsi-panel-height = <0x780>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,display-topology = <0x02 0x00 0x02>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = <0x240909 0x26240909 0x6030400>; | |
| qcom,mdss-dsi-panel-framerate = <0x78>; | |
| qcom,mdss-dsi-h-pulse-width = <0x04>; | |
| qcom,mdss-dsi-v-pulse-width = <0x02>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_s6e3ha3_amoled_wqhd_cmd { | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-on-command = [05 01 00 00 05 00 02 11 00 39 01 00 00 00 00 05 2a 00 00 05 9f 39 01 00 00 00 00 05 2b 00 00 09 ff 39 01 00 00 00 00 03 f0 5a 5a 39 01 00 00 00 00 02 b0 10 39 01 00 00 00 00 02 b5 a0 39 01 00 00 00 00 02 c4 03 39 01 00 00 00 00 0a f6 42 57 37 00 aa cc d0 00 00 39 01 00 00 00 00 02 f9 03 39 01 00 00 00 00 14 c2 00 00 d8 d8 00 80 2b 05 08 0e 07 0b 05 0d 0a 15 13 20 1e 39 01 00 00 78 00 03 f0 a5 a5 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 02 53 20 39 01 00 00 00 00 02 51 60 05 01 00 00 05 00 02 29 00]; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 3c 00 02 28 00 05 01 00 00 b4 00 02 10 00]; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,mdss-dsi-color-order = "rgb_swap_rgb"; | |
| qcom,mdss-dsi-bl-min-level = <0x01>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-h-back-porch = <0x64>; | |
| qcom,mdss-dsi-v-back-porch = <0x1f>; | |
| qcom,mdss-dsi-panel-name = "Dual s6e3ha3 amoled cmd mode dsi panel"; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-lp11-init; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-panel-width = <0x2d0>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; | |
| qcom,mdss-dsi-te-check-enable; | |
| qcom,mdss-dsi-tx-eot-append; | |
| qcom,mdss-dsi-lp-mode-off = [39 00 00 00 05 00 03 f0 5a 5a 39 00 00 00 05 00 03 f1 5a 5a 39 00 00 00 05 00 03 fc 5a 5a 39 00 00 00 05 00 02 b0 2d 39 00 00 00 05 00 02 cb 4d 39 00 00 00 05 00 02 b0 17 39 00 00 00 05 00 02 cb 04 39 00 00 00 05 00 02 b0 0e 39 00 00 00 05 00 02 cb 06 39 00 00 00 05 00 02 b0 0f 39 00 00 00 05 00 02 cb 05 39 00 00 00 05 00 02 b0 02 39 00 00 00 05 00 02 f2 b8 39 00 00 00 05 00 02 b0 03 39 00 00 00 05 00 02 f2 80 39 00 00 00 05 00 02 b0 03 39 00 00 00 05 00 02 f4 8a 39 00 00 00 05 00 02 b0 08 39 00 00 00 05 00 02 b1 10 39 00 00 00 05 00 02 b0 09 39 00 00 00 05 00 02 b1 0a 39 00 00 00 05 00 02 b0 0d 39 00 00 00 05 00 02 b1 80 39 00 00 00 05 00 02 b0 00 39 00 00 00 05 00 02 f7 03 39 00 00 00 05 00 02 fe 30 39 01 00 00 05 00 02 fe b0]; | |
| qcom,mdss-dsi-te-pin-select = <0x01>; | |
| qcom,mdss-dsi-te-using-te-pin; | |
| qcom,mdss-dsi-h-front-porch = <0x64>; | |
| qcom,mdss-dsi-v-front-porch = <0x1e>; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsi-panel-height = <0xa00>; | |
| qcom,mdss-dsi-te-dcs-command = <0x01>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,dcs-cmd-by-left; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-pan-physical-width-dimension = <0x44>; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| phandle = <0x53b>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
| qcom,mdss-dsi-lane-map = "lane_map_0123"; | |
| qcom,mdss-pan-physical-height-dimension = <0x7a>; | |
| qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-bl-max-level = <0xff>; | |
| qcom,mdss-dsi-lp-mode-on = [39 00 00 00 05 00 03 f0 5a 5a 39 00 00 00 05 00 03 f1 5a 5a 39 00 00 00 05 00 03 fc 5a 5a 39 00 00 00 05 00 02 b0 17 39 00 00 00 05 00 02 cb 10 39 00 00 00 05 00 02 b0 2d 39 00 00 00 05 00 02 cb cd 39 00 00 00 05 00 02 b0 0e 39 00 00 00 05 00 02 cb 02 39 00 00 00 05 00 02 b0 0f 39 00 00 00 05 00 02 cb 09 39 00 00 00 05 00 02 b0 02 39 00 00 00 05 00 02 f2 c9 39 00 00 00 05 00 02 b0 03 39 00 00 00 05 00 02 f2 c0 39 00 00 00 05 00 02 b0 03 39 00 00 00 05 00 02 f4 aa 39 00 00 00 05 00 02 b0 08 39 00 00 00 05 00 02 b1 30 39 00 00 00 05 00 02 b0 09 39 00 00 00 05 00 02 b1 0a 39 00 00 00 05 00 02 b0 0d 39 00 00 00 05 00 02 b1 10 39 00 00 00 05 00 02 b0 00 39 00 00 00 05 00 02 f7 03 39 00 00 00 05 00 02 fe 30 39 01 00 00 05 00 02 fe b0]; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-h-pulse-width = <0x28>; | |
| qcom,mdss-dsi-v-pulse-width = <0x08>; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
| }; | |
| qcom,mdss_dsi_dual_sim_dsc_375_cmd { | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-color-order = "rgb_swap_rgb"; | |
| qcom,mdss-dsi-t-clk-pre = <0x2d>; | |
| qcom,mdss-dsi-panel-name = "Sim dual cmd mode DSC 3.75:1 dsi panel"; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; | |
| qcom,mdss-dsi-te-check-enable; | |
| qcom,mdss-dsi-te-using-wd; | |
| qcom,mdss-dsi-te-pin-select = <0x01>; | |
| qcom,mdss-dsi-te-using-te-pin; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-te-dcs-command = <0x01>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,mdss-dsi-hor-line-idle = <0x00 0x28 0x100 0x28 0x78 0x80 0x78 0xf0 0x40>; | |
| qcom,cmd-sync-wait-broadcast; | |
| phandle = <0x4f0>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
| qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
| qcom,mdss-dsi-bl-max-level = <0xfff>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,panel-supply-entries = <0x4de>; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,platform-reset-gpio = <0x34 0x06 0x00>; | |
| qcom,mdss-dsi-t-clk-post = <0x0d>; | |
| qcom,panel-ack-disabled; | |
| qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@1 { | |
| qcom,mdss-dsi-on-command = [15 01 00 00 00 00 02 ff 20 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 01 15 01 00 00 00 00 02 01 55 15 01 00 00 00 00 02 02 45 15 01 00 00 00 00 02 05 40 15 01 00 00 00 00 02 06 19 15 01 00 00 00 00 02 07 1e 15 01 00 00 00 00 02 0b 73 15 01 00 00 00 00 02 0c 73 15 01 00 00 00 00 02 0e b0 15 01 00 00 00 00 02 0f ae 15 01 00 00 00 00 02 11 b8 15 01 00 00 00 00 02 13 00 15 01 00 00 00 00 02 58 80 15 01 00 00 00 00 02 59 01 15 01 00 00 00 00 02 5a 00 15 01 00 00 00 00 02 5b 01 15 01 00 00 00 00 02 5c 80 15 01 00 00 00 00 02 5d 81 15 01 00 00 00 00 02 5e 00 15 01 00 00 00 00 02 5f 01 15 01 00 00 00 00 02 72 31 15 01 00 00 00 00 02 68 03 15 01 00 00 00 00 02 ff 24 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 1c 15 01 00 00 00 00 02 01 0b 15 01 00 00 00 00 02 02 0c 15 01 00 00 00 00 02 03 01 15 01 00 00 00 00 02 04 0f 15 01 00 00 00 00 02 05 10 15 01 00 00 00 00 02 06 10 15 01 00 00 00 00 02 07 10 15 01 00 00 00 00 02 08 89 15 01 00 00 00 00 02 09 8a 15 01 00 00 00 00 02 0a 13 15 01 00 00 00 00 02 0b 13 15 01 00 00 00 00 02 0c 15 15 01 00 00 00 00 02 0d 15 15 01 00 00 00 00 02 0e 17 15 01 00 00 00 00 02 0f 17 15 01 00 00 00 00 02 10 1c 15 01 00 00 00 00 02 11 0b 15 01 00 00 00 00 02 12 0c 15 01 00 00 00 00 02 13 01 15 01 00 00 00 00 02 14 0f 15 01 00 00 00 00 02 15 10 15 01 00 00 00 00 02 16 10 15 01 00 00 00 00 02 17 10 15 01 00 00 00 00 02 18 89 15 01 00 00 00 00 02 19 8a 15 01 00 00 00 00 02 1a 13 15 01 00 00 00 00 02 1b 13 15 01 00 00 00 00 02 1c 15 15 01 00 00 00 00 02 1d 15 15 01 00 00 00 00 02 1e 17 15 01 00 00 00 00 02 1f 17 15 01 00 00 00 00 02 20 40 15 01 00 00 00 00 02 21 01 15 01 00 00 00 00 02 22 00 15 01 00 00 00 00 02 23 40 15 01 00 00 00 00 02 24 40 15 01 00 00 00 00 02 25 6d 15 01 00 00 00 00 02 26 40 15 01 00 00 00 00 02 27 40 15 01 00 00 00 00 02 e0 00 15 01 00 00 00 00 02 dc 21 15 01 00 00 00 00 02 dd 22 15 01 00 00 00 00 02 de 07 15 01 00 00 00 00 02 df 07 15 01 00 00 00 00 02 e3 6d 15 01 00 00 00 00 02 e1 07 15 01 00 00 00 00 02 e2 07 15 01 00 00 00 00 02 29 d8 15 01 00 00 00 00 02 2a 2a 15 01 00 00 00 00 02 4b 03 15 01 00 00 00 00 02 4c 11 15 01 00 00 00 00 02 4d 10 15 01 00 00 00 00 02 4e 01 15 01 00 00 00 00 02 4f 01 15 01 00 00 00 00 02 50 10 15 01 00 00 00 00 02 51 00 15 01 00 00 00 00 02 52 80 15 01 00 00 00 00 02 53 00 15 01 00 00 00 00 02 56 00 15 01 00 00 00 00 02 54 07 15 01 00 00 00 00 02 58 07 15 01 00 00 00 00 02 55 25 15 01 00 00 00 00 02 5b 43 15 01 00 00 00 00 02 5c 00 15 01 00 00 00 00 02 5f 73 15 01 00 00 00 00 02 60 73 15 01 00 00 00 00 02 63 22 15 01 00 00 00 00 02 64 00 15 01 00 00 00 00 02 67 08 15 01 00 00 00 00 02 68 04 15 01 00 00 00 00 02 72 02 15 01 00 00 00 00 02 7a 80 15 01 00 00 00 00 02 7b 91 15 01 00 00 00 00 02 7c d8 15 01 00 00 00 00 02 7d 60 15 01 00 00 00 00 02 7f 15 15 01 00 00 00 00 02 75 15 15 01 00 00 00 00 02 b3 c0 15 01 00 00 00 00 02 b4 00 15 01 00 00 00 00 02 b5 00 15 01 00 00 00 00 02 78 00 15 01 00 00 00 00 02 79 00 15 01 00 00 00 00 02 80 00 15 01 00 00 00 00 02 83 00 15 01 00 00 00 00 02 93 0a 15 01 00 00 00 00 02 94 0a 15 01 00 00 00 00 02 8a 00 15 01 00 00 00 00 02 9b ff 15 01 00 00 00 00 02 9d b0 15 01 00 00 00 00 02 9f 63 15 01 00 00 00 00 02 98 10 15 01 00 00 00 00 02 ec 00 15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 04 3b 03 0a 0a 15 01 00 00 00 00 02 35 00 15 01 00 00 00 00 02 e5 01 15 01 00 00 00 00 02 bb 10 15 01 00 00 00 00 02 fb 01 05 01 00 00 78 00 02 11 00 05 01 00 00 78 00 02 29 00]; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-h-back-porch = <0x20>; | |
| qcom,mdss-dsi-v-back-porch = <0x07>; | |
| qcom,mdss-dsi-panel-width = <0x2d0>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-h-front-porch = <0x64>; | |
| qcom,mdss-dsi-v-front-porch = <0x08>; | |
| qcom,mdss-dsc-bit-per-component = <0x0a>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsi-panel-height = <0xa00>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,display-topology = <0x02 0x02 0x02>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = <0x180606 0x21200606 0x4030400>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x10>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsc-slice-width = <0x2d0>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsc-slice-height = <0x10>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| }; | |
| timing@0 { | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 11 91 09 20 00 20 02 00 03 1c 04 21 00 0f 03 19 01 97 39 01 00 00 00 00 03 92 10 f0 15 01 00 00 00 00 02 90 03 15 01 00 00 00 00 02 03 01 39 01 00 00 00 00 06 f0 55 aa 52 08 04 15 01 00 00 00 00 02 c0 03 39 01 00 00 00 00 06 f0 55 aa 52 08 07 15 01 00 00 00 00 02 ef 01 39 01 00 00 00 00 06 f0 55 aa 52 08 00 15 01 00 00 00 00 02 b4 01 15 01 00 00 00 00 02 35 00 39 01 00 00 00 00 06 f0 55 aa 52 08 01 39 01 00 00 00 00 05 ff aa 55 a5 80 15 01 00 00 00 00 02 6f 01 15 01 00 00 00 00 02 f3 10 39 01 00 00 00 00 05 ff aa 55 a5 00 05 01 00 00 78 00 01 11 05 01 00 00 78 00 01 29]; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-h-back-porch = <0x64>; | |
| qcom,mdss-dsi-v-back-porch = <0x07>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-h-front-porch = <0x1e>; | |
| qcom,mdss-dsi-v-front-porch = <0x08>; | |
| qcom,mdss-dsc-bit-per-component = <0x0a>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-panel-height = <0xf00>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,display-topology = <0x02 0x02 0x02>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = <0x1c0707 0x23210707 0x5030400>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x04>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsc-slice-width = <0x438>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsc-slice-height = <0x20>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_test_oled_cmd { | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-color-order = "rgb_swap_rgb"; | |
| qcom,mdss-dsi-panel-name = "Dual test cmd mode DSI amoled non-DSC panel"; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x02 0x00 0x02 0x01 0x02>; | |
| qcom,mdss-dsi-te-check-enable; | |
| qcom,mdss-dsi-hfp-power-mode; | |
| qcom,mdss-dsi-te-pin-select = <0x01>; | |
| qcom,mdss-dsi-te-using-te-pin; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-te-dcs-command = <0x01>; | |
| qcom,mdss-dsi-hbp-power-mode; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| phandle = <0x4f4>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
| qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
| qcom,mdss-dsi-bl-max-level = <0xfff>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-hsa-power-mode; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,adjust-timer-wakeup-ms = <0x01>; | |
| qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@0 { | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_nt35597_wqxga_video { | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-t-clk-pre = <0x2d>; | |
| qcom,mdss-dsi-bl-min-level = <0x01>; | |
| qcom,mdss-dsi-panel-name = "Dual nt35597 video mode dsi panel without DSC"; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-max-refresh-rate = <0x3c>; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; | |
| qcom,mdss-dsi-pan-enable-dynamic-fps; | |
| qcom,mdss-dsi-panel-hdr-enabled; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; | |
| qcom,mdss-dsi-mode-sel-gpio-state = "dual_port"; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-panel-peak-brightness = <0x401640>; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-underflow-color = <0x3ff>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-pan-physical-width-dimension = <0x4a>; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,cmd-sync-wait-broadcast; | |
| phandle = <0x4f1>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
| qcom,mdss-pan-physical-height-dimension = <0x83>; | |
| qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; | |
| qcom,mdss-dsi-panel-blackness-level = <0xc9e>; | |
| qcom,mdss-dsi-bl-max-level = <0xfff>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,panel-supply-entries = <0x4de>; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; | |
| qcom,mdss-dsi-min-refresh-rate = <0x37>; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,platform-reset-gpio = <0x34 0x06 0x00>; | |
| qcom,mdss-dsi-t-clk-post = <0x0d>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@0 { | |
| qcom,mdss-dsi-on-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 ba 03 15 01 00 00 00 00 02 e5 01 15 01 00 00 00 00 02 35 00 15 01 00 00 00 00 02 bb 03 15 01 00 00 00 00 02 b0 03 39 01 00 00 00 00 06 3b 03 08 08 64 9a 15 01 00 00 00 00 02 ff e0 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 6b 3d 15 01 00 00 00 00 02 6c 3d 15 01 00 00 00 00 02 6d 3d 15 01 00 00 00 00 02 6e 3d 15 01 00 00 00 00 02 6f 3d 15 01 00 00 00 00 02 35 02 15 01 00 00 00 00 02 36 72 15 01 00 00 00 00 02 37 10 15 01 00 00 00 00 02 08 c0 15 01 00 00 00 00 02 ff 10 05 01 00 00 78 00 02 11 00 05 01 00 00 32 00 02 29 00]; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 0a 00 02 28 00 05 01 00 00 3c 00 02 10 00]; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-h-back-porch = <0x20>; | |
| qcom,mdss-dsi-v-back-porch = <0x07>; | |
| qcom,mdss-dsi-panel-width = <0x2d0>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-h-front-porch = <0x64>; | |
| qcom,mdss-dsi-v-front-porch = <0x08>; | |
| qcom,mdss-dsi-panel-height = <0xa00>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,display-topology = <0x02 0x00 0x02 0x01 0x00 0x02>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,config-select = <0x4df>; | |
| qcom,mdss-dsi-h-pulse-width = <0x10>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-panel-timings = <0x1c0807 0x23220707 0x5030400>; | |
| config1 { | |
| qcom,split-mode = "pingpong-split"; | |
| phandle = <0x53c>; | |
| }; | |
| config0 { | |
| qcom,split-mode = "dualctl-split"; | |
| phandle = <0x4df>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_sharp_4k_dsc_video { | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-t-clk-pre = <0x27>; | |
| qcom,mdss-dsi-panel-name = "Sharp 4k video mode dsc dsi panel"; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0xc8 0x00 0xc8 0x01 0xc8>; | |
| qcom,mdss-dsi-tx-eot-append; | |
| qcom,mdss-dsi-panel-hdr-enabled; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-panel-peak-brightness = <0x401640>; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-pan-physical-width-dimension = <0x47>; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| phandle = <0x4e1>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
| qcom,mdss-pan-physical-height-dimension = <0x81>; | |
| qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; | |
| qcom,mdss-dsi-panel-blackness-level = <0xc9e>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-traffic-mode = "burst_mode"; | |
| qcom,adjust-timer-wakeup-ms = <0x01>; | |
| qcom,mdss-dsi-t-clk-post = <0x0c>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@0 { | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 11 91 09 20 00 20 02 00 03 1c 04 21 00 0f 03 19 01 97 39 01 00 00 00 00 03 92 10 f0 15 01 00 00 00 00 02 90 03 15 01 00 00 00 00 02 03 01 39 01 00 00 00 00 06 f0 55 aa 52 08 04 15 01 00 00 00 00 02 c0 03 39 01 00 00 00 00 06 f0 55 aa 52 08 07 15 01 00 00 00 00 02 ef 01 39 01 00 00 00 00 06 f0 55 aa 52 08 00 15 01 00 00 00 00 02 b4 10 15 01 00 00 00 00 02 35 00 39 01 00 00 00 00 06 f0 55 aa 52 08 01 39 01 00 00 00 00 05 ff aa 55 a5 80 15 01 00 00 00 00 02 6f 01 15 01 00 00 00 00 02 f3 10 39 01 00 00 00 00 05 ff aa 55 a5 00 05 01 00 00 78 00 01 11 05 01 00 00 78 00 01 29]; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-h-back-porch = <0x64>; | |
| qcom,mdss-dsi-v-back-porch = <0x07>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-h-front-porch = <0x1e>; | |
| qcom,mdss-dsi-v-front-porch = <0x08>; | |
| qcom,mdss-dsc-bit-per-component = <0x08>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x01>; | |
| qcom,mdss-dsi-panel-height = <0xf00>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| qcom,display-topology = <0x02 0x02 0x02>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = <0x180606 0x21200606 0x4030400>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x04>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,mdss-dsc-slice-width = <0x438>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsc-slice-height = <0x20>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,mdss-dsc-bit-per-pixel = <0x08>; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_r63417_truly_1080p_cmd { | |
| qcom,esd-check-enabled; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-t-clk-pre = <0x29>; | |
| qcom,mdss-dsi-bl-min-level = <0x01>; | |
| qcom,mdss-dsi-panel-name = "r63417 truly 1080p cmd mode dsi panel"; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-panel-status-check-mode = "reg_read"; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x0a 0x00 0x0a 0x01 0x0a>; | |
| qcom,mdss-dsi-te-check-enable; | |
| qcom,mdss-dsi-tx-eot-append; | |
| qcom,mdss-dsi-te-pin-select = <0x01>; | |
| qcom,mdss-dsi-te-using-te-pin; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; | |
| qcom,mdss-dsi-te-dcs-command = <0x01>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-panel-status-read-length = <0x01>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| phandle = <0x4f5>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
| qcom,mdss-dsi-panel-status-value = <0x1c>; | |
| qcom,mdss-dsi-bl-max-level = <0xfff>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-traffic-mode = "burst_mode"; | |
| qcom,mdss-dsi-panel-on-check-value = <0x1c>; | |
| qcom,mdss-dsi-t-clk-post = <0x0c>; | |
| qcom,mdss-dsi-post-init-delay = <0x01>; | |
| qcom,mdss-dsi-display-timings { | |
| timing@0 { | |
| qcom,mdss-dsi-on-command = [23 01 00 00 00 00 02 d6 01 15 01 00 00 00 00 02 35 00 15 01 00 00 00 00 02 51 ff 15 01 00 00 00 00 02 53 2c 15 01 00 00 00 00 02 55 00 05 01 00 00 78 00 02 11 00 23 01 00 00 00 00 02 b0 04 29 01 00 00 00 00 07 b3 04 00 00 00 00 00 29 01 00 00 00 00 03 b6 3a d3 29 01 00 00 00 00 03 c0 00 00 29 01 00 00 00 00 23 c1 84 60 10 eb ff 6f ce ff ff 17 02 58 73 ae b1 20 c6 ff ff 1f f3 ff 5f 10 10 10 10 00 02 01 22 22 00 01 29 01 00 00 00 00 08 c2 31 f7 80 06 08 00 00 29 01 00 00 00 00 17 c4 70 00 00 00 00 04 00 00 00 0c 06 00 00 00 00 00 04 00 00 00 0c 06 29 01 00 00 00 00 29 c6 78 69 00 69 00 69 00 00 00 00 00 69 00 69 00 69 10 19 07 00 78 00 69 00 69 00 69 00 00 00 00 00 69 00 69 00 69 10 19 07 29 01 00 00 00 00 0a cb 31 fc 3f 8c 00 00 00 00 c0 23 01 00 00 00 00 02 cc 0b 29 01 00 00 00 00 0b d0 11 81 bb 1e 1e 4c 19 19 0c 00 29 01 00 00 00 00 1a d3 1b 33 bb bb b3 33 33 33 00 01 00 a0 d8 a0 0d 4e 4e 33 3b 22 72 07 3d bf 33 29 01 00 00 00 00 08 d5 06 00 00 01 51 01 32 29 01 00 00 00 00 1f c7 01 0a 11 18 26 33 3e 50 38 42 52 60 67 6e 77 01 0a 11 18 26 33 3e 50 38 42 52 60 67 6e 77 29 01 00 00 14 00 14 c8 01 00 00 00 00 fc 00 00 00 00 00 fc 00 00 00 00 00 fc 00 05 01 00 00 14 00 02 29 00]; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-h-back-porch = <0x40>; | |
| qcom,mdss-dsi-v-back-porch = <0x10>; | |
| qcom,mdss-dsi-panel-clockrate = <0x35a4e900>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-h-front-porch = <0x60>; | |
| qcom,mdss-dsi-v-front-porch = <0x04>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsi-panel-height = <0x780>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,display-topology = <0x01 0x00 0x01>; | |
| qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = <0x1e0808 0x24220808 0x5030400>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x10>; | |
| qcom,mdss-dsi-v-pulse-width = <0x01>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| qcom,mdss-dsi-panel-timings = <0xe6382600 0x686e2a3c 0x44030400>; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_dual_sim_video { | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-t-clk-pre = <0x2d>; | |
| qcom,mdss-dsi-panel-name = "Sim dual video mode dsi panel"; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-reset-sequence = <0x01 0x14 0x00 0xc8 0x01 0x14>; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-virtual-channel-id = <0x00>; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-border-color = <0x00>; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| phandle = <0x4ec>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
| qcom,mdss-dsi-bl-max-level = <0xfff>; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,panel-supply-entries = <0x4de>; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; | |
| qcom,mdss-dsi-stream = <0x00>; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,platform-reset-gpio = <0x34 0x06 0x00>; | |
| qcom,mdss-dsi-t-clk-post = <0x0d>; | |
| qcom,panel-ack-disabled; | |
| qcom,mdss-dsi-panel-broadcast-mode; | |
| qcom,mdss-dsi-display-timings { | |
| timing@0 { | |
| qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-v-bottom-border = <0x00>; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-h-back-porch = <0x2c>; | |
| qcom,mdss-dsi-v-back-porch = <0x04>; | |
| qcom,mdss-dsi-panel-width = <0x500>; | |
| qcom,mdss-dsi-h-sync-skew = <0x00>; | |
| qcom,mdss-dsi-h-front-porch = <0x78>; | |
| qcom,mdss-dsi-v-front-porch = <0x08>; | |
| qcom,mdss-dsi-v-top-border = <0x00>; | |
| qcom,mdss-dsi-panel-height = <0x5a0>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x00>; | |
| qcom,mdss-dsi-h-left-border = <0x00>; | |
| qcom,display-topology = <0x02 0x00 0x02 0x01 0x00 0x02>; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-panel-phy-timings = <0x1c0707 0x23210707 0x5030400>; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x10>; | |
| qcom,mdss-dsi-v-pulse-width = <0x04>; | |
| qcom,default-topology-index = <0x00>; | |
| qcom,mdss-dsi-h-right-border = <0x00>; | |
| }; | |
| }; | |
| }; | |
| qcom,sde-dspp-blocks { | |
| qcom,sde-dspp-dither = <0x82c 0x10007>; | |
| qcom,sde-dspp-sixzone = <0x900 0x10007>; | |
| qcom,sde-dspp-hsic = <0x800 0x10007>; | |
| qcom,sde-dspp-gc = <0x17c0 0x10008>; | |
| qcom,sde-dspp-memcolor = <0x880 0x10007>; | |
| qcom,sde-dspp-pcc = <0x1700 0x40000>; | |
| qcom,sde-dspp-hist = <0x800 0x10007>; | |
| qcom,sde-dspp-vlut = <0xa00 0x10008>; | |
| qcom,sde-dspp-gamut = <0x1000 0x40000>; | |
| qcom,sde-dspp-igc = <0x00 0x30001>; | |
| }; | |
| qcom,sde-reg-bus { | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,msm-bus,num-cases = <0x04>; | |
| qcom,msm-bus,vectors-KBps = <0x01 0x24e 0x00 0x00 0x01 0x24e 0x00 0x12c00 0x01 0x24e 0x00 0x249f0 0x01 0x24e 0x00 0x493e0>; | |
| qcom,msm-bus,name = "mdss_reg"; | |
| qcom,msm-bus,active-only; | |
| }; | |
| }; | |
| qcom,smp2pgpio-ssr-smp2p-2-out { | |
| compatible = "qcom,smp2pgpio"; | |
| gpio-controller; | |
| #interrupt-cells = <0x02>; | |
| phandle = <0xb4>; | |
| qcom,entry-name = "master-kernel"; | |
| #gpio-cells = <0x02>; | |
| qcom,remote-pid = <0x02>; | |
| interrupt-controller; | |
| }; | |
| qcom,msm-compress-dsp { | |
| compatible = "qcom,msm-compress-dsp"; | |
| phandle = <0x277>; | |
| }; | |
| qcom,vfe-lite@acc4000 { | |
| clock-rates = <0x00 0x00 0x00 0x00 0x00 0x00 0x18148d00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x23c34600 0x00>; | |
| compatible = "qcom,vfe-lite170"; | |
| clocks = <0x22 0x0c 0x22 0x0d 0xa5 0x55 0xa5 0x09 0xa5 0x54 0xa5 0x2f 0xa5 0x30 0xa5 0x06>; | |
| reg-names = "ife-lite"; | |
| clock-control-debugfs = "true"; | |
| clock-names = "camera_ahb\0camera_axi\0soc_ahb_clk\0cpas_ahb_clk\0slow_ahb_clk_src\0ife_clk\0ife_clk_src\0camnoc_axi_clk"; | |
| regulator-names = "camss"; | |
| status = "ok"; | |
| interrupts = <0x00 0x1d5 0x00>; | |
| phandle = <0x96>; | |
| reg = <0xacc4000 0x4000>; | |
| src-clock-name = "ife_clk_src"; | |
| interrupt-names = "ife-lite"; | |
| reg-cam-base = "\0\f@"; | |
| cell-index = <0x02>; | |
| camss-supply = <0x1bb>; | |
| clock-cntl-level = "svs\0svs_l1\0turbo"; | |
| }; | |
| rpmh-regulator-ldoa22 { | |
| qcom,supported-modes = <0x02 0x04>; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "ldoa22"; | |
| mboxes = <0x8a 0x00>; | |
| qcom,regulator-type = "pmic4-ldo"; | |
| qcom,mode-threshold-currents = <0x00 0x2710>; | |
| regulator-l22 { | |
| qcom,init-mode = <0x02>; | |
| phandle = <0x348>; | |
| qcom,init-voltage = <0x2bb380>; | |
| regulator-min-microvolt = <0x2bb380>; | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x328980>; | |
| regulator-name = "pm8998_l22"; | |
| }; | |
| }; | |
| spi@a8c000 { | |
| compatible = "qcom,spi-geni"; | |
| clocks = <0x22 0x62 0x22 0x6e 0x22 0x6f>; | |
| qcom,wrapper-core = <0x5b>; | |
| reg-names = "se_phys"; | |
| pinctrl-1 = <0x75>; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| status = "disabled"; | |
| #address-cells = <0x01>; | |
| interrupts = <0x00 0x164 0x00>; | |
| #size-cells = <0x00>; | |
| dma-names = "tx\0rx"; | |
| phandle = <0x2e9>; | |
| reg = <0xa8c000 0x4000>; | |
| pinctrl-0 = <0x74>; | |
| dmas = <0x5e 0x00 0x03 0x01 0x40 0x00 0x5e 0x01 0x03 0x01 0x40 0x00>; | |
| spi-max-frequency = <0x2faf080>; | |
| pinctrl-names = "default\0sleep"; | |
| }; | |
| qcom,rmnet-ipa { | |
| compatible = "qcom,rmnet-ipa3"; | |
| qcom,ipa-napi-enable; | |
| status = "disabled"; | |
| qcom,ipa-loaduC; | |
| qcom,ipa-advertise-sg-support; | |
| qcom,rmnet-ipa-ssr; | |
| }; | |
| qcom,msm-sec-auxpcm { | |
| qcom,msm-auxpcm-interface = "secondary"; | |
| compatible = "qcom,msm-auxpcm-dev"; | |
| qcom,msm-cpudai-auxpcm-sync = <0x01 0x01>; | |
| qcom,msm-cpudai-auxpcm-frame = <0x05 0x04>; | |
| qcom,msm-cpudai-auxpcm-quant = <0x02 0x02>; | |
| qcom,msm-cpudai-afe-clk-ver = <0x02>; | |
| qcom,msm-cpudai-auxpcm-slot-mapping = <0x01 0x01>; | |
| qcom,msm-cpudai-auxpcm-num-slots = <0x01 0x01>; | |
| qcom,msm-cpudai-auxpcm-data = <0x00 0x00>; | |
| qcom,msm-cpudai-auxpcm-pcm-clk-rate = <0x1f4000 0x1f4000>; | |
| phandle = <0x285>; | |
| qcom,msm-cpudai-auxpcm-mode = <0x00 0x00>; | |
| }; | |
| replicator@6046000 { | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "replicator-base"; | |
| coresight-name = "coresight-replicator"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x351>; | |
| arm,primecell-periphid = <0x3b909>; | |
| reg = <0x6046000 0x1000>; | |
| ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@1 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x124>; | |
| phandle = <0x136>; | |
| slave-mode; | |
| }; | |
| }; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x123>; | |
| phandle = <0x135>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,smp2pgpio_client_rdbg_5_out { | |
| gpios = <0x28 0x00 0x00>; | |
| compatible = "qcom,smp2pgpio_client_rdbg_5_out"; | |
| }; | |
| qcom,msm_gsi { | |
| compatible = "qcom,msm_gsi"; | |
| }; | |
| cti@6c0a000 { | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti-dlmm_cti1"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x384>; | |
| arm,primecell-periphid = <0x3b966>; | |
| reg = <0x6c0a000 0x1000>; | |
| }; | |
| qcom,cc-debug@100000 { | |
| compatible = "qcom,debugcc-sdm845"; | |
| clocks = <0x21 0x00>; | |
| qcom,videocc = <0xa4>; | |
| clock-names = "xo_clk_src"; | |
| qcom,dispcc = <0x20>; | |
| qcom,gcc = <0x22>; | |
| #clock-cells = <0x01>; | |
| phandle = <0x315>; | |
| qcom,cpucc = <0xa7>; | |
| qcom,camcc = <0xa5>; | |
| qcom,gpucc = <0xa6>; | |
| qcom,cc-count = <0x06>; | |
| }; | |
| apps-smmu@0x15000000 { | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| compatible = "qcom,qsmmu-v500"; | |
| qcom,msm-bus,vectors-KBps = <0x8b 0x273 0x00 0x00 0x8b 0x273 0x00 0x3e8>; | |
| #iommu-cells = <0x02>; | |
| reg-names = "base\0tcu-base"; | |
| qcom,actlr = <0x880 0x08 0x103 0x881 0x08 0x103 0xc80 0x08 0x103 0xc81 0x08 0x103 0x1090 0x00 0x103 0x1091 0x00 0x103 0x10a0 0x08 0x103 0x10b0 0x00 0x103 0x10a1 0x08 0x103 0x10a3 0x08 0x103 0x10a4 0x08 0x103 0x10b4 0x00 0x103 0x10a5 0x08 0x103>; | |
| qcom,skip-init; | |
| qcom,mmu500-errata-1 = <0x800 0x3ff 0xc00 0x3ff>; | |
| #global-interrupts = <0x01>; | |
| qcom,msm-bus,name = "apps_smmu"; | |
| ranges; | |
| #address-cells = <0x01>; | |
| interrupts = <0x00 0x41 0x04 0x00 0x60 0x04 0x00 0x61 0x04 0x00 0x62 0x04 0x00 0x63 0x04 0x00 0x64 0x04 0x00 0x65 0x04 0x00 0x66 0x04 0x00 0x67 0x04 0x00 0x68 0x04 0x00 0x69 0x04 0x00 0x6a 0x04 0x00 0x6b 0x04 0x00 0x6c 0x04 0x00 0x6d 0x04 0x00 0x6e 0x04 0x00 0x6f 0x04 0x00 0x70 0x04 0x00 0x71 0x04 0x00 0x72 0x04 0x00 0x73 0x04 0x00 0x74 0x04 0x00 0x75 0x04 0x00 0x76 0x04 0x00 0xb5 0x04 0x00 0xb6 0x04 0x00 0xb7 0x04 0x00 0xb8 0x04 0x00 0xb9 0x04 0x00 0xba 0x04 0x00 0xbb 0x04 0x00 0xbc 0x04 0x00 0xbd 0x04 0x00 0xbe 0x04 0x00 0xbf 0x04 0x00 0xc0 0x04 0x00 0x13b 0x04 0x00 0x13c 0x04 0x00 0x13d 0x04 0x00 0x13e 0x04 0x00 0x13f 0x04 0x00 0x140 0x04 0x00 0x141 0x04 0x00 0x142 0x04 0x00 0x143 0x04 0x00 0x144 0x04 0x00 0x145 0x04 0x00 0x146 0x04 0x00 0x147 0x04 0x00 0x148 0x04 0x00 0x149 0x04 0x00 0x14a 0x04 0x00 0x14b 0x04 0x00 0x14c 0x04 0x00 0x14d 0x04 0x00 0x14e 0x04 0x00 0x14f 0x04 0x00 0x150 0x04 0x00 0x151 0x04 0x00 0x152 0x04 0x00 0x153 0x04 0x00 0x154 0x04 0x00 0x155 0x04 0x00 0x156 0x04 0x00 0x157 0x04>; | |
| #size-cells = <0x01>; | |
| phandle = <0x29>; | |
| reg = <0x15000000 0x80000 0x150c2000 0x20>; | |
| qcom,use-3-lvl-tables; | |
| qcom,disable-atos; | |
| qcom,msm-bus,active-only; | |
| anoc_1_tbu@0x150c5000 { | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| compatible = "qcom,qsmmuv500-tbu"; | |
| qcom,msm-bus,vectors-KBps = <0x8b 0x273 0x00 0x00 0x8b 0x273 0x00 0x3e8>; | |
| reg-names = "base\0status-reg"; | |
| qcom,msm-bus,name = "apps_smmu"; | |
| phandle = <0x3ab>; | |
| qcom,regulator-names = "vdd"; | |
| vdd-supply = <0x1a4>; | |
| reg = <0x150c5000 0x1000 0x150c2200 0x08>; | |
| qcom,msm-bus,active-only; | |
| qcom,stream-id-range = <0x00 0x400>; | |
| }; | |
| anoc_2_tbu@0x150c9000 { | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| compatible = "qcom,qsmmuv500-tbu"; | |
| qcom,msm-bus,vectors-KBps = <0x8b 0x273 0x00 0x00 0x8b 0x273 0x00 0x3e8>; | |
| reg-names = "base\0status-reg"; | |
| qcom,msm-bus,name = "apps_smmu"; | |
| phandle = <0x3ac>; | |
| qcom,regulator-names = "vdd"; | |
| vdd-supply = <0x1a5>; | |
| reg = <0x150c9000 0x1000 0x150c2208 0x08>; | |
| qcom,msm-bus,active-only; | |
| qcom,stream-id-range = <0x400 0x400>; | |
| }; | |
| mnoc_sf_0_tbu@0x150d5000 { | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| compatible = "qcom,qsmmuv500-tbu"; | |
| qcom,msm-bus,vectors-KBps = <0x89 0x304 0x00 0x00 0x89 0x304 0x00 0x3e8>; | |
| reg-names = "base\0status-reg"; | |
| qcom,msm-bus,name = "mnoc_sf_0_tbu"; | |
| phandle = <0x3af>; | |
| qcom,regulator-names = "vdd"; | |
| vdd-supply = <0x1a8>; | |
| reg = <0x150d5000 0x1000 0x150c2220 0x08>; | |
| qcom,msm-bus,active-only; | |
| qcom,stream-id-range = <0x1000 0x400>; | |
| }; | |
| adsp_tbu@0x150dd000 { | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| compatible = "qcom,qsmmuv500-tbu"; | |
| qcom,msm-bus,vectors-KBps = <0x8b 0x273 0x00 0x00 0x8b 0x273 0x00 0x3e8>; | |
| reg-names = "base\0status-reg"; | |
| qcom,msm-bus,name = "apps_smmu"; | |
| phandle = <0x3b1>; | |
| qcom,regulator-names = "vdd"; | |
| vdd-supply = <0x1a9>; | |
| reg = <0x150dd000 0x1000 0x150c2230 0x08>; | |
| qcom,msm-bus,active-only; | |
| qcom,stream-id-range = <0x1800 0x400>; | |
| }; | |
| mnoc_hf_0_tbu@0x150cd000 { | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| compatible = "qcom,qsmmuv500-tbu"; | |
| qcom,msm-bus,vectors-KBps = <0x16 0x305 0x00 0x00 0x16 0x305 0x00 0x3e8>; | |
| reg-names = "base\0status-reg"; | |
| qcom,msm-bus,name = "mnoc_hf_0_tbu"; | |
| phandle = <0x3ad>; | |
| qcom,regulator-names = "vdd"; | |
| vdd-supply = <0x1a6>; | |
| reg = <0x150cd000 0x1000 0x150c2210 0x08>; | |
| qcom,msm-bus,active-only; | |
| qcom,stream-id-range = <0x800 0x400>; | |
| }; | |
| mnoc_hf_1_tbu@0x150d1000 { | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| compatible = "qcom,qsmmuv500-tbu"; | |
| qcom,msm-bus,vectors-KBps = <0x16 0x305 0x00 0x00 0x16 0x305 0x00 0x3e8>; | |
| reg-names = "base\0status-reg"; | |
| qcom,msm-bus,name = "mnoc_hf_1_tbu"; | |
| phandle = <0x3ae>; | |
| qcom,regulator-names = "vdd"; | |
| vdd-supply = <0x1a7>; | |
| reg = <0x150d1000 0x1000 0x150c2218 0x08>; | |
| qcom,msm-bus,active-only; | |
| qcom,stream-id-range = <0xc00 0x400>; | |
| }; | |
| anoc_1_pcie_tbu@0x150e1000 { | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| compatible = "qcom,qsmmuv500-tbu"; | |
| clocks = <0x22 0x06>; | |
| qcom,msm-bus,vectors-KBps = <0x8b 0x273 0x00 0x00 0x8b 0x273 0x00 0x3e8>; | |
| reg-names = "base\0status-reg"; | |
| clock-names = "gcc_aggre_noc_pcie_tbu_clk"; | |
| qcom,msm-bus,name = "apps_smmu"; | |
| phandle = <0x3b2>; | |
| qcom,regulator-names = "vdd"; | |
| vdd-supply = <0x1aa>; | |
| reg = <0x150e1000 0x1000 0x150c2238 0x08>; | |
| qcom,msm-bus,active-only; | |
| qcom,stream-id-range = <0x1c00 0x400>; | |
| }; | |
| compute_dsp_tbu@0x150d9000 { | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| compatible = "qcom,qsmmuv500-tbu"; | |
| qcom,msm-bus,vectors-KBps = <0x8b 0x273 0x00 0x00 0x8b 0x273 0x00 0x3e8>; | |
| reg-names = "base\0status-reg"; | |
| qcom,msm-bus,name = "apps_smmu"; | |
| phandle = <0x3b0>; | |
| reg = <0x150d9000 0x1000 0x150c2228 0x08>; | |
| qcom,msm-bus,active-only; | |
| qcom,stream-id-range = <0x1400 0x400>; | |
| }; | |
| }; | |
| qcom,gdsc@0x17d034 { | |
| compatible = "qcom,gdsc"; | |
| status = "ok"; | |
| phandle = <0x1a4>; | |
| reg = <0x17d034 0x04>; | |
| qcom,no-status-check-on-disable; | |
| qcom,gds-timeout = <0x1f4>; | |
| regulator-name = "hlos1_vote_aggre_noc_mmu_tbu1_gdsc"; | |
| }; | |
| ssphy@88eb000 { | |
| compatible = "qcom,usb-ssphy-qmp-v2"; | |
| clocks = <0x22 0xa5 0x22 0xa8 0x21 0x00 0x22 0xa4 0x22 0xa9>; | |
| resets = <0x22 0x14 0x22 0x15>; | |
| reg-names = "qmp_phy_base\0vls_clamp_reg"; | |
| clock-names = "aux_clk\0pipe_clk\0ref_clk_src\0ref_clk\0cfg_ahb_clk"; | |
| qcom,qmp-phy-reg-offset = <0x974 0x8d8 0x8dc 0x804 0x800 0x808>; | |
| status = "ok"; | |
| qcom,vbus-valid-override; | |
| qcom,vdd-voltage-level = <0x00 0xd6d80 0xd6d80>; | |
| phandle = <0x2b9>; | |
| core-supply = <0x2e>; | |
| vdd-supply = <0x2f>; | |
| reg = <0x88eb000 0x1000 0x1fcbff0 0x04>; | |
| reset-names = "phy_reset\0phy_phy_reset"; | |
| qcom,qmp-phy-init-seq = <0x48 0x07 0x00 0x80 0x14 0x00 0x34 0x04 0x00 0x138 0x30 0x00 0x3c 0x02 0x00 0x8c 0x08 0x00 0x15c 0x06 0x00 0x164 0x01 0x00 0x13c 0x80 0x00 0xb0 0x82 0x00 0xb8 0xab 0x00 0xbc 0xea 0x00 0xc0 0x02 0x00 0x60 0x06 0x00 0x68 0x16 0x00 0x70 0x36 0x00 0xdc 0x00 0x00 0xd8 0x3f 0x00 0xf8 0x01 0x00 0xf4 0xc9 0x00 0x148 0x0a 0x00 0xa0 0x00 0x00 0x9c 0x34 0x00 0x98 0x15 0x00 0x90 0x04 0x00 0x154 0x00 0x00 0x94 0x00 0x00 0xf0 0x00 0x00 0x40 0x0a 0x00 0xd0 0x80 0x00 0x10 0x01 0x00 0x1c 0x31 0x00 0x20 0x01 0x00 0x14 0x00 0x00 0x18 0x00 0x00 0x24 0x85 0x00 0x28 0x07 0x00 0x4c0 0x0c 0x00 0x564 0x50 0x00 0x430 0x0b 0x00 0x4d4 0x0e 0x00 0x4d8 0x4e 0x00 0x4dc 0x18 0x00 0x4f8 0x77 0x00 0x4fc 0x80 0x00 0x504 0x03 0x00 0x50c 0x1c 0x00 0x434 0x75 0x00 0x444 0x80 0x00 0x408 0x0a 0x00 0x40c 0x06 0x00 0x500 0x00 0x00 0x260 0x10 0x00 0x2a4 0x12 0x00 0x28c 0xc6 0x00 0x248 0x06 0x00 0x244 0x06 0x00 0x8c8 0x83 0x00 0x8cc 0x09 0x00 0x8d0 0xa2 0x00 0x8d4 0x40 0x00 0x8c4 0x02 0x00 0x864 0x1b 0x00 0x80c 0x9f 0x00 0x810 0x9f 0x00 0x814 0xb5 0x00 0x818 0x4c 0x00 0x81c 0x64 0x00 0x820 0x6a 0x00 0x824 0x15 0x00 0x828 0x0d 0x00 0x82c 0x15 0x00 0x830 0x0d 0x00 0x834 0x15 0x00 0x838 0x0d 0x00 0x83c 0x15 0x00 0x840 0x0d 0x00 0x844 0x15 0x00 0x848 0x0d 0x00 0x84c 0x15 0x00 0x850 0x0d 0x00 0x85c 0x02 0x00 0x8a0 0x04 0x00 0x88c 0x44 0x00 0x880 0xd1 0x00 0x884 0x1f 0x00 0x888 0x47 0x00 0x870 0xe7 0x00 0x874 0x03 0x00 0x878 0x40 0x00 0x87c 0x00 0x00 0x9d8 0xba 0x00 0x8b8 0x75 0x00 0x8b0 0x86 0x00 0x8bc 0x13 0x00 0xa0c 0x21 0x00 0xa10 0x60 0x00 0xffffffff 0xffffffff 0x00>; | |
| }; | |
| qcom,dsi-display@13 { | |
| compatible = "qcom,dsi-display"; | |
| clocks = <0x2bc 0x06 0x2bc 0x09>; | |
| pinctrl-1 = <0x41c 0x41e>; | |
| clock-names = "mux_byte_clk\0mux_pixel_clk"; | |
| qcom,dsi-panel = <0x4f0>; | |
| label = "dsi_dual_sim_dsc_375_cmd_display"; | |
| phandle = <0x54d>; | |
| qcom,dsi-ctrl = <0x2c3 0x2c4>; | |
| qcom,display-type = "primary"; | |
| pinctrl-0 = <0x41b 0x41d>; | |
| qcom,dsi-phy = <0x2c5 0x2c6>; | |
| pinctrl-names = "panel_active\0panel_suspend"; | |
| }; | |
| i2c@890000 { | |
| compatible = "qcom,i2c-geni"; | |
| clocks = <0x22 0x54 0x22 0x6c 0x22 0x6d>; | |
| qcom,wrapper-core = <0x35>; | |
| pinctrl-1 = <0x42>; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| status = "ok"; | |
| #address-cells = <0x01>; | |
| interrupts = <0x00 0x25d 0x00>; | |
| #size-cells = <0x00>; | |
| dma-names = "tx\0rx"; | |
| phandle = <0x2cf>; | |
| reg = <0x890000 0x4000>; | |
| pinctrl-0 = <0x41>; | |
| dmas = <0x38 0x00 0x04 0x03 0x40 0x00 0x38 0x01 0x04 0x03 0x40 0x00>; | |
| qcom,clk-freq-out = <0x186a0>; | |
| pinctrl-names = "default\0sleep"; | |
| lt8912@48 { | |
| compatible = "lontium,lt8912"; | |
| lt,enable-audio = <0x01>; | |
| pinctrl-1 = <0x430>; | |
| status = "okay"; | |
| lt,hdmien-gpio = <0x34 0x0d 0x00>; | |
| lt,pwren-gpio = <0x34 0x08 0x00>; | |
| reg = <0x48>; | |
| pinctrl-0 = <0x42f>; | |
| lt,hdmidet-gpio = <0x34 0x79 0x00>; | |
| pinctrl-names = "hdmidet_active\0hdmidet_suspend"; | |
| lt,reset-gpio = <0x34 0x0c 0x00>; | |
| }; | |
| }; | |
| qcom,dsi-display@4 { | |
| compatible = "qcom,dsi-display"; | |
| clocks = <0x2bc 0x06 0x2bc 0x09>; | |
| lab-supply = <0x4e2>; | |
| pinctrl-1 = <0x41c 0x41e>; | |
| clock-names = "mux_byte_clk\0mux_pixel_clk"; | |
| vddio-supply = <0x120>; | |
| qcom,dsi-panel = <0x4e7>; | |
| label = "dsi_dual_nt35597_truly_video_display"; | |
| ibb-supply = <0x4e3>; | |
| phandle = <0x544>; | |
| qcom,dsi-ctrl = <0x2c3 0x2c4>; | |
| qcom,display-type = "primary"; | |
| qcom,panel-mode-gpio = <0x34 0x34 0x00>; | |
| pinctrl-0 = <0x41b 0x41d>; | |
| qcom,dsi-phy = <0x2c5 0x2c6>; | |
| qcom,platform-reset-gpio = <0x34 0x06 0x00>; | |
| pinctrl-names = "panel_active\0panel_suspend"; | |
| }; | |
| rpmh-regulator-ldoa12 { | |
| qcom,supported-modes = <0x02 0x04>; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "ldoa12"; | |
| mboxes = <0x8a 0x00>; | |
| qcom,regulator-type = "pmic4-ldo"; | |
| qcom,mode-threshold-currents = <0x00 0x01>; | |
| regulator-l12 { | |
| qcom,init-mode = <0x02>; | |
| phandle = <0x121>; | |
| qcom,init-voltage = <0x1b7740>; | |
| regulator-min-microvolt = <0x1b7740>; | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x1b7740>; | |
| regulator-name = "pm8998_l12"; | |
| }; | |
| }; | |
| qcom,msm-dai-tdm-quin-tx { | |
| compatible = "qcom,msm-dai-tdm"; | |
| qcom,msm-cpudai-tdm-group-port-id = <0x9041>; | |
| qcom,msm-cpudai-tdm-clk-internal = <0x01>; | |
| qcom,msm-cpudai-tdm-sync-mode = <0x01>; | |
| qcom,msm-cpudai-tdm-clk-rate = <0x177000>; | |
| qcom,msm-cpudai-tdm-data-out = <0x00>; | |
| qcom,msm-cpudai-tdm-data-delay = <0x01>; | |
| qcom,msm-cpudai-tdm-group-id = <0x9141>; | |
| qcom,msm-cpudai-tdm-invert-sync = <0x01>; | |
| qcom,msm-cpudai-tdm-group-num-ports = <0x01>; | |
| qcom,msm-cpudai-tdm-sync-src = <0x01>; | |
| qcom,msm-dai-q6-tdm-quin-tx-0 { | |
| compatible = "qcom,msm-dai-q6-tdm"; | |
| qcom,msm-cpudai-tdm-dev-id = <0x9041>; | |
| phandle = <0x4c7>; | |
| qcom,msm-cpudai-tdm-data-align = <0x00>; | |
| }; | |
| }; | |
| cti@7320000 { | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti-cpu3"; | |
| clock-names = "apb_pclk"; | |
| cpu = <0x14>; | |
| phandle = <0x399>; | |
| arm,primecell-periphid = <0x3b966>; | |
| reg = <0x7320000 0x1000>; | |
| }; | |
| qcom,ipe1 { | |
| clock-rates = <0x00 0x00 0x00 0x00 0x18148d00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x20113a80 0x00 0x00 0x00 0x00 0x23c34600>; | |
| compatible = "qcom,cam-ipe"; | |
| clocks = <0xa5 0x39 0xa5 0x3a 0xa5 0x3b 0xa5 0x3c 0xa5 0x3d>; | |
| reg-names = "ipe1_top"; | |
| clock-control-debugfs = "true"; | |
| clock-names = "ipe_1_ahb_clk\0ipe_1_areg_clk\0ipe_1_axi_clk\0ipe_1_clk\0ipe_1_clk_src"; | |
| regulator-names = "ipe1-vdd"; | |
| status = "ok"; | |
| phandle = <0x99>; | |
| ipe1-vdd-supply = <0x1c4>; | |
| reg = <0xac91000 0x3000>; | |
| src-clock-name = "ipe_1_clk_src"; | |
| reg-cam-base = <0x91000>; | |
| cell-index = <0x01>; | |
| clock-cntl-level = "svs\0svs_l1\0nominal\0turbo"; | |
| }; | |
| spi@890000 { | |
| compatible = "qcom,spi-geni"; | |
| clocks = <0x22 0x54 0x22 0x6c 0x22 0x6d>; | |
| qcom,wrapper-core = <0x35>; | |
| reg-names = "se_phys"; | |
| pinctrl-1 = <0x52>; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| status = "disabled"; | |
| #address-cells = <0x01>; | |
| interrupts = <0x00 0x25d 0x00>; | |
| #size-cells = <0x00>; | |
| dma-names = "tx\0rx"; | |
| phandle = <0x2d7>; | |
| reg = <0x890000 0x4000>; | |
| pinctrl-0 = <0x51>; | |
| dmas = <0x38 0x00 0x04 0x01 0x40 0x00 0x38 0x01 0x04 0x01 0x40 0x00>; | |
| spi-max-frequency = <0x2faf080>; | |
| pinctrl-names = "default\0sleep"; | |
| }; | |
| cti@601e000 { | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti14"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x394>; | |
| arm,primecell-periphid = <0x3b966>; | |
| reg = <0x601e000 0x1000>; | |
| }; | |
| tpda@6831000 { | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "tpda-base"; | |
| coresight-name = "coresight-tpda-modem"; | |
| clock-names = "apb_pclk"; | |
| qcom,dsb-elem-size = <0x00 0x20>; | |
| phandle = <0x362>; | |
| arm,primecell-periphid = <0x3b969>; | |
| reg = <0x6831000 0x1000>; | |
| qcom,tpda-atid = <0x43>; | |
| qcom,cmb-elem-size = <0x00 0x40>; | |
| ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@1 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x157>; | |
| phandle = <0x158>; | |
| slave-mode; | |
| }; | |
| }; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x156>; | |
| phandle = <0x155>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| timer { | |
| compatible = "arm,armv8-timer"; | |
| interrupts = <0x01 0x01 0xf08 0x01 0x02 0xf08 0x01 0x03 0xf08 0x01 0x00 0xf08>; | |
| clock-frequency = <0x124f800>; | |
| }; | |
| qcom,rpmh-master-stats@b221200 { | |
| compatible = "qcom,rpmh-master-stats-v1"; | |
| qcom,use-alt-unit = <0x03>; | |
| reg = <0xb221200 0x60>; | |
| }; | |
| i2c@888000 { | |
| compatible = "qcom,i2c-geni"; | |
| clocks = <0x22 0x50 0x22 0x6c 0x22 0x6d>; | |
| qcom,wrapper-core = <0x35>; | |
| pinctrl-1 = <0x3e>; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| status = "disabled"; | |
| #address-cells = <0x01>; | |
| interrupts = <0x00 0x25b 0x00>; | |
| #size-cells = <0x00>; | |
| dma-names = "tx\0rx"; | |
| phandle = <0x2cd>; | |
| reg = <0x888000 0x4000>; | |
| pinctrl-0 = <0x3d>; | |
| dmas = <0x38 0x00 0x02 0x03 0x40 0x00 0x38 0x01 0x02 0x03 0x40 0x00>; | |
| pinctrl-names = "default\0sleep"; | |
| }; | |
| tpda@7832000 { | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "tpda-base"; | |
| coresight-name = "coresight-tpda-olc"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x37a>; | |
| arm,primecell-periphid = <0x3b969>; | |
| reg = <0x7832000 0x1000>; | |
| qcom,tpda-atid = <0x45>; | |
| qcom,cmb-elem-size = <0x00 0x40>; | |
| ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@1 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x179>; | |
| phandle = <0x17a>; | |
| slave-mode; | |
| }; | |
| }; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x178>; | |
| phandle = <0x18e>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| i2c@a94000 { | |
| compatible = "qcom,i2c-geni"; | |
| clocks = <0x22 0x66 0x22 0x6e 0x22 0x6f>; | |
| qcom,wrapper-core = <0x5b>; | |
| pinctrl-1 = <0x6a>; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| status = "disabled"; | |
| #address-cells = <0x01>; | |
| interrupts = <0x00 0x166 0x00>; | |
| #size-cells = <0x00>; | |
| dma-names = "tx\0rx"; | |
| phandle = <0x2e3>; | |
| reg = <0xa94000 0x4000>; | |
| pinctrl-0 = <0x69>; | |
| dmas = <0x5e 0x00 0x05 0x03 0x40 0x00 0x5e 0x01 0x05 0x03 0x40 0x00>; | |
| pinctrl-names = "default\0sleep"; | |
| }; | |
| qcom,gdsc@0x110004 { | |
| compatible = "qcom,gdsc"; | |
| status = "ok"; | |
| phandle = <0x2b7>; | |
| reg = <0x110004 0x04>; | |
| regulator-name = "usb30_sec_gdsc"; | |
| qcom,poll-cfg-gdscr; | |
| }; | |
| funnel@6883000 { | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "funnel-base"; | |
| coresight-name = "coresight-funnel-spss"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x37e>; | |
| arm,primecell-periphid = <0x3b908>; | |
| reg = <0x6883000 0x1000>; | |
| ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@1 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x17f>; | |
| phandle = <0x17b>; | |
| slave-mode; | |
| }; | |
| }; | |
| port@2 { | |
| reg = <0x01>; | |
| endpoint { | |
| remote-endpoint = <0x180>; | |
| phandle = <0x18b>; | |
| slave-mode; | |
| }; | |
| }; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x17e>; | |
| phandle = <0x13d>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| dsi_panel_pwr_supply { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| phandle = <0x4de>; | |
| qcom,panel-supply-entry@1 { | |
| qcom,supply-name = "lab"; | |
| qcom,supply-disable-load = <0x64>; | |
| qcom,supply-max-voltage = <0x5b8d80>; | |
| qcom,supply-enable-load = <0x186a0>; | |
| qcom,supply-min-voltage = <0x4630c0>; | |
| reg = <0x01>; | |
| }; | |
| qcom,panel-supply-entry@2 { | |
| qcom,supply-name = "ibb"; | |
| qcom,supply-disable-load = <0x64>; | |
| qcom,supply-post-on-sleep = <0x14>; | |
| qcom,supply-max-voltage = <0x5b8d80>; | |
| qcom,supply-enable-load = <0x186a0>; | |
| qcom,supply-min-voltage = <0x4630c0>; | |
| reg = <0x02>; | |
| }; | |
| qcom,panel-supply-entry@0 { | |
| qcom,supply-name = "vddio"; | |
| qcom,supply-disable-load = <0x50>; | |
| qcom,supply-post-on-sleep = <0x14>; | |
| qcom,supply-max-voltage = <0x1c3a90>; | |
| qcom,supply-enable-load = <0xf230>; | |
| qcom,supply-min-voltage = <0x1c3a90>; | |
| reg = <0x00>; | |
| }; | |
| }; | |
| spi@888000 { | |
| compatible = "qcom,spi-geni"; | |
| clocks = <0x22 0x50 0x22 0x6c 0x22 0x6d>; | |
| qcom,wrapper-core = <0x35>; | |
| reg-names = "se_phys"; | |
| pinctrl-1 = <0x4e>; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| status = "disabled"; | |
| #address-cells = <0x01>; | |
| interrupts = <0x00 0x25b 0x00>; | |
| #size-cells = <0x00>; | |
| dma-names = "tx\0rx"; | |
| phandle = <0x2d5>; | |
| reg = <0x888000 0x4000>; | |
| pinctrl-0 = <0x4d>; | |
| dmas = <0x38 0x00 0x02 0x01 0x40 0x00 0x38 0x01 0x02 0x01 0x40 0x00>; | |
| spi-max-frequency = <0x2faf080>; | |
| pinctrl-names = "default\0sleep"; | |
| }; | |
| cti@601b000 { | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti11"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x391>; | |
| arm,primecell-periphid = <0x3b966>; | |
| reg = <0x601b000 0x1000>; | |
| }; | |
| spi@a94000 { | |
| compatible = "qcom,spi-geni"; | |
| clocks = <0x22 0x66 0x22 0x6e 0x22 0x6f>; | |
| qcom,wrapper-core = <0x5b>; | |
| reg-names = "se_phys"; | |
| pinctrl-1 = <0x79>; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| status = "disabled"; | |
| #address-cells = <0x01>; | |
| interrupts = <0x00 0x166 0x00>; | |
| #size-cells = <0x00>; | |
| dma-names = "tx\0rx"; | |
| phandle = <0x2eb>; | |
| reg = <0xa94000 0x4000>; | |
| pinctrl-0 = <0x78>; | |
| dmas = <0x5e 0x00 0x05 0x01 0x40 0x00 0x5e 0x01 0x05 0x01 0x40 0x00>; | |
| spi-max-frequency = <0x2faf080>; | |
| pinctrl-names = "default\0sleep"; | |
| }; | |
| qcom,cam-cpas@ac40000 { | |
| vdd-corner-ahb-mapping = "suspend\0suspend\0minsvs\0lowsvs\0svs\0svs_l1\0nominal\0nominal\0nominal\0turbo\0turbo"; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| clock-rates = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x124f800 0x00 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x00>; | |
| qcom,msm-bus,num-cases = <0x07>; | |
| compatible = "qcom,cam-cpas"; | |
| clocks = <0x22 0x0c 0x22 0x0d 0xa5 0x55 0xa5 0x54 0xa5 0x09 0xa5 0x06>; | |
| qcom,msm-bus,vectors-KBps = <0x01 0x24d 0x00 0x00 0x01 0x24d 0x00 0x12ad4 0x01 0x24d 0x00 0x12ad4 0x01 0x24d 0x00 0x249f0 0x01 0x24d 0x00 0x249f0 0x01 0x24d 0x00 0x493e0 0x01 0x24d 0x00 0x493e0>; | |
| reg-names = "cam_cpas_top\0cam_camnoc"; | |
| client-names = "csiphy0\0csiphy1\0csiphy2\0csiphy3\0cci0\0csid0\0csid1\0csid2\0ife0\0ife1\0ife2\0ipe0\0ipe1\0cam-cdm-intf0\0cpas-cdm0\0bps0\0icp0\0jpeg-dma0\0jpeg-enc0\0fd0\0lrmecpas0"; | |
| clock-names = "gcc_ahb_clk\0gcc_axi_clk\0soc_ahb_clk\0slow_ahb_clk_src\0cpas_ahb_clk\0camnoc_axi_clk"; | |
| regulator-names = "camss-vdd"; | |
| qcom,cpas-hw-ver = <0x170110>; | |
| qcom,msm-bus,name = "cam_ahb"; | |
| client-id-based; | |
| status = "ok"; | |
| interrupts = <0x00 0x1cb 0x00>; | |
| label = "cpas"; | |
| camss-vdd-supply = <0x1bb>; | |
| client-bus-camnoc-based; | |
| arch-compat = "cpas_top"; | |
| reg = <0xac40000 0x1000 0xac42000 0x5000>; | |
| src-clock-name = "slow_ahb_clk_src"; | |
| camnoc-axi-min-ib-bw = <0xb2d05e00>; | |
| interrupt-names = "cpas_camnoc"; | |
| reg-cam-base = <0x40000 0x42000>; | |
| vdd-corners = <0x01 0x11 0x31 0x41 0x81 0xc1 0x101 0x141 0x151 0x181 0x1a1>; | |
| client-axi-port-names = "cam_hf_1\0cam_hf_2\0cam_hf_2\0cam_hf_2\0cam_sf_1\0cam_hf_1\0cam_hf_2\0cam_hf_2\0cam_hf_1\0cam_hf_2\0cam_hf_2\0cam_sf_1\0cam_sf_1\0cam_sf_1\0cam_sf_1\0cam_sf_1\0cam_sf_1\0cam_sf_1\0cam_sf_1\0cam_sf_1\0cam_sf_1"; | |
| cell-index = <0x00>; | |
| clock-cntl-level = "suspend\0minsvs\0lowsvs\0svs\0svs_l1\0nominal\0turbo"; | |
| qcom,axi-port-list { | |
| qcom,axi-port2 { | |
| qcom,axi-port-name = "cam_hf_2"; | |
| qcom,axi-port-camnoc { | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| qcom,msm-bus,vectors-KBps = <0x93 0x30a 0x00 0x00 0x93 0x30a 0x00 0x00>; | |
| qcom,msm-bus-vector-dyn-vote; | |
| qcom,msm-bus,name = "cam_hf_2_camnoc"; | |
| }; | |
| qcom,axi-port-mnoc { | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| qcom,msm-bus,vectors-KBps = <0x91 0x200 0x00 0x00 0x91 0x200 0x00 0x00>; | |
| qcom,msm-bus-vector-dyn-vote; | |
| qcom,msm-bus,name = "cam_hf_2_mnoc"; | |
| }; | |
| }; | |
| qcom,axi-port3 { | |
| qcom,axi-port-name = "cam_sf_1"; | |
| qcom,axi-port-camnoc { | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| qcom,msm-bus,vectors-KBps = <0x94 0x30a 0x00 0x00 0x94 0x30a 0x00 0x00>; | |
| qcom,msm-bus-vector-dyn-vote; | |
| qcom,msm-bus,name = "cam_sf_1_camnoc"; | |
| }; | |
| qcom,axi-port-mnoc { | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| qcom,msm-bus,vectors-KBps = <0x89 0x200 0x00 0x00 0x89 0x200 0x00 0x00>; | |
| qcom,msm-bus-vector-dyn-vote; | |
| qcom,msm-bus,name = "cam_sf_1_mnoc"; | |
| }; | |
| }; | |
| qcom,axi-port1 { | |
| qcom,axi-port-name = "cam_hf_1"; | |
| qcom,axi-port-camnoc { | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| qcom,msm-bus,vectors-KBps = <0x92 0x30a 0x00 0x00 0x92 0x30a 0x00 0x00>; | |
| qcom,msm-bus-vector-dyn-vote; | |
| qcom,msm-bus,name = "cam_hf_1_camnoc"; | |
| }; | |
| qcom,axi-port-mnoc { | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| qcom,msm-bus,vectors-KBps = <0x88 0x200 0x00 0x00 0x88 0x200 0x00 0x00>; | |
| qcom,msm-bus-vector-dyn-vote; | |
| qcom,msm-bus,name = "cam_hf_1_mnoc"; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,smp2pgpio-rdbg-1-in { | |
| compatible = "qcom,smp2pgpio"; | |
| gpio-controller; | |
| #interrupt-cells = <0x02>; | |
| phandle = <0x25>; | |
| qcom,entry-name = "rdbg"; | |
| #gpio-cells = <0x02>; | |
| qcom,is-inbound; | |
| qcom,remote-pid = <0x01>; | |
| interrupt-controller; | |
| }; | |
| qcedev@1de0000 { | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| compatible = "qcom,qcedev"; | |
| clocks = <0x22 0x11 0x22 0x11 0x22 0x0f 0x22 0x10>; | |
| qcom,ce-hw-instance = <0x00>; | |
| qcom,msm-bus,vectors-KBps = <0x7d 0x200 0x00 0x00 0x7d 0x200 0x60180 0x60180>; | |
| qcom,bam-ee = <0x00>; | |
| reg-names = "crypto-base\0crypto-bam-base"; | |
| qcom,bam-pipe-pair = <0x03>; | |
| qcom,request-bw-before-clk; | |
| clock-names = "core_clk_src\0core_clk\0iface_clk\0bus_clk"; | |
| qcom,msm-bus,name = "qcedev-noc"; | |
| qcom,ce-opp-freq = <0xa37d070>; | |
| qcom,ce-device = <0x00>; | |
| interrupts = <0x00 0x110 0x00>; | |
| phandle = <0x326>; | |
| reg = <0x1de0000 0x20000 0x1dc4000 0x24000>; | |
| iommus = <0x29 0x706 0x01 0x29 0x716 0x01>; | |
| qcom,ce-hw-shared; | |
| qcom,smmu-s1-enable; | |
| qcom_cedev_ns_cb { | |
| compatible = "qcom,qcedev,context-bank"; | |
| virtual-size = <0x40000000>; | |
| label = "ns_context"; | |
| iommus = <0x29 0x712 0x00 0x29 0x71f 0x00>; | |
| virtual-addr = <0x60000000>; | |
| }; | |
| qcom_cedev_s_cb { | |
| compatible = "qcom,qcedev,context-bank"; | |
| virtual-size = <0x40000000>; | |
| label = "secure_context"; | |
| iommus = <0x29 0x713 0x00 0x29 0x71c 0x00 0x29 0x71d 0x00 0x29 0x71e 0x00>; | |
| virtual-addr = "` \0"; | |
| qcom,secure-context-bank; | |
| }; | |
| }; | |
| tmc@6b09000 { | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "tmc-base"; | |
| coresight-name = "coresight-tmc-etf-swao"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x353>; | |
| arm,primecell-periphid = <0x3b961>; | |
| reg = <0x6b09000 0x1000>; | |
| coresight-csr = <0x128>; | |
| ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@1 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x12a>; | |
| phandle = <0x12b>; | |
| slave-mode; | |
| }; | |
| }; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x129>; | |
| phandle = <0x125>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| funnel@0x6b08000 { | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "funnel-base"; | |
| coresight-name = "coresight-funnel-swao"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x354>; | |
| arm,primecell-periphid = <0x3b908>; | |
| reg = <0x6b08000 0x1000>; | |
| ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@1 { | |
| reg = <0x06>; | |
| endpoint { | |
| remote-endpoint = <0x12c>; | |
| phandle = <0x188>; | |
| slave-mode; | |
| }; | |
| }; | |
| port@2 { | |
| reg = <0x07>; | |
| endpoint { | |
| remote-endpoint = <0x12d>; | |
| phandle = <0x12e>; | |
| slave-mode; | |
| }; | |
| }; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x12b>; | |
| phandle = <0x12a>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| etm@7640000 { | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| coresight-name = "coresight-etm6"; | |
| clock-names = "apb_pclk"; | |
| cpu = <0x17>; | |
| phandle = <0x3a8>; | |
| arm,primecell-periphid = <0xbb95d>; | |
| reg = <0x7640000 0x1000>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x198>; | |
| phandle = <0x1a1>; | |
| }; | |
| }; | |
| }; | |
| turing_etm0 { | |
| compatible = "qcom,coresight-remote-etm"; | |
| coresight-name = "coresight-turing-etm0"; | |
| qcom,inst-id = <0x0d>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x186>; | |
| phandle = <0x170>; | |
| }; | |
| }; | |
| }; | |
| qcom,smp2pgpio-smp2p-2-out { | |
| compatible = "qcom,smp2pgpio"; | |
| gpio-controller; | |
| #interrupt-cells = <0x02>; | |
| phandle = <0x1b5>; | |
| qcom,entry-name = "smp2p"; | |
| #gpio-cells = <0x02>; | |
| qcom,remote-pid = <0x02>; | |
| interrupt-controller; | |
| }; | |
| rpmh-regulator-msslvl { | |
| compatible = "qcom,rpmh-arc-regulator"; | |
| qcom,resource-name = "mss.lvl"; | |
| mboxes = <0x8a 0x00>; | |
| regulator-s2-level { | |
| phandle = <0xad>; | |
| regulator-min-microvolt = <0x01>; | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x10000>; | |
| regulator-name = "pm8005_s2_level"; | |
| }; | |
| }; | |
| qcom,ipa_fws { | |
| compatible = "qcom,pil-tz-generic"; | |
| qcom,pil-force-shutdown; | |
| qcom,firmware-name = "ipa_fws"; | |
| qcom,pas-id = <0x0f>; | |
| memory-region = <0xe9>; | |
| }; | |
| qcom,camera-flash@0 { | |
| compatible = "qcom,camera-flash"; | |
| flash-source = <0x50f 0x510>; | |
| status = "ok"; | |
| torch-source = <0x511 0x512>; | |
| phandle = <0x56d>; | |
| reg = <0x00 0x00>; | |
| switch-source = <0x513>; | |
| cell-index = <0x00>; | |
| }; | |
| qcom,csid1@acba000 { | |
| clock-rates = <0x00 0x00 0x00 0x00 0x00 0x00 0x16e36000 0x00 0x00 0x00 0x18148d00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x20113a80 0x00 0x00 0x00 0x23c34600 0x00 0x00>; | |
| compatible = "qcom,csid170"; | |
| clocks = <0x22 0x0c 0x22 0x0d 0xa5 0x55 0xa5 0x09 0xa5 0x54 0xa5 0x2c 0xa5 0x2d 0xa5 0x2b 0xa5 0x0a 0xa5 0x29 0xa5 0x2a 0xa5 0x06 0xa5 0x28>; | |
| reg-names = "csid"; | |
| clock-control-debugfs = "true"; | |
| clock-names = "camera_ahb\0camera_axi\0soc_ahb_clk\0cpas_ahb_clk\0slow_ahb_clk_src\0ife_csid_clk\0ife_csid_clk_src\0ife_cphy_rx_clk\0cphy_rx_clk_src\0ife_clk\0ife_clk_src\0camnoc_axi_clk\0ife_axi_clk"; | |
| regulator-names = "camss\0ife1"; | |
| status = "ok"; | |
| interrupts = <0x00 0x1d2 0x00>; | |
| ife1-supply = <0x1c2>; | |
| phandle = <0x93>; | |
| reg = <0xacba000 0x1000>; | |
| src-clock-name = "ife_csid_clk_src"; | |
| interrupt-names = "csid"; | |
| reg-cam-base = <0xba000>; | |
| cell-index = <0x01>; | |
| camss-supply = <0x1bb>; | |
| clock-cntl-level = "svs\0turbo"; | |
| }; | |
| jtagmm@7440000 { | |
| compatible = "qcom,jtagv8-mm"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "etm-base"; | |
| clock-names = "core_clk"; | |
| phandle = <0x2f2>; | |
| reg = <0x7440000 0x1000>; | |
| qcom,coresight-jtagmm-cpu = <0x15>; | |
| }; | |
| qcom,glink-ssr-spss { | |
| compatible = "qcom,glink_ssr"; | |
| qcom,xprt = "mailbox"; | |
| qcom,notify-edges = <0xe5>; | |
| label = "spss"; | |
| qcom,edge = "spss"; | |
| phandle = <0xe4>; | |
| }; | |
| qcom,msm-dai-tdm-quin-rx { | |
| compatible = "qcom,msm-dai-tdm"; | |
| qcom,msm-cpudai-tdm-group-port-id = <0x9040>; | |
| qcom,msm-cpudai-tdm-clk-internal = <0x01>; | |
| qcom,msm-cpudai-tdm-sync-mode = <0x01>; | |
| qcom,msm-cpudai-tdm-clk-rate = <0x177000>; | |
| qcom,msm-cpudai-tdm-data-out = <0x00>; | |
| qcom,msm-cpudai-tdm-data-delay = <0x01>; | |
| qcom,msm-cpudai-tdm-group-id = <0x9140>; | |
| qcom,msm-cpudai-tdm-invert-sync = <0x01>; | |
| qcom,msm-cpudai-tdm-group-num-ports = <0x01>; | |
| qcom,msm-cpudai-tdm-sync-src = <0x01>; | |
| qcom,msm-dai-q6-tdm-quin-rx-0 { | |
| compatible = "qcom,msm-dai-q6-tdm"; | |
| qcom,msm-cpudai-tdm-dev-id = <0x9040>; | |
| phandle = <0x4c6>; | |
| qcom,msm-cpudai-tdm-data-align = <0x00>; | |
| }; | |
| }; | |
| stm@6002000 { | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "stm-base\0stm-stimulus-base"; | |
| coresight-name = "coresight-stm"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x35b>; | |
| arm,primecell-periphid = <0x3b962>; | |
| reg = <0x6002000 0x1000 0x16280000 0x180000>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x13b>; | |
| phandle = <0x13f>; | |
| }; | |
| }; | |
| }; | |
| qcom,ipa@01e00000 { | |
| qcom,msm-bus,num-paths = <0x04>; | |
| qcom,msm-bus,num-cases = <0x05>; | |
| compatible = "qcom,ipa"; | |
| qcom,ipa-hw-mode = <0x00>; | |
| qcom,msm-bus,vectors-KBps = <0x5a 0x200 0x00 0x00 0x5a 0x249 0x00 0x00 0x01 0x2a4 0x00 0x00 0x8f 0x309 0x00 0x00 0x5a 0x200 0x13880 0x927c0 0x5a 0x249 0x13880 0x55730 0x01 0x2a4 0x9c40 0x9c40 0x8f 0x309 0x00 0x4b 0x5a 0x200 0x13880 0x9c400 0x5a 0x249 0x13880 0x9c400 0x01 0x2a4 0x13880 0x13880 0x8f 0x309 0x00 0x96 0x5a 0x200 0x324b0 0xea600 0x5a 0x249 0x324b0 0xea600 0x01 0x2a4 0x324b0 0x27100 0x8f 0x309 0x00 0x12c 0x5a 0x200 0x324b0 0x36ee80 0x5a 0x249 0x324b0 0x36ee80 0x01 0x2a4 0x324b0 0x493e0 0x8f 0x309 0x00 0x163>; | |
| qcom,use-64-bit-dma-mask; | |
| reg-names = "ipa-base\0gsi-base"; | |
| qcom,bandwidth-vote-for-ipa; | |
| qcom,ipa-ram-mmap = <0x280 0x00 0x00 0x288 0x78 0x4000 0x308 0x78 0x4000 0x388 0x78 0x4000 0x408 0x78 0x4000 0x0f 0x00 0x07 0x08 0x0e 0x488 0x78 0x4000 0x508 0x78 0x4000 0x0f 0x00 0x07 0x08 0x0e 0x588 0x78 0x4000 0x608 0x78 0x4000 0x688 0x140 0x7c8 0x00 0x800 0x7d0 0x200 0x9d0 0x200 0x00 0x00 0x00 0xbd8 0x1024 0x2000 0x00 0x2000 0x00 0x2000 0x00 0x2000 0x00 0x80 0x200 0x2000 0x2000 0x00 0x2000 0x00 0x2000 0x00 0x2000 0x00 0x1c00 0x400>; | |
| qcom,modem-cfg-emb-pipe-flt; | |
| qcom,ipa-wdi2; | |
| qcom,msm-bus,name = "ipa"; | |
| status = "disabled"; | |
| interrupts = <0x00 0x137 0x00 0x00 0x1b0 0x00>; | |
| phandle = <0x329>; | |
| qcom,use-ipa-tethering-bridge; | |
| qcom,bus-vector-names = "MIN\0SVS2\0SVS\0NOMINAL\0TURBO"; | |
| qcom,ee = <0x00>; | |
| reg = <0x1e00000 0x34000 0x1e04000 0x2c000>; | |
| qcom,ipa-hw-ver = <0x0d>; | |
| interrupt-names = "ipa-irq\0gsi-irq"; | |
| qcom,smmu-fast-map; | |
| qcom,arm-smmu; | |
| ipa_smmu_wlan { | |
| compatible = "qcom,ipa-smmu-wlan-cb"; | |
| phandle = <0x32b>; | |
| iommus = <0x29 0x721 0x00>; | |
| qcom,additional-mapping = <0x1e60000 0x1e60000 0x80000>; | |
| }; | |
| ipa_smmu_ap { | |
| compatible = "qcom,ipa-smmu-ap-cb"; | |
| phandle = <0x32a>; | |
| iommus = <0x29 0x720 0x00>; | |
| qcom,additional-mapping = <0x146bd000 0x146bd000 0x2000>; | |
| qcom,iova-mapping = <0x20000000 0x40000000>; | |
| }; | |
| qcom,smp2pgpio_map_ipa_1_in { | |
| gpios = <0xe8 0x00 0x00>; | |
| compatible = "qcom,smp2pgpio-map-ipa-1-in"; | |
| }; | |
| ipa_smmu_uc { | |
| compatible = "qcom,ipa-smmu-uc-cb"; | |
| phandle = <0x32c>; | |
| iommus = <0x29 0x722 0x00>; | |
| qcom,iova-mapping = <0x40000000 0x20000000>; | |
| }; | |
| qcom,smp2pgpio_map_ipa_1_out { | |
| gpios = <0xe7 0x00 0x00>; | |
| compatible = "qcom,smp2pgpio-map-ipa-1-out"; | |
| }; | |
| }; | |
| tpdm@684c000 { | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "tpdm-base"; | |
| coresight-name = "coresight-tpdm-prng"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x378>; | |
| arm,primecell-periphid = <0x3b968>; | |
| reg = <0x684c000 0x1000>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x176>; | |
| phandle = <0x150>; | |
| }; | |
| }; | |
| }; | |
| qcom,gdsc@0xad0b134 { | |
| compatible = "qcom,gdsc"; | |
| status = "ok"; | |
| phandle = <0x1bb>; | |
| reg = <0xad0b134 0x04>; | |
| regulator-name = "titan_top_gdsc"; | |
| qcom,poll-cfg-gdscr; | |
| }; | |
| tpdm@6c28000 { | |
| qcom,msr-fix-req; | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "tpdm-base"; | |
| coresight-name = "coresight-tpdm-center"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x367>; | |
| arm,primecell-periphid = <0x3b968>; | |
| reg = <0x6c28000 0x1000>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x15e>; | |
| phandle = <0x14a>; | |
| }; | |
| }; | |
| }; | |
| qcom,gdsc@0xab008b4 { | |
| compatible = "qcom,gdsc"; | |
| qcom,support-hw-trigger; | |
| status = "ok"; | |
| phandle = <0x261>; | |
| reg = <0xab008b4 0x04>; | |
| regulator-name = "vcodec1_gdsc"; | |
| qcom,poll-cfg-gdscr; | |
| }; | |
| qcom,msm-dai-mi2s { | |
| compatible = "qcom,msm-dai-mi2s"; | |
| phandle = <0x4b5>; | |
| qcom,msm-dai-q6-mi2s-prim { | |
| compatible = "qcom,msm-dai-q6-mi2s"; | |
| qcom,msm-mi2s-tx-lines = <0x00>; | |
| qcom,msm-dai-q6-mi2s-dev-id = <0x00>; | |
| qcom,msm-mi2s-rx-lines = <0x03>; | |
| phandle = <0x280>; | |
| }; | |
| qcom,msm-dai-q6-mi2s-quin { | |
| compatible = "qcom,msm-dai-q6-mi2s"; | |
| qcom,msm-mi2s-tx-lines = <0x02>; | |
| qcom,msm-dai-q6-mi2s-dev-id = <0x04>; | |
| qcom,msm-mi2s-rx-lines = <0x01>; | |
| phandle = <0x4b6>; | |
| }; | |
| qcom,msm-dai-q6-mi2s-senary { | |
| compatible = "qcom,msm-dai-q6-mi2s"; | |
| qcom,msm-mi2s-tx-lines = <0x03>; | |
| qcom,msm-dai-q6-mi2s-dev-id = <0x06>; | |
| qcom,msm-mi2s-rx-lines = <0x00>; | |
| phandle = <0x4b7>; | |
| }; | |
| qcom,msm-dai-q6-mi2s-sec { | |
| compatible = "qcom,msm-dai-q6-mi2s"; | |
| qcom,msm-mi2s-tx-lines = <0x02>; | |
| qcom,msm-dai-q6-mi2s-dev-id = <0x01>; | |
| pinctrl-1 = <0x26e 0x26f 0x270>; | |
| qcom,msm-mi2s-rx-lines = <0x01>; | |
| phandle = <0x281>; | |
| pinctrl-0 = <0x26b 0x26c 0x26d>; | |
| pinctrl-names = "default\0sleep"; | |
| }; | |
| qcom,msm-dai-q6-mi2s-quat { | |
| compatible = "qcom,msm-dai-q6-mi2s"; | |
| qcom,msm-mi2s-tx-lines = <0x02>; | |
| qcom,msm-dai-q6-mi2s-dev-id = <0x03>; | |
| qcom,msm-mi2s-rx-lines = <0x01>; | |
| phandle = <0x283>; | |
| }; | |
| qcom,msm-dai-q6-mi2s-tert { | |
| compatible = "qcom,msm-dai-q6-mi2s"; | |
| qcom,msm-mi2s-tx-lines = <0x03>; | |
| qcom,msm-dai-q6-mi2s-dev-id = <0x02>; | |
| qcom,msm-mi2s-rx-lines = <0x00>; | |
| phandle = <0x282>; | |
| }; | |
| }; | |
| qcom,qup_uart@0xa84000 { | |
| compatible = "qcom,msm-geni-console"; | |
| clocks = <0x22 0x5e 0x22 0x6e 0x22 0x6f>; | |
| qcom,wrapper-core = <0x5b>; | |
| reg-names = "se_phys"; | |
| pinctrl-1 = <0x5a>; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| status = "ok"; | |
| interrupts = <0x00 0x162 0x00>; | |
| phandle = <0x2dc>; | |
| reg = <0xa84000 0x4000>; | |
| pinctrl-0 = <0x59>; | |
| pinctrl-names = "default\0sleep"; | |
| }; | |
| qcom,dsi-display@21 { | |
| compatible = "qcom,dsi-display"; | |
| clocks = <0x2bc 0x06 0x2bc 0x09>; | |
| clock-names = "mux_byte_clk\0mux_pixel_clk"; | |
| label = "ext_dsi_bridge_display"; | |
| phandle = <0x555>; | |
| qcom,dsi-ctrl = <0x2c3>; | |
| qcom,display-type = "primary"; | |
| qcom,dsi-phy = <0x2c5>; | |
| ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| phandle = <0x556>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| funnel@6832000 { | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "funnel-base"; | |
| coresight-name = "coresight-funnel-modem"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x361>; | |
| arm,primecell-periphid = <0x3b908>; | |
| reg = <0x6832000 0x1000>; | |
| ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@1 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x155>; | |
| phandle = <0x156>; | |
| slave-mode; | |
| }; | |
| }; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x154>; | |
| phandle = <0x143>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| rpmh-regulator-ldoa20 { | |
| qcom,supported-modes = <0x02 0x04>; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "ldoa20"; | |
| mboxes = <0x8a 0x00>; | |
| qcom,regulator-type = "pmic4-ldo"; | |
| qcom,mode-threshold-currents = <0x00 0x2710>; | |
| regulator-l20 { | |
| qcom,init-mode = <0x04>; | |
| phandle = <0x346>; | |
| qcom,init-voltage = <0x294280>; | |
| regulator-min-microvolt = <0x294280>; | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x2d2a80>; | |
| regulator-name = "pm8998_l20"; | |
| }; | |
| }; | |
| qcom,msm-rtb { | |
| compatible = "qcom,msm-rtb"; | |
| qcom,rtb-size = <0x100000>; | |
| }; | |
| qcom,msm-eud@88e0000 { | |
| compatible = "qcom,msm-eud"; | |
| clocks = <0x22 0xa9>; | |
| reg-names = "eud_base"; | |
| clock-names = "cfg_ahb_clk"; | |
| status = "ok"; | |
| interrupts = <0x00 0x1ec 0x04>; | |
| phandle = <0x2b2>; | |
| reg = <0x88e0000 0x2000>; | |
| vdda33-supply = <0xba>; | |
| interrupt-names = "eud_irq"; | |
| }; | |
| dbm@a6f8000 { | |
| compatible = "qcom,usb-dbm-1p5"; | |
| phandle = <0x2b1>; | |
| reg = <0xa6f8000 0x400>; | |
| qcom,reset-ep-after-lpm-resume; | |
| }; | |
| qcom,camcc@ad00000 { | |
| qcom,cam_cc_csi2phytimer_clk_src-opp-handle = <0x8f>; | |
| compatible = "qcom,cam_cc-sdm845-v2\0syscon"; | |
| #reset-cells = <0x01>; | |
| qcom,cam_cc_ife_0_clk_src-opp-handle = <0x92>; | |
| reg-names = "cc_base"; | |
| qcom,cam_cc_icp_clk_src-opp-handle = <0x97>; | |
| qcom,cam_cc_cci_clk_src-opp-handle = <0x90>; | |
| vdd_cx-supply = <0x1b>; | |
| vdd_mx-supply = <0x8c>; | |
| qcom,cam_cc_csi1phytimer_clk_src-opp-handle = <0x8e>; | |
| qcom,cam_cc_ipe_1_clk_src-opp-handle = <0x99>; | |
| qcom,cam_cc_ife_0_csid_clk_src-opp-handle = <0x91>; | |
| qcom,cam_cc_csi3phytimer_clk_src-opp-handle = <0x9b>; | |
| #clock-cells = <0x01>; | |
| phandle = <0xa5>; | |
| qcom,cam_cc_ife_lite_clk_src-opp-handle = <0x96>; | |
| qcom,cam_cc_ife_1_clk_src-opp-handle = <0x94>; | |
| reg = <0xad00000 0x10000>; | |
| qcom,cam_cc_bps_clk_src-opp-handle = <0x9a>; | |
| qcom,cam_cc_ife_1_csid_clk_src-opp-handle = <0x93>; | |
| qcom,cam_cc_ife_lite_csid_clk_src-opp-handle = <0x95>; | |
| qcom,cam_cc_ipe_0_clk_src-opp-handle = <0x98>; | |
| qcom,cam_cc_csi0phytimer_clk_src-opp-handle = <0x8d>; | |
| }; | |
| apps_iommu_test_device { | |
| compatible = "iommu-debug-test"; | |
| iommus = <0x29 0x20 0x00>; | |
| }; | |
| tpdm@7860000 { | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "tpdm-base"; | |
| coresight-name = "coresight-tpdm-apss"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x36b>; | |
| arm,primecell-periphid = <0x3b968>; | |
| reg = <0x7860000 0x1000>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x163>; | |
| phandle = <0x162>; | |
| }; | |
| }; | |
| }; | |
| qcom,smp2pgpio_test_smp2p_2_out { | |
| gpios = <0x1b5 0x00 0x00>; | |
| compatible = "qcom,smp2pgpio_test_smp2p_2_out"; | |
| }; | |
| qcom,l3-cpu4 { | |
| compatible = "devfreq-simple-dev"; | |
| clocks = <0x86 0x04>; | |
| clock-names = "devfreq_clk"; | |
| governor = "performance"; | |
| phandle = <0x88>; | |
| }; | |
| qcom,msm-ext-disp { | |
| compatible = "qcom,msm-ext-disp"; | |
| phandle = <0x4f9>; | |
| qcom,msm-ext-disp-audio-codec-rx { | |
| compatible = "qcom,msm-ext-disp-audio-codec-rx"; | |
| phandle = <0x530>; | |
| }; | |
| }; | |
| kgsl_iommu_test_device { | |
| compatible = "iommu-debug-test"; | |
| status = "disabled"; | |
| iommus = <0x1ab 0x07>; | |
| }; | |
| qcom,dsi-display@11 { | |
| compatible = "qcom,dsi-display"; | |
| clocks = <0x2bc 0x06 0x2bc 0x09>; | |
| pinctrl-1 = <0x41c 0x41e>; | |
| clock-names = "mux_byte_clk\0mux_pixel_clk"; | |
| qcom,dsi-panel = <0x4ee>; | |
| label = "dsi_dual_sim_cmd_display"; | |
| phandle = <0x54b>; | |
| qcom,dsi-ctrl = <0x2c3 0x2c4>; | |
| qcom,display-type = "primary"; | |
| pinctrl-0 = <0x41b 0x41d>; | |
| qcom,dsi-phy = <0x2c5 0x2c6>; | |
| pinctrl-names = "panel_active\0panel_suspend"; | |
| }; | |
| ssphy@88e8000 { | |
| compatible = "qcom,usb-ssphy-qmp-dp-combo"; | |
| clocks = <0x22 0xa0 0x22 0xa3 0x21 0x00 0x22 0x9f 0x22 0xa2 0x22 0xa9>; | |
| resets = <0x22 0x13 0x22 0x11>; | |
| extcon = <0x4f8>; | |
| reg-names = "qmp_phy_base"; | |
| clock-names = "aux_clk\0pipe_clk\0ref_clk_src\0ref_clk\0com_aux_clk\0cfg_ahb_clk"; | |
| qcom,qmp-phy-reg-offset = <0x1d74 0x1cd8 0x1cdc 0x1c04 0x1c00 0x1c08 0x2a18 0x08 0x04 0x1c 0x00 0x10 0x0c 0x1a0c>; | |
| qcom,vbus-valid-override; | |
| qcom,vdd-voltage-level = <0x00 0xd6d80 0xd6d80>; | |
| phandle = <0x2b4>; | |
| core-supply = <0x2e>; | |
| vdd-supply = <0x2f>; | |
| reg = <0x88e8000 0x3000>; | |
| reset-names = "global_phy_reset\0phy_reset"; | |
| qcom,qmp-phy-init-seq = <0x1048 0x07 0x00 0x1080 0x14 0x00 0x1034 0x08 0x00 0x1138 0x30 0x00 0x103c 0x02 0x00 0x108c 0x08 0x00 0x115c 0x16 0x00 0x1164 0x01 0x00 0x113c 0x80 0x00 0x10b0 0x82 0x00 0x10b8 0xab 0x00 0x10bc 0xea 0x00 0x10c0 0x02 0x00 0x1060 0x06 0x00 0x1068 0x16 0x00 0x1070 0x36 0x00 0x10dc 0x00 0x00 0x10d8 0x3f 0x00 0x10f8 0x01 0x00 0x10f4 0xc9 0x00 0x1148 0x0a 0x00 0x10a0 0x00 0x00 0x109c 0x34 0x00 0x1098 0x15 0x00 0x1090 0x04 0x00 0x1154 0x00 0x00 0x1094 0x00 0x00 0x10f0 0x00 0x00 0x1040 0x0a 0x00 0x1010 0x01 0x00 0x101c 0x31 0x00 0x1020 0x01 0x00 0x1014 0x00 0x00 0x1018 0x00 0x00 0x1024 0x85 0x00 0x1028 0x07 0x00 0x1430 0x0b 0x00 0x14d4 0x0f 0x00 0x14d8 0x4e 0x00 0x14dc 0x18 0x00 0x14f8 0x77 0x00 0x14fc 0x80 0x00 0x1504 0x03 0x00 0x150c 0x16 0x00 0x1564 0x05 0x00 0x14c0 0x03 0x00 0x1830 0x0b 0x00 0x18d4 0x0f 0x00 0x18d8 0x4e 0x00 0x18dc 0x18 0x00 0x18f8 0x77 0x00 0x18fc 0x80 0x00 0x1904 0x03 0x00 0x190c 0x16 0x00 0x1964 0x05 0x00 0x18c0 0x03 0x00 0x1260 0x10 0x00 0x12a4 0x12 0x00 0x128c 0x16 0x00 0x1248 0x09 0x00 0x1244 0x06 0x00 0x1660 0x10 0x00 0x16a4 0x12 0x00 0x168c 0x16 0x00 0x1648 0x09 0x00 0x1644 0x06 0x00 0x1cc8 0x83 0x00 0x1ccc 0x09 0x00 0x1cd0 0xa2 0x00 0x1cd4 0x40 0x00 0x1cc4 0x02 0x00 0x1c80 0xd1 0x00 0x1c84 0x1f 0x00 0x1c88 0x47 0x00 0x1c64 0x1b 0x00 0x1434 0x75 0x00 0x1834 0x75 0x00 0x1dd8 0xba 0x00 0x1c0c 0x9f 0x00 0x1c10 0x9f 0x00 0x1c14 0xb7 0x00 0x1c18 0x4e 0x00 0x1c1c 0x65 0x00 0x1c20 0x6b 0x00 0x1c24 0x15 0x00 0x1c28 0x0d 0x00 0x1c2c 0x15 0x00 0x1c30 0x0d 0x00 0x1c34 0x15 0x00 0x1c38 0x0d 0x00 0x1c3c 0x15 0x00 0x1c40 0x1d 0x00 0x1c44 0x15 0x00 0x1c48 0x0d 0x00 0x1c4c 0x15 0x00 0x1c50 0x0d 0x00 0x1e0c 0x21 0x00 0x1e10 0x60 0x00 0x1c5c 0x02 0x00 0x1ca0 0x04 0x00 0x1c8c 0x44 0x00 0x1c70 0xe7 0x00 0x1c74 0x03 0x00 0x1c78 0x40 0x00 0x1c7c 0x00 0x00 0x1cb8 0x75 0x00 0x1cb0 0x86 0x00 0x1cbc 0x13 0x00 0x1cac 0x04 0x00 0xffffffff 0xffffffff 0x00>; | |
| }; | |
| qcom,dsi-display@2 { | |
| compatible = "qcom,dsi-display"; | |
| clocks = <0x2bc 0x06 0x2bc 0x09>; | |
| lab-supply = <0x4e2>; | |
| pinctrl-1 = <0x41c 0x41e>; | |
| clock-names = "mux_byte_clk\0mux_pixel_clk"; | |
| vddio-supply = <0x120>; | |
| qcom,dsi-panel = <0x4e5>; | |
| label = "dsi_sharp_1080_cmd_display"; | |
| ibb-supply = <0x4e3>; | |
| phandle = <0x542>; | |
| qcom,dsi-ctrl = <0x2c3>; | |
| qcom,display-type = "primary"; | |
| qcom,panel-mode-gpio = <0x34 0x34 0x00>; | |
| pinctrl-0 = <0x41b 0x41d>; | |
| qcom,platform-te-gpio = <0x34 0x0a 0x00>; | |
| qcom,dsi-phy = <0x2c5>; | |
| qcom,platform-reset-gpio = <0x34 0x06 0x00>; | |
| pinctrl-names = "panel_active\0panel_suspend"; | |
| }; | |
| rpmh-regulator-ldoa10 { | |
| qcom,supported-modes = <0x02 0x04>; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "ldoa10"; | |
| mboxes = <0x8a 0x00>; | |
| qcom,regulator-type = "pmic4-ldo"; | |
| qcom,mode-threshold-currents = <0x00 0x01>; | |
| regulator-l10 { | |
| qcom,init-mode = <0x02>; | |
| phandle = <0x33f>; | |
| qcom,init-voltage = <0x1a0040>; | |
| regulator-min-microvolt = <0x1a0040>; | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x2cad80>; | |
| regulator-name = "pm8998_l10"; | |
| }; | |
| }; | |
| qcom,msm-dai-tdm-sec-tx { | |
| compatible = "qcom,msm-dai-tdm"; | |
| qcom,msm-cpudai-tdm-group-port-id = <0x9011>; | |
| qcom,msm-cpudai-tdm-clk-internal = <0x01>; | |
| qcom,msm-cpudai-tdm-sync-mode = <0x01>; | |
| qcom,msm-cpudai-tdm-clk-rate = <0x177000>; | |
| qcom,msm-cpudai-tdm-data-out = <0x00>; | |
| qcom,msm-cpudai-tdm-data-delay = <0x01>; | |
| qcom,msm-cpudai-tdm-group-id = <0x9111>; | |
| qcom,msm-cpudai-tdm-invert-sync = <0x01>; | |
| qcom,msm-cpudai-tdm-group-num-ports = <0x01>; | |
| qcom,msm-cpudai-tdm-sync-src = <0x01>; | |
| qcom,msm-dai-q6-tdm-sec-tx-0 { | |
| compatible = "qcom,msm-dai-q6-tdm"; | |
| qcom,msm-cpudai-tdm-dev-id = <0x9011>; | |
| phandle = <0x2a5>; | |
| qcom,msm-cpudai-tdm-data-align = <0x00>; | |
| }; | |
| }; | |
| ufsice@1d90000 { | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| compatible = "qcom,ice"; | |
| clocks = <0x22 0x8a 0x22 0x88 0x22 0x89 0x22 0x8c>; | |
| vdd-hba-supply = <0xa8>; | |
| qcom,msm-bus,vectors-KBps = <0x01 0x28a 0x00 0x00 0x01 0x28a 0x3e8 0x00>; | |
| qcom,enable-ice-clk; | |
| clock-names = "ufs_core_clk\0bus_clk\0iface_clk\0ice_core_clk"; | |
| qcom,msm-bus,name = "ufs_ice_noc"; | |
| qcom,op-freq-hz = <0x00 0x00 0x00 0x11e1a300>; | |
| phandle = <0xaa>; | |
| qcom,bus-vector-names = "MIN\0MAX"; | |
| reg = <0x1d90000 0x8000>; | |
| qcom,instance-type = "ufs"; | |
| }; | |
| qcom,smp2p-cdsp@1799000c { | |
| compatible = "qcom,smp2p"; | |
| interrupts = <0x00 0x240 0x01>; | |
| reg = <0x1799000c 0x04>; | |
| qcom,remote-pid = <0x05>; | |
| qcom,irq-bitmask = <0x40>; | |
| }; | |
| qcom,gdsc@0xab00814 { | |
| compatible = "qcom,gdsc"; | |
| status = "ok"; | |
| phandle = <0xc0>; | |
| reg = <0xab00814 0x04>; | |
| regulator-name = "venus_gdsc"; | |
| qcom,poll-cfg-gdscr; | |
| }; | |
| qcom,cam_smmu { | |
| non-fatal-fault-disabled; | |
| compatible = "qcom,msm-cam-smmu"; | |
| status = "ok"; | |
| msm_cam_smmu_lrme { | |
| compatible = "qcom,msm-cam-smmu-cb"; | |
| label = "lrme"; | |
| iommus = <0x29 0x1038 0x00 0x29 0x1058 0x00>; | |
| iova-mem-map { | |
| phandle = <0x3bd>; | |
| iova-mem-region-shared { | |
| iova-region-name = "shared"; | |
| iova-region-id = <0x01>; | |
| status = "ok"; | |
| iova-region-len = <0x6400000>; | |
| iova-region-start = "\a@\0"; | |
| }; | |
| iova-mem-region-io { | |
| iova-region-name = "io"; | |
| iova-region-id = <0x03>; | |
| status = "ok"; | |
| iova-region-len = <0xd2800000>; | |
| iova-region-start = <0xd800000>; | |
| }; | |
| }; | |
| }; | |
| msm_cam_smmu_fd { | |
| compatible = "qcom,msm-cam-smmu-cb"; | |
| label = "fd"; | |
| iommus = <0x29 0x1070 0x00>; | |
| iova-mem-map { | |
| phandle = <0x3bc>; | |
| iova-mem-region-io { | |
| iova-region-name = "io"; | |
| iova-region-id = <0x03>; | |
| status = "ok"; | |
| iova-region-len = <0xd8c00000>; | |
| iova-region-start = "\a@\0"; | |
| }; | |
| }; | |
| }; | |
| msm_cam_smmu_icp { | |
| compatible = "qcom,msm-cam-smmu-cb"; | |
| label = "icp"; | |
| iommus = <0x29 0x107a 0x02 0x29 0x1020 0x08 0x29 0x1040 0x08 0x29 0x1030 0x00 0x29 0x1050 0x00>; | |
| iova-mem-map { | |
| phandle = <0x3ba>; | |
| iova-mem-region-firmware { | |
| iova-region-name = "firmware"; | |
| iova-region-id = <0x00>; | |
| status = "ok"; | |
| iova-region-len = <0x500000>; | |
| iova-region-start = <0x00>; | |
| }; | |
| iova-mem-region-secondary-heap { | |
| iova-region-name = "secheap"; | |
| iova-region-id = <0x04>; | |
| status = "ok"; | |
| iova-region-len = <0x100000>; | |
| iova-region-start = <0x10a00000>; | |
| }; | |
| iova-mem-qdss-region { | |
| iova-region-name = "qdss"; | |
| iova-region-id = <0x05>; | |
| status = "ok"; | |
| iova-region-len = <0x100000>; | |
| iova-region-start = <0x10b00000>; | |
| qdss-phy-addr = <0x16790000>; | |
| }; | |
| iova-mem-region-shared { | |
| iova-granularity = <0x15>; | |
| iova-region-name = "shared"; | |
| iova-region-id = <0x01>; | |
| status = "ok"; | |
| iova-region-len = "\t`\0"; | |
| iova-region-start = "\a@\0"; | |
| }; | |
| iova-mem-region-io { | |
| iova-region-name = "io"; | |
| iova-region-id = <0x03>; | |
| status = "ok"; | |
| iova-region-len = <0xcf300000>; | |
| iova-region-start = <0x10c00000>; | |
| }; | |
| }; | |
| }; | |
| msm_cam_smmu_cpas_cdm { | |
| compatible = "qcom,msm-cam-smmu-cb"; | |
| label = "cpas-cdm0"; | |
| iommus = <0x29 0x1000 0x00>; | |
| iova-mem-map { | |
| phandle = <0x3bb>; | |
| iova-mem-region-io { | |
| iova-region-name = "io"; | |
| iova-region-id = <0x03>; | |
| status = "ok"; | |
| iova-region-len = <0xd8c00000>; | |
| iova-region-start = "\a@\0"; | |
| }; | |
| }; | |
| }; | |
| msm_cam_smmu_jpeg { | |
| compatible = "qcom,msm-cam-smmu-cb"; | |
| label = "jpeg"; | |
| iommus = <0x29 0x1060 0x08 0x29 0x1068 0x08>; | |
| iova-mem-map { | |
| phandle = <0x3b9>; | |
| iova-mem-region-io { | |
| iova-region-name = "io"; | |
| iova-region-id = <0x03>; | |
| status = "ok"; | |
| iova-region-len = <0xd8c00000>; | |
| iova-region-start = "\a@\0"; | |
| }; | |
| }; | |
| }; | |
| msm_cam_smmu_secure { | |
| compatible = "qcom,msm-cam-smmu-cb"; | |
| label = "cam-secure"; | |
| qcom,secure-cb; | |
| }; | |
| msm_cam_icp_fw { | |
| compatible = "qcom,msm-cam-smmu-fw-dev"; | |
| label = "icp"; | |
| memory-region = <0x1c0>; | |
| }; | |
| msm_cam_smmu_ife { | |
| compatible = "qcom,msm-cam-smmu-cb"; | |
| label = "ife"; | |
| iommus = <0x29 0x808 0x00 0x29 0x810 0x08 0x29 0xc08 0x00 0x29 0xc10 0x08>; | |
| iova-mem-map { | |
| phandle = <0x3b8>; | |
| iova-mem-region-io { | |
| iova-region-name = "io"; | |
| iova-region-id = <0x03>; | |
| status = "ok"; | |
| iova-region-len = <0xd8c00000>; | |
| iova-region-start = "\a@\0"; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,glink-qos-config-adsp { | |
| compatible = "qcom,glink-qos-config"; | |
| qcom,tput-stats-cycle = <0x0a>; | |
| qcom,mtu-size = <0x800>; | |
| qcom,flow-info = <0x3c 0x00 0x3c 0x00 0x3c 0x00 0x3c 0x00>; | |
| phandle = <0xde>; | |
| }; | |
| qcom,ipc_router_q6_xprt { | |
| compatible = "qcom,ipc_router_glink_xprt"; | |
| qcom,ch-name = "IPCRTR"; | |
| qcom,glink-xprt = "smem"; | |
| qcom,xprt-remote = "lpass"; | |
| qcom,xprt-linkid = <0x01>; | |
| qcom,fragmented-data; | |
| qcom,xprt-version = <0x01>; | |
| }; | |
| dsi_panel_pwr_supply_vdd_no_labibb { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| phandle = <0x53f>; | |
| qcom,panel-supply-entry@1 { | |
| qcom,supply-name = "vdd"; | |
| qcom,supply-disable-load = <0x00>; | |
| qcom,supply-post-on-sleep = <0x00>; | |
| qcom,supply-max-voltage = <0x2dc6c0>; | |
| qcom,supply-enable-load = <0xd13a8>; | |
| qcom,supply-min-voltage = <0x2dc6c0>; | |
| reg = <0x01>; | |
| }; | |
| qcom,panel-supply-entry@0 { | |
| qcom,supply-name = "vddio"; | |
| qcom,supply-disable-load = <0x50>; | |
| qcom,supply-post-on-sleep = <0x14>; | |
| qcom,supply-max-voltage = <0x1c3a90>; | |
| qcom,supply-enable-load = <0xf230>; | |
| qcom,supply-min-voltage = <0x1c3a90>; | |
| reg = <0x00>; | |
| }; | |
| }; | |
| qcom,msm-pri-auxpcm { | |
| qcom,msm-auxpcm-interface = "primary"; | |
| compatible = "qcom,msm-auxpcm-dev"; | |
| qcom,msm-cpudai-auxpcm-sync = <0x01 0x01>; | |
| qcom,msm-cpudai-auxpcm-frame = <0x05 0x04>; | |
| qcom,msm-cpudai-auxpcm-quant = <0x02 0x02>; | |
| qcom,msm-cpudai-afe-clk-ver = <0x02>; | |
| qcom,msm-cpudai-auxpcm-slot-mapping = <0x01 0x01>; | |
| qcom,msm-cpudai-auxpcm-num-slots = <0x01 0x01>; | |
| qcom,msm-cpudai-auxpcm-data = <0x00 0x00>; | |
| qcom,msm-cpudai-auxpcm-pcm-clk-rate = <0x1f4000 0x1f4000>; | |
| phandle = <0x284>; | |
| qcom,msm-cpudai-auxpcm-mode = <0x00 0x00>; | |
| }; | |
| i2c@a80000 { | |
| compatible = "qcom,i2c-geni"; | |
| clocks = <0x22 0x5c 0x22 0x6e 0x22 0x6f>; | |
| qcom,wrapper-core = <0x5b>; | |
| pinctrl-1 = <0x60>; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| status = "disabled"; | |
| #address-cells = <0x01>; | |
| interrupts = <0x00 0x161 0x00>; | |
| #size-cells = <0x00>; | |
| dma-names = "tx\0rx"; | |
| phandle = <0x2de>; | |
| reg = <0xa80000 0x4000>; | |
| pinctrl-0 = <0x5f>; | |
| dmas = <0x5e 0x00 0x00 0x03 0x40 0x00 0x5e 0x01 0x00 0x03 0x40 0x00>; | |
| pinctrl-names = "default\0sleep"; | |
| }; | |
| qcom,csiphy@ac67000 { | |
| phandle = <0x8f>; | |
| }; | |
| cti@6018000 { | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti8"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x134>; | |
| arm,primecell-periphid = <0x3b966>; | |
| reg = <0x6018000 0x1000>; | |
| }; | |
| qcom,videocc@ab00000 { | |
| compatible = "qcom,video_cc-sdm845-v2\0syscon"; | |
| #reset-cells = <0x01>; | |
| reg-names = "cc_base"; | |
| vdd_cx-supply = <0x1b>; | |
| #clock-cells = <0x01>; | |
| phandle = <0xa4>; | |
| reg = <0xab00000 0x10000>; | |
| }; | |
| qcom,smp2pgpio-ssr-smp2p-5-in { | |
| compatible = "qcom,smp2pgpio"; | |
| gpio-controller; | |
| #interrupt-cells = <0x02>; | |
| phandle = <0xbd>; | |
| qcom,entry-name = "slave-kernel"; | |
| #gpio-cells = <0x02>; | |
| qcom,is-inbound; | |
| qcom,remote-pid = <0x05>; | |
| interrupt-controller; | |
| }; | |
| qcom,bps { | |
| clock-rates = <0x00 0x00 0x00 0x00 0x18148d00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x23c34600 0x00 0x00 0x00 0x00 0x23c34600>; | |
| compatible = "qcom,cam-bps"; | |
| clocks = <0xa5 0x00 0xa5 0x01 0xa5 0x02 0xa5 0x03 0xa5 0x04>; | |
| reg-names = "bps_top"; | |
| clock-control-debugfs = "true"; | |
| clock-names = "bps_ahb_clk\0bps_areg_clk\0bps_axi_clk\0bps_clk\0bps_clk_src"; | |
| regulator-names = "bps-vdd"; | |
| status = "ok"; | |
| phandle = <0x9a>; | |
| reg = <0xac6f000 0x3000>; | |
| src-clock-name = "bps_clk_src"; | |
| reg-cam-base = <0x6f000>; | |
| cell-index = <0x00>; | |
| bps-vdd-supply = <0x1c5>; | |
| clock-cntl-level = "svs\0svs_l1\0nominal\0turbo"; | |
| }; | |
| spi@a80000 { | |
| compatible = "qcom,spi-geni"; | |
| clocks = <0x22 0x5c 0x22 0x6e 0x22 0x6f>; | |
| qcom,wrapper-core = <0x5b>; | |
| reg-names = "se_phys"; | |
| pinctrl-1 = <0x6f>; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| status = "ok"; | |
| #address-cells = <0x01>; | |
| interrupts = <0x00 0x161 0x00>; | |
| #size-cells = <0x00>; | |
| dma-names = "tx\0rx"; | |
| phandle = <0x2e6>; | |
| reg = <0xa80000 0x4000>; | |
| pinctrl-0 = <0x6f>; | |
| dmas = <0x5e 0x00 0x00 0x01 0x40 0x00 0x5e 0x01 0x00 0x01 0x40 0x00>; | |
| spi-max-frequency = <0x2faf080>; | |
| pinctrl-names = "default\0sleep"; | |
| }; | |
| qcom,msm-voip-dsp { | |
| compatible = "qcom,msm-voip-dsp"; | |
| phandle = <0x274>; | |
| }; | |
| qcom,fd@ac5a000 { | |
| clock-rates = <0x00 0x00 0x00 0x00 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x20113a80 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x23c34600 0x00 0x00>; | |
| compatible = "qcom,fd41"; | |
| clocks = <0x22 0x0c 0x22 0x0d 0xa5 0x55 0xa5 0x09 0xa5 0x06 0xa5 0x19 0xa5 0x18 0xa5 0x1a>; | |
| reg-names = "fd_core\0fd_wrapper"; | |
| clock-control-debugfs = "true"; | |
| clock-names = "gcc_ahb_clk\0gcc_axi_clk\0soc_ahb_clk\0cpas_ahb_clk\0camnoc_axi_clk\0fd_core_clk_src\0fd_core_clk\0fd_core_uar_clk"; | |
| regulator-names = "camss-vdd"; | |
| status = "ok"; | |
| interrupts = <0x00 0x1ce 0x00>; | |
| camss-vdd-supply = <0x1bb>; | |
| phandle = <0x3c0>; | |
| reg = <0xac5a000 0x1000 0xac5b000 0x400>; | |
| src-clock-name = "fd_core_clk_src"; | |
| interrupt-names = "fd"; | |
| reg-cam-base = <0x5a000 0x5b000>; | |
| cell-index = <0x00>; | |
| clock-cntl-level = "svs\0svs_l1\0turbo"; | |
| }; | |
| qcom,smp2pgpio-smp2p-5-in { | |
| compatible = "qcom,smp2pgpio"; | |
| gpio-controller; | |
| #interrupt-cells = <0x02>; | |
| phandle = <0x1b8>; | |
| qcom,entry-name = "smp2p"; | |
| #gpio-cells = <0x02>; | |
| qcom,is-inbound; | |
| qcom,remote-pid = <0x05>; | |
| interrupt-controller; | |
| }; | |
| rpmh-regulator-ldoa2 { | |
| qcom,supported-modes = <0x02 0x04>; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "ldoa2"; | |
| mboxes = <0x8a 0x00>; | |
| qcom,regulator-type = "pmic4-ldo"; | |
| qcom,mode-threshold-currents = <0x00 0x7530>; | |
| regulator-l2 { | |
| qcom,init-mode = <0x02>; | |
| phandle = <0x33a>; | |
| qcom,init-voltage = <0x124f80>; | |
| regulator-min-microvolt = <0x124f80>; | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x124f80>; | |
| regulator-always-on; | |
| regulator-name = "pm8998_l2"; | |
| }; | |
| }; | |
| qcom,gdsc@0xaf03000 { | |
| compatible = "qcom,gdsc"; | |
| qcom,en-rest-wait-val = <0x05>; | |
| qcom,support-hw-trigger; | |
| proxy-supply = <0x19>; | |
| qcom,proxy-consumer-enable; | |
| status = "ok"; | |
| phandle = <0x19>; | |
| reg = <0xaf03000 0x04>; | |
| regulator-name = "mdss_core_gdsc"; | |
| qcom,en-few-wait-val = <0x06>; | |
| qcom,poll-cfg-gdscr; | |
| }; | |
| qcom,msm-hdmi-dba-codec-rx { | |
| compatible = "qcom,msm-hdmi-dba-codec-rx"; | |
| qcom,dba-bridge-chip = "adv7533"; | |
| phandle = <0x4c3>; | |
| }; | |
| qcom,msm-imem@146bf000 { | |
| compatible = "qcom,msm-imem"; | |
| ranges = <0x00 0x146bf000 0x1000>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| reg = <0x146bf000 0x1000>; | |
| kaslr_offset@6d0 { | |
| compatible = "qcom,msm-imem-kaslr_offset"; | |
| reg = <0x6d0 0x0c>; | |
| }; | |
| diag_dload@c8 { | |
| compatible = "qcom,msm-imem-diag-dload"; | |
| reg = <0xc8 0xc8>; | |
| }; | |
| mem_dump_table@10 { | |
| compatible = "qcom,msm-imem-mem_dump_table"; | |
| reg = <0x10 0x08>; | |
| }; | |
| restart_reason@65c { | |
| compatible = "qcom,msm-imem-restart_reason"; | |
| reg = <0x65c 0x04>; | |
| }; | |
| boot_stats@6b0 { | |
| compatible = "qcom,msm-imem-boot_stats"; | |
| reg = <0x6b0 0x20>; | |
| }; | |
| pil@94c { | |
| compatible = "qcom,msm-imem-pil"; | |
| reg = <0x94c 0xc8>; | |
| }; | |
| dload_type@1c { | |
| compatible = "qcom,msm-imem-dload-type"; | |
| reg = <0x1c 0x04>; | |
| }; | |
| }; | |
| qcom,qup_uart@0x89c000 { | |
| interrupts-extended = <0x01 0x00 0x260 0x00>; | |
| compatible = "qcom,msm-geni-serial-hs"; | |
| clocks = <0x22 0x5a 0x22 0x6c 0x22 0x6d>; | |
| qcom,wrapper-core = <0x35>; | |
| reg-names = "se_phys"; | |
| pinctrl-1 = <0x37>; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| qcom,wakeup-byte = <0xfd>; | |
| status = "disabled"; | |
| phandle = <0x2ca>; | |
| reg = <0x89c000 0x4000>; | |
| pinctrl-0 = <0x36>; | |
| pinctrl-names = "default\0sleep"; | |
| }; | |
| qcom,vfe0@acaf000 { | |
| clock-rates = <0x00 0x00 0x00 0x00 0x00 0x00 0x18148d00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x23c34600 0x00 0x00>; | |
| compatible = "qcom,vfe170"; | |
| clocks = <0x22 0x0c 0x22 0x0d 0xa5 0x55 0xa5 0x09 0xa5 0x54 0xa5 0x22 0xa5 0x23 0xa5 0x06 0xa5 0x21>; | |
| reg-names = "ife"; | |
| clocks-option = <0xa5 0x27>; | |
| clock-names-option = "ife_dsp_clk"; | |
| clock-control-debugfs = "true"; | |
| clock-rates-option = <0x23c34600>; | |
| clock-names = "camera_ahb\0camera_axi\0soc_ahb_clk\0cpas_ahb_clk\0slow_ahb_clk_src\0ife_clk\0ife_clk_src\0camnoc_axi_clk\0ife_axi_clk"; | |
| regulator-names = "camss\0ife0"; | |
| status = "ok"; | |
| interrupts = <0x00 0x1d1 0x00>; | |
| phandle = <0x92>; | |
| ife0-supply = <0x1c1>; | |
| reg = <0xacaf000 0x4000>; | |
| src-clock-name = "ife_clk_src"; | |
| interrupt-names = "ife"; | |
| reg-cam-base = <0xaf000>; | |
| cell-index = <0x00>; | |
| camss-supply = <0x1bb>; | |
| clock-cntl-level = "svs\0svs_l1\0turbo"; | |
| }; | |
| cti@6015000 { | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti5"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x38c>; | |
| arm,primecell-periphid = <0x3b966>; | |
| reg = <0x6015000 0x1000>; | |
| }; | |
| qusb@88e3000 { | |
| compatible = "qcom,qusb2phy-v2"; | |
| clocks = <0x21 0x00 0x22 0xa9>; | |
| resets = <0x22 0x09>; | |
| qcom,qusb-phy-init-seq = <0x23 0x210 0x03 0x04 0x7c 0x18c 0x80 0x2c 0x0a 0x184 0x19 0xb4 0x40 0x194 0x20 0x198 0x21 0x214 0x00 0x220 0x58 0x224 0x20 0x240 0x29 0x244 0xca 0x248 0x04 0x24c 0x03 0x250 0x00 0x23c 0x22 0x210>; | |
| reg-names = "qusb_phy_base\0refgen_north_bg_reg_addr"; | |
| clock-names = "ref_clk_src\0cfg_ahb_clk"; | |
| qcom,override-bias-ctrl2; | |
| status = "disabled"; | |
| qcom,qusb-phy-reg-offset = <0x240 0x1a0 0x210 0x230 0xa8 0x254 0x198 0x228 0x22c 0x27c 0x280 0x284 0x288 0x2a0>; | |
| qcom,vdd-voltage-level = <0x00 0xd6d80 0xd6d80>; | |
| phandle = <0x2b8>; | |
| reg = <0x88e3000 0x400 0x88e7014 0x04>; | |
| reset-names = "phy_reset"; | |
| phy_type = "utmi"; | |
| }; | |
| qcom,smp2pgpio-ssr-smp2p-2-in { | |
| compatible = "qcom,smp2pgpio"; | |
| gpio-controller; | |
| #interrupt-cells = <0x02>; | |
| phandle = <0xb3>; | |
| qcom,entry-name = "slave-kernel"; | |
| #gpio-cells = <0x02>; | |
| qcom,is-inbound; | |
| qcom,remote-pid = <0x02>; | |
| interrupt-controller; | |
| }; | |
| qcom,smp2pgpio_client_rdbg_5_in { | |
| gpios = <0x27 0x00 0x00>; | |
| compatible = "qcom,smp2pgpio_client_rdbg_5_in"; | |
| }; | |
| qcom,mdss_dp_pll@c011000 { | |
| compatible = "qcom,mdss_dp_pll_10nm"; | |
| clocks = <0x20 0x00 0x21 0x00 0x22 0x9f 0x22 0xa9 0x22 0xa3>; | |
| reg-names = "pll_base\0phy_base\0ln_tx0_base\0ln_tx1_base\0gdsc_base"; | |
| clock-names = "iface_clk\0ref_clk_src\0ref_clk\0cfg_ahb_clk\0pipe_clk"; | |
| gdsc-supply = <0x19>; | |
| label = "MDSS DP PLL"; | |
| clock-rate = <0x00>; | |
| #clock-cells = <0x01>; | |
| phandle = <0x30>; | |
| reg = <0x88ea000 0x200 0x88eaa00 0x200 0x88ea200 0x200 0x88ea600 0x200 0xaf03000 0x08>; | |
| cell-index = <0x00>; | |
| qcom,platform-supply-entries { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| qcom,platform-supply-entry@0 { | |
| qcom,supply-name = "gdsc"; | |
| qcom,supply-disable-load = <0x00>; | |
| qcom,supply-max-voltage = <0x00>; | |
| qcom,supply-enable-load = <0x00>; | |
| qcom,supply-min-voltage = <0x00>; | |
| reg = <0x00>; | |
| }; | |
| }; | |
| }; | |
| sdhci@8804000 { | |
| pinctrl-5 = <0x3f7 0x3fd 0x403>; | |
| qcom,msm-bus,num-paths = <0x02>; | |
| qcom,msm-bus,num-cases = <0x08>; | |
| vdd-io-supply = <0x341>; | |
| compatible = "qcom,sdhci-msm-v5"; | |
| clocks = <0x22 0x70 0x22 0x71>; | |
| pinctrl-3 = <0x3f5 0x3fb 0x401>; | |
| qcom,msm-bus,vectors-KBps = <0x51 0x200 0x00 0x00 0x01 0x260 0x00 0x00 0x51 0x200 0x416 0x640 0x01 0x260 0x640 0x640 0x51 0x200 0xcc3e 0x13880 0x01 0x260 0x13880 0x13880 0x51 0x200 0xff50 0x186a0 0x01 0x260 0x186a0 0x186a0 0x51 0x200 0x1fe9e 0x30d40 0x01 0x260 0x208c8 0x208c8 0x51 0x200 0x3fd3e 0x30d40 0x01 0x260 0x249f0 0x249f0 0x51 0x200 0x3fd3e 0x61a80 0x01 0x260 0x493e0 0x493e0 0x51 0x200 0x146cc2 0x3e8000 0x01 0x260 0x146cc2 0x3e8000>; | |
| reg-names = "hc_mem"; | |
| pinctrl-1 = <0x3f3 0x3f9 0x3ff 0x3f1>; | |
| qcom,vdd-io-voltage-level = <0x1b9680 0x2d2a80>; | |
| clock-names = "iface_clk\0core_clk"; | |
| qcom,bus-width = <0x04>; | |
| cd-gpios = <0x34 0x7e 0x01>; | |
| qcom,bus-speed-mode = "SDR12\0SDR25\0SDR50\0DDR50\0SDR104"; | |
| qcom,pm-qos-legacy-latency-us = <0x46 0x46 0x46 0x46>; | |
| qcom,clk-rates = <0x61a80 0x1312d00 0x17d7840 0x2faf080 0x5f5e100 0xc02a560>; | |
| qcom,msm-bus,name = "sdhc2"; | |
| qcom,vdd-io-current-level = <0xc8 0x55f0>; | |
| qcom,pm-qos-cpu-groups = <0x3f 0xc0>; | |
| status = "ok"; | |
| interrupts = <0x00 0xcc 0x00 0x00 0xde 0x00>; | |
| qcom,vdd-voltage-level = <0x2d0370 0x2d2a80>; | |
| qcom,pm-qos-irq-latency = <0x46 0x46>; | |
| pinctrl-4 = <0x3f6 0x3fc 0x402>; | |
| phandle = <0x318>; | |
| qcom,devfreq,freq-table = <0x2faf080 0xc02a560>; | |
| pinctrl-2 = <0x3f4 0x3fa 0x400>; | |
| qcom,restore-after-cx-collapse; | |
| vdd-supply = <0x347>; | |
| reg = <0x8804000 0x1000>; | |
| pinctrl-0 = <0x3f2 0x3f8 0x3fe 0x3f1>; | |
| qcom,vdd-current-level = <0xc8 0xc3500>; | |
| qcom,large-address-bus; | |
| qcom,bus-bw-vectors-bps = <0x00 0x61a80 0x1312d00 0x17d7840 0x2faf080 0x60152b0 0xbebc200 0xffffffff>; | |
| interrupt-names = "hc_irq\0pwr_irq"; | |
| pinctrl-names = "active\0sleep\0ds_400KHz\0ds_50MHz\0ds_100MHz\0ds_200MHz"; | |
| qcom,pm-qos-irq-type = "affine_irq"; | |
| }; | |
| qcom,smp2pgpio-smp2p-2-in { | |
| compatible = "qcom,smp2pgpio"; | |
| gpio-controller; | |
| #interrupt-cells = <0x02>; | |
| phandle = <0x1b4>; | |
| qcom,entry-name = "smp2p"; | |
| #gpio-cells = <0x02>; | |
| qcom,is-inbound; | |
| qcom,remote-pid = <0x02>; | |
| interrupt-controller; | |
| }; | |
| cti@7220000 { | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti-cpu2"; | |
| clock-names = "apb_pclk"; | |
| cpu = <0x13>; | |
| phandle = <0x398>; | |
| arm,primecell-periphid = <0x3b966>; | |
| reg = <0x7220000 0x1000>; | |
| }; | |
| qcom,msm-dai-tdm-sec-rx { | |
| compatible = "qcom,msm-dai-tdm"; | |
| qcom,msm-cpudai-tdm-group-port-id = <0x9010>; | |
| qcom,msm-cpudai-tdm-clk-internal = <0x01>; | |
| qcom,msm-cpudai-tdm-sync-mode = <0x01>; | |
| qcom,msm-cpudai-tdm-clk-rate = <0x177000>; | |
| qcom,msm-cpudai-tdm-data-out = <0x00>; | |
| qcom,msm-cpudai-tdm-data-delay = <0x01>; | |
| qcom,msm-cpudai-tdm-group-id = <0x9110>; | |
| qcom,msm-cpudai-tdm-invert-sync = <0x01>; | |
| qcom,msm-cpudai-tdm-group-num-ports = <0x01>; | |
| qcom,msm-cpudai-tdm-sync-src = <0x01>; | |
| qcom,msm-dai-q6-tdm-sec-rx-0 { | |
| compatible = "qcom,msm-dai-q6-tdm"; | |
| qcom,msm-cpudai-tdm-dev-id = <0x9010>; | |
| phandle = <0x2a4>; | |
| qcom,msm-cpudai-tdm-data-align = <0x00>; | |
| }; | |
| }; | |
| qcom,msm-ultra-low-latency { | |
| compatible = "qcom,msm-pcm-dsp"; | |
| qcom,latency-level = "ultra"; | |
| qcom,msm-pcm-low-latency; | |
| qcom,msm-pcm-dsp-id = <0x02>; | |
| phandle = <0x273>; | |
| }; | |
| qcom,gdsc@0x17d040 { | |
| compatible = "qcom,gdsc"; | |
| status = "ok"; | |
| phandle = <0x1a6>; | |
| reg = <0x17d040 0x04>; | |
| qcom,no-status-check-on-disable; | |
| qcom,gds-timeout = <0x1f4>; | |
| regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc"; | |
| }; | |
| qcom,kgsl-hyp { | |
| compatible = "qcom,pil-tz-generic"; | |
| qcom,firmware-name = "a630_zap"; | |
| qcom,pas-id = <0x0d>; | |
| memory-region = <0x2ab>; | |
| phandle = <0x4c8>; | |
| }; | |
| qcom,gmu { | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| compatible = "qcom,gpu-gmu"; | |
| clocks = <0xa6 0x04 0xa6 0x0a 0x22 0x1a 0x22 0x29>; | |
| qcom,msm-bus,vectors-KBps = <0x1a 0x2734 0x00 0x00 0x1a 0x2734 0x00 0x64>; | |
| reg-names = "kgsl_gmu_reg\0kgsl_gmu_pdc_reg"; | |
| clock-names = "gmu_clk\0cxo_clk\0axi_clk\0memnoc_clk"; | |
| regulator-names = "vddcx\0vdd"; | |
| qcom,msm-bus,name = "cnoc"; | |
| interrupts = <0x00 0x130 0x00 0x00 0x131 0x00>; | |
| label = "kgsl-gmu"; | |
| phandle = <0x9c>; | |
| vddcx-supply = <0x1a3>; | |
| vdd-supply = <0x2ad>; | |
| reg = <0x506a000 0x30000 0xb200000 0x300000>; | |
| interrupt-names = "kgsl_hfi_irq\0kgsl_gmu_irq"; | |
| gmu_kernel { | |
| compatible = "qcom,smmu-gmu-kernel-cb"; | |
| phandle = <0x4ce>; | |
| iommus = <0x1ab 0x05>; | |
| }; | |
| qcom,gmu-pwrlevels { | |
| compatible = "qcom,gmu-pwrlevels"; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| qcom,gmu-pwrlevel@1 { | |
| qcom,gmu-freq = <0xbebc200>; | |
| reg = <0x01>; | |
| }; | |
| qcom,gmu-pwrlevel@2 { | |
| qcom,gmu-freq = <0x1dcd6500>; | |
| reg = <0x02>; | |
| }; | |
| qcom,gmu-pwrlevel@0 { | |
| qcom,gmu-freq = <0x00>; | |
| reg = <0x00>; | |
| }; | |
| }; | |
| gmu_user { | |
| compatible = "qcom,smmu-gmu-user-cb"; | |
| phandle = <0x4cd>; | |
| iommus = <0x1ab 0x04>; | |
| }; | |
| }; | |
| qcom,cpu4-memlat-mon { | |
| compatible = "qcom,arm-memlat-mon"; | |
| qcom,cachemiss-ev = <0x2a>; | |
| phandle = <0x30e>; | |
| qcom,target-dev = <0x85>; | |
| qcom,core-dev-table = <0x493e0 0x2fa 0x79e00 0x6b8 0xc4e00 0x826 0xfd200 0xb71 0x122a00 0xf27 0x180600 0x134f 0x1a5e00 0x172b 0x1de200 0x1ae1>; | |
| qcom,cpulist = <0x15 0x16 0x17 0x18>; | |
| }; | |
| rpmh-regulator-ldoa19 { | |
| qcom,supported-modes = <0x02 0x04>; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "ldoa19"; | |
| mboxes = <0x8a 0x00>; | |
| qcom,regulator-type = "pmic4-ldo"; | |
| qcom,mode-threshold-currents = <0x00 0x01>; | |
| regulator-l19 { | |
| qcom,init-mode = <0x02>; | |
| phandle = <0x345>; | |
| qcom,init-voltage = <0x2b9440>; | |
| regulator-min-microvolt = <0x2b9440>; | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = "\0/]"; | |
| regulator-name = "pm8998_l19"; | |
| }; | |
| }; | |
| cti@6012000 { | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti2"; | |
| clock-names = "apb_pclk"; | |
| qcom,cti-gpio-trigout = <0x04>; | |
| phandle = <0x389>; | |
| arm,primecell-periphid = <0x3b966>; | |
| reg = <0x6012000 0x1000>; | |
| pinctrl-0 = <0x185>; | |
| pinctrl-names = "cti-trigout-pctrl"; | |
| }; | |
| qcom,smp2pgpio_client_rdbg_2_in { | |
| gpios = <0x23 0x00 0x00>; | |
| compatible = "qcom,smp2pgpio_client_rdbg_2_in"; | |
| }; | |
| qcom,lrme@ac6b000 { | |
| clock-rates = <0x00 0x00 0x00 0x00 0x00 0xbebc200 0xbebc200 0x00 0x00 0x00 0x00 0x00 0x10089d40 0x10089d40 0x00 0x00 0x00 0x00 0x00 0x1312d000 0x1312d000 0x00 0x00 0x00 0x00 0x00 0x17d78400 0x17d78400>; | |
| compatible = "qcom,lrme"; | |
| clocks = <0x22 0x0c 0x22 0x0d 0xa5 0x55 0xa5 0x09 0xa5 0x06 0xa5 0x41 0xa5 0x40>; | |
| reg-names = "lrme"; | |
| clock-names = "camera_ahb\0camera_axi\0soc_ahb_clk\0cpas_ahb_clk\0camnoc_axi_clk\0lrme_clk_src\0lrme_clk"; | |
| regulator-names = "camss"; | |
| status = "ok"; | |
| interrupts = <0x00 0x1dc 0x00>; | |
| phandle = <0x4d2>; | |
| reg = <0xac6b000 0xa00>; | |
| src-clock-name = "lrme_clk_src"; | |
| interrupt-names = "lrme"; | |
| reg-cam-base = <0x6b000>; | |
| cell-index = <0x00>; | |
| camss-supply = <0x1bb>; | |
| clock-cntl-level = "lowsvs\0svs\0svs_l1\0turbo"; | |
| }; | |
| qcom,glink-smem-native-xprt-modem@86000000 { | |
| compatible = "qcom,glink-smem-native-xprt"; | |
| reg-names = "smem\0irq-reg-base"; | |
| interrupts = <0x00 0x1c1 0x01>; | |
| label = "mpss"; | |
| qcom,irq-mask = <0x1000>; | |
| reg = <0x86000000 0x200000 0x1799000c 0x04>; | |
| }; | |
| qcom,msm-adsp-loader { | |
| compatible = "qcom,adsp-loader"; | |
| status = "ok"; | |
| qcom,adsp-state = <0x00>; | |
| }; | |
| funnel@6861000 { | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "funnel-base"; | |
| coresight-name = "coresight-funnel-turing"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x372>; | |
| arm,primecell-periphid = <0x3b908>; | |
| reg = <0x6861000 0x1000>; | |
| ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@1 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x16e>; | |
| phandle = <0x171>; | |
| slave-mode; | |
| }; | |
| }; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x16d>; | |
| phandle = <0x14e>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| tpda@78c0000 { | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "tpda-base"; | |
| coresight-name = "coresight-tpda-llm-silver"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x36c>; | |
| arm,primecell-periphid = <0x3b969>; | |
| reg = <0x78c0000 0x1000>; | |
| qcom,tpda-atid = <0x48>; | |
| qcom,cmb-elem-size = <0x00 0x20>; | |
| ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@1 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x165>; | |
| phandle = <0x166>; | |
| slave-mode; | |
| }; | |
| }; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x164>; | |
| phandle = <0x190>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,qbt1000 { | |
| compatible = "qcom,qbt1000"; | |
| qcom,finger-detect-gpio = <0xe6 0x05 0x00>; | |
| clock-names = "core\0iface"; | |
| clock-frequency = <0x17d7840>; | |
| }; | |
| qcom,gdsc@0x17d030 { | |
| compatible = "qcom,gdsc"; | |
| status = "ok"; | |
| phandle = <0x1a9>; | |
| reg = <0x17d030 0x04>; | |
| qcom,no-status-check-on-disable; | |
| qcom,gds-timeout = <0x1f4>; | |
| regulator-name = "hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc"; | |
| }; | |
| dsi_panel_pwr_supply_no_labibb { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| phandle = <0x53e>; | |
| qcom,panel-supply-entry@0 { | |
| qcom,supply-name = "vddio"; | |
| qcom,supply-disable-load = <0x50>; | |
| qcom,supply-post-on-sleep = <0x14>; | |
| qcom,supply-max-voltage = <0x1c3a90>; | |
| qcom,supply-enable-load = <0xf230>; | |
| qcom,supply-min-voltage = <0x1c3a90>; | |
| reg = <0x00>; | |
| }; | |
| }; | |
| qcom,dsi-display@0 { | |
| compatible = "qcom,dsi-display"; | |
| clocks = <0x2bc 0x06 0x2bc 0x09>; | |
| lab-supply = <0x4e2>; | |
| pinctrl-1 = <0x41c 0x41e>; | |
| clock-names = "mux_byte_clk\0mux_pixel_clk"; | |
| vddio-supply = <0x120>; | |
| qcom,dsi-panel = <0x4e1>; | |
| label = "dsi_sharp_4k_dsc_video_display"; | |
| ibb-supply = <0x4e3>; | |
| phandle = <0x540>; | |
| qcom,dsi-ctrl = <0x2c3 0x2c4>; | |
| qcom,display-type = "primary"; | |
| qcom,panel-mode-gpio = <0x34 0x34 0x00>; | |
| pinctrl-0 = <0x41b 0x41d>; | |
| qcom,platform-te-gpio = <0x34 0x0a 0x00>; | |
| qcom,dsi-phy = <0x2c5 0x2c6>; | |
| qcom,platform-reset-gpio = <0x34 0x06 0x00>; | |
| pinctrl-names = "panel_active\0panel_suspend"; | |
| }; | |
| etm@7540000 { | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| coresight-name = "coresight-etm5"; | |
| clock-names = "apb_pclk"; | |
| cpu = <0x16>; | |
| phandle = <0x3a7>; | |
| arm,primecell-periphid = <0xbb95d>; | |
| reg = <0x7540000 0x1000>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x197>; | |
| phandle = <0x1a0>; | |
| }; | |
| }; | |
| }; | |
| qcom,smp2pgpio-smp2p-15-out { | |
| compatible = "qcom,smp2pgpio"; | |
| gpio-controller; | |
| #interrupt-cells = <0x02>; | |
| phandle = <0x1b1>; | |
| qcom,entry-name = "smp2p"; | |
| #gpio-cells = <0x02>; | |
| qcom,remote-pid = <0x0f>; | |
| interrupt-controller; | |
| }; | |
| qcom,kgsl-3d0@5000000 { | |
| qcom,idle-timeout = <0x50>; | |
| qcom,initial-pwrlevel = <0x07>; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,msm-bus,num-cases = <0x0d>; | |
| tzone-names = "gpu0-usr\0gpu1-usr"; | |
| cache-slices = <0x2d 0x0c 0x2d 0x0b>; | |
| compatible = "qcom,kgsl-3d0\0qcom,kgsl-3d"; | |
| qcom,tsens-name = "tsens_tz_sensor12"; | |
| clocks = <0x1c 0x03 0xa6 0x0a 0x22 0x1a 0x22 0x29 0xa6 0x04 0x86 0x10>; | |
| qcom,msm-bus,vectors-KBps = <0x1a 0x200 0x00 0x00 0x1a 0x200 0x00 0x61a80 0x1a 0x200 0x00 0x927c0 0x1a 0x200 0x00 0xc3500 0x1a 0x200 0x00 0x124f80 0x1a 0x200 0x00 0x192580 0x1a 0x200 0x00 0x2162e0 0x1a 0x200 0x00 0x2990a0 0x1a 0x200 0x00 0x2ee000 0x1a 0x200 0x00 0x3e12a0 0x1a 0x200 0x00 0x4f1a00 0x1a 0x200 0x00 0x5ee8e0 0x1a 0x200 0x00 0x6e1b80>; | |
| qcom,id = <0x00>; | |
| qcom,ubwc-mode = <0x02>; | |
| reg-names = "kgsl_3d0_reg_memory\0kgsl_3d0_cx_dbgc_memory\0cx_misc"; | |
| qcom,chipid = <0x6030001>; | |
| qcom,gpubw-dev = <0x2ac>; | |
| clock-names = "core_clk\0rbbmtimer_clk\0mem_clk\0mem_iface_clk\0gmu_clk\0l3_vote"; | |
| qcom,bus-width = <0x20>; | |
| regulator-names = "vddcx\0vdd"; | |
| qcom,pm-qos-active-latency = <0x1cc>; | |
| qcom,gpu-quirk-hfi-use-reg; | |
| qcom,msm-bus,name = "grp3d"; | |
| status = "ok"; | |
| interrupts = <0x00 0x12c 0x00>; | |
| label = "kgsl-3d0"; | |
| phandle = <0x9d>; | |
| qcom,gpu-qdss-stm = <0x161c0000 0x40000>; | |
| qcom,min-access-length = <0x20>; | |
| qcom,isense-clk-on-level = <0x01>; | |
| vddcx-supply = <0x1a3>; | |
| cache-slice-names = "gpu\0gpuhtw"; | |
| qcom,bus-control; | |
| vdd-supply = <0x2ad>; | |
| reg = <0x5000000 0x40000 0x5061000 0x800 0x509e000 0x1000>; | |
| qcom,no-nap; | |
| qcom,snapshot-size = <0x100000>; | |
| #cooling-cells = <0x02>; | |
| interrupt-names = "kgsl_3d0_irq"; | |
| qcom,gpu-quirk-secvid-set-once; | |
| qcom,highest-bank-bit = <0x0f>; | |
| qcom,gpu-pwrlevels { | |
| compatible = "qcom,gpu-pwrlevels"; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| qcom,gpu-pwrlevel@8 { | |
| qcom,bus-min = <0x00>; | |
| qcom,bus-max = <0x00>; | |
| qcom,bus-freq = <0x00>; | |
| qcom,gpu-freq = <0x00>; | |
| reg = <0x08>; | |
| }; | |
| qcom,gpu-pwrlevel@6 { | |
| qcom,bus-min = <0x05>; | |
| qcom,bus-max = <0x07>; | |
| qcom,bus-freq = <0x06>; | |
| qcom,gpu-freq = <0x14628180>; | |
| reg = <0x06>; | |
| }; | |
| qcom,gpu-pwrlevel@4 { | |
| qcom,bus-min = <0x08>; | |
| qcom,bus-max = <0x0b>; | |
| qcom,bus-freq = <0x09>; | |
| qcom,gpu-freq = <0x1efe9200>; | |
| reg = <0x04>; | |
| }; | |
| qcom,gpu-pwrlevel@2 { | |
| qcom,bus-min = <0x0a>; | |
| qcom,bus-max = <0x0c>; | |
| qcom,bus-freq = <0x0c>; | |
| qcom,gpu-freq = <0x283baec0>; | |
| reg = <0x02>; | |
| }; | |
| qcom,gpu-pwrlevel@0 { | |
| qcom,bus-min = <0x0c>; | |
| qcom,bus-max = <0x0c>; | |
| qcom,bus-freq = <0x0c>; | |
| qcom,gpu-freq = <0x2ee8aac0>; | |
| reg = <0x00>; | |
| }; | |
| qcom,gpu-pwrlevel@7 { | |
| qcom,bus-min = <0x03>; | |
| qcom,bus-max = <0x05>; | |
| qcom,bus-freq = <0x04>; | |
| qcom,gpu-freq = <0xf518240>; | |
| reg = <0x07>; | |
| }; | |
| qcom,gpu-pwrlevel@5 { | |
| qcom,bus-min = <0x07>; | |
| qcom,bus-max = <0x09>; | |
| qcom,bus-freq = <0x08>; | |
| qcom,gpu-freq = <0x18ad2380>; | |
| reg = <0x05>; | |
| }; | |
| qcom,gpu-pwrlevel@3 { | |
| qcom,bus-min = <0x09>; | |
| qcom,bus-max = <0x0c>; | |
| qcom,bus-freq = <0x0a>; | |
| qcom,gpu-freq = <0x23863d00>; | |
| reg = <0x03>; | |
| }; | |
| qcom,gpu-pwrlevel@1 { | |
| qcom,bus-min = <0x0c>; | |
| qcom,bus-max = <0x0c>; | |
| qcom,bus-freq = <0x0c>; | |
| qcom,gpu-freq = <0x2a51bd80>; | |
| reg = <0x01>; | |
| }; | |
| }; | |
| qcom,l3-pwrlevels { | |
| compatible = "qcom,l3-pwrlevels"; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| qcom,l3-pwrlevel@0 { | |
| qcom,l3-freq = <0x00>; | |
| reg = <0x00>; | |
| }; | |
| qcom,l3-pwrlevel@1 { | |
| qcom,l3-freq = <0x3010b000>; | |
| reg = <0x01>; | |
| }; | |
| qcom,l3-pwrlevel@2 { | |
| qcom,l3-freq = <0x4dd1e000>; | |
| reg = <0x02>; | |
| }; | |
| }; | |
| qcom,gpu-coresights { | |
| compatible = "qcom,gpu-coresight"; | |
| status = "disabled"; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| qcom,gpu-coresight@0 { | |
| coresight-name = "coresight-gfx"; | |
| coresight-atid = <0x32>; | |
| reg = <0x00>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x2ae>; | |
| phandle = <0x147>; | |
| }; | |
| }; | |
| }; | |
| qcom,gpu-coresight@1 { | |
| coresight-name = "coresight-gfx-cx"; | |
| coresight-atid = <0x33>; | |
| reg = <0x01>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x2af>; | |
| phandle = <0x148>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,gpu-mempools { | |
| compatible = "qcom,gpu-mempools"; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| qcom,gpu-mempool@3 { | |
| qcom,mempool-reserved = <0x20>; | |
| qcom,mempool-page-size = <0x100000>; | |
| reg = <0x03>; | |
| }; | |
| qcom,gpu-mempool@1 { | |
| qcom,mempool-reserved = <0x400>; | |
| qcom,mempool-page-size = <0x2000>; | |
| qcom,mempool-allocate; | |
| reg = <0x01>; | |
| }; | |
| qcom,gpu-mempool@2 { | |
| qcom,mempool-reserved = <0x100>; | |
| qcom,mempool-page-size = <0x10000>; | |
| reg = <0x02>; | |
| }; | |
| qcom,gpu-mempool@0 { | |
| qcom,mempool-reserved = <0x800>; | |
| qcom,mempool-page-size = <0x1000>; | |
| qcom,mempool-allocate; | |
| reg = <0x00>; | |
| }; | |
| }; | |
| }; | |
| rpmh-regulator-vsa2 { | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "vsa2"; | |
| mboxes = <0x8a 0x00>; | |
| regulator-lvs2 { | |
| phandle = <0x34c>; | |
| regulator-min-microvolt = <0x1b7740>; | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x1b7740>; | |
| regulator-name = "pm8998_lvs2"; | |
| }; | |
| }; | |
| qcom,gdsc@0x177004 { | |
| compatible = "qcom,gdsc"; | |
| status = "ok"; | |
| phandle = <0xa8>; | |
| reg = <0x177004 0x04>; | |
| regulator-name = "ufs_phy_gdsc"; | |
| qcom,poll-cfg-gdscr; | |
| }; | |
| qcom,ipc_router_cdsp_xprt { | |
| compatible = "qcom,ipc_router_glink_xprt"; | |
| qcom,ch-name = "IPCRTR"; | |
| qcom,glink-xprt = "smem"; | |
| qcom,xprt-remote = "cdsp"; | |
| qcom,xprt-linkid = <0x01>; | |
| qcom,fragmented-data; | |
| qcom,xprt-version = <0x01>; | |
| }; | |
| qcom,gdsc@0xad09004 { | |
| compatible = "qcom,gdsc"; | |
| status = "ok"; | |
| phandle = <0x1c1>; | |
| reg = <0xad09004 0x04>; | |
| regulator-name = "ife_0_gdsc"; | |
| qcom,poll-cfg-gdscr; | |
| }; | |
| arm,smmu-kgsl@5040000 { | |
| compatible = "qcom,smmu-v2"; | |
| clocks = <0x22 0x29>; | |
| #iommu-cells = <0x01>; | |
| qcom,dynamic; | |
| attach-impl-defs = <0x6000 0x2378 0x6060 0x1055 0x678c 0x08 0x6794 0x28 0x6800 0x06 0x6900 0x3ff 0x6924 0x204 0x6928 0x11000 0x6930 0x800 0x6960 0xffffffff 0x6b64 0x1a5551 0x6b68 0x9a82a382>; | |
| clock-names = "gcc_gpu_memnoc_gfx_clk"; | |
| #global-interrupts = <0x02>; | |
| status = "ok"; | |
| interrupts = <0x00 0xe5 0x04 0x00 0xe7 0x04 0x00 0x16c 0x04 0x00 0x16d 0x04 0x00 0x16e 0x04 0x00 0x16f 0x04 0x00 0x170 0x04 0x00 0x171 0x04 0x00 0x172 0x04 0x00 0x173 0x04>; | |
| phandle = <0x1ab>; | |
| qcom,regulator-names = "vdd"; | |
| vdd-supply = <0x1a3>; | |
| reg = <0x5040000 0x10000>; | |
| qcom,use-3-lvl-tables; | |
| qcom,disable-atos; | |
| }; | |
| qseecom@86d00000 { | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,msm-bus,num-cases = <0x04>; | |
| qcom,no-clock-support; | |
| qcom,qsee-reentrancy-support = <0x02>; | |
| compatible = "qcom,qseecom"; | |
| clocks = <0x22 0x11 0x22 0x11 0x22 0x0f 0x22 0x10>; | |
| qcom,fde-key-size; | |
| qcom,msm-bus,vectors-KBps = <0x7d 0x200 0x00 0x00 0x7d 0x200 0x30d40 0x61a80 0x7d 0x200 0x493e0 0xc3500 0x7d 0x200 0x61a80 0xf4240>; | |
| reg-names = "secapp-region"; | |
| qcom,hlos-num-ce-hw-instances = <0x01>; | |
| clock-names = "core_clk_src\0core_clk\0iface_clk\0bus_clk"; | |
| qcom,qsee-ce-hw-instance = <0x00>; | |
| qcom,msm-bus,name = "qseecom-noc"; | |
| qcom,ce-opp-freq = <0xa37d070>; | |
| qcom,support-fde; | |
| phandle = <0x323>; | |
| qcom,commonlib64-loaded-by-uefi; | |
| qcom,disk-encrypt-pipe-pair = <0x02>; | |
| reg = <0x86d00000 0x2200000>; | |
| qcom,hlos-ce-hw-instance = <0x00>; | |
| }; | |
| jtagmm@7340000 { | |
| compatible = "qcom,jtagv8-mm"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "etm-base"; | |
| clock-names = "core_clk"; | |
| phandle = <0x2f1>; | |
| reg = <0x7340000 0x1000>; | |
| qcom,coresight-jtagmm-cpu = <0x14>; | |
| }; | |
| qcom,smp2pgpio_client_rdbg_2_out { | |
| gpios = <0x24 0x00 0x00>; | |
| compatible = "qcom,smp2pgpio_client_rdbg_2_out"; | |
| }; | |
| qcom,glink-smem-native-xprt-adsp@86000000 { | |
| compatible = "qcom,glink-smem-native-xprt"; | |
| qcom,ramp-time = <0xaf>; | |
| reg-names = "smem\0irq-reg-base"; | |
| interrupts = <0x00 0x9c 0x01>; | |
| label = "lpass"; | |
| cpu-affinity = <0x01 0x02>; | |
| qcom,qos-config = <0xde>; | |
| qcom,irq-mask = <0x100>; | |
| reg = <0x86000000 0x200000 0x1799000c 0x04>; | |
| }; | |
| qcom,csid0@acb3000 { | |
| clock-rates = <0x00 0x00 0x00 0x00 0x00 0x00 0x16e36000 0x00 0x00 0x00 0x18148d00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x20113a80 0x00 0x00 0x00 0x23c34600 0x00 0x00>; | |
| compatible = "qcom,csid170"; | |
| clocks = <0x22 0x0c 0x22 0x0d 0xa5 0x55 0xa5 0x09 0xa5 0x54 0xa5 0x25 0xa5 0x26 0xa5 0x24 0xa5 0x0a 0xa5 0x22 0xa5 0x23 0xa5 0x06 0xa5 0x21>; | |
| reg-names = "csid"; | |
| clock-control-debugfs = "true"; | |
| clock-names = "camera_ahb\0camera_axi\0soc_ahb_clk\0cpas_ahb_clk\0slow_ahb_clk_src\0ife_csid_clk\0ife_csid_clk_src\0ife_cphy_rx_clk\0cphy_rx_clk_src\0ife_clk\0ife_clk_src\0camnoc_axi_clk\0ife_axi_clk"; | |
| regulator-names = "camss\0ife0"; | |
| status = "ok"; | |
| interrupts = <0x00 0x1d0 0x00>; | |
| phandle = <0x91>; | |
| ife0-supply = <0x1c1>; | |
| reg = <0xacb3000 0x1000>; | |
| src-clock-name = "ife_csid_clk_src"; | |
| interrupt-names = "csid"; | |
| reg-cam-base = "\0\v0"; | |
| cell-index = <0x00>; | |
| camss-supply = <0x1bb>; | |
| clock-cntl-level = "svs\0turbo"; | |
| }; | |
| qcom,ghd { | |
| compatible = "qcom,gladiator-hang-detect-v2"; | |
| qcom,threshold-arr = <0x1799041c 0x17990420>; | |
| qcom,config-reg = <0x17990434>; | |
| }; | |
| qcom,msm-lsm-client { | |
| compatible = "qcom,msm-lsm-client"; | |
| phandle = <0x27a>; | |
| }; | |
| tpdm@6840000 { | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "tpdm-base"; | |
| coresight-name = "coresight-tpdm-vsense"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x379>; | |
| arm,primecell-periphid = <0x3b968>; | |
| reg = <0x6840000 0x1000>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x177>; | |
| phandle = <0x14f>; | |
| }; | |
| }; | |
| }; | |
| i2c@a9c000 { | |
| compatible = "qcom,i2c-geni"; | |
| clocks = <0x22 0x6a 0x22 0x6e 0x22 0x6f>; | |
| qcom,wrapper-core = <0x5b>; | |
| pinctrl-1 = <0x6e>; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| status = "disabled"; | |
| #address-cells = <0x01>; | |
| interrupts = <0x00 0x168 0x00>; | |
| #size-cells = <0x00>; | |
| dma-names = "tx\0rx"; | |
| phandle = <0x2e5>; | |
| reg = <0xa9c000 0x4000>; | |
| pinctrl-0 = <0x6d>; | |
| dmas = <0x5e 0x00 0x07 0x03 0x40 0x00 0x5e 0x01 0x07 0x03 0x40 0x00>; | |
| pinctrl-names = "default\0sleep"; | |
| }; | |
| qcom,gdsc@0xad06004 { | |
| compatible = "qcom,gdsc"; | |
| qcom,support-hw-trigger; | |
| status = "ok"; | |
| phandle = <0x1c5>; | |
| reg = <0xad06004 0x04>; | |
| regulator-name = "bps_gdsc"; | |
| qcom,poll-cfg-gdscr; | |
| }; | |
| qcom,msm-pcm-voice { | |
| compatible = "qcom,msm-pcm-voice"; | |
| qcom,destroy-cvd; | |
| phandle = <0x275>; | |
| }; | |
| qcom,smp2pgpio-ssr-smp2p-3-out { | |
| compatible = "qcom,smp2pgpio"; | |
| gpio-controller; | |
| #interrupt-cells = <0x02>; | |
| phandle = <0xb9>; | |
| qcom,entry-name = "master-kernel"; | |
| #gpio-cells = <0x02>; | |
| qcom,remote-pid = <0x03>; | |
| interrupt-controller; | |
| }; | |
| qcom,cpu4-l3lat-mon { | |
| compatible = "qcom,arm-memlat-mon"; | |
| qcom,cachemiss-ev = <0x17>; | |
| phandle = <0x310>; | |
| qcom,target-dev = <0x88>; | |
| qcom,core-dev-table = <0x493e0 0x11e1a300 0xc9900 0x22551000 0x114900 0x2ca1c800 0x14cd00 0x38137800 0x19c800 0x48190800 0x1e7800 0x4dd1e000 0x249f00 0x538ab800 0x29e500 0x5efc6800>; | |
| qcom,cpulist = <0x15 0x16 0x17 0x18>; | |
| }; | |
| cpuss_dump { | |
| compatible = "qcom,cpuss-dump"; | |
| qcom,l1_i_cache2 { | |
| qcom,dump-node = <0xc4>; | |
| qcom,dump-id = <0x62>; | |
| }; | |
| qcom,l1_tlb_dump400 { | |
| qcom,dump-node = <0xda>; | |
| qcom,dump-id = <0x124>; | |
| }; | |
| qcom,l1_i_cache0 { | |
| qcom,dump-node = <0xc2>; | |
| qcom,dump-id = <0x60>; | |
| }; | |
| qcom,l1_tlb_dump700 { | |
| qcom,dump-node = <0xdd>; | |
| qcom,dump-id = <0x127>; | |
| }; | |
| qcom,l1_tlb_dump0 { | |
| qcom,dump-node = <0xd6>; | |
| qcom,dump-id = <0x120>; | |
| }; | |
| qcom,llcc3_d_cache { | |
| qcom,dump-node = <0xd4>; | |
| qcom,dump-id = <0x142>; | |
| }; | |
| qcom,l1_d_cache3 { | |
| qcom,dump-node = <0xcd>; | |
| qcom,dump-id = <0x83>; | |
| }; | |
| qcom,l1_i_cache103 { | |
| qcom,dump-node = <0xc9>; | |
| qcom,dump-id = <0x67>; | |
| }; | |
| qcom,l1_d_cache102 { | |
| qcom,dump-node = <0xd0>; | |
| qcom,dump-id = <0x86>; | |
| }; | |
| qcom,l1_d_cache1 { | |
| qcom,dump-node = <0xcb>; | |
| qcom,dump-id = <0x81>; | |
| }; | |
| qcom,l1_tlb_dump300 { | |
| qcom,dump-node = <0xd9>; | |
| qcom,dump-id = <0x123>; | |
| }; | |
| qcom,l1_i_cache101 { | |
| qcom,dump-node = <0xc7>; | |
| qcom,dump-id = <0x65>; | |
| }; | |
| qcom,l1_d_cache100 { | |
| qcom,dump-node = <0xce>; | |
| qcom,dump-id = <0x84>; | |
| }; | |
| qcom,l1_tlb_dump600 { | |
| qcom,dump-node = <0xdc>; | |
| qcom,dump-id = <0x126>; | |
| }; | |
| qcom,l1_i_cache3 { | |
| qcom,dump-node = <0xc5>; | |
| qcom,dump-id = <0x63>; | |
| }; | |
| qcom,llcc4_d_cache { | |
| qcom,dump-node = <0xd5>; | |
| qcom,dump-id = <0x143>; | |
| }; | |
| qcom,l1_i_cache1 { | |
| qcom,dump-node = <0xc3>; | |
| qcom,dump-id = <0x61>; | |
| }; | |
| qcom,llcc1_d_cache { | |
| qcom,dump-node = <0xd2>; | |
| qcom,dump-id = <0x140>; | |
| }; | |
| qcom,l1_tlb_dump200 { | |
| qcom,dump-node = <0xd8>; | |
| qcom,dump-id = <0x122>; | |
| }; | |
| qcom,l1_tlb_dump500 { | |
| qcom,dump-node = <0xdb>; | |
| qcom,dump-id = <0x125>; | |
| }; | |
| qcom,l1_d_cache103 { | |
| qcom,dump-node = <0xd1>; | |
| qcom,dump-id = <0x87>; | |
| }; | |
| qcom,l1_d_cache2 { | |
| qcom,dump-node = <0xcc>; | |
| qcom,dump-id = <0x82>; | |
| }; | |
| qcom,l1_i_cache102 { | |
| qcom,dump-node = <0xc8>; | |
| qcom,dump-id = <0x66>; | |
| }; | |
| qcom,l1_d_cache101 { | |
| qcom,dump-node = <0xcf>; | |
| qcom,dump-id = <0x85>; | |
| }; | |
| qcom,l1_d_cache0 { | |
| qcom,dump-node = <0xca>; | |
| qcom,dump-id = <0x80>; | |
| }; | |
| qcom,llcc2_d_cache { | |
| qcom,dump-node = <0xd3>; | |
| qcom,dump-id = <0x141>; | |
| }; | |
| qcom,l1_tlb_dump100 { | |
| qcom,dump-node = <0xd7>; | |
| qcom,dump-id = <0x121>; | |
| }; | |
| qcom,l1_i_cache100 { | |
| qcom,dump-node = <0xc6>; | |
| qcom,dump-id = <0x64>; | |
| }; | |
| }; | |
| qcom,gpi-dma@0xa00000 { | |
| #dma-cells = <0x05>; | |
| compatible = "qcom,gpi-dma"; | |
| qcom,iova-range = <0x00 0x100000 0x00 0x100000>; | |
| reg-names = "gpi-top"; | |
| qcom,smmu-cfg = <0x01>; | |
| status = "ok"; | |
| interrupts = <0x00 0x117 0x00 0x00 0x118 0x00 0x00 0x119 0x00 0x00 0x11a 0x00 0x00 0x11b 0x00 0x00 0x11c 0x00 0x00 0x125 0x00 0x00 0x126 0x00 0x00 0x127 0x00 0x00 0x128 0x00 0x00 0x129 0x00 0x00 0x12a 0x00 0x00 0x12b 0x00>; | |
| qcom,gpii-mask = <0xfa>; | |
| phandle = <0x5e>; | |
| qcom,max-num-gpii = <0x0d>; | |
| reg = <0xa00000 0x60000>; | |
| iommus = <0x29 0x6d6 0x00>; | |
| qcom,ev-factor = <0x02>; | |
| }; | |
| spi@a9c000 { | |
| compatible = "qcom,spi-geni"; | |
| clocks = <0x22 0x6a 0x22 0x6e 0x22 0x6f>; | |
| qcom,wrapper-core = <0x5b>; | |
| reg-names = "se_phys"; | |
| pinctrl-1 = <0x7d>; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| status = "disabled"; | |
| #address-cells = <0x01>; | |
| interrupts = <0x00 0x168 0x00>; | |
| #size-cells = <0x00>; | |
| dma-names = "tx\0rx"; | |
| phandle = <0x2ed>; | |
| reg = <0xa9c000 0x4000>; | |
| pinctrl-0 = <0x7c>; | |
| dmas = <0x5e 0x00 0x07 0x01 0x40 0x00 0x5e 0x01 0x07 0x01 0x40 0x00>; | |
| spi-max-frequency = <0x2faf080>; | |
| pinctrl-names = "default\0sleep"; | |
| }; | |
| qcom,ipc_router_dsps_xprt { | |
| compatible = "qcom,ipc_router_glink_xprt"; | |
| qcom,dynamic-wakeup-source; | |
| qcom,ch-name = "IPCRTR"; | |
| qcom,glink-xprt = "smem"; | |
| qcom,xprt-remote = "dsps"; | |
| qcom,xprt-linkid = <0x01>; | |
| qcom,low-latency-xprt; | |
| qcom,fragmented-data; | |
| qcom,xprt-version = <0x01>; | |
| }; | |
| funnel@6c0b000 { | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "funnel-base"; | |
| coresight-name = "coresight-funnel-dl-mm"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x370>; | |
| arm,primecell-periphid = <0x3b908>; | |
| reg = <0x6c0b000 0x1000>; | |
| ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@1 { | |
| reg = <0x01>; | |
| endpoint { | |
| remote-endpoint = <0x16b>; | |
| phandle = <0x16c>; | |
| slave-mode; | |
| }; | |
| }; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x16a>; | |
| phandle = <0x14b>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,spcom { | |
| compatible = "qcom,spcom"; | |
| qcom,spcom-ch-names = "sp_kernel\0sp_ssr"; | |
| status = "ok"; | |
| }; | |
| qcom,rmtfs_sharedmem@0 { | |
| compatible = "qcom,sharedmem-uio"; | |
| reg-names = "rmtfs"; | |
| qcom,client-id = <0x01>; | |
| qcom,guard-memory; | |
| reg = <0x00 0x200000>; | |
| }; | |
| syscon@17970018 { | |
| compatible = "syscon"; | |
| phandle = <0xa7>; | |
| reg = <0x17970018 0x04>; | |
| }; | |
| mailbox@af20000 { | |
| compatible = "qcom,tcs-drv"; | |
| qcom,drv-id = <0x00>; | |
| #mbox-cells = <0x01>; | |
| interrupts = <0x00 0x81 0x00>; | |
| label = "display_rsc"; | |
| phandle = <0x2b>; | |
| reg = <0xaf20000 0x100 0xaf21c00 0x3000>; | |
| qcom,tcs-config = <0x00 0x01 0x01 0x01 0x02 0x00 0x03 0x01>; | |
| }; | |
| qcom,gfxcc@5090000 { | |
| compatible = "qcom,gfxcc-sdm845-v2"; | |
| #reset-cells = <0x01>; | |
| reg-names = "cc_base"; | |
| qcom,gpu_cc_gx_gfx3d_clk_src-opp-handle = <0x9d>; | |
| vdd_gfx-supply = <0x1d>; | |
| #clock-cells = <0x01>; | |
| phandle = <0x1c>; | |
| reg = <0x5090000 0x9000>; | |
| }; | |
| qcom,mdss_dsi_pll@ae94a00 { | |
| compatible = "qcom,mdss_dsi_pll_10nm"; | |
| clocks = <0x20 0x00>; | |
| reg-names = "pll_base\0phy_base\0gdsc_base"; | |
| qcom,dsi-pll-ssc-mode = "down-spread"; | |
| clock-names = "iface_clk"; | |
| gdsc-supply = <0x19>; | |
| label = "MDSS DSI 0 PLL"; | |
| clock-rate = <0x00>; | |
| #clock-cells = <0x01>; | |
| phandle = <0x2bc>; | |
| reg = <0xae94a00 0x1e0 0xae94400 0x800 0xaf03000 0x08>; | |
| qcom,dsi-pll-ssc-en; | |
| cell-index = <0x00>; | |
| qcom,platform-supply-entries { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| qcom,platform-supply-entry@0 { | |
| qcom,supply-name = "gdsc"; | |
| qcom,supply-disable-load = <0x00>; | |
| qcom,supply-max-voltage = <0x00>; | |
| qcom,supply-enable-load = <0x00>; | |
| qcom,supply-min-voltage = <0x00>; | |
| reg = <0x00>; | |
| }; | |
| }; | |
| }; | |
| tpdm@6880000 { | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "tpdm-base"; | |
| coresight-name = "coresight-tpdm-spss"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x37d>; | |
| arm,primecell-periphid = <0x3b968>; | |
| reg = <0x6880000 0x1000>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x17d>; | |
| phandle = <0x17c>; | |
| }; | |
| }; | |
| }; | |
| qcom,smem@86000000 { | |
| compatible = "qcom,smem"; | |
| reg-names = "smem\0irq-reg-base\0aux-mem1\0smem_targ_info_reg"; | |
| qcom,mpu-enabled; | |
| reg = <0x86000000 0x200000 0x17911008 0x04 0x778000 0x7000 0x1fd4000 0x08>; | |
| }; | |
| qcom,dsi-display@18 { | |
| compatible = "qcom,dsi-display"; | |
| clocks = <0x2bc 0x06 0x2bc 0x09>; | |
| lab-supply = <0x4e2>; | |
| pinctrl-1 = <0x41c 0x41e>; | |
| clock-names = "src_byte_clk\0src_pixel_clk"; | |
| vddio-supply = <0x120>; | |
| qcom,dsi-panel = <0x4f5>; | |
| label = "dsi_r63417_truly_1080_cmd_display"; | |
| ibb-supply = <0x4e3>; | |
| phandle = <0x552>; | |
| qcom,dsi-ctrl = <0x2c3>; | |
| qcom,display-type = "primary"; | |
| qcom,panel-mode-gpio = <0x34 0x34 0x00>; | |
| pinctrl-0 = <0x41b 0x41d>; | |
| qcom,platform-te-gpio = <0x34 0x0a 0x00>; | |
| qcom,dsi-phy = <0x2c5>; | |
| qcom,platform-reset-gpio = <0x34 0x06 0x00>; | |
| pinctrl-names = "panel_active\0panel_suspend"; | |
| }; | |
| qcom,dsi-display@9 { | |
| compatible = "qcom,dsi-display"; | |
| clocks = <0x2bc 0x06 0x2bc 0x09>; | |
| pinctrl-1 = <0x41c 0x41e>; | |
| clock-names = "mux_byte_clk\0mux_pixel_clk"; | |
| qcom,dsi-panel = <0x4ec>; | |
| label = "dsi_dual_sim_vid_display"; | |
| phandle = <0x549>; | |
| qcom,dsi-ctrl = <0x2c3 0x2c4>; | |
| qcom,display-type = "primary"; | |
| pinctrl-0 = <0x41b 0x41d>; | |
| qcom,dsi-phy = <0x2c5 0x2c6>; | |
| pinctrl-names = "panel_active\0panel_suspend"; | |
| }; | |
| rpmh-regulator-ldoa17 { | |
| qcom,supported-modes = <0x02 0x04>; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "ldoa17"; | |
| mboxes = <0x8a 0x00>; | |
| qcom,regulator-type = "pmic4-ldo"; | |
| qcom,mode-threshold-currents = <0x00 0x2710>; | |
| regulator-l17 { | |
| qcom,init-mode = <0x02>; | |
| phandle = <0xed>; | |
| qcom,init-voltage = <0x13e5c0>; | |
| regulator-min-microvolt = <0x13e5c0>; | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x13e5c0>; | |
| regulator-name = "pm8998_l17"; | |
| }; | |
| }; | |
| cti@6b04000 { | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti-swao_cti0"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x39e>; | |
| arm,primecell-periphid = <0x3b966>; | |
| reg = <0x6b04000 0x1000>; | |
| }; | |
| qcom,glink-ssr-cdsp { | |
| compatible = "qcom,glink_ssr"; | |
| qcom,xprt = "smem"; | |
| qcom,notify-edges = <0xe5 0xe1 0xe2>; | |
| label = "cdsp"; | |
| qcom,edge = "cdsp"; | |
| phandle = <0xe3>; | |
| }; | |
| csr@6b0e000 { | |
| compatible = "qcom,coresight-csr"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "csr-base"; | |
| coresight-name = "coresight-swao-csr"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x350>; | |
| qcom,timestamp-support; | |
| qcom,blk-size = <0x01>; | |
| reg = <0x6b0e000 0x1000>; | |
| }; | |
| qcom,memlat-cpu4 { | |
| compatible = "qcom,devbw"; | |
| qcom,active-only; | |
| qcom,src-dst-ports = <0x01 0x200>; | |
| governor = "powersave"; | |
| qcom,bw-tbl = <0x2fa 0x478 0x6b8 0x826 0xa25 0xb71 0xf27 0x134f 0x172b 0x1ae1>; | |
| status = "ok"; | |
| phandle = <0x85>; | |
| }; | |
| msm_tspp@0x8880000 { | |
| pinctrl-5 = <0x11c 0x11e>; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,msm-bus,num-cases = <0x02>; | |
| compatible = "qcom,msm_tspp"; | |
| clocks = <0x22 0x77 0x22 0x79>; | |
| pinctrl-3 = <0x11e>; | |
| qcom,msm-bus,vectors-KBps = <0x52 0x200 0x00 0x00 0x52 0x200 0x3000 0x6000>; | |
| qcom,smmu-s1-bypass; | |
| reg-names = "MSM_TSIF0_PHYS\0MSM_TSIF1_PHYS\0MSM_TSPP_PHYS\0MSM_TSPP_BAM_PHYS"; | |
| pinctrl-1 = <0x11c>; | |
| clock-names = "iface_clk\0ref_clk"; | |
| qcom,msm-bus,name = "tsif"; | |
| pinctrl-6 = <0x11c 0x11d 0x11e 0x11f>; | |
| interrupts = <0x00 0x79 0x00 0x00 0x77 0x00 0x00 0x78 0x00 0x00 0x7a 0x00>; | |
| pinctrl-4 = <0x11e 0x11f>; | |
| phandle = <0x336>; | |
| pinctrl-2 = <0x11c 0x11d>; | |
| reg = <0x88a7000 0x200 0x88a8000 0x200 0x88a9000 0x1000 0x8884000 0x23000>; | |
| iommus = <0x29 0x20 0x0f>; | |
| pinctrl-0; | |
| interrupt-names = "TSIF_TSPP_IRQ\0TSIF0_IRQ\0TSIF1_IRQ\0TSIF_BAM_IRQ"; | |
| pinctrl-names = "disabled\0tsif0-mode1\0tsif0-mode2\0tsif1-mode1\0tsif1-mode2\0dual-tsif-mode1\0dual-tsif-mode2"; | |
| }; | |
| rpmh-regulator-bobb1 { | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "bobb1"; | |
| mboxes = <0x8a 0x00>; | |
| qcom,send-defaults; | |
| qcom,regulator-type = "pmic4-bob"; | |
| regulator-bob { | |
| qcom,init-mode = <0x00>; | |
| phandle = <0x34d>; | |
| qcom,init-voltage = <0x328980>; | |
| regulator-min-microvolt = <0x328980>; | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x36ee80>; | |
| regulator-name = "pmi8998_bob"; | |
| }; | |
| regulator-bob-ao { | |
| qcom,init-mode = <0x03>; | |
| phandle = <0x34e>; | |
| qcom,init-voltage = <0x328980>; | |
| regulator-min-microvolt = <0x328980>; | |
| qcom,set = <0x01>; | |
| regulator-max-microvolt = <0x36ee80>; | |
| regulator-name = "pmi8998_bob_ao"; | |
| }; | |
| }; | |
| apps_iommu_coherent_test_device { | |
| compatible = "iommu-debug-test"; | |
| dma-coherent; | |
| iommus = <0x29 0x20 0x00>; | |
| }; | |
| qcom,smp2pgpio_test_smp2p_3_in { | |
| gpios = <0x1b6 0x00 0x00>; | |
| compatible = "qcom,smp2pgpio_test_smp2p_3_in"; | |
| }; | |
| tpdm@78a0000 { | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "tpdm-base"; | |
| coresight-name = "coresight-tpdm-llm-silver"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x36d>; | |
| arm,primecell-periphid = <0x3b968>; | |
| reg = <0x78a0000 0x1000>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x166>; | |
| phandle = <0x165>; | |
| }; | |
| }; | |
| }; | |
| qcom,icnss@18800000 { | |
| compatible = "qcom,icnss"; | |
| reg-names = "membase\0smmu_iova_base\0smmu_iova_ipa"; | |
| vdd-0.8-cx-mx-supply = <0xeb>; | |
| vdd-1.3-rfa-supply = <0xed>; | |
| qcom,vdd-0.8-cx-mx-config = "\0\f5\0\0\f5"; | |
| qcom,gpio-force-fatal-error = <0xea 0x00 0x00>; | |
| vdd-1.8-xo-supply = <0xec>; | |
| interrupts = <0x00 0x19e 0x00 0x00 0x19f 0x00 0x00 0x1a0 0x00 0x00 0x1a1 0x00 0x00 0x1a2 0x00 0x00 0x1a3 0x00 0x00 0x1a4 0x00 0x00 0x1a5 0x00 0x00 0x1a6 0x00 0x00 0x1a7 0x00 0x00 0x1a8 0x00 0x00 0x1a9 0x00>; | |
| qcom,vdd-3.3-ch0-config = <0x2f5d00 0x328980>; | |
| qcom,wlan-msa-memory = <0x100000>; | |
| vdd-3.3-ch0-supply = <0xee>; | |
| reg = <0x18800000 0x800000 0xa0000000 0x10000000 0xb0000000 0x10000>; | |
| iommus = <0x29 0x40 0x01>; | |
| qcom,gpio-early-crash-ind = <0xea 0x01 0x00>; | |
| }; | |
| i2c@898000 { | |
| compatible = "qcom,i2c-geni"; | |
| clocks = <0x22 0x58 0x22 0x6c 0x22 0x6d>; | |
| qcom,wrapper-core = <0x35>; | |
| pinctrl-1 = <0x46>; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| status = "disabled"; | |
| #address-cells = <0x01>; | |
| interrupts = <0x00 0x25f 0x00>; | |
| #size-cells = <0x00>; | |
| dma-names = "tx\0rx"; | |
| phandle = <0x2d1>; | |
| reg = <0x898000 0x4000>; | |
| pinctrl-0 = <0x45>; | |
| dmas = <0x38 0x00 0x06 0x03 0x40 0x00 0x38 0x01 0x06 0x03 0x40 0x00>; | |
| pinctrl-names = "default\0sleep"; | |
| }; | |
| qcom,mpm2-sleep-counter@0x0c221000 { | |
| compatible = "qcom,mpm2-sleep-counter"; | |
| reg = <0xc221000 0x1000>; | |
| clock-frequency = <0x8000>; | |
| }; | |
| qcom,l3-cpu0 { | |
| compatible = "devfreq-simple-dev"; | |
| clocks = <0x86 0x03>; | |
| clock-names = "devfreq_clk"; | |
| governor = "performance"; | |
| phandle = <0x87>; | |
| }; | |
| qcom,aopclk { | |
| compatible = "qcom,aop-qmp-clk-v1"; | |
| mbox-names = "qdss_clk"; | |
| mboxes = <0x80 0x00>; | |
| #clock-cells = <0x01>; | |
| phandle = <0x7e>; | |
| }; | |
| ufshc@1d84000 { | |
| qcom,msm-bus,num-paths = <0x02>; | |
| qcom,msm-bus,num-cases = <0x16>; | |
| compatible = "qcom,ufshc"; | |
| clocks = <0x22 0xb1 0x22 0xb7 0x22 0x89 0x22 0xb3 0x22 0xb5 0x21 0x00 0x22 0x92 0x22 0x90 0x22 0x91>; | |
| vdd-hba-supply = <0xa8>; | |
| qcom,msm-bus,vectors-KBps = <0x7b 0x200 0x00 0x00 0x01 0x2f5 0x00 0x00 0x7b 0x200 0x39a 0x00 0x01 0x2f5 0x3e8 0x00 0x7b 0x200 0x734 0x00 0x01 0x2f5 0x3e8 0x00 0x7b 0x200 0xe68 0x00 0x01 0x2f5 0x3e8 0x00 0x7b 0x200 0x1cd0 0x00 0x01 0x2f5 0x3e8 0x00 0x7b 0x200 0x734 0x00 0x01 0x2f5 0x3e8 0x00 0x7b 0x200 0xe68 0x00 0x01 0x2f5 0x3e8 0x00 0x7b 0x200 0x1cd0 0x00 0x01 0x2f5 0x3e8 0x00 0x7b 0x200 0x39a0 0x00 0x01 0x2f5 0x3e8 0x00 0x7b 0x200 0x1f334 0x00 0x01 0x2f5 0x3e8 0x00 0x7b 0x200 0x3e667 0x00 0x01 0x2f5 0x3e8 0x00 0x7b 0x200 0x200000 0x00 0x01 0x2f5 0x19000 0x00 0x7b 0x200 0x3e667 0x00 0x01 0x2f5 0x3e8 0x00 0x7b 0x200 0x7cccd 0x00 0x01 0x2f5 0x3e8 0x00 0x7b 0x200 0x400000 0x00 0x01 0x2f5 0x32000 0x00 0x7b 0x200 0x247ae 0x00 0x01 0x2f5 0x3e8 0x00 0x7b 0x200 0x48ccd 0x00 0x01 0x2f5 0x3e8 0x00 0x7b 0x200 0x200000 0x00 0x01 0x2f5 0x19000 0x00 0x7b 0x200 0x48ccd 0x00 0x01 0x2f5 0x3e8 0x00 0x7b 0x200 0x9199a 0x00 0x01 0x2f5 0x3e8 0x00 0x7b 0x200 0x400000 0x00 0x01 0x2f5 0x32000 0x64000 0x7b 0x200 0x74a000 0x00 0x01 0x2f5 0x4b000 0x00>; | |
| vdd-hba-fixed-regulator; | |
| resets = <0x22 0x0e>; | |
| pinctrl-1 = <0xac>; | |
| lanes-per-direction = <0x02>; | |
| clock-names = "core_clk\0bus_aggr_clk\0iface_clk\0core_clk_unipro\0core_clk_ice\0ref_clk\0tx_lane0_sync_clk\0rx_lane0_sync_clk\0rx_lane1_sync_clk"; | |
| phy-names = "ufsphy"; | |
| qcom,msm-bus,name = "ufshc_mem"; | |
| vcc-max-microamp = <0x927c0>; | |
| qcom,pm-qos-cpu-groups = <0x0f 0xf0>; | |
| status = "ok"; | |
| interrupts = <0x00 0x109 0x00>; | |
| ufs-qcom-crypto = <0xaa>; | |
| vcc-supply = <0x346>; | |
| vccq2-max-microamp = <0x927c0>; | |
| phandle = <0x317>; | |
| qcom,vddp-ref-clk-max-microamp = <0x64>; | |
| qcom,bus-vector-names = "MIN\0PWM_G1_L1\0PWM_G2_L1\0PWM_G3_L1\0PWM_G4_L1\0PWM_G1_L2\0PWM_G2_L2\0PWM_G3_L2\0PWM_G4_L2\0HS_RA_G1_L1\0HS_RA_G2_L1\0HS_RA_G3_L1\0HS_RA_G1_L2\0HS_RA_G2_L2\0HS_RA_G3_L2\0HS_RB_G1_L1\0HS_RB_G2_L1\0HS_RB_G3_L1\0HS_RB_G1_L2\0HS_RB_G2_L2\0HS_RB_G3_L2\0MAX"; | |
| phys = <0xa9>; | |
| reg = <0x1d84000 0x2500>; | |
| vcc-voltage-level = <0x2d0370 0x2d2a80>; | |
| qcom,pm-qos-default-cpu = <0x00>; | |
| pinctrl-0 = <0xab>; | |
| reset-names = "core_reset"; | |
| freq-table-hz = <0x2faf080 0xbebc200 0x00 0x00 0x00 0x00 0x23c3460 0x8f0d180 0x47868c0 0x11e1a300 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>; | |
| vccq2-supply = <0x4dd>; | |
| non-removable; | |
| qcom,vddp-ref-clk-supply = <0x33a>; | |
| dev-ref-clk-freq = <0x00>; | |
| pinctrl-names = "dev-reset-assert\0dev-reset-deassert"; | |
| qcom,pm-qos-cpu-group-latency-us = <0x46 0x46>; | |
| }; | |
| gpio-regulator@2 { | |
| regulator-enable-ramp-delay = <0xe9>; | |
| compatible = "regulator-fixed"; | |
| enable-active-high; | |
| phandle = <0x572>; | |
| reg = <0x02 0x00>; | |
| regulator-name = "camera_ldo"; | |
| }; | |
| qcom,smp2p-dsps@1799000c { | |
| compatible = "qcom,smp2p"; | |
| interrupts = <0x00 0xac 0x01>; | |
| reg = <0x1799000c 0x04>; | |
| qcom,remote-pid = <0x03>; | |
| qcom,irq-bitmask = <0x4000000>; | |
| }; | |
| modem_etm0 { | |
| compatible = "qcom,coresight-remote-etm"; | |
| coresight-name = "coresight-modem-etm0"; | |
| qcom,inst-id = <0x02>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x189>; | |
| phandle = <0x141>; | |
| }; | |
| }; | |
| }; | |
| spi@898000 { | |
| compatible = "qcom,spi-geni"; | |
| clocks = <0x22 0x58 0x22 0x6c 0x22 0x6d>; | |
| qcom,wrapper-core = <0x35>; | |
| reg-names = "se_phys"; | |
| pinctrl-1 = <0x56>; | |
| clock-names = "se-clk\0m-ahb\0s-ahb"; | |
| status = "disabled"; | |
| #address-cells = <0x01>; | |
| interrupts = <0x00 0x25f 0x00>; | |
| #size-cells = <0x00>; | |
| dma-names = "tx\0rx"; | |
| phandle = <0x2d9>; | |
| reg = <0x898000 0x4000>; | |
| pinctrl-0 = <0x55>; | |
| dmas = <0x38 0x00 0x06 0x01 0x40 0x00 0x38 0x01 0x06 0x01 0x40 0x00>; | |
| spi-max-frequency = <0x2faf080>; | |
| pinctrl-names = "default\0sleep"; | |
| }; | |
| ad-hoc-bus { | |
| compatible = "qcom,msm-bus-device"; | |
| reg-names = "aggre1_noc-base\0aggre2_noc-base\0config_noc-base\0dc_noc-base\0gladiator_noc-base\0mc_virt-base\0mem_noc-base\0mmss_noc-base\0system_noc-base\0ipa_virt-base\0camnoc_virt-base"; | |
| mbox-names = "apps_rsc\0disp_rsc"; | |
| mboxes = <0x8a 0x00 0x2b 0x00>; | |
| phandle = <0x3c1>; | |
| reg = <0x16e0000 0x40000 0x1700000 0x40000 0x1500000 0x40000 0x14e0000 0x40000 0x17900000 0x40000 0x1380000 0x40000 0x1380000 0x40000 0x1740000 0x40000 0x1620000 0x40000 0x1620000 0x40000 0x1620000 0x40000>; | |
| slv-ipa-core-slave { | |
| qcom,bus-dev = <0x20a>; | |
| cell-id = <0x309>; | |
| qcom,bcms = <0x242>; | |
| label = "slv-ipa-core-slave"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x209>; | |
| qcom,buswidth = <0x08>; | |
| }; | |
| bcm-sn7 { | |
| cell-id = <0x1b71>; | |
| label = "SN7"; | |
| qcom,bcm-name = "SN7"; | |
| phandle = <0x256>; | |
| qcom,rscs = <0x1c6>; | |
| qcom,bcm-dev; | |
| }; | |
| bcm-sh0 { | |
| cell-id = <0x1b5b>; | |
| label = "SH0"; | |
| qcom,bcm-name = "SH0"; | |
| phandle = <0x247>; | |
| qcom,rscs = <0x1c6>; | |
| qcom,bcm-dev; | |
| }; | |
| slv-qns-memnoc-snoc { | |
| qcom,bus-dev = <0x210>; | |
| cell-id = <0x308>; | |
| qcom,bcms = <0x249>; | |
| label = "slv-qns-memnoc-snoc"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x20f>; | |
| qcom,connections = <0x248>; | |
| qcom,buswidth = <0x08>; | |
| }; | |
| mas-qnm-mnoc-sf_display { | |
| qcom,bus-dev = <0x230>; | |
| cell-id = <0x4e22>; | |
| label = "mas-qnm-mnoc-sf_display"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x25c>; | |
| qcom,qport = <0x07>; | |
| qcom,connections = <0x22f>; | |
| qcom,buswidth = <0x20>; | |
| }; | |
| fab-mem_noc_display { | |
| clocks; | |
| qcom,bypass-qos-prg; | |
| cell-id = <0x6591>; | |
| qcom,base-offset = <0x10000>; | |
| qcom,base-name = "mem_noc-base"; | |
| label = "fab-mem_noc_display"; | |
| phandle = <0x230>; | |
| qcom,bus-type = <0x01>; | |
| qcom,fab-dev; | |
| qcom,qos-off = <0x1000>; | |
| }; | |
| slv-qhs-imem-cfg { | |
| qcom,bus-dev = <0x1d6>; | |
| cell-id = <0x273>; | |
| qcom,bcms = <0x1d7>; | |
| label = "slv-qhs-imem-cfg"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x201>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| fab-ipa_virt { | |
| clocks; | |
| qcom,bypass-qos-prg; | |
| cell-id = <0x1809>; | |
| qcom,base-name = "ipa_virt-base"; | |
| label = "fab-ipa_virt"; | |
| phandle = <0x20a>; | |
| qcom,fab-dev; | |
| }; | |
| slv-qns-a2noc-snoc { | |
| qcom,bus-dev = <0x1ce>; | |
| cell-id = <0x2751>; | |
| label = "slv-qns-a2noc-snoc"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x1cf>; | |
| qcom,connections = <0x238>; | |
| qcom,buswidth = <0x10>; | |
| }; | |
| fab-mc_virt { | |
| clocks; | |
| qcom,bypass-qos-prg; | |
| cell-id = <0x1807>; | |
| qcom,base-name = "mc_virt-base"; | |
| label = "fab-mc_virt"; | |
| phandle = <0x20c>; | |
| qcom,fab-dev; | |
| }; | |
| slv-qns-mem-noc-hf_display { | |
| qcom,bus-dev = <0x232>; | |
| cell-id = <0x5023>; | |
| qcom,bcms = <0x25f>; | |
| label = "slv-qns-mem-noc-hf_display"; | |
| qcom,agg-ports = <0x02>; | |
| phandle = <0x231>; | |
| qcom,connections = <0x25e>; | |
| qcom,buswidth = <0x20>; | |
| }; | |
| slv-qhs-crypto0-cfg { | |
| qcom,bus-dev = <0x1d6>; | |
| cell-id = <0x271>; | |
| qcom,bcms = <0x1d7>; | |
| label = "slv-qhs-crypto0-cfg"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x1fd>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| slv-qxs-pcie-gen3 { | |
| qcom,bus-dev = <0x21b>; | |
| cell-id = <0x29a>; | |
| qcom,bcms = <0x257>; | |
| label = "slv-qxs-pcie-gen3"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x223>; | |
| qcom,buswidth = <0x08>; | |
| }; | |
| bcm-sn12 { | |
| cell-id = <0x1b76>; | |
| label = "SN12"; | |
| qcom,bcm-name = "SN12"; | |
| phandle = <0x227>; | |
| qcom,rscs = <0x1c6>; | |
| qcom,bcm-dev; | |
| }; | |
| slv-qhs-usb3-0 { | |
| qcom,bus-dev = <0x1d6>; | |
| cell-id = <0x247>; | |
| qcom,bcms = <0x1d7>; | |
| label = "slv-qhs-usb3-0"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x1f1>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| mas-qxm-venus1 { | |
| qcom,bus-dev = <0x216>; | |
| qcom,node-qos-bcms = <0x1b64 0x00 0x01>; | |
| cell-id = <0x40>; | |
| qcom,bcms = <0x219>; | |
| label = "mas-qxm-venus1"; | |
| qcom,prio = <0x00>; | |
| qcom,agg-ports = <0x01>; | |
| qcom,forwarding; | |
| phandle = <0x3e2>; | |
| qcom,qport = <0x07>; | |
| qcom,connections = <0x218>; | |
| qcom,buswidth = <0x20>; | |
| qcom,ap-owned; | |
| }; | |
| slv-qns-memnoc-gc { | |
| qcom,bus-dev = <0x21b>; | |
| cell-id = <0x306>; | |
| qcom,bcms = <0x252>; | |
| label = "slv-qns-memnoc-gc"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x22a>; | |
| qcom,connections = <0x251>; | |
| qcom,buswidth = <0x08>; | |
| }; | |
| bcm-acv { | |
| cell-id = <0x1b7d>; | |
| label = "ACV"; | |
| qcom,bcm-name = "ACV"; | |
| phandle = <0x244>; | |
| qcom,rscs = <0x1c6>; | |
| qcom,bcm-dev; | |
| }; | |
| mas-qhm-cnoc { | |
| qcom,bus-dev = <0x204>; | |
| cell-id = <0x7e>; | |
| label = "mas-qhm-cnoc"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x23b>; | |
| qcom,connections = <0x202 0x203>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| slv-qhs-sdc4 { | |
| qcom,bus-dev = <0x1d6>; | |
| cell-id = <0x261>; | |
| qcom,bcms = <0x1d7>; | |
| label = "slv-qhs-sdc4"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x1db>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| slv-qhs-glm { | |
| qcom,bus-dev = <0x1d6>; | |
| cell-id = <0x2d6>; | |
| qcom,bcms = <0x1d7>; | |
| label = "slv-qhs-glm"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x1e0>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| mas-qnm-apps { | |
| qcom,bus-dev = <0x210>; | |
| cell-id = <0x83>; | |
| qcom,bcms = <0x214>; | |
| label = "mas-qnm-apps"; | |
| qcom,prio = <0x00>; | |
| qcom,agg-ports = <0x02>; | |
| phandle = <0x241>; | |
| qcom,qport = <0x02 0x03>; | |
| qcom,connections = <0x20e>; | |
| qcom,buswidth = <0x20>; | |
| qcom,ap-owned; | |
| }; | |
| bcm-sn5 { | |
| cell-id = <0x1b6f>; | |
| label = "SN5"; | |
| qcom,bcm-name = "SN5"; | |
| phandle = <0x258>; | |
| qcom,rscs = <0x1c6>; | |
| qcom,bcm-dev; | |
| }; | |
| slv-qns-camnoc-uncomp { | |
| qcom,bus-dev = <0x1d3>; | |
| cell-id = <0x30a>; | |
| label = "slv-qns-camnoc-uncomp"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x1d2>; | |
| qcom,buswidth = <0x20>; | |
| }; | |
| mas-xm-pcie3-1 { | |
| qcom,bus-dev = <0x1ce>; | |
| cell-id = <0x64>; | |
| label = "mas-xm-pcie3-1"; | |
| qcom,prio = <0x02>; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x3ce>; | |
| qcom,qport = <0x06>; | |
| qcom,connections = <0x1d1>; | |
| qcom,buswidth = <0x08>; | |
| qcom,ap-owned; | |
| }; | |
| mas-qxm-camnoc-hf1 { | |
| qcom,bus-dev = <0x216>; | |
| qcom,node-qos-bcms = <0x1b64 0x00 0x01>; | |
| cell-id = <0x91>; | |
| qcom,bcms = <0x1d4>; | |
| label = "mas-qxm-camnoc-hf1"; | |
| qcom,prio = <0x00>; | |
| qcom,agg-ports = <0x01>; | |
| qcom,forwarding; | |
| phandle = <0x3dc>; | |
| qcom,qport = <0x02>; | |
| qcom,connections = <0x217>; | |
| qcom,buswidth = <0x20>; | |
| qcom,ap-owned; | |
| }; | |
| slv-srvc-snoc { | |
| qcom,bus-dev = <0x21b>; | |
| cell-id = <0x24b>; | |
| qcom,bcms = <0x24e>; | |
| label = "slv-srvc-snoc"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x21a>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| mas-qhm-memnoc-cfg { | |
| qcom,bus-dev = <0x210>; | |
| cell-id = <0x82>; | |
| label = "mas-qhm-memnoc-cfg"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x23f>; | |
| qcom,connections = <0x212 0x213>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| slv-qhs-a2-noc-cfg { | |
| qcom,bus-dev = <0x1d6>; | |
| cell-id = <0x2b0>; | |
| qcom,bcms = <0x1d7>; | |
| label = "slv-qhs-a2-noc-cfg"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x1e2>; | |
| qcom,connections = <0x23a>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| slv-qhs-pimem-cfg { | |
| qcom,bus-dev = <0x1d6>; | |
| cell-id = <0x2a9>; | |
| qcom,bcms = <0x1d7>; | |
| label = "slv-qhs-pimem-cfg"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x1fe>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| slv-qxs-pimem { | |
| qcom,bus-dev = <0x21b>; | |
| cell-id = <0x2c8>; | |
| label = "slv-qxs-pimem"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x21c>; | |
| qcom,buswidth = <0x08>; | |
| }; | |
| fab-config_noc { | |
| clocks; | |
| qcom,bypass-qos-prg; | |
| cell-id = <0x1400>; | |
| qcom,base-name = "config_noc-base"; | |
| label = "fab-config_noc"; | |
| phandle = <0x1d6>; | |
| qcom,bus-type = <0x01>; | |
| qcom,fab-dev; | |
| }; | |
| slv-srvc-aggre2-noc { | |
| qcom,bus-dev = <0x1ce>; | |
| cell-id = <0x2ea>; | |
| qcom,bcms = <0x226>; | |
| label = "slv-srvc-aggre2-noc"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x1cd>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| slv-qxs-pcie { | |
| qcom,bus-dev = <0x21b>; | |
| cell-id = <0x299>; | |
| qcom,bcms = <0x256>; | |
| label = "slv-qxs-pcie"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x224>; | |
| qcom,buswidth = <0x08>; | |
| }; | |
| bcm-ce0 { | |
| cell-id = <0x1b7a>; | |
| label = "CE0"; | |
| qcom,bcm-name = "CE0"; | |
| phandle = <0x1d0>; | |
| qcom,rscs = <0x1c6>; | |
| qcom,bcm-dev; | |
| }; | |
| mas-qhm-qdss-bam { | |
| qcom,bus-dev = <0x1ce>; | |
| cell-id = <0x35>; | |
| label = "mas-qhm-qdss-bam"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x3ca>; | |
| qcom,connections = <0x1cf>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| bcm-mm1_display { | |
| cell-id = <0x697b>; | |
| label = "MM1_DISPLAY"; | |
| qcom,bcm-name = "MM1"; | |
| phandle = <0x233>; | |
| qcom,rscs = <0x1c7>; | |
| qcom,bcm-dev; | |
| }; | |
| bcm-mc0 { | |
| cell-id = <0x1b58>; | |
| label = "MC0"; | |
| qcom,bcm-name = "MC0"; | |
| phandle = <0x243>; | |
| qcom,rscs = <0x1c6>; | |
| qcom,bcm-dev; | |
| }; | |
| slv-qhs-tlmm-south { | |
| qcom,bus-dev = <0x1d6>; | |
| cell-id = <0x2f3>; | |
| qcom,bcms = <0x1d7>; | |
| label = "slv-qhs-tlmm-south"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x1d8>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| mas-qxm-mdp1_display { | |
| qcom,bus-dev = <0x232>; | |
| cell-id = <0x4e24>; | |
| qcom,bcms = <0x233>; | |
| label = "mas-qxm-mdp1_display"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x3e8>; | |
| qcom,qport = <0x04>; | |
| qcom,connections = <0x231>; | |
| qcom,buswidth = <0x20>; | |
| }; | |
| slv-qhs-sdc2 { | |
| qcom,bus-dev = <0x1d6>; | |
| cell-id = <0x260>; | |
| qcom,bcms = <0x1d7>; | |
| label = "slv-qhs-sdc2"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x1dc>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| mas-qxm-ipa { | |
| qcom,bus-dev = <0x1ce>; | |
| qcom,node-qos-bcms = <0x1b7b 0x00 0x01>; | |
| qcom,defer-init-qos; | |
| cell-id = <0x5a>; | |
| label = "mas-qxm-ipa"; | |
| qcom,prio = <0x02>; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x3cd>; | |
| qcom,qport = <0x02>; | |
| qcom,connections = <0x1cf>; | |
| qcom,buswidth = <0x08>; | |
| qcom,ap-owned; | |
| }; | |
| mas-qnm-cnoc { | |
| qcom,bus-dev = <0x1ce>; | |
| cell-id = <0x76>; | |
| label = "mas-qnm-cnoc"; | |
| qcom,prio = <0x01>; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x23e>; | |
| qcom,qport = <0x00>; | |
| qcom,connections = <0x1cf>; | |
| qcom,buswidth = <0x08>; | |
| qcom,ap-owned; | |
| }; | |
| mas-xm-sdc4 { | |
| qcom,bus-dev = <0x1c9>; | |
| cell-id = <0x50>; | |
| label = "mas-xm-sdc4"; | |
| qcom,prio = <0x01>; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x3c6>; | |
| qcom,qport = <0x02>; | |
| qcom,connections = <0x1ca>; | |
| qcom,buswidth = <0x08>; | |
| qcom,ap-owned; | |
| }; | |
| slv-qhs-spdm { | |
| qcom,bus-dev = <0x1d6>; | |
| cell-id = <0x279>; | |
| qcom,bcms = <0x1d7>; | |
| label = "slv-qhs-spdm"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x1fc>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| fab-aggre2_noc { | |
| clocks; | |
| cell-id = <0x1803>; | |
| qcom,base-offset = <0x4000>; | |
| qcom,base-name = "aggre2_noc-base"; | |
| label = "fab-aggre2_noc"; | |
| phandle = <0x1ce>; | |
| qcom,bus-type = <0x01>; | |
| qcom,fab-dev; | |
| qcom,qos-off = <0x1000>; | |
| }; | |
| bcm-sn3 { | |
| cell-id = <0x1b6d>; | |
| label = "SN3"; | |
| qcom,bcm-name = "SN3"; | |
| phandle = <0x250>; | |
| qcom,rscs = <0x1c6>; | |
| qcom,bcm-dev; | |
| }; | |
| mas-qxm-camnoc-sf { | |
| qcom,bus-dev = <0x216>; | |
| qcom,node-qos-bcms = <0x1b64 0x00 0x01>; | |
| cell-id = <0x89>; | |
| qcom,bcms = <0x219>; | |
| label = "mas-qxm-camnoc-sf"; | |
| qcom,prio = <0x00>; | |
| qcom,agg-ports = <0x01>; | |
| qcom,forwarding; | |
| phandle = <0x3dd>; | |
| qcom,qport = <0x00>; | |
| qcom,connections = <0x218>; | |
| qcom,buswidth = <0x20>; | |
| qcom,ap-owned; | |
| }; | |
| slv-qhs-gpuss-cfg { | |
| qcom,bus-dev = <0x1d6>; | |
| cell-id = <0x256>; | |
| qcom,bcms = <0x1d7>; | |
| label = "slv-qhs-gpuss-cfg"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x1eb>; | |
| qcom,buswidth = <0x08>; | |
| }; | |
| slv-qhs-aoss { | |
| qcom,bus-dev = <0x1d6>; | |
| cell-id = <0x2ec>; | |
| qcom,bcms = <0x1d7>; | |
| label = "slv-qhs-aoss"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x1f8>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| mas-qxm-gpu { | |
| qcom,bus-dev = <0x210>; | |
| cell-id = <0x1a>; | |
| label = "mas-qxm-gpu"; | |
| qcom,prio = <0x00>; | |
| qcom,agg-ports = <0x02>; | |
| phandle = <0x3da>; | |
| qcom,qport = <0x0a 0x0b>; | |
| qcom,connections = <0x20d 0x20e 0x20f>; | |
| qcom,buswidth = <0x20>; | |
| qcom,ap-owned; | |
| }; | |
| slv-qhs-dcc-cfg { | |
| qcom,bus-dev = <0x1d6>; | |
| cell-id = <0x2aa>; | |
| qcom,bcms = <0x1d7>; | |
| label = "slv-qhs-dcc-cfg"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x1e6>; | |
| qcom,connections = <0x23b>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| slv-qns-apps-io { | |
| qcom,bus-dev = <0x210>; | |
| cell-id = <0x2fe>; | |
| qcom,bcms = <0x245>; | |
| label = "slv-qns-apps-io"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x20d>; | |
| qcom,buswidth = <0x20>; | |
| }; | |
| mas-qxm-venus-arm9 { | |
| qcom,bus-dev = <0x216>; | |
| qcom,node-qos-bcms = <0x1b64 0x00 0x01>; | |
| cell-id = <0x8a>; | |
| qcom,bcms = <0x219>; | |
| label = "mas-qxm-venus-arm9"; | |
| qcom,prio = <0x00>; | |
| qcom,agg-ports = <0x01>; | |
| qcom,forwarding; | |
| phandle = <0x3e3>; | |
| qcom,qport = <0x08>; | |
| qcom,connections = <0x218>; | |
| qcom,buswidth = <0x08>; | |
| qcom,ap-owned; | |
| }; | |
| slv-qhs-venus-cfg { | |
| qcom,bus-dev = <0x1d6>; | |
| cell-id = <0x254>; | |
| qcom,bcms = <0x1d7>; | |
| label = "slv-qhs-venus-cfg"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x1ec>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| bcm-mm3 { | |
| cell-id = <0x1b66>; | |
| label = "MM3"; | |
| qcom,bcm-name = "MM3"; | |
| phandle = <0x219>; | |
| qcom,rscs = <0x1c6>; | |
| qcom,bcm-dev; | |
| }; | |
| slv-qns-gnoc-memnoc { | |
| qcom,bus-dev = <0x208>; | |
| cell-id = <0x2fb>; | |
| label = "slv-qns-gnoc-memnoc"; | |
| qcom,agg-ports = <0x02>; | |
| phandle = <0x207>; | |
| qcom,connections = <0x241>; | |
| qcom,buswidth = <0x20>; | |
| }; | |
| bcm-sh5 { | |
| cell-id = <0x1b60>; | |
| label = "SH5"; | |
| qcom,bcm-name = "SH5"; | |
| phandle = <0x214>; | |
| qcom,rscs = <0x1c6>; | |
| qcom,bcm-dev; | |
| }; | |
| mas-xm-sdc2 { | |
| qcom,bus-dev = <0x1c9>; | |
| cell-id = <0x51>; | |
| label = "mas-xm-sdc2"; | |
| qcom,prio = <0x01>; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x3c5>; | |
| qcom,qport = <0x01>; | |
| qcom,connections = <0x1ca>; | |
| qcom,buswidth = <0x08>; | |
| qcom,ap-owned; | |
| }; | |
| mas-xm-pcie-0 { | |
| qcom,bus-dev = <0x1c9>; | |
| cell-id = <0x2d>; | |
| label = "mas-xm-pcie-0"; | |
| qcom,prio = <0x02>; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x3c9>; | |
| qcom,qport = <0x05>; | |
| qcom,connections = <0x1cc>; | |
| qcom,buswidth = <0x08>; | |
| qcom,ap-owned; | |
| }; | |
| slv-qns2-mem-noc_display { | |
| qcom,bus-dev = <0x232>; | |
| cell-id = <0x5022>; | |
| qcom,bcms = <0x25d>; | |
| label = "slv-qns2-mem-noc_display"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x234>; | |
| qcom,connections = <0x25c>; | |
| qcom,buswidth = <0x20>; | |
| }; | |
| slv-qhs-snoc-cfg { | |
| qcom,bus-dev = <0x1d6>; | |
| cell-id = <0x282>; | |
| qcom,bcms = <0x1d7>; | |
| label = "slv-qhs-snoc-cfg"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x1df>; | |
| qcom,connections = <0x23d>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| bcm-sn1 { | |
| cell-id = <0x1b6b>; | |
| label = "SN1"; | |
| qcom,bcm-name = "SN1"; | |
| phandle = <0x255>; | |
| qcom,rscs = <0x1c6>; | |
| qcom,bcm-dev; | |
| }; | |
| slv-qhs-display-cfg { | |
| qcom,bus-dev = <0x1d6>; | |
| cell-id = <0x24e>; | |
| qcom,bcms = <0x1d7>; | |
| label = "slv-qhs-display-cfg"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x1e4>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| mas-qnm-gladiator-sodv { | |
| qcom,bus-dev = <0x21b>; | |
| cell-id = <0x8b>; | |
| qcom,bcms = <0x227>; | |
| label = "mas-qnm-gladiator-sodv"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x240>; | |
| qcom,connections = <0x21c 0x223 0x21e 0x21f 0x220 0x224 0x225 0x221>; | |
| qcom,buswidth = <0x08>; | |
| }; | |
| slv-qhs-ufs-card-cfg { | |
| qcom,bus-dev = <0x1d6>; | |
| cell-id = <0x2f4>; | |
| qcom,bcms = <0x1d7>; | |
| label = "slv-qhs-ufs-card-cfg"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x1f3>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| mas-qnm-memnoc { | |
| qcom,bus-dev = <0x21b>; | |
| cell-id = <0x8e>; | |
| qcom,bcms = <0x228>; | |
| label = "mas-qnm-memnoc"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x248>; | |
| qcom,connections = <0x21e 0x21f 0x21c 0x220 0x221>; | |
| qcom,buswidth = <0x08>; | |
| }; | |
| mas-qxm-rot_display { | |
| qcom,bus-dev = <0x232>; | |
| cell-id = <0x4e25>; | |
| qcom,bcms = <0x235>; | |
| label = "mas-qxm-rot_display"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x3e9>; | |
| qcom,qport = <0x05>; | |
| qcom,connections = <0x234>; | |
| qcom,buswidth = <0x20>; | |
| }; | |
| mas-qhm-qup1 { | |
| qcom,bus-dev = <0x1c9>; | |
| cell-id = <0x56>; | |
| qcom,bcms = <0x1cb>; | |
| label = "mas-qhm-qup1"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x3c3>; | |
| qcom,connections = <0x1ca>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| mas-qxm-camnoc-hf1-uncomp { | |
| qcom,bus-dev = <0x1d3>; | |
| cell-id = <0x93>; | |
| qcom,bcms = <0x1d4>; | |
| label = "mas-qxm-camnoc-hf1-uncomp"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x3d3>; | |
| qcom,connections = <0x1d2>; | |
| qcom,buswidth = <0x20>; | |
| }; | |
| mas-xm-usb3-1 { | |
| qcom,bus-dev = <0x1ce>; | |
| cell-id = <0x65>; | |
| label = "mas-xm-usb3-1"; | |
| qcom,prio = <0x02>; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x3d1>; | |
| qcom,qport = <0x0b>; | |
| qcom,connections = <0x1cf>; | |
| qcom,buswidth = <0x08>; | |
| qcom,ap-owned; | |
| qcom,node-qos-clks { | |
| clocks = <0x22 0x0a>; | |
| clock-names = "clk-usb3-sec-axi-no-rate"; | |
| }; | |
| }; | |
| mas-qnm-snoc-gc { | |
| qcom,bus-dev = <0x210>; | |
| cell-id = <0x86>; | |
| label = "mas-qnm-snoc-gc"; | |
| qcom,prio = <0x00>; | |
| qcom,agg-ports = <0x01>; | |
| qcom,forwarding; | |
| phandle = <0x251>; | |
| qcom,qport = <0x08>; | |
| qcom,connections = <0x20e>; | |
| qcom,buswidth = <0x08>; | |
| qcom,ap-owned; | |
| }; | |
| mas-qxm-pimem { | |
| qcom,bus-dev = <0x21b>; | |
| cell-id = <0x8d>; | |
| qcom,bcms = <0x22b>; | |
| label = "mas-qxm-pimem"; | |
| qcom,prio = <0x02>; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x3e4>; | |
| qcom,qport = <0x03>; | |
| qcom,connections = <0x21e 0x22a>; | |
| qcom,buswidth = <0x08>; | |
| qcom,ap-owned; | |
| }; | |
| slv-qhs-vsense-ctrl-cfg { | |
| qcom,bus-dev = <0x1d6>; | |
| cell-id = <0x2f6>; | |
| qcom,bcms = <0x1d7>; | |
| label = "slv-qhs-vsense-ctrl-cfg"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x1fa>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| bcm-mm1 { | |
| cell-id = <0x1b64>; | |
| label = "MM1"; | |
| qcom,bcm-name = "MM1"; | |
| phandle = <0x1d4>; | |
| qcom,rscs = <0x1c6>; | |
| qcom,bcm-dev; | |
| }; | |
| slv-qhs-pcie-gen3-cfg { | |
| qcom,bus-dev = <0x1d6>; | |
| cell-id = <0x29c>; | |
| qcom,bcms = <0x1d7>; | |
| label = "slv-qhs-pcie-gen3-cfg"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x1e9>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| slv-qhs-memnoc { | |
| qcom,bus-dev = <0x204>; | |
| cell-id = <0x2f9>; | |
| label = "slv-qhs-memnoc"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x202>; | |
| qcom,connections = <0x23f>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| bcm-sh3 { | |
| cell-id = <0x1b5e>; | |
| label = "SH3"; | |
| qcom,bcm-name = "SH3"; | |
| phandle = <0x211>; | |
| qcom,rscs = <0x1c6>; | |
| qcom,bcm-dev; | |
| }; | |
| mas-ipa-core-master { | |
| qcom,bus-dev = <0x20a>; | |
| cell-id = <0x8f>; | |
| label = "mas-ipa-core-master"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x3d8>; | |
| qcom,connections = <0x209>; | |
| qcom,buswidth = <0x08>; | |
| }; | |
| slv-qhs-pdm { | |
| qcom,bus-dev = <0x1d6>; | |
| cell-id = <0x267>; | |
| qcom,bcms = <0x1d7>; | |
| label = "slv-qhs-pdm"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x1e1>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| mas-qhm-spdm { | |
| qcom,bus-dev = <0x1d6>; | |
| cell-id = <0x24>; | |
| qcom,bcms = <0x1d7>; | |
| label = "mas-qhm-spdm"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x3d5>; | |
| qcom,connections = <0x1d5>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| slv-qhs-ipa { | |
| qcom,bus-dev = <0x1d6>; | |
| cell-id = <0x2a4>; | |
| qcom,bcms = <0x1d7>; | |
| label = "slv-qhs-ipa"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x1f5>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| mas-xm-gic { | |
| qcom,bus-dev = <0x21b>; | |
| cell-id = <0x95>; | |
| qcom,bcms = <0x227>; | |
| label = "mas-xm-gic"; | |
| qcom,prio = <0x01>; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x3e5>; | |
| qcom,qport = <0x00>; | |
| qcom,connections = <0x21e 0x22a>; | |
| qcom,buswidth = <0x08>; | |
| qcom,ap-owned; | |
| }; | |
| mas-qxm-mdp0 { | |
| qcom,bus-dev = <0x216>; | |
| qcom,node-qos-bcms = <0x1b64 0x00 0x01>; | |
| cell-id = <0x16>; | |
| qcom,bcms = <0x1d4>; | |
| label = "mas-qxm-mdp0"; | |
| qcom,prio = <0x00>; | |
| qcom,agg-ports = <0x01>; | |
| qcom,forwarding; | |
| phandle = <0x3de>; | |
| qcom,qport = <0x03>; | |
| qcom,connections = <0x217>; | |
| qcom,buswidth = <0x20>; | |
| qcom,ap-owned; | |
| }; | |
| mas-pm-gnoc-cfg { | |
| qcom,bus-dev = <0x208>; | |
| cell-id = <0x7f>; | |
| label = "mas-pm-gnoc-cfg"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x3d7>; | |
| qcom,connections = <0x205>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| mas-acm-tcu { | |
| qcom,bus-dev = <0x210>; | |
| cell-id = <0x68>; | |
| qcom,bcms = <0x211>; | |
| label = "mas-acm-tcu"; | |
| qcom,prio = <0x07>; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x3d9>; | |
| qcom,qport = <0x00>; | |
| qcom,connections = <0x20d 0x20e 0x20f>; | |
| qcom,buswidth = <0x08>; | |
| qcom,ap-owned; | |
| }; | |
| bcm-sn15 { | |
| cell-id = <0x1b79>; | |
| label = "SN15"; | |
| qcom,bcm-name = "SN15"; | |
| phandle = <0x228>; | |
| qcom,rscs = <0x1c6>; | |
| qcom,bcm-dev; | |
| }; | |
| fab-dc_noc { | |
| clocks; | |
| qcom,bypass-qos-prg; | |
| cell-id = <0x1806>; | |
| qcom,base-name = "dc_noc-base"; | |
| label = "fab-dc_noc"; | |
| phandle = <0x204>; | |
| qcom,bus-type = <0x01>; | |
| qcom,fab-dev; | |
| }; | |
| slv-srvc-mnoc { | |
| qcom,bus-dev = <0x216>; | |
| cell-id = <0x25b>; | |
| label = "slv-srvc-mnoc"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x215>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| slv-srvc-memnoc { | |
| qcom,bus-dev = <0x210>; | |
| cell-id = <0x303>; | |
| label = "slv-srvc-memnoc"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x212>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| mas-xm-ufs-mem { | |
| qcom,bus-dev = <0x1c9>; | |
| cell-id = <0x7b>; | |
| label = "mas-xm-ufs-mem"; | |
| qcom,prio = <0x02>; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x3c8>; | |
| qcom,qport = <0x04>; | |
| qcom,connections = <0x1ca>; | |
| qcom,buswidth = <0x08>; | |
| qcom,ap-owned; | |
| }; | |
| bcm-sn8 { | |
| cell-id = <0x1b72>; | |
| label = "SN8"; | |
| qcom,bcm-name = "SN8"; | |
| phandle = <0x257>; | |
| qcom,rscs = <0x1c6>; | |
| qcom,bcm-dev; | |
| }; | |
| bcm-sh0_display { | |
| cell-id = <0x6979>; | |
| label = "SH0_DISPLAY"; | |
| qcom,bcm-name = "SH0"; | |
| phandle = <0x25b>; | |
| qcom,rscs = <0x1c7>; | |
| qcom,bcm-dev; | |
| }; | |
| bcm-sh1 { | |
| cell-id = <0x1b5c>; | |
| label = "SH1"; | |
| qcom,bcm-name = "SH1"; | |
| phandle = <0x245>; | |
| qcom,rscs = <0x1c6>; | |
| qcom,bcm-dev; | |
| }; | |
| mas-qhm-snoc-cfg { | |
| qcom,bus-dev = <0x21b>; | |
| cell-id = <0x36>; | |
| label = "mas-qhm-snoc-cfg"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x23d>; | |
| qcom,connections = <0x21a>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| bcm-ip0 { | |
| cell-id = <0x1b7b>; | |
| label = "IP0"; | |
| qcom,bcm-name = "IP0"; | |
| phandle = <0x242>; | |
| qcom,rscs = <0x1c6>; | |
| qcom,bcm-dev; | |
| }; | |
| mas-qnm-snoc { | |
| qcom,bus-dev = <0x1d6>; | |
| cell-id = <0x2733>; | |
| qcom,bcms = <0x1d7>; | |
| label = "mas-qnm-snoc"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x24f>; | |
| qcom,connections = <0x1d8 0x1d9 0x1da 0x1db 0x1dc 0x1dd 0x1de 0x1df 0x1e0 0x1e1 0x1e2 0x1e3 0x1e4 0x1e5 0x1e6 0x1e7 0x1e8 0x1e9 0x1ea 0x1eb 0x1ec 0x1ed 0x1ee 0x1ef 0x1f0 0x1f1 0x1f2 0x1f3 0x1f4 0x1f5 0x1f6 0x1f7 0x1f8 0x1f9 0x1fa 0x1fb 0x1fc 0x1fd 0x1fe 0x1ff 0x200 0x201>; | |
| qcom,buswidth = <0x08>; | |
| }; | |
| bcm-mm2_display { | |
| cell-id = <0x697c>; | |
| label = "MM2_DISPLAY"; | |
| qcom,bcm-name = "MM2"; | |
| phandle = <0x25d>; | |
| qcom,rscs = <0x1c7>; | |
| qcom,bcm-dev; | |
| }; | |
| slv-srvc-gnoc { | |
| qcom,bus-dev = <0x208>; | |
| cell-id = <0x2fc>; | |
| label = "slv-srvc-gnoc"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x205>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| mas-qxm-camnoc-hf0-uncomp { | |
| qcom,bus-dev = <0x1d3>; | |
| cell-id = <0x92>; | |
| qcom,bcms = <0x1d4>; | |
| label = "mas-qxm-camnoc-hf0-uncomp"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x3d2>; | |
| qcom,connections = <0x1d2>; | |
| qcom,buswidth = <0x20>; | |
| }; | |
| slv-qhs-qupv3-north { | |
| qcom,bus-dev = <0x1d6>; | |
| cell-id = <0x263>; | |
| qcom,bcms = <0x1d7>; | |
| label = "slv-qhs-qupv3-north"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x1f0>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| fab-gladiator_noc { | |
| clocks; | |
| qcom,bypass-qos-prg; | |
| cell-id = <0x1804>; | |
| qcom,base-name = "gladiator_noc-base"; | |
| label = "fab-gladiator_noc"; | |
| phandle = <0x208>; | |
| qcom,bus-type = <0x01>; | |
| qcom,fab-dev; | |
| }; | |
| mas-qhm-a2noc-cfg { | |
| qcom,bus-dev = <0x1ce>; | |
| cell-id = <0x7c>; | |
| label = "mas-qhm-a2noc-cfg"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x23a>; | |
| qcom,connections = <0x1cd>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| mas-xm-ufs-card { | |
| qcom,bus-dev = <0x1c9>; | |
| cell-id = <0x7a>; | |
| label = "mas-xm-ufs-card"; | |
| qcom,prio = <0x02>; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x3c7>; | |
| qcom,qport = <0x03>; | |
| qcom,connections = <0x1ca>; | |
| qcom,buswidth = <0x08>; | |
| qcom,ap-owned; | |
| }; | |
| slv-qxs-imem { | |
| qcom,bus-dev = <0x21b>; | |
| cell-id = <0x249>; | |
| qcom,bcms = <0x255>; | |
| label = "slv-qxs-imem"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x21e>; | |
| qcom,buswidth = <0x08>; | |
| }; | |
| fab-mmss_noc { | |
| clocks; | |
| cell-id = <0x800>; | |
| qcom,base-offset = <0x9000>; | |
| qcom,base-name = "mmss_noc-base"; | |
| label = "fab-mmss_noc"; | |
| phandle = <0x216>; | |
| qcom,bus-type = <0x01>; | |
| qcom,fab-dev; | |
| qcom,qos-off = <0x1000>; | |
| }; | |
| slv-ebi { | |
| qcom,bus-dev = <0x20c>; | |
| cell-id = <0x200>; | |
| qcom,bcms = <0x243 0x244>; | |
| label = "slv-ebi"; | |
| qcom,agg-ports = <0x04>; | |
| phandle = <0x20b>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| slv-qhs-camera-cfg { | |
| qcom,bus-dev = <0x1d6>; | |
| cell-id = <0x24d>; | |
| qcom,bcms = <0x1d7>; | |
| label = "slv-qhs-camera-cfg"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x1da>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| bcm-qup0 { | |
| cell-id = <0x1b7f>; | |
| label = "QUP0"; | |
| qcom,bcm-name = "QUP0"; | |
| phandle = <0x1cb>; | |
| qcom,rscs = <0x1c6>; | |
| qcom,bcm-dev; | |
| }; | |
| slv-qhs-usb3-1 { | |
| qcom,bus-dev = <0x1d6>; | |
| cell-id = <0x2ef>; | |
| qcom,bcms = <0x1d7>; | |
| label = "slv-qhs-usb3-1"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x1f4>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| slv-qns-memnoc-sf { | |
| qcom,bus-dev = <0x21b>; | |
| cell-id = <0x307>; | |
| qcom,bcms = <0x254>; | |
| label = "slv-qns-memnoc-sf"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x21d>; | |
| qcom,connections = <0x253>; | |
| qcom,buswidth = <0x10>; | |
| }; | |
| slv-qhs-cpr-cx { | |
| qcom,bus-dev = <0x1d6>; | |
| cell-id = <0x28b>; | |
| qcom,bcms = <0x1d7>; | |
| label = "slv-qhs-cpr-cx"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x1f6>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| mas-xm-qdss-etr { | |
| qcom,bus-dev = <0x1ce>; | |
| cell-id = <0x3c>; | |
| label = "mas-xm-qdss-etr"; | |
| qcom,prio = <0x02>; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x3cf>; | |
| qcom,qport = <0x07>; | |
| qcom,connections = <0x1cf>; | |
| qcom,buswidth = <0x08>; | |
| qcom,ap-owned; | |
| }; | |
| slv-xs-sys-tcu-cfg { | |
| qcom,bus-dev = <0x21b>; | |
| cell-id = <0x2a0>; | |
| qcom,bcms = <0x24e>; | |
| label = "slv-xs-sys-tcu-cfg"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x225>; | |
| qcom,buswidth = <0x08>; | |
| }; | |
| mas-llcc-mc_display { | |
| qcom,bus-dev = <0x22e>; | |
| cell-id = <0x4e20>; | |
| label = "mas-llcc-mc_display"; | |
| qcom,agg-ports = <0x04>; | |
| phandle = <0x25a>; | |
| qcom,connections = <0x22d>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| mas-alc { | |
| qcom,bus-dev = <0x20c>; | |
| cell-id = <0x90>; | |
| qcom,bcms = <0x22c>; | |
| label = "mas-alc"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x3e6>; | |
| qcom,buswidth = <0x01>; | |
| }; | |
| mas-qxm-camnoc-sf-uncomp { | |
| qcom,bus-dev = <0x1d3>; | |
| cell-id = <0x94>; | |
| qcom,bcms = <0x1d4>; | |
| label = "mas-qxm-camnoc-sf-uncomp"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x3d4>; | |
| qcom,connections = <0x1d2>; | |
| qcom,buswidth = <0x20>; | |
| }; | |
| bcm-sn6 { | |
| cell-id = <0x1b70>; | |
| label = "SN6"; | |
| qcom,bcm-name = "SN6"; | |
| phandle = <0x24e>; | |
| qcom,rscs = <0x1c6>; | |
| qcom,bcm-dev; | |
| }; | |
| slv-qns2-mem-noc { | |
| qcom,bus-dev = <0x216>; | |
| cell-id = <0x304>; | |
| qcom,bcms = <0x24b>; | |
| label = "slv-qns2-mem-noc"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x218>; | |
| qcom,connections = <0x24a>; | |
| qcom,buswidth = <0x20>; | |
| }; | |
| slv-qhs-ddrss-cfg { | |
| qcom,bus-dev = <0x1d6>; | |
| cell-id = <0x2ee>; | |
| qcom,bcms = <0x1d7>; | |
| label = "slv-qhs-ddrss-cfg"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x1e7>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| slv-qhs-aop { | |
| qcom,bus-dev = <0x1d6>; | |
| cell-id = <0x2eb>; | |
| qcom,bcms = <0x1d7>; | |
| label = "slv-qhs-aop"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x1ef>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| mas-qnm-mnoc-hf { | |
| qcom,bus-dev = <0x210>; | |
| qcom,node-qos-bcms = <0x1b64 0x00 0x01>; | |
| cell-id = <0x84>; | |
| label = "mas-qnm-mnoc-hf"; | |
| qcom,prio = <0x00>; | |
| qcom,agg-ports = <0x02>; | |
| qcom,forwarding; | |
| phandle = <0x24c>; | |
| qcom,qport = <0x04 0x05>; | |
| qcom,connections = <0x20d 0x20e>; | |
| qcom,buswidth = <0x20>; | |
| qcom,ap-owned; | |
| }; | |
| slv-qhs-prng { | |
| qcom,bus-dev = <0x1d6>; | |
| cell-id = <0x26a>; | |
| qcom,bcms = <0x1d7>; | |
| label = "slv-qhs-prng"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x1f9>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| bcm-sn11 { | |
| cell-id = <0x1b75>; | |
| label = "SN11"; | |
| qcom,bcm-name = "SN11"; | |
| phandle = <0x226>; | |
| qcom,rscs = <0x1c6>; | |
| qcom,bcm-dev; | |
| }; | |
| mas-qxm-venus0 { | |
| qcom,bus-dev = <0x216>; | |
| qcom,node-qos-bcms = <0x1b64 0x00 0x01>; | |
| cell-id = <0x3f>; | |
| qcom,bcms = <0x219>; | |
| label = "mas-qxm-venus0"; | |
| qcom,prio = <0x00>; | |
| qcom,agg-ports = <0x01>; | |
| qcom,forwarding; | |
| phandle = <0x3e1>; | |
| qcom,qport = <0x06>; | |
| qcom,connections = <0x218>; | |
| qcom,buswidth = <0x20>; | |
| qcom,ap-owned; | |
| }; | |
| slv-xs-qdss-stm { | |
| qcom,bus-dev = <0x21b>; | |
| cell-id = <0x24c>; | |
| qcom,bcms = <0x258>; | |
| label = "slv-xs-qdss-stm"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x221>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| slv-qhs-tsif { | |
| qcom,bus-dev = <0x1d6>; | |
| cell-id = <0x23f>; | |
| qcom,bcms = <0x1d7>; | |
| label = "slv-qhs-tsif"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x1ed>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| mas-qnm-aggre1-noc { | |
| qcom,bus-dev = <0x21b>; | |
| cell-id = <0x274f>; | |
| qcom,bcms = <0x222>; | |
| label = "mas-qnm-aggre1-noc"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x236>; | |
| qcom,connections = <0x21c 0x21d 0x21e 0x21f 0x220 0x221>; | |
| qcom,buswidth = <0x10>; | |
| }; | |
| fab-camnoc_virt { | |
| clocks; | |
| qcom,bypass-qos-prg; | |
| cell-id = <0x180a>; | |
| qcom,base-name = "camnoc_virt-base"; | |
| label = "fab-camnoc_virt"; | |
| phandle = <0x1d3>; | |
| qcom,fab-dev; | |
| }; | |
| mas-qhm-a1noc-cfg { | |
| qcom,bus-dev = <0x1c9>; | |
| cell-id = <0x79>; | |
| label = "mas-qhm-a1noc-cfg"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x239>; | |
| qcom,connections = <0x1c8>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| mas-llcc-mc { | |
| qcom,bus-dev = <0x20c>; | |
| cell-id = <0x81>; | |
| label = "mas-llcc-mc"; | |
| qcom,agg-ports = <0x04>; | |
| phandle = <0x246>; | |
| qcom,connections = <0x20b>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| bcm-sn4 { | |
| cell-id = <0x1b6e>; | |
| label = "SN4"; | |
| qcom,bcm-name = "SN4"; | |
| phandle = <0x22b>; | |
| qcom,rscs = <0x1c6>; | |
| qcom,bcm-dev; | |
| }; | |
| rsc-disp { | |
| cell-id = <0x1f41>; | |
| label = "disp_rsc"; | |
| phandle = <0x1c7>; | |
| qcom,rsc-dev; | |
| qcom,req_state = <0x03>; | |
| }; | |
| slv-qns-pcie-snoc { | |
| qcom,bus-dev = <0x1ce>; | |
| cell-id = <0x2e9>; | |
| label = "slv-qns-pcie-snoc"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x1d1>; | |
| qcom,connections = <0x237>; | |
| qcom,buswidth = <0x10>; | |
| }; | |
| slv-qhs-mnoc-cfg { | |
| qcom,bus-dev = <0x1d6>; | |
| cell-id = <0x280>; | |
| qcom,bcms = <0x1d7>; | |
| label = "slv-qhs-mnoc-cfg"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x1dd>; | |
| qcom,connections = <0x23c>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| mas-acm-l3 { | |
| qcom,bus-dev = <0x208>; | |
| cell-id = <0x01>; | |
| label = "mas-acm-l3"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x3d6>; | |
| qcom,connections = <0x205 0x206 0x207>; | |
| qcom,buswidth = <0x10>; | |
| }; | |
| mas-qxm-camnoc-hf0 { | |
| qcom,bus-dev = <0x216>; | |
| qcom,node-qos-bcms = <0x1b64 0x00 0x01>; | |
| cell-id = <0x88>; | |
| qcom,bcms = <0x1d4>; | |
| label = "mas-qxm-camnoc-hf0"; | |
| qcom,prio = <0x00>; | |
| qcom,agg-ports = <0x01>; | |
| qcom,forwarding; | |
| phandle = <0x3db>; | |
| qcom,qport = <0x01>; | |
| qcom,connections = <0x217>; | |
| qcom,buswidth = <0x20>; | |
| qcom,ap-owned; | |
| }; | |
| slv-qns-gladiator-sodv { | |
| qcom,bus-dev = <0x208>; | |
| cell-id = <0x2d8>; | |
| label = "slv-qns-gladiator-sodv"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x206>; | |
| qcom,connections = <0x240>; | |
| qcom,buswidth = <0x08>; | |
| }; | |
| slv-qhs-tcsr { | |
| qcom,bus-dev = <0x1d6>; | |
| cell-id = <0x26f>; | |
| qcom,bcms = <0x1d7>; | |
| label = "slv-qhs-tcsr"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x1e5>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| slv-qhs-spss-cfg { | |
| qcom,bus-dev = <0x1d6>; | |
| cell-id = <0x2f1>; | |
| qcom,bcms = <0x1d7>; | |
| label = "slv-qhs-spss-cfg"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x1d9>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| slv-qns-cnoc-a2noc { | |
| qcom,bus-dev = <0x1d6>; | |
| cell-id = <0x2d5>; | |
| qcom,bcms = <0x1d7>; | |
| label = "slv-qns-cnoc-a2noc"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x1d5>; | |
| qcom,connections = <0x23e>; | |
| qcom,buswidth = <0x08>; | |
| }; | |
| slv-qhs-apss { | |
| qcom,bus-dev = <0x21b>; | |
| cell-id = <0x2a1>; | |
| qcom,bcms = <0x24e>; | |
| label = "slv-qhs-apss"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x21f>; | |
| qcom,buswidth = <0x08>; | |
| }; | |
| fab-mc_virt_display { | |
| clocks; | |
| qcom,bypass-qos-prg; | |
| cell-id = <0x6590>; | |
| qcom,base-name = "mc_virt-base"; | |
| label = "fab-mc_virt_display"; | |
| phandle = <0x22e>; | |
| qcom,fab-dev; | |
| }; | |
| mas-qnm-mnoc-sf { | |
| qcom,bus-dev = <0x210>; | |
| qcom,node-qos-bcms = <0x1b64 0x00 0x01>; | |
| cell-id = <0x85>; | |
| label = "mas-qnm-mnoc-sf"; | |
| qcom,prio = <0x00>; | |
| qcom,agg-ports = <0x01>; | |
| qcom,forwarding; | |
| phandle = <0x24a>; | |
| qcom,qport = <0x07>; | |
| qcom,connections = <0x20d 0x20e 0x20f>; | |
| qcom,buswidth = <0x20>; | |
| qcom,ap-owned; | |
| }; | |
| slv-qhs-mdsp-ms-mpu-cfg { | |
| qcom,bus-dev = <0x210>; | |
| cell-id = <0x2fd>; | |
| label = "slv-qhs-mdsp-ms-mpu-cfg"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x213>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| slv-qhs-compute-dsp-cfg { | |
| qcom,bus-dev = <0x1d6>; | |
| cell-id = <0x2ed>; | |
| qcom,bcms = <0x1d7>; | |
| label = "slv-qhs-compute-dsp-cfg"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x1ee>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| slv-qns-a1noc-snoc { | |
| qcom,bus-dev = <0x1c9>; | |
| cell-id = <0x274e>; | |
| label = "slv-qns-a1noc-snoc"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x1ca>; | |
| qcom,connections = <0x236>; | |
| qcom,buswidth = <0x10>; | |
| }; | |
| bcm-sn2 { | |
| cell-id = <0x1b6c>; | |
| label = "SN2"; | |
| qcom,bcm-name = "SN2"; | |
| phandle = <0x252>; | |
| qcom,rscs = <0x1c6>; | |
| qcom,bcm-dev; | |
| }; | |
| mas-qnm-mnoc-hf_display { | |
| qcom,bus-dev = <0x230>; | |
| cell-id = <0x4e21>; | |
| label = "mas-qnm-mnoc-hf_display"; | |
| qcom,agg-ports = <0x02>; | |
| phandle = <0x25e>; | |
| qcom,qport = <0x04 0x05>; | |
| qcom,connections = <0x22f>; | |
| qcom,buswidth = <0x20>; | |
| }; | |
| slv-qns-llcc_display { | |
| qcom,bus-dev = <0x230>; | |
| cell-id = <0x5021>; | |
| qcom,bcms = <0x25b>; | |
| label = "slv-qns-llcc_display"; | |
| qcom,agg-ports = <0x04>; | |
| phandle = <0x22f>; | |
| qcom,connections = <0x25a>; | |
| qcom,buswidth = <0x10>; | |
| }; | |
| slv-qhs-llcc { | |
| qcom,bus-dev = <0x204>; | |
| cell-id = <0x2f8>; | |
| label = "slv-qhs-llcc"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x203>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| fab-mmss_noc_display { | |
| clocks; | |
| qcom,bypass-qos-prg; | |
| cell-id = <0x6592>; | |
| qcom,base-name = "mmss_noc-base"; | |
| label = "fab-mmss_noc_display"; | |
| phandle = <0x232>; | |
| qcom,bus-type = <0x01>; | |
| qcom,fab-dev; | |
| }; | |
| mas-qhm-qup2 { | |
| qcom,bus-dev = <0x1ce>; | |
| cell-id = <0x54>; | |
| qcom,bcms = <0x1cb>; | |
| label = "mas-qhm-qup2"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x3cb>; | |
| qcom,connections = <0x1cf>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| bcm-mm3_display { | |
| cell-id = <0x697d>; | |
| label = "MM3_DISPLAY"; | |
| qcom,bcm-name = "MM3"; | |
| phandle = <0x235>; | |
| qcom,rscs = <0x1c7>; | |
| qcom,bcm-dev; | |
| }; | |
| slv-qhs-tlmm-north { | |
| qcom,bus-dev = <0x1d6>; | |
| cell-id = <0x2db>; | |
| qcom,bcms = <0x1d7>; | |
| label = "slv-qhs-tlmm-north"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x1ff>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| rsc-apps { | |
| cell-id = <0x1f40>; | |
| label = "apps_rsc"; | |
| phandle = <0x1c6>; | |
| qcom,rsc-dev; | |
| qcom,req_state = <0x02>; | |
| }; | |
| fab-mem_noc { | |
| clocks; | |
| cell-id = <0x1808>; | |
| qcom,base-offset = <0x10000>; | |
| qcom,base-name = "mem_noc-base"; | |
| label = "fab-mem_noc"; | |
| phandle = <0x210>; | |
| qcom,bus-type = <0x01>; | |
| qcom,fab-dev; | |
| qcom,qos-off = <0x1000>; | |
| }; | |
| mas-qnm-snoc-sf { | |
| qcom,bus-dev = <0x210>; | |
| cell-id = <0x87>; | |
| label = "mas-qnm-snoc-sf"; | |
| qcom,prio = <0x00>; | |
| qcom,agg-ports = <0x01>; | |
| qcom,forwarding; | |
| phandle = <0x253>; | |
| qcom,qport = <0x09>; | |
| qcom,connections = <0x20d 0x20e>; | |
| qcom,buswidth = <0x10>; | |
| qcom,ap-owned; | |
| }; | |
| bcm-mc0_display { | |
| cell-id = <0x6978>; | |
| label = "MC0_DISPLAY"; | |
| qcom,bcm-name = "MC0"; | |
| phandle = <0x259>; | |
| qcom,rscs = <0x1c7>; | |
| qcom,bcm-dev; | |
| }; | |
| bcm-mm2 { | |
| cell-id = <0x1b65>; | |
| label = "MM2"; | |
| qcom,bcm-name = "MM2"; | |
| phandle = <0x24b>; | |
| qcom,rscs = <0x1c6>; | |
| qcom,bcm-dev; | |
| }; | |
| slv-qhs-pcie0-cfg { | |
| qcom,bus-dev = <0x1d6>; | |
| cell-id = <0x29b>; | |
| qcom,bcms = <0x1d7>; | |
| label = "slv-qhs-pcie0-cfg"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x1ea>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| bcm-sh4 { | |
| cell-id = <0x1b5f>; | |
| label = "SH4"; | |
| qcom,bcm-name = "SH4"; | |
| phandle = <0x3c2>; | |
| qcom,rscs = <0x1c6>; | |
| qcom,bcm-dev; | |
| }; | |
| mas-qxm-rot { | |
| qcom,bus-dev = <0x216>; | |
| qcom,node-qos-bcms = <0x1b64 0x00 0x01>; | |
| cell-id = <0x19>; | |
| qcom,bcms = <0x219>; | |
| label = "mas-qxm-rot"; | |
| qcom,prio = <0x00>; | |
| qcom,agg-ports = <0x01>; | |
| qcom,forwarding; | |
| phandle = <0x3e0>; | |
| qcom,qport = <0x05>; | |
| qcom,connections = <0x218>; | |
| qcom,buswidth = <0x20>; | |
| qcom,ap-owned; | |
| }; | |
| mas-qhm-tsif { | |
| qcom,bus-dev = <0x1c9>; | |
| cell-id = <0x52>; | |
| label = "mas-qhm-tsif"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x3c4>; | |
| qcom,connections = <0x1ca>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| slv-qhs-a1-noc-cfg { | |
| qcom,bus-dev = <0x1d6>; | |
| cell-id = <0x2af>; | |
| qcom,bcms = <0x1d7>; | |
| label = "slv-qhs-a1-noc-cfg"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x1f7>; | |
| qcom,connections = <0x239>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| slv-qns-pcie-a1noc-snoc { | |
| qcom,bus-dev = <0x1c9>; | |
| cell-id = <0x2754>; | |
| label = "slv-qns-pcie-a1noc-snoc"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x1cc>; | |
| qcom,connections = <0x237>; | |
| qcom,buswidth = <0x10>; | |
| }; | |
| bcm-alc { | |
| cell-id = <0x1b7e>; | |
| label = "ALC"; | |
| qcom,bcm-name = "ALC"; | |
| phandle = <0x22c>; | |
| qcom,rscs = <0x1c6>; | |
| qcom,bcm-dev; | |
| }; | |
| slv-srvc-cnoc { | |
| qcom,bus-dev = <0x1d6>; | |
| cell-id = <0x286>; | |
| qcom,bcms = <0x1d7>; | |
| label = "slv-srvc-cnoc"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x1f2>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| mas-qhm-mnoc-cfg { | |
| qcom,bus-dev = <0x216>; | |
| cell-id = <0x67>; | |
| label = "mas-qhm-mnoc-cfg"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x23c>; | |
| qcom,connections = <0x215>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| fab-system_noc { | |
| clocks; | |
| cell-id = <0x400>; | |
| qcom,base-offset = <0x9000>; | |
| qcom,base-name = "system_noc-base"; | |
| label = "fab-system_noc"; | |
| phandle = <0x21b>; | |
| qcom,bus-type = <0x01>; | |
| qcom,fab-dev; | |
| qcom,qos-off = <0x1000>; | |
| }; | |
| mas-qxm-crypto { | |
| qcom,bus-dev = <0x1ce>; | |
| cell-id = <0x7d>; | |
| qcom,bcms = <0x1d0>; | |
| label = "mas-qxm-crypto"; | |
| qcom,prio = <0x02>; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x3cc>; | |
| qcom,qport = <0x01>; | |
| qcom,connections = <0x1cf>; | |
| qcom,buswidth = <0x08>; | |
| qcom,ap-owned; | |
| }; | |
| bcm-sn0 { | |
| cell-id = <0x1b6a>; | |
| label = "SN0"; | |
| qcom,bcm-name = "SN0"; | |
| phandle = <0x254>; | |
| qcom,rscs = <0x1c6>; | |
| qcom,bcm-dev; | |
| }; | |
| slv-qhs-qdss-cfg { | |
| qcom,bus-dev = <0x1d6>; | |
| cell-id = <0x27b>; | |
| qcom,bcms = <0x1d7>; | |
| label = "slv-qhs-qdss-cfg"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x1e3>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| slv-qns-llcc { | |
| qcom,bus-dev = <0x210>; | |
| cell-id = <0x302>; | |
| qcom,bcms = <0x247>; | |
| label = "slv-qns-llcc"; | |
| qcom,agg-ports = <0x04>; | |
| phandle = <0x20e>; | |
| qcom,connections = <0x246>; | |
| qcom,buswidth = <0x10>; | |
| }; | |
| mas-qxm-mdp1 { | |
| qcom,bus-dev = <0x216>; | |
| qcom,node-qos-bcms = <0x1b64 0x00 0x01>; | |
| cell-id = <0x17>; | |
| qcom,bcms = <0x1d4>; | |
| label = "mas-qxm-mdp1"; | |
| qcom,prio = <0x00>; | |
| qcom,agg-ports = <0x01>; | |
| qcom,forwarding; | |
| phandle = <0x3df>; | |
| qcom,qport = <0x04>; | |
| qcom,connections = <0x217>; | |
| qcom,buswidth = <0x20>; | |
| qcom,ap-owned; | |
| }; | |
| bcm-mm0_display { | |
| cell-id = <0x697a>; | |
| label = "MM0_DISPLAY"; | |
| qcom,bcm-name = "MM0"; | |
| phandle = <0x25f>; | |
| qcom,rscs = <0x1c7>; | |
| qcom,bcm-dev; | |
| }; | |
| mas-xm-usb3-0 { | |
| qcom,bus-dev = <0x1ce>; | |
| cell-id = <0x3d>; | |
| label = "mas-xm-usb3-0"; | |
| qcom,prio = <0x02>; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x3d0>; | |
| qcom,qport = <0x0a>; | |
| qcom,connections = <0x1cf>; | |
| qcom,buswidth = <0x08>; | |
| qcom,ap-owned; | |
| qcom,node-qos-clks { | |
| clocks = <0x22 0x09>; | |
| clock-names = "clk-usb3-prim-axi-no-rate"; | |
| }; | |
| }; | |
| mas-qxm-mdp0_display { | |
| qcom,bus-dev = <0x232>; | |
| cell-id = <0x4e23>; | |
| qcom,bcms = <0x233>; | |
| label = "mas-qxm-mdp0_display"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x3e7>; | |
| qcom,qport = <0x03>; | |
| qcom,connections = <0x231>; | |
| qcom,buswidth = <0x20>; | |
| }; | |
| slv-qhs-qupv3-south { | |
| qcom,bus-dev = <0x1d6>; | |
| cell-id = <0x265>; | |
| qcom,bcms = <0x1d7>; | |
| label = "slv-qhs-qupv3-south"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x1fb>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| slv-ebi_display { | |
| qcom,bus-dev = <0x22e>; | |
| cell-id = <0x5020>; | |
| qcom,bcms = <0x259>; | |
| label = "slv-ebi_display"; | |
| qcom,agg-ports = <0x04>; | |
| phandle = <0x22d>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| mas-qnm-aggre2-noc { | |
| qcom,bus-dev = <0x21b>; | |
| cell-id = <0x2750>; | |
| qcom,bcms = <0x226>; | |
| label = "mas-qnm-aggre2-noc"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x238>; | |
| qcom,connections = <0x21c 0x21d 0x223 0x21e 0x21f 0x220 0x224 0x225 0x221>; | |
| qcom,buswidth = <0x10>; | |
| }; | |
| slv-qns-mem-noc-hf { | |
| qcom,bus-dev = <0x216>; | |
| cell-id = <0x305>; | |
| qcom,bcms = <0x24d>; | |
| label = "slv-qns-mem-noc-hf"; | |
| qcom,agg-ports = <0x02>; | |
| phandle = <0x217>; | |
| qcom,connections = <0x24c>; | |
| qcom,buswidth = <0x20>; | |
| }; | |
| slv-srvc-aggre1-noc { | |
| qcom,bus-dev = <0x1c9>; | |
| cell-id = <0x2e8>; | |
| qcom,bcms = <0x222>; | |
| label = "slv-srvc-aggre1-noc"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x1c8>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| bcm-mm0 { | |
| cell-id = <0x1b63>; | |
| label = "MM0"; | |
| qcom,bcm-name = "MM0"; | |
| phandle = <0x24d>; | |
| qcom,rscs = <0x1c6>; | |
| qcom,bcm-dev; | |
| }; | |
| mas-qnm-pcie-anoc { | |
| qcom,bus-dev = <0x21b>; | |
| cell-id = <0x8c>; | |
| qcom,bcms = <0x229>; | |
| label = "mas-qnm-pcie-anoc"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x237>; | |
| qcom,connections = <0x21e 0x21f 0x220 0x21d 0x221>; | |
| qcom,buswidth = <0x10>; | |
| }; | |
| bcm-cn0 { | |
| cell-id = <0x1b7c>; | |
| label = "CN0"; | |
| qcom,bcm-name = "CN0"; | |
| phandle = <0x1d7>; | |
| qcom,rscs = <0x1c6>; | |
| qcom,bcm-dev; | |
| }; | |
| slv-qhs-phy-refgen-south { | |
| qcom,bus-dev = <0x1d6>; | |
| cell-id = <0x2f0>; | |
| qcom,bcms = <0x1d7>; | |
| label = "slv-qhs-phy-refgen-south"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x1e8>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| bcm-sn9 { | |
| cell-id = <0x1b73>; | |
| label = "SN9"; | |
| qcom,bcm-name = "SN9"; | |
| phandle = <0x222>; | |
| qcom,rscs = <0x1c6>; | |
| qcom,bcm-dev; | |
| }; | |
| slv-qhs-ufs-mem-cfg { | |
| qcom,bus-dev = <0x1d6>; | |
| cell-id = <0x2f5>; | |
| qcom,bcms = <0x1d7>; | |
| label = "slv-qhs-ufs-mem-cfg"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x1de>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| bcm-sh2 { | |
| cell-id = <0x1b5d>; | |
| label = "SH2"; | |
| qcom,bcm-name = "SH2"; | |
| phandle = <0x249>; | |
| qcom,rscs = <0x1c6>; | |
| qcom,bcm-dev; | |
| }; | |
| slv-qhs-clk-ctl { | |
| qcom,bus-dev = <0x1d6>; | |
| cell-id = <0x26c>; | |
| qcom,bcms = <0x1d7>; | |
| label = "slv-qhs-clk-ctl"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x200>; | |
| qcom,buswidth = <0x04>; | |
| }; | |
| fab-aggre1_noc { | |
| clocks; | |
| cell-id = <0x1802>; | |
| qcom,base-offset = <0x4000>; | |
| qcom,base-name = "aggre1_noc-base"; | |
| label = "fab-aggre1_noc"; | |
| phandle = <0x1c9>; | |
| qcom,bus-type = <0x01>; | |
| qcom,fab-dev; | |
| qcom,qos-off = <0x1000>; | |
| }; | |
| bcm-sn14 { | |
| cell-id = <0x1b78>; | |
| label = "SN14"; | |
| qcom,bcm-name = "SN14"; | |
| phandle = <0x229>; | |
| qcom,rscs = <0x1c6>; | |
| qcom,bcm-dev; | |
| }; | |
| slv-qns-cnoc { | |
| qcom,bus-dev = <0x21b>; | |
| cell-id = <0x2734>; | |
| qcom,bcms = <0x250>; | |
| label = "slv-qns-cnoc"; | |
| qcom,agg-ports = <0x01>; | |
| phandle = <0x220>; | |
| qcom,connections = <0x24f>; | |
| qcom,buswidth = <0x08>; | |
| }; | |
| }; | |
| qcom,msm-pcm-loopback { | |
| compatible = "qcom,msm-pcm-loopback"; | |
| phandle = <0x276>; | |
| }; | |
| qcom,vidc@aa00000 { | |
| cache-slices = <0x2d 0x02 0x2d 0x03>; | |
| compatible = "qcom,msm-vidc\0qcom,sdm845-vidc"; | |
| clocks = <0xa4 0x0b 0xa4 0x08 0xa4 0x0a 0xa4 0x05 0xa4 0x04 0xa4 0x07 0xa4 0x06>; | |
| qcom,proxy-clock-names = "core_clk\0iface_clk\0bus_clk\0core0_clk\0core0_bus_clk\0core1_clk\0core1_bus_clk"; | |
| clock-names = "core_clk\0iface_clk\0bus_clk\0core0_clk\0core0_bus_clk\0core1_clk\0core1_bus_clk"; | |
| venus-core1-supply = <0x261>; | |
| venus-supply = <0xc0>; | |
| status = "ok"; | |
| qcom,allowed-clock-rates = <0x5f5e100 0xbebc200 0x13ab6680 0x18148d00 0x1a76e700 0x1fc4ef40>; | |
| interrupts = <0x00 0xae 0x04>; | |
| venus-core0-supply = <0x260>; | |
| phandle = <0x3ea>; | |
| qcom,clock-configs = <0x01 0x00 0x00 0x01 0x00 0x01 0x00>; | |
| cache-slice-names = "vidsc0\0vidsc1"; | |
| reg = <0xaa00000 0x200000>; | |
| bus_cnoc { | |
| compatible = "qcom,msm-vidc,bus"; | |
| qcom,bus-range-kbps = <0x3e8 0x3e8>; | |
| label = "cnoc"; | |
| qcom,bus-slave = <0x254>; | |
| qcom,bus-master = <0x01>; | |
| qcom,bus-governor = "performance"; | |
| }; | |
| venus_bus_llcc { | |
| compatible = "qcom,msm-vidc,bus"; | |
| qcom,bus-range-kbps = <0x4268 0x33b260>; | |
| label = "venus-llcc"; | |
| qcom,bus-slave = <0x302>; | |
| qcom,bus-master = <0x3f>; | |
| qcom,bus-governor = "msm-vidc-llcc"; | |
| }; | |
| secure_non_pixel_cb { | |
| compatible = "qcom,msm-vidc,context-bank"; | |
| buffer-types = <0x480>; | |
| label = "venus_sec_non_pixel"; | |
| virtual-addr-pool = <0x1000000 0x24800000>; | |
| iommus = <0x29 0x10a4 0x08 0x29 0x10b4 0x00>; | |
| qcom,secure-context-bank; | |
| }; | |
| secure_bitstream_cb { | |
| compatible = "qcom,msm-vidc,context-bank"; | |
| buffer-types = <0x241>; | |
| label = "venus_sec_bitstream"; | |
| virtual-addr-pool = <0x4b000000 0x25800000>; | |
| iommus = <0x29 0x10a1 0x08 0x29 0x10a5 0x08>; | |
| qcom,secure-context-bank; | |
| }; | |
| venus_bus_ddr { | |
| compatible = "qcom,msm-vidc,bus"; | |
| qcom,bus-range-kbps = <0x3e8 0x33b260>; | |
| label = "venus-ddr"; | |
| qcom,bus-slave = <0x200>; | |
| qcom,bus-master = <0x81>; | |
| qcom,bus-governor = "msm-vidc-ddr"; | |
| }; | |
| non_secure_cb { | |
| compatible = "qcom,msm-vidc,context-bank"; | |
| buffer-types = <0xfff>; | |
| label = "venus_ns"; | |
| virtual-addr-pool = <0x70800000 0x6f800000>; | |
| iommus = <0x29 0x10a0 0x08 0x29 0x10b0 0x00>; | |
| }; | |
| arm9_bus_ddr { | |
| compatible = "qcom,msm-vidc,bus"; | |
| qcom,bus-range-kbps = <0x3e8 0x3e8>; | |
| label = "venus-arm9-ddr"; | |
| qcom,bus-slave = <0x200>; | |
| qcom,bus-master = <0x3f>; | |
| qcom,bus-governor = "performance"; | |
| }; | |
| secure_pixel_cb { | |
| compatible = "qcom,msm-vidc,context-bank"; | |
| buffer-types = <0x106>; | |
| label = "venus_sec_pixel"; | |
| virtual-addr-pool = <0x25800000 0x25800000>; | |
| iommus = <0x29 0x10a3 0x08>; | |
| qcom,secure-context-bank; | |
| }; | |
| }; | |
| rpmh-regulator-ldoa9 { | |
| qcom,supported-modes = <0x02 0x04>; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "ldoa9"; | |
| mboxes = <0x8a 0x00>; | |
| qcom,regulator-type = "pmic4-ldo"; | |
| qcom,mode-threshold-currents = <0x00 0x01>; | |
| regulator-l9 { | |
| qcom,init-mode = <0x02>; | |
| phandle = <0x33e>; | |
| qcom,init-voltage = <0x1a0040>; | |
| regulator-min-microvolt = <0x1a0040>; | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x2cad80>; | |
| regulator-name = "pm8998_l9"; | |
| }; | |
| }; | |
| qcom,msm-pcm-routing { | |
| compatible = "qcom,msm-pcm-routing"; | |
| phandle = <0x27b>; | |
| }; | |
| qcom,smp2pgpio-smp2p-3-out { | |
| compatible = "qcom,smp2pgpio"; | |
| gpio-controller; | |
| #interrupt-cells = <0x02>; | |
| phandle = <0x1b7>; | |
| qcom,entry-name = "smp2p"; | |
| #gpio-cells = <0x02>; | |
| qcom,remote-pid = <0x03>; | |
| interrupt-controller; | |
| }; | |
| funnel@6845000 { | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "funnel-base"; | |
| coresight-name = "coresight-funnel-lpass"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x364>; | |
| arm,primecell-periphid = <0x3b908>; | |
| reg = <0x6845000 0x1000>; | |
| ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@1 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x15a>; | |
| phandle = <0x15d>; | |
| slave-mode; | |
| }; | |
| }; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x159>; | |
| phandle = <0x14d>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| cti@7120000 { | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti-cpu1"; | |
| clock-names = "apb_pclk"; | |
| cpu = <0x12>; | |
| phandle = <0x397>; | |
| arm,primecell-periphid = <0x3b966>; | |
| reg = <0x7120000 0x1000>; | |
| }; | |
| qcom,gpucc@5090000 { | |
| compatible = "qcom,gpucc-sdm845-v2\0syscon"; | |
| #reset-cells = <0x01>; | |
| qcom,gpu_cc_gmu_clk_src-opp-handle = <0x9c>; | |
| reg-names = "cc_base"; | |
| vdd_cx-supply = <0x1b>; | |
| vdd_mx-supply = <0x8c>; | |
| #clock-cells = <0x01>; | |
| phandle = <0xa6>; | |
| reg = <0x5090000 0x9000>; | |
| }; | |
| qcom,turing@8300000 { | |
| qcom,proxy-timeout-ms = <0x2710>; | |
| compatible = "qcom,pil-tz-generic"; | |
| qcom,vdd_cx-uV-uA = <0x181 0x186a0>; | |
| clocks = <0x21 0x00>; | |
| qcom,proxy-clock-names = "xo"; | |
| qcom,firmware-name = "cdsp"; | |
| qcom,gpio-proxy-unvote = <0xbd 0x02 0x00>; | |
| qcom,gpio-stop-ack = <0xbd 0x03 0x00>; | |
| clock-names = "xo"; | |
| qcom,gpio-err-ready = <0xbd 0x01 0x00>; | |
| qcom,smem-id = <0x259>; | |
| qcom,pas-id = <0x12>; | |
| qcom,gpio-err-fatal = <0xbd 0x00 0x00>; | |
| vdd_cx-supply = <0x1b>; | |
| status = "ok"; | |
| interrupts = <0x00 0x242 0x01>; | |
| mbox-names = "cdsp-pil"; | |
| memory-region = <0xbc>; | |
| mboxes = <0x80 0x00>; | |
| qcom,proxy-reg-names = "vdd_cx"; | |
| qcom,ssctl-instance-id = <0x17>; | |
| reg = <0x8300000 0x100000>; | |
| qcom,signal-aop; | |
| qcom,gpio-force-stop = <0xbe 0x00 0x00>; | |
| qcom,sysmon-id = <0x07>; | |
| }; | |
| tpdm@7830000 { | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "tpdm-base"; | |
| coresight-name = "coresight-tpdm-olc"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x37b>; | |
| arm,primecell-periphid = <0x3b968>; | |
| reg = <0x7830000 0x1000>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x17a>; | |
| phandle = <0x179>; | |
| }; | |
| }; | |
| }; | |
| qcom,qsee_ipc_irq_bridge { | |
| compatible = "qcom,qsee-ipc-irq-bridge"; | |
| qcom,qsee-ipc-irq-spss { | |
| qcom,rx-irq-clr = <0x1888008 0x04>; | |
| interrupts = <0x00 0x15d 0x04>; | |
| label = "spss"; | |
| qcom,dev-name = "qsee_ipc_irq_spss"; | |
| qcom,rx-irq-clr-mask = <0x01>; | |
| }; | |
| }; | |
| qcom,msm-dai-tdm-tert-tx { | |
| compatible = "qcom,msm-dai-tdm"; | |
| qcom,msm-cpudai-tdm-group-port-id = <0x9021>; | |
| qcom,msm-cpudai-tdm-clk-internal = <0x01>; | |
| qcom,msm-cpudai-tdm-sync-mode = <0x01>; | |
| qcom,msm-cpudai-tdm-clk-rate = <0x177000>; | |
| qcom,msm-cpudai-tdm-data-out = <0x00>; | |
| qcom,msm-cpudai-tdm-data-delay = <0x01>; | |
| qcom,msm-cpudai-tdm-group-id = <0x9121>; | |
| qcom,msm-cpudai-tdm-invert-sync = <0x01>; | |
| qcom,msm-cpudai-tdm-group-num-ports = <0x01>; | |
| qcom,msm-cpudai-tdm-sync-src = <0x01>; | |
| qcom,msm-dai-q6-tdm-tert-tx-0 { | |
| compatible = "qcom,msm-dai-q6-tdm"; | |
| qcom,msm-cpudai-tdm-dev-id = <0x9021>; | |
| phandle = <0x2a7>; | |
| qcom,msm-cpudai-tdm-data-align = <0x00>; | |
| }; | |
| }; | |
| qcom,rpm-stats@c300000 { | |
| compatible = "qcom,rpm-stats"; | |
| reg-names = "phys_addr_base\0offset_addr"; | |
| reg = <0xc300000 0x1000 0xc3f0004 0x04>; | |
| }; | |
| cti@69e5000 { | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti-ddr_dl_1_cti1"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x382>; | |
| arm,primecell-periphid = <0x3b966>; | |
| reg = <0x69e5000 0x1000>; | |
| }; | |
| funnel@7800000 { | |
| compatible = "arm,primecell"; | |
| clocks = <0x7e 0x00>; | |
| reg-names = "funnel-base"; | |
| coresight-name = "coresight-funnel-apss"; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x3aa>; | |
| arm,primecell-periphid = <0x3b908>; | |
| reg = <0x7800000 0x1000>; | |
| ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@7 { | |
| reg = <0x06>; | |
| endpoint { | |
| remote-endpoint = <0x1a1>; | |
| phandle = <0x198>; | |
| slave-mode; | |
| }; | |
| }; | |
| port@5 { | |
| reg = <0x04>; | |
| endpoint { | |
| remote-endpoint = <0x19f>; | |
| phandle = <0x196>; | |
| slave-mode; | |
| }; | |
| }; | |
| port@3 { | |
| reg = <0x02>; | |
| endpoint { | |
| remote-endpoint = <0x19d>; | |
| phandle = <0x194>; | |
| slave-mode; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x19b>; | |
| phandle = <0x192>; | |
| slave-mode; | |
| }; | |
| }; | |
| port@8 { | |
| reg = <0x07>; | |
| endpoint { | |
| remote-endpoint = <0x1a2>; | |
| phandle = <0x199>; | |
| slave-mode; | |
| }; | |
| }; | |
| port@6 { | |
| reg = <0x05>; | |
| endpoint { | |
| remote-endpoint = <0x1a0>; | |
| phandle = <0x197>; | |
| slave-mode; | |
| }; | |
| }; | |
| port@4 { | |
| reg = <0x03>; | |
| endpoint { | |
| remote-endpoint = <0x19e>; | |
| phandle = <0x195>; | |
| slave-mode; | |
| }; | |
| }; | |
| port@2 { | |
| reg = <0x01>; | |
| endpoint { | |
| remote-endpoint = <0x19c>; | |
| phandle = <0x193>; | |
| slave-mode; | |
| }; | |
| }; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x19a>; | |
| phandle = <0x18d>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| aop-msg-client { | |
| compatible = "qcom,debugfs-qmp-client"; | |
| mbox-names = "aop"; | |
| mboxes = <0x80 0x00>; | |
| }; | |
| syscon@0x5091508 { | |
| compatible = "syscon"; | |
| phandle = <0x1e>; | |
| reg = <0x5091508 0x04>; | |
| }; | |
| qcom,glink-fifo-config-wdsp { | |
| qcom,in-write-idx-reg = <0x12010>; | |
| compatible = "qcom,glink-fifo-config"; | |
| phandle = <0xdf>; | |
| qcom,out-read-idx-reg = <0x12000>; | |
| qcom,out-write-idx-reg = <0x12004>; | |
| qcom,in-read-idx-reg = <0x1200c>; | |
| }; | |
| msm_cdc_pinctrl@64 { | |
| compatible = "qcom,msm-cdc-pinctrl"; | |
| pinctrl-1 = <0x408>; | |
| qcom,cdc-rst-n-gpio = <0x34 0x40 0x00>; | |
| status = "okay"; | |
| phandle = <0x539>; | |
| pinctrl-0 = <0x409>; | |
| pinctrl-names = "aud_active\0aud_sleep"; | |
| }; | |
| rpmh-regulator-ldoa25 { | |
| qcom,supported-modes = <0x02 0x04>; | |
| compatible = "qcom,rpmh-vrm-regulator"; | |
| qcom,resource-name = "ldoa25"; | |
| mboxes = <0x8a 0x00>; | |
| qcom,regulator-type = "pmic4-ldo"; | |
| qcom,mode-threshold-currents = <0x00 0x2710>; | |
| regulator-l25 { | |
| qcom,init-mode = <0x02>; | |
| phandle = <0xee>; | |
| qcom,init-voltage = <0x2dc6c0>; | |
| regulator-min-microvolt = <0x2dc6c0>; | |
| qcom,set = <0x03>; | |
| regulator-max-microvolt = <0x328980>; | |
| regulator-name = "pm8998_l25"; | |
| }; | |
| }; | |
| qcom,msm-tert-auxpcm { | |
| qcom,msm-auxpcm-interface = "tertiary"; | |
| compatible = "qcom,msm-auxpcm-dev"; | |
| qcom,msm-cpudai-auxpcm-sync = <0x01 0x01>; | |
| qcom,msm-cpudai-auxpcm-frame = <0x05 0x04>; | |
| qcom,msm-cpudai-auxpcm-quant = <0x02 0x02>; | |
| qcom,msm-cpudai-afe-clk-ver = <0x02>; | |
| qcom,msm-cpudai-auxpcm-slot-mapping = <0x01 0x01>; | |
| qcom,msm-cpudai-auxpcm-num-slots = <0x01 0x01>; | |
| qcom,msm-cpudai-auxpcm-data = <0x00 0x00>; | |
| qcom,msm-cpudai-auxpcm-pcm-clk-rate = <0x1f4000 0x1f4000>; | |
| phandle = <0x286>; | |
| qcom,msm-cpudai-auxpcm-mode = <0x00 0x00>; | |
| }; | |
| qcom,jpegdma@0xac52000 { | |
| clock-rates = <0x00 0x00 0x00 0x00 0x00 0x23c34600 0x00>; | |
| compatible = "qcom,cam_jpeg_dma"; | |
| clocks = <0x22 0x0c 0x22 0x0d 0xa5 0x55 0xa5 0x09 0xa5 0x06 0xa5 0x3f 0xa5 0x3e>; | |
| reg-names = "jpegdma_hw"; | |
| clock-names = "camera_ahb\0camera_axi\0soc_ahb_clk\0cpas_ahb_clk\0camnoc_axi_clk\0jpegdma_clk_src\0jpegdma_clk"; | |
| regulator-names = "camss-vdd"; | |
| status = "ok"; | |
| interrupts = <0x00 0x1db 0x00>; | |
| camss-vdd-supply = <0x1bb>; | |
| phandle = <0x3bf>; | |
| reg = <0xac52000 0x4000>; | |
| src-clock-name = "jpegdma_clk_src"; | |
| interrupt-names = "jpegdma"; | |
| reg-cam-base = <0x52000>; | |
| cell-index = <0x00>; | |
| clock-cntl-level = "nominal"; | |
| }; | |
| }; | |
| energy-costs { | |
| compatible = "sched-energy"; | |
| phandle = <0x4d4>; | |
| cluster-cost0 { | |
| idle-cost-data = <0x04 0x03 0x02 0x01>; | |
| phandle = <0x05>; | |
| busy-cost-data = <0x493e0 0x03 0x62700 0x04 0x75300 0x04 0x8ca00 0x04 0x9f600 0x05 0xb6d00 0x05 0xc9900 0x06 0xdc500 0x07 0xef100 0x07 0x101d00 0x08 0x114900 0x09 0x12c000 0x09 0x143700 0x0a 0x15ae00 0x0b 0x172500 0x0c 0x189c00 0x0d 0x19c800 0x0f 0x1af400 0x11>; | |
| }; | |
| core-cost0 { | |
| idle-cost-data = <0x0a 0x08 0x06 0x04>; | |
| phandle = <0x04>; | |
| busy-cost-data = <0x493e0 0x0c 0x62700 0x11 0x75300 0x15 0x8ca00 0x1b 0x9f600 0x1f 0xb6d00 0x25 0xc9900 0x2a 0xdc500 0x2f 0xef100 0x34 0x101d00 0x39 0x114900 0x3e 0x12c000 0x46 0x143700 0x4e 0x15ae00 0x59 0x172500 0x67 0x189c00 0x7a 0x19c800 0x8d 0x1af400 0xa0>; | |
| }; | |
| cluster-cost1 { | |
| idle-cost-data = <0x04 0x03 0x02 0x01>; | |
| phandle = <0x0d>; | |
| busy-cost-data = <0x493e0 0x18 0x62700 0x18 0x75300 0x19 0x8ca00 0x19 0x9f600 0x1a 0xb6d00 0x1b 0xc9900 0x1c 0xdc500 0x1d 0xef100 0x1e 0x101d00 0x20 0x114900 0x22 0x127500 0x25 0x13a100 0x28 0x14cd00 0x2d 0x164400 0x32 0x177000 0x39 0x189c00 0x40 0x19c800 0x4a 0x1af400 0x54 0x1c2000 0x60 0x1d4c00 0x6a 0x1e7800 0x71 0x1fef00 0x78 0x211b00 0x7d 0x224700 0x7f 0x237300 0x82 0x249f00 0x87 0x25cb00 0x8c 0x26f700 0x91 0x286e00 0x96 0x29e500 0x9b 0x2a3000 0xa0 0x2a7b00 0xa5 0x2ac600 0xaa 0x2b5c00 0xb4 0x2d1e00 0xbe>; | |
| }; | |
| core-cost1 { | |
| idle-cost-data = <0x64 0x50 0x3c 0x28>; | |
| phandle = <0x0c>; | |
| busy-cost-data = <0x493e0 0xbd 0x62700 0x20b 0x75300 0x2fb 0x8ca00 0x41c 0x9f600 0x4f9 0xb6d00 0x600 0xc9900 0x6c8 0xdc500 0x786 0xef100 0x83c 0x101d00 0x8ec 0x114900 0x998 0x127500 0xa44 0x13a100 0xaf4 0x14cd00 0xbb0 0x164400 0xcb7 0x177000 0xdab 0x189c00 0xeca 0x19c800 0x1020 0x1af400 0x11b7 0x1c2000 0x139b 0x1d4c00 0x15cf 0x1e7800 0x1852 0x1fef00 0x1bd0 0x211b00 0x1ec4 0x224700 0x21b4 0x237300 0x2480 0x249f00 0x272e 0x25cb00 0x2a36 0x26f700 0x2f0d 0x286e00 0x3d46 0x29e500 0x63f2 0x2a3000 0x7530 0x2a7b00 0x88b8 0x2ac600 0x9c40 0x2b5c00 0xc350 0x2d1e00 0xea60>; | |
| }; | |
| }; | |
| psci { | |
| compatible = "arm,psci-1.0"; | |
| method = "smc"; | |
| }; | |
| firmware { | |
| phandle = <0x4d6>; | |
| android { | |
| compatible = "android,firmware"; | |
| fstab { | |
| compatible = "android,fstab"; | |
| vendor { | |
| compatible = "android,vendor"; | |
| dev = "/dev/block/platform/soc/1d84000.ufshc/by-name/vendor"; | |
| type = "ext4"; | |
| status = "ok"; | |
| fsmgr_flags = "wait,slotselect,avb"; | |
| mnt_flags = "ro,barrier=1,discard"; | |
| }; | |
| }; | |
| vbmeta { | |
| compatible = "android,vbmeta"; | |
| parts = "vbmeta,boot,system,vendor,dtbo"; | |
| }; | |
| }; | |
| }; | |
| aliases { | |
| i2c3 = "/soc/i2c@890000"; | |
| i2c1 = "/soc/i2c@88c000"; | |
| sdhc2 = "/soc/sdhci@8804000"; | |
| spi0 = "/soc/spi@a80000"; | |
| pci-domain1 = "/soc/qcom,pcie@0x1c08000"; | |
| i2c2 = "/soc/i2c@894000"; | |
| hsuart0 = "/soc/qcom,qup_uart@0x898000"; | |
| ufshc1 = "/soc/ufshc@1d84000"; | |
| i2c0 = "/soc/i2c@a88000"; | |
| pci-domain0 = "/soc/qcom,pcie@0x1c00000"; | |
| serial0 = "/soc/qcom,qup_uart@0xa84000"; | |
| }; | |
| chosen { | |
| bootargs = "rcupdate.rcu_expedited=1 console=ttyMSM0,115200n8 earlycon=msm_geni_serial,0xA84000 androidboot.hardware=qcom androidboot.console=ttyMSM0 video=vfb:640x400,bpp=32,memsize=3072000 msm_rtb.filter=0x237 ehci-hcd.park=3 lpm_levels.sleep_disabled=1 service_locator.enable=1 swiotlb=2048 androidboot.configfs=true loop.max_part=7 androidboot.usbcontroller=a600000.dwc3 buildvariant=user androidboot.verifiedbootstate=orange androidboot.keymaster=1 dm=\"1 vroot none ro 1,0 9288120 verity 1 PARTUUID=b7c55260-8e93-4826-0372-3ff6799e4a58 PARTUUID=b7c55260-8e93-4826-0372-3ff6799e4a58 4096 4096 1161015 1161015 sha1 f0b683d562b70b99635e3e5837618bd7f9669291 cf232e47b2daa98a4f1998d763361644c27aae89 10 restart_on_corruption ignore_zero_blocks use_fec_from_device PARTUUID=b7c55260-8e93-4826-0372-3ff6799e4a58 fec_roots 2 fec_blocks 1170158 fec_start 1170158\" root=/dev/dm-0 androidboot.vbmeta.device=PARTUUID=be58868a-cb9a-690a-946f-788ba09f1197 androidboot.vbmeta.avb_version=1.0 androidboot.vbmeta.device_state=unlocked androidboot.vbmeta.hash_alg=sha256 androidboot.vbmeta.size=5760 androidboot.vbmeta.digest=4399cd852dd2c424c1e43b6dc00b5fede5838eca837c98bce87374046538bf8c androidboot.vbmeta.invalidate_on_error=yes androidboot.veritymode=enforcing androidboot.bootdevice=1d84000.ufshc androidboot.serialno=9f487767 androidboot.baseband=msm msm_drm.dsi_display0=dsi_innolux_td4328_1080p_cmd_display: androidboot.slot_suffix=_a skip_initramfs rootwait ro init=/init androidboot.dtbo_idx=22 androidboot.dtb_idx=7"; | |
| linux,initrd-start = <0x00 0x84f60000>; | |
| linux,initrd-end = <0x00 0x855feabc>; | |
| kaslr-seed = <0x00 0x00>; | |
| }; | |
| memory { | |
| device_type = "memory"; | |
| reg = <0x00 0x80000000 0x01 0x00 0x01 0x80000000 0x00 0xfc7a0000>; | |
| ddr_device_type = <0x07>; | |
| }; | |
| cpus { | |
| #address-cells = <0x02>; | |
| #size-cells = <0x00>; | |
| cpu@300 { | |
| qcom,lmh-dcvs = <0x02>; | |
| compatible = "arm,armv8"; | |
| cpu-release-addr = <0x00 0x90000000>; | |
| device_type = "cpu"; | |
| sched-energy-costs = <0x04 0x05>; | |
| next-level-cache = <0x09>; | |
| enable-method = "psci"; | |
| phandle = <0x14>; | |
| reg = <0x00 0x300>; | |
| cache-size = <0x8000>; | |
| #cooling-cells = <0x02>; | |
| efficiency = <0x400>; | |
| l2-cache { | |
| compatible = "arm,arch-cache"; | |
| cache-level = <0x02>; | |
| next-level-cache = <0x06>; | |
| phandle = <0x09>; | |
| cache-size = <0x20000>; | |
| }; | |
| l1-dcache { | |
| compatible = "arm,arch-cache"; | |
| phandle = <0xcd>; | |
| qcom,dump-size = <0xa000>; | |
| }; | |
| l1-tlb { | |
| phandle = <0xd9>; | |
| qcom,dump-size = <0x6000>; | |
| }; | |
| l1-icache { | |
| compatible = "arm,arch-cache"; | |
| phandle = <0xc5>; | |
| qcom,dump-size = <0x12000>; | |
| }; | |
| }; | |
| cpu@600 { | |
| qcom,lmh-dcvs = <0x0a>; | |
| compatible = "arm,armv8"; | |
| cpu-release-addr = <0x00 0x90000000>; | |
| device_type = "cpu"; | |
| sched-energy-costs = <0x0c 0x0d>; | |
| next-level-cache = <0x0f>; | |
| enable-method = "psci"; | |
| phandle = <0x17>; | |
| reg = <0x00 0x600>; | |
| cache-size = <0x20000>; | |
| #cooling-cells = <0x02>; | |
| efficiency = <0x6cc>; | |
| l2-cache { | |
| compatible = "arm,arch-cache"; | |
| cache-level = <0x02>; | |
| next-level-cache = <0x06>; | |
| phandle = <0x0f>; | |
| cache-size = <0x40000>; | |
| }; | |
| l1-dcache { | |
| compatible = "arm,arch-cache"; | |
| phandle = <0xd0>; | |
| qcom,dump-size = <0x14000>; | |
| }; | |
| l1-tlb { | |
| phandle = <0xdc>; | |
| qcom,dump-size = <0x6800>; | |
| }; | |
| l1-icache { | |
| compatible = "arm,arch-cache"; | |
| phandle = <0xc8>; | |
| qcom,dump-size = <0x24000>; | |
| }; | |
| }; | |
| cpu-map { | |
| cluster1 { | |
| core0 { | |
| cpu = <0x15>; | |
| }; | |
| core3 { | |
| cpu = <0x18>; | |
| }; | |
| core1 { | |
| cpu = <0x16>; | |
| }; | |
| core2 { | |
| cpu = <0x17>; | |
| }; | |
| }; | |
| cluster0 { | |
| core0 { | |
| cpu = <0x11>; | |
| }; | |
| core3 { | |
| cpu = <0x14>; | |
| }; | |
| core1 { | |
| cpu = <0x12>; | |
| }; | |
| core2 { | |
| cpu = <0x13>; | |
| }; | |
| }; | |
| }; | |
| cpu@200 { | |
| qcom,lmh-dcvs = <0x02>; | |
| compatible = "arm,armv8"; | |
| cpu-release-addr = <0x00 0x90000000>; | |
| device_type = "cpu"; | |
| sched-energy-costs = <0x04 0x05>; | |
| next-level-cache = <0x08>; | |
| enable-method = "psci"; | |
| phandle = <0x13>; | |
| reg = <0x00 0x200>; | |
| cache-size = <0x8000>; | |
| #cooling-cells = <0x02>; | |
| efficiency = <0x400>; | |
| l2-cache { | |
| compatible = "arm,arch-cache"; | |
| cache-level = <0x02>; | |
| next-level-cache = <0x06>; | |
| phandle = <0x08>; | |
| cache-size = <0x20000>; | |
| }; | |
| l1-dcache { | |
| compatible = "arm,arch-cache"; | |
| phandle = <0xcc>; | |
| qcom,dump-size = <0xa000>; | |
| }; | |
| l1-tlb { | |
| phandle = <0xd8>; | |
| qcom,dump-size = <0x6000>; | |
| }; | |
| l1-icache { | |
| compatible = "arm,arch-cache"; | |
| phandle = <0xc4>; | |
| qcom,dump-size = <0x12000>; | |
| }; | |
| }; | |
| cpu@500 { | |
| qcom,lmh-dcvs = <0x0a>; | |
| compatible = "arm,armv8"; | |
| cpu-release-addr = <0x00 0x90000000>; | |
| device_type = "cpu"; | |
| sched-energy-costs = <0x0c 0x0d>; | |
| next-level-cache = <0x0e>; | |
| enable-method = "psci"; | |
| phandle = <0x16>; | |
| reg = <0x00 0x500>; | |
| cache-size = <0x20000>; | |
| #cooling-cells = <0x02>; | |
| efficiency = <0x6cc>; | |
| l2-cache { | |
| compatible = "arm,arch-cache"; | |
| cache-level = <0x02>; | |
| next-level-cache = <0x06>; | |
| phandle = <0x0e>; | |
| cache-size = <0x40000>; | |
| }; | |
| l1-dcache { | |
| compatible = "arm,arch-cache"; | |
| phandle = <0xcf>; | |
| qcom,dump-size = <0x14000>; | |
| }; | |
| l1-tlb { | |
| phandle = <0xdb>; | |
| qcom,dump-size = <0x6800>; | |
| }; | |
| l1-icache { | |
| compatible = "arm,arch-cache"; | |
| phandle = <0xc7>; | |
| qcom,dump-size = <0x24000>; | |
| }; | |
| }; | |
| cpu@0 { | |
| qcom,lmh-dcvs = <0x02>; | |
| compatible = "arm,armv8"; | |
| cpu-release-addr = <0x00 0x90000000>; | |
| device_type = "cpu"; | |
| sched-energy-costs = <0x04 0x05>; | |
| next-level-cache = <0x03>; | |
| enable-method = "psci"; | |
| phandle = <0x11>; | |
| reg = <0x00 0x00>; | |
| cache-size = <0x8000>; | |
| #cooling-cells = <0x02>; | |
| efficiency = <0x400>; | |
| l2-cache { | |
| compatible = "arm,arch-cache"; | |
| cache-level = <0x02>; | |
| next-level-cache = <0x06>; | |
| phandle = <0x03>; | |
| cache-size = <0x20000>; | |
| l3-cache { | |
| compatible = "arm,arch-cache"; | |
| cache-level = <0x03>; | |
| phandle = <0x06>; | |
| cache-size = <0x200000>; | |
| }; | |
| }; | |
| l1-dcache { | |
| compatible = "arm,arch-cache"; | |
| phandle = <0xca>; | |
| qcom,dump-size = <0xa000>; | |
| }; | |
| l1-tlb { | |
| phandle = <0xd6>; | |
| qcom,dump-size = <0x6000>; | |
| }; | |
| l1-icache { | |
| compatible = "arm,arch-cache"; | |
| phandle = <0xc2>; | |
| qcom,dump-size = <0x12000>; | |
| }; | |
| }; | |
| cpu@100 { | |
| qcom,lmh-dcvs = <0x02>; | |
| compatible = "arm,armv8"; | |
| cpu-release-addr = <0x00 0x90000000>; | |
| device_type = "cpu"; | |
| sched-energy-costs = <0x04 0x05>; | |
| next-level-cache = <0x07>; | |
| enable-method = "psci"; | |
| phandle = <0x12>; | |
| reg = <0x00 0x100>; | |
| cache-size = <0x8000>; | |
| #cooling-cells = <0x02>; | |
| efficiency = <0x400>; | |
| l2-cache { | |
| compatible = "arm,arch-cache"; | |
| cache-level = <0x02>; | |
| next-level-cache = <0x06>; | |
| phandle = <0x07>; | |
| cache-size = <0x20000>; | |
| }; | |
| l1-dcache { | |
| compatible = "arm,arch-cache"; | |
| phandle = <0xcb>; | |
| qcom,dump-size = <0xa000>; | |
| }; | |
| l1-tlb { | |
| phandle = <0xd7>; | |
| qcom,dump-size = <0x6000>; | |
| }; | |
| l1-icache { | |
| compatible = "arm,arch-cache"; | |
| phandle = <0xc3>; | |
| qcom,dump-size = <0x12000>; | |
| }; | |
| }; | |
| cpu@400 { | |
| qcom,lmh-dcvs = <0x0a>; | |
| compatible = "arm,armv8"; | |
| cpu-release-addr = <0x00 0x90000000>; | |
| device_type = "cpu"; | |
| sched-energy-costs = <0x0c 0x0d>; | |
| next-level-cache = <0x0b>; | |
| enable-method = "psci"; | |
| phandle = <0x15>; | |
| reg = <0x00 0x400>; | |
| cache-size = <0x20000>; | |
| #cooling-cells = <0x02>; | |
| efficiency = <0x6cc>; | |
| l2-cache { | |
| compatible = "arm,arch-cache"; | |
| cache-level = <0x02>; | |
| next-level-cache = <0x06>; | |
| phandle = <0x0b>; | |
| cache-size = <0x40000>; | |
| }; | |
| l1-dcache { | |
| compatible = "arm,arch-cache"; | |
| phandle = <0xce>; | |
| qcom,dump-size = <0x14000>; | |
| }; | |
| l1-tlb { | |
| phandle = <0xda>; | |
| qcom,dump-size = <0x6800>; | |
| }; | |
| l1-icache { | |
| compatible = "arm,arch-cache"; | |
| phandle = <0xc6>; | |
| qcom,dump-size = <0x24000>; | |
| }; | |
| }; | |
| cpu@700 { | |
| qcom,lmh-dcvs = <0x0a>; | |
| compatible = "arm,armv8"; | |
| cpu-release-addr = <0x00 0x90000000>; | |
| device_type = "cpu"; | |
| sched-energy-costs = <0x0c 0x0d>; | |
| next-level-cache = <0x10>; | |
| enable-method = "psci"; | |
| phandle = <0x18>; | |
| reg = <0x00 0x700>; | |
| cache-size = <0x20000>; | |
| #cooling-cells = <0x02>; | |
| efficiency = <0x6cc>; | |
| l2-cache { | |
| compatible = "arm,arch-cache"; | |
| cache-level = <0x02>; | |
| next-level-cache = <0x06>; | |
| phandle = <0x10>; | |
| cache-size = <0x40000>; | |
| }; | |
| l1-dcache { | |
| compatible = "arm,arch-cache"; | |
| phandle = <0xd1>; | |
| qcom,dump-size = <0x14000>; | |
| }; | |
| l1-tlb { | |
| phandle = <0xdd>; | |
| qcom,dump-size = <0x6800>; | |
| }; | |
| l1-icache { | |
| compatible = "arm,arch-cache"; | |
| phandle = <0xc9>; | |
| qcom,dump-size = <0x24000>; | |
| }; | |
| }; | |
| }; | |
| }; |
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