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January 10, 2014 01:35
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/*** | |
* MSP430G2231 | |
* SPI Example | |
* Using MCP23S17 | |
* | |
* Kerry D. Wong | |
* http://www.kerrywong.com | |
* | |
* 3/2013 | |
* | |
* This program reads the GPIO pin status | |
* from MCP23S17 | |
*/ | |
#include <msp430.h> | |
#define CS BIT4 // Chip Select on P1.4 | |
#define REG_ADDR_IODIRA 0x00 | |
#define REG_ADDR_IODIRB 0x01 | |
#define REG_ADDR_GPIOA 0x12 | |
#define REG_ADDR_GPIOB 0x13 | |
void P1_init() { | |
P1OUT = CS; | |
P1DIR = CS; | |
P1OUT |= CS; | |
} // P1_init | |
void USI_init() { | |
// Enable SCLK, Master mode, enable output and reset USI | |
USICTL0 = USIPE5 + USIMST + USIOE + USISWRST; | |
// Mode 0 requires CKPH=1, enable interrupt | |
USICTL1 = USICKPH + USIIE; | |
// SMCLK div 8 -> 921.6 kHz USI clock | |
USICKCTL = USIDIV_3 + USISSEL_2; | |
// Clear USI for use | |
USICTL0 &= ~USISWRST; | |
USICNT = 1; // clear 1st transmit due to errata USI5 | |
__delay_cycles(50); // finish clearing (minimum (n+1)*16 cycles) | |
USICTL0 |= USIPE7 + USIPE6; // Enable SDI/SDO pins. | |
USICTL1 &= ~USIIFG; | |
} // USI_init | |
unsigned int w = 0; | |
void main(void) { | |
WDTCTL = WDTPW + WDTHOLD; | |
P1_init(); | |
USI_init(); | |
P1OUT &= ~CS; | |
//01000000 | |
//address pins A2 A1 A0 are 000 | |
USISRL = 0x40; | |
USICNT = 8; | |
while (!(USIIFG & USICTL1)); | |
//By default IOCON = 0 | |
//Write to IO direction register | |
USISRL = REG_ADDR_IODIRA; | |
USICNT = 8; | |
while (!(USIIFG & USICTL1)); | |
//set all directions to INPUT (default is input) | |
USISR = 0xFF; | |
USICNT = USI16B + 16; | |
while (!(USIIFG & USICTL1)); | |
P1OUT |= CS; | |
for (;;) { | |
P1OUT &= ~CS; | |
//01000000 | |
//address pings A2 A1 A0 are 000, read | |
USISRL = 0x41; | |
USICNT = 8; | |
while (!(USIIFG & USICTL1)); | |
//Write to Port A | |
USISRL = REG_ADDR_GPIOA; | |
USICNT = 8; | |
while (!(USIIFG & USICTL1)); | |
//clock out 16 bits | |
USISRL = 0; | |
USICNT = 16; | |
while (!(USIIFG & USICTL1)); | |
P1OUT |= CS; | |
//w contains the bits read from MCP23S17 | |
w = USISR; | |
__delay_cycles(100000l); | |
} | |
} |
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