ram.v

module memory(CLK, WR, addr, data);
// default parameters
parameter WORD = 32; 
parameter LEN  = 65535;

input  CLK;
input  WR; // 0:read 0:write
input  [WORD-1:0]addr;
inout  [WORD-1:0]data;

reg [WORD-1:0]mem[0:LEN];
reg [WORD-1:0]tmp;

assign data = WR ? tmp : 32'bz;

always @(posedge CLK) begin
  // write
  if(WR == 1'b1)
    mem[addr] <= tmp;
  // read
  else
    tmp <= mem[addr];
end

initial begin
  $readmemh("mem.dat", mem);
end

endmodule

module TEST;
reg  [31:0]addr;
reg  [31:0]data;
reg  wr; 
reg  clk;

memory m(clk, wr, addr, data);

initial begin
  $dumpfile("memory.vcd");
  $dumpvars(0, TEST);
  // write 435 to 0x324
  clk <= 1'b0;
  wr <= 1'b1;
  addr <= 32'h324;
  data <= 32'd435;
#1
  clk = 1'b1;
#1
  // read 
  clk = 1'b0;
  wr <= 1'b0;
  addr <= 32'h324;
#1
  clk = 1'b1;
#1
  clk = 1'b0;
#1
  clk = 1'b1;
#1
  clk = 1'b0;
  $finish;
end

endmodule