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Guide to Using the TSP61033 Boost Converter IC
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tps61033-notes.md

TPS61033 Community Reference Guide

This guide summarizes key design considerations, best practices, and common issues for the TPS61033 boost converter, based on collective notes from datasheets, application notes, and community discussions.

1. Overview and Core Functionality

The TPS61033 is a high-efficiency synchronous boost converter. It's frequently used in battery-powered applications to step-up a lower input voltage (e.g., from a Li-ion battery) to a stable, higher output voltage (e.g., 5V).

  • Key Application: Boosting 3.3V-4.2V inputs to a 5V output.
  • Performance: Capable of delivering up to 3A output current at 5V from a 3.7V input, provided the layout is optimal and the input supply is robust.
  • Efficiency: Can achieve over 90% efficiency, but this depends heavily on the specific operating conditions (Vin, Vout, Iout) and component selection.
  • Revisions: Be aware of different device revisions (e.g., TPS61033 vs. TPS610333). The TPS610333 has a lower valley switching current limit (1.8A) compared to the TPS61033 (5A).

2. Critical Design Considerations: Layout

Layout is the single most critical factor for the TPS61033's stability and reliability. Poor layout is the most common cause of IC failure, including overheating, instability, and internal MOSFET damage.

Best Practices:

  • Prototyping: Do not use breadboards, perfboards, or long wires for testing. The high parasitic inductance and resistance will negatively affect performance and can easily damage the IC. Always use the official Evaluation Module (EVM) or a well-designed custom PCB.
  • Capacitor Placement: Place input and output capacitors as close as physically possible to the IC's pins. This is not a suggestion; it is a requirement for stable operation.
  • Minimize Loop Area: The path from the IC's VOUT pin, through the output capacitor(s), and back to the GND pin forms a critical high-frequency current loop. This loop's area must be minimized to reduce parasitic inductance, which is a primary cause of damaging voltage spikes on the SW node.
  • Trace Characteristics: Use short, wide traces for all power paths (VIN, VOUT, GND, SW).
  • Ground Plane: Use a solid ground plane directly under the IC and associated components for a low-impedance return path.
  • Feedback Resistors: Place the feedback (FB) pin resistors as close as possible to the FB pin to prevent noise coupling into the feedback path, which can cause output voltage inaccuracies.
  • Avoid Vias in Critical Paths: Do not use vias in the high-frequency output decoupling path (VOUT -> Capacitor -> GND).

3. Component Selection

Strict adherence to datasheet recommendations for external components is essential to prevent instability and damage.

Inductor Selection

  • Recommended Range: Use an inductor with a value between 0.33 µH and 1.3 µH.
  • High Current Operation: For high output currents (above 1A), an inductor of 0.47 µH is frequently recommended.
  • Warning: Using an inductor with a value significantly outside the recommended range (e.g., 2.2 µH or 3.3 µH) is not recommended. It can lead to instability, unstable switching currents, and potential damage to the internal MOSFETs.
  • Key Parameters: Beyond the inductance value, ensure the inductor's Saturation Current (ISAT) is rated higher than the peak switching current and that its DC Resistance (DCR) is low to maximize efficiency.

Capacitor Selection

  • Output Capacitors:
    • Proper placement is more critical than the exact value, but the value is still important for stability and transient response.
    • For output currents lower than 1A, a total of at least 2x 22µF ceramic capacitors is recommended.
    • For output currents higher than 1A, use at least 4x 22µF capacitors.
    • Place a smaller 10µF ceramic capacitor as close as possible to the VOUT and GND pins for high-frequency decoupling, in addition to the larger bulk capacitors.
  • Input Capacitors: Place input capacitors close to the VIN and GND pins to supply the high-frequency switching currents and stabilize the input voltage.

4. Pin Functions and Operating Modes

Enable (EN) Pin

  • Functionality: A logic high on the EN pin enables the device. A logic low disables it and puts it into a low-power shutdown mode.
  • Shutdown: In shutdown mode, the load is fully disconnected from the input, preventing reverse current flow.
  • Timing: For reliable operation, maintain the EN pin in a high or low state for a minimum duration of 100 µs.

MODE Pin and PFM/PWM Operation

  • MODE High (Forced PWM): The device operates in a fixed-frequency Pulse Width Modulation (FPWM) mode (typically 2.4 MHz). This provides predictable switching noise but is less efficient at light loads.
  • MODE Low (Auto PFM/PWM): The device automatically transitions between PWM mode at higher loads and a power-saving Pulse Frequency Modulation (PFM) mode at light loads. This improves light-load efficiency.
  • Switching Modes: You can switch the MODE pin during operation, but expect a transient (overshoot or undershoot) on the output voltage. Transients are larger at lighter loads.

Pass-Through Mode

  • Condition: When the input voltage (VIN) rises above the set output voltage (VOUT), the device enters a "pass-through" mode.
  • Behavior: In this mode, the high-side FET is held on, and VOUT will follow VIN, minus a small voltage drop. The device stops switching.
  • Recovery: The TPS61033 will resume switching in PWM mode to regulate the output if VOUT drops to about 97% of its target voltage (due to VIN dropping or load increasing).

Power Good (PG) Pin

  • Functionality: The PG pin is an open-drain output that indicates the status of the output voltage. It is typically pulled low when the output is out of regulation and goes high-impedance (pulled high by an external resistor) when the output is stable.
  • Power Sequencing: The PG pin is useful for power sequencing. It can be connected to the enable pin of a downstream regulator to ensure the next power rail only turns on after the TPS61033 output is stable.

5. Troubleshooting and Common Issues

  • Failure to Start / Overheating: This is almost always a layout issue. If the output capacitors are not placed correctly and extremely close to the IC, the device may fail to start under no-load conditions and overheat.
  • MOSFET Damage on Power-up: This is also a common symptom of poor layout. High parasitic inductance causes large voltage spikes on the SW pin that exceed the absolute maximum ratings of the IC, destroying the internal MOSFETs.
  • Output Current Limited: If you cannot achieve the expected output current, first check that your input power supply is not current-limiting. A lab bench supply's current limit must be set high enough to handle the input current, which is significantly higher than the output current in a boost converter. I_IN ≈ (V_OUT * I_OUT) / (V_IN * Efficiency).
  • Output Voltage Drops Under Load: This can be caused by an undersized inductor (saturating), high DCR in the inductor, or insufficient input/output capacitance. For dynamic loads, increasing the total output capacitance can help mitigate voltage droop.

6. Simulation and Design Tools

  • WEBENCH: The TPS61033 is not available in TI's WEBENCH Power Designer.
  • PSpice Model: A PSpice model for the TPS61033 is available for download.
  • "PSpice for TI": This is a free simulation tool from TI that can be used with the TPS61033 PSpice model to simulate circuit behavior. When simulating, you may need to define a global parameter named "Dither" and set it to 0 to avoid errors.
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