inter.v

`timescale 1ps / 1ps
`default_nettype none

module tb ();

task waitclock;
begin
  @(posedge clk);
  #1;
end
endtask

reg clk;
initial clk = 1'b0;
always #1 clk = ~clk;

reg rst;
initial rst = 1'b0;

wire txfifo_free;
reg [4:0] rd;
reg [4:0] wr;
sender sender (
    .clk(clk)
  , .rst(rst)
  , .wr(wr)
  , .rd(rd)
  , .txfifo_free(txfifo_free)
);

initial begin
  $dumpfile("./test.vcd");
  $dumpvars(0, tb);

  wr = 5'd31;
  rd = 5'd1;

  rst = 1'b1;

  waitclock;
  waitclock;
  waitclock;
  waitclock;
  waitclock;
  waitclock;
  waitclock;
  waitclock;

  rst = 1'b0;

  #5000;

  wr = 5'd0;
  rd = 5'd31;

  #5000;

  $finish;
end


endmodule

module sender (
    input wire clk
  , input wire rst
  , input wire [4:0] wr
  , input wire [4:0] rd
  , output reg txfifo_free
);

reg [15:0] tx_wr_ptr;
always @(clk) begin
  if (rst) begin
    tx_wr_ptr <= 16'b0;
  end else begin
    tx_wr_ptr <= tx_wr_ptr + wr;
  end
end

reg [15:0] tx_rd_ptr;
always @(clk) begin
  if (rst) begin
    tx_rd_ptr <= 16'b0;
  end else begin
    tx_rd_ptr <= tx_rd_ptr + rd;
  end
end

wire [15:0] txfifo_free_space = tx_rd_ptr - tx_wr_ptr;
reg [1:0] txfifo_free_pre;
always @(posedge clk) begin
  if (rst) begin
    txfifo_free_pre <= 2'b00;
    txfifo_free     <= 1'b0;
  end else begin
    txfifo_free <= 1'b0;
    // when free space become 50%
    if (txfifo_free_pre == 2'b01 && txfifo_free_space[15:14] == 2'b10) begin
      txfifo_free <= 1'b1;
    end
    txfifo_free_pre <= txfifo_free_space[15:14];
  end
end
wire [1:0] now = txfifo_free_space[15:14];

endmodule

`default_nettype wire