Created
November 17, 2013 21:33
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package simulations | |
import org.scalatest.FunSuite | |
import org.junit.runner.RunWith | |
import org.scalatest.junit.JUnitRunner | |
@RunWith(classOf[JUnitRunner]) | |
class CircuitSuite extends CircuitSimulator with FunSuite { | |
val InverterDelay = 1 | |
val AndGateDelay = 3 | |
val OrGateDelay = 5 | |
test("andGate example") { | |
val in1, in2, out = new Wire | |
andGate(in1, in2, out) | |
in1.setSignal(false) | |
in2.setSignal(false) | |
run | |
assert(out.getSignal === false, "and 1") | |
in1.setSignal(true) | |
run | |
assert(out.getSignal === false, "and 2") | |
in2.setSignal(true) | |
run | |
assert(out.getSignal === true, "and 3") | |
} | |
test("orGate example") { | |
val in1, in2, out = new Wire | |
orGate(in1, in2, out) | |
in1.setSignal(false) | |
in2.setSignal(false) | |
run | |
assert(out.getSignal === false, "and 1") | |
in1.setSignal(true) | |
run | |
assert(out.getSignal === true, "and 2") | |
in2.setSignal(true) | |
run | |
assert(out.getSignal === true, "and 3") | |
} | |
test("orGate2 example") { | |
val in1, in2, out = new Wire | |
orGate2(in1, in2, out) | |
in1.setSignal(false) | |
in2.setSignal(false) | |
run | |
assert(out.getSignal === false, "and 1") | |
in1.setSignal(true) | |
run | |
assert(out.getSignal === true, "and 2") | |
in2.setSignal(true) | |
run | |
assert(out.getSignal === true, "and 3") | |
} | |
test("demux id") { | |
val i, o = new Wire | |
demux(i, List(), List(o)) | |
run | |
assert(o.getSignal === false) | |
i setSignal true | |
run | |
assert(o.getSignal === true) | |
} | |
test("demux zero") { | |
val r = new scala.util.Random | |
for(n <- 1 to 5) { | |
val inp = new Wire | |
val ctrl = for(i<-List.range(0, n)) yield new Wire | |
val outp = for(i<-List.range(0, 1<<n)) yield new Wire | |
demux(inp, ctrl, outp) | |
inp setSignal false | |
for(i <- 1 to 1000) { | |
run | |
assert(outp.count(_.getSignal == true) === 0) | |
val next = ctrl(r.nextInt(n)) | |
next.setSignal(!next.getSignal) | |
} | |
} | |
} | |
test("demux only one") { | |
val r = new scala.util.Random | |
for(n <- 1 to 5) { | |
val inp = new Wire | |
val ctrl = for(i<-List.range(0, n)) yield new Wire | |
val outp = for(i<-List.range(0, 1<<n)) yield new Wire | |
inp setSignal true | |
demux(inp, ctrl, outp) | |
for(i <- 1 to 1000) { | |
run | |
assert(outp.count(_.getSignal == true) === 1) | |
val next = ctrl(r.nextInt(n)) | |
next.setSignal(!next.getSignal) | |
} | |
} | |
} | |
test("demux right one") { | |
val r = new scala.util.Random | |
for(n <- 1 to 5) { | |
val inp = new Wire | |
val ctrl = for(i<-List.range(0, n)) yield new Wire | |
val outp = for(i<-List.range(0, 1<<n)) yield new Wire | |
inp setSignal true | |
demux(inp, ctrl, outp) | |
var index = 0 | |
for(i <- 1 to 1000) { | |
run | |
assert(outp((1<<n)-1-index).getSignal === true) | |
val rand = r.nextInt(n) | |
val next = ctrl(n-1-rand) | |
next.setSignal(!next.getSignal) | |
index = index ^ (1<<rand) | |
} | |
} | |
} | |
} |
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