gistfile1.tcl

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity mpg is
    Port ( clk : in  STD_LOGIC;
           btn : in  STD_LOGIC;
           led : out  STD_LOGIC_VECTOR (3 downto 0);
			  catod : out STD_LOGIC_VECTOR (7 downto 0);
			  anod : out STD_LOGIC_VECTOR (3 downto 0)
			 );
end mpg;

architecture Behavioral of mpg is

signal cnt  : std_logic_vector(14 downto 0);
signal cnt16 : std_logic_vector(15 downto 0);
signal cnt2 : std_logic_vector(1 downto 0) := "00";
signal q0   : std_logic;
signal q1   : std_logic;
signal q2   : std_logic;
signal en   : std_logic;
signal HEX  : std_logic_vector (3 downto 0);
signal sel  : std_logic_vector (1 downto 0);
signal numar : std_logic_vector (15 downto 0) := "0001001000110100";

begin
    
    process(clk)
    begin   
        if rising_edge(clk) then
		      if en = '1' then
					numar <= numar + 1;
				end if;
        end if;
    end process;
	 
    process(clk)
    begin   
        if rising_edge(clk) then
            cnt <= cnt + 1;    
        end if;
    end process;
	 
    process(clk)
    begin   
        if rising_edge(clk) then
            cnt16 <= cnt16 + 1;    
        end if;
    end process;
    
	 sel <= cnt16 (15 downto 14);
	 

	 
    process(cnt(cnt'high))
    begin   
      if rising_edge(cnt(cnt'high)) then
			q0 <= btn;
		end if;
    end process;
    
    process(clk)
    begin   
        if rising_edge(clk) then
            q1 <= q0;
            q2 <= q1;
        end if;
    end process;
    
    en <= q1 and not q2;
    
    process(clk, en)
    begin   
        if rising_edge(clk) then
            if en = '1' then
                cnt2 <= cnt2 + 1;
            end if;
        end if;
    end process;
   
    with HEX SELect
    catod (6 downto 0 )<= "1111001" when "0001",   --1
         "0100100" when "0010",   --2
         "0110000" when "0011",   --3
         "0011001" when "0100",   --4
         "0010010" when "0101",   --5
         "0000010" when "0110",   --6
         "1111000" when "0111",   --7
         "0000000" when "1000",   --8
         "0010000" when "1001",   --9
         "0001000" when "1010",   --A
         "0000011" when "1011",   --b
         "1000110" when "1100",   --C
         "0100001" when "1101",   --d
         "0000110" when "1110",   --E
         "0001110" when "1111",   --F
         "1000000" when others;   --0
 
    catod(7) <= '1';
	 
    process(cnt2)
    begin
        case cnt2 is 
            when "00"   => led <= "0001";
            when "01"   => led <= "0010";
            when "10"   => led <= "0100";
            when others => led <= "1000";
        end case;
    end process;
	 
    process(sel)
    begin
        case sel is 
            when "00"   => HEX <= numar (3 downto 0);
            when "01"   => HEX <= numar (7 downto 4);
            when "10"   => HEX <= numar (11 downto 8);
            when others => HEX <= numar (15 downto 12);
        end case;
    end process;
	 
    process(sel)
    begin
        case sel is 
            when "00"   => anod <= "1110";
            when "01"   => anod <= "1101";
            when "10"   => anod <= "1011";
            when others => anod <= "0111";
        end case;
    end process;
	 
end Behavioral;