Created
January 24, 2014 05:31
-
-
Save stephenmm/8592485 to your computer and use it in GitHub Desktop.
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
" | |
" You will have to restart vim for this to take effect. In any case | |
" it is a good idea to read ":he new-filetype" so that you know what | |
" is going on, and why the above lines work. | |
" | |
" Written originally by Dominic Mitchell, Jan 2006. | |
" happygiraffe.net | |
" | |
" Modified by Aaron Bieber, May 2007. | |
" blog.aaronbieber.com | |
" | |
" Modified by Tim Harper, July 2008 - current | |
" tim.theenchanter.com | |
" @(#) $Id$ | |
" Add this to ou .vimrc | |
" Autocmd BufNewFile,BufRead *.hlp set filetype=hlpFile | |
" Autocmd BufNewFile,BufRead *.help set filetype=hlpFile | |
if version < 600 | |
syntax clear | |
elseif exists("b:current_syntax") | |
finish | |
endif | |
let lace_case_insensitive=1 | |
" Taken from the SystemVerilog 3.1a Annex B: | |
syn keyword systemverilogStatement alias always always_comb always_ff always_latch | |
syn keyword systemverilogStatement and assert assign assume automatic before begin | |
syn keyword systemverilogStatement bind bins binsof bit break buf bufif0 bufif1 | |
syn keyword systemverilogStatement byte case casex casez cell chandle class clocking | |
syn keyword systemverilogStatement cmos config const constraint context continue cover | |
syn keyword systemverilogStatement covergroup coverpoint cross deassign default | |
syn keyword systemverilogStatement defparam design disable dist edge else end | |
syn keyword systemverilogStatement endcase endclass endclocking endconfig endfunction | |
syn keyword systemverilogStatement endgenerate endgroup endinterface endmodule | |
syn keyword systemverilogStatement endpackage endprimitive endprogram endproperty | |
syn keyword systemverilogStatement endspecify endsequence endtable endtask enum event | |
syn keyword systemverilogStatement expect export extends extern final first_match for | |
syn keyword systemverilogStatement force foreach forever fork forkjoin function generate | |
syn keyword systemverilogStatement genvar highz0 highz1 if iff ifnone ignore_bins | |
syn keyword systemverilogStatement illegal_bins incdir include initial inout | |
syn keyword systemverilogStatement input inside instance int integer interface intersect | |
syn keyword systemverilogStatement join join_any join_none large liblist library local | |
syn keyword systemverilogStatement localparam logic longint macromodule matches medium | |
syn keyword systemverilogStatement modport module nand negedge new nmos nor | |
syn keyword systemverilogStatement noshowcancelled notif0 notif1 null or output | |
syn keyword systemverilogStatement package packed parameter pmos posedge primitive | |
syn keyword systemverilogStatement priority program property protected pull0 pull1 | |
syn keyword systemverilogStatement pulldown pullup pulsestyle_onevent pulsestyle_ondetect | |
syn keyword systemverilogStatement pure rand randc randcase randsequence rcmos | |
syn keyword systemverilogStatement real realtime ref reg release repeat return | |
syn keyword systemverilogStatement rnmos rpmos rtran rtranif0 rtranif1 scalared sequence | |
syn keyword systemverilogStatement shortint shortreal showcancelled signed small solve | |
syn keyword systemverilogStatement specify specparam static string strong0 strong1 struct | |
syn keyword systemverilogStatement super supply0 supply1 table tagged task this | |
syn keyword systemverilogStatement throughout time timeprecision timeunit tran | |
syn keyword systemverilogStatement tranif0 tranif1 tri tri0 tri1 triand trior trireg type | |
syn keyword systemverilogStatement typedef union unique unsigned use var vectored virtual | |
syn keyword systemverilogStatement void wait wait_order wand weak0 weak1 | |
syn keyword systemverilogStatement while wildcard wire with within wor xnor xor | |
" LRM 3.7 String methods: | |
syn keyword systemverilogStatement len getc putc toupper tolower compare | |
syn keyword systemverilogStatement icompare substr | |
syn keyword systemverilogStatement itoa hextoa octtoa bintoa realtoa | |
syn keyword systemverilogStatement atoi atohex atooct atobin atoreal | |
" LRM 3.8 events: | |
syn keyword systemverilogStatement triggered | |
" LRM 3.10 methods for enumerated types: | |
syn keyword systemverilogStatement first last next prev num name | |
" LRM 4.6 Dynamic Arrays: | |
syn keyword systemverilogStatement delete | |
" LRM 4.10 Associative Array methods: | |
syn keyword systemverilogStatement num exists | |
" LRM 4.15.1 Array locator methods: | |
syn keyword systemverilogStatement find find_index find_first find_first_index | |
syn keyword systemverilogStatement find_last find_last_index min max unique unique_index | |
" LRM 4.15.2 Array ordering methods: | |
syn keyword systemverilogStatement reverse sort rsort shuffle | |
" LRM 4.15.3 Array reduction methods: | |
syn keyword systemverilogStatement sum product | |
" LRM 4.15.4 Array iterator query: | |
syn keyword systemverilogStatement index | |
"" LRM 7.10.1 Builtin package: | |
syn keyword systemverilogStatement std | |
" LRM Annex C standard library | |
syn keyword systemverilogStatement get put try_get try_put peek try_peek | |
syn keyword systemverilogStatement kill self await suspend resume | |
" LRM Annex D List methods | |
syn keyword systemverilogStatement next prev eq neq data | |
syn keyword systemverilogStatement size empty push_front push_back | |
syn keyword systemverilogStatement front back pop_front pop_back | |
syn keyword systemverilogStatement start finish insert insert_range | |
syn keyword systemverilogStatement erase erase_range set swap clear purge | |
syn match systemverilogGlobal "`celldefine" | |
syn match systemverilogGlobal "`default_nettype" | |
syn match systemverilogGlobal "`define" | |
syn match systemverilogGlobal "`else" | |
syn match systemverilogGlobal "`elsif" | |
syn match systemverilogGlobal "`endcelldefine" | |
syn match systemverilogGlobal "`endif" | |
syn match systemverilogGlobal "`ifdef" | |
syn match systemverilogGlobal "`ifndef" | |
syn match systemverilogGlobal "`include" | |
syn match systemverilogGlobal "`line" | |
syn match systemverilogGlobal "`nounconnected_drive" | |
syn match systemverilogGlobal "`resetall" | |
syn match systemverilogGlobal "`timescale" | |
syn match systemverilogGlobal "`unconnected_drive" | |
syn match systemverilogGlobal "`undef" | |
syn match systemverilogGlobal "$[a-zA-Z0-9_]\+\>" | |
syn match systemverilogOperator /[&|~><!)(*#%@+/=?:;}{,.\^\-\[\]]/ | |
syn keyword hlpStatement ff gox gx make mk cp pd cd hg mkdir perl cat v find grep xargs ftp setenv tar gunzip diff tkdiff pushd wget python gvim screen sed ack rsync top ps ls scp echo date time | |
hi hlpHiBold term=bold cterm=bold gui=bold | |
hi hlpHiRed term=bold ctermfg=Red guifg=Red | |
hi hlpHiGreen term=bold ctermfg=Green guifg=Green | |
hi hlpHiHeading term=bold ctermfg=Blue guifg=Blue | |
" Inline elements. | |
" Block elements. | |
"syn match hlpHeader2 /^\(\(\s\{2\}\)*\)#\s.\+/ | |
syn match hlpComment /#\s.\+/ | |
syn match hlpHeading /^#\s.\+/ | |
syn match hlpCodeComment /\/\/\s.\+/ | |
syn match hlpConstant /[$A-Z_]\{2,\}/ | |
syn match hlpListBullet /^\(\s\s\)\+\*+ / | |
syn match hlpAdded /^+\+.*/ | |
syn match hlpRemoved /^-\+.*/ | |
syn match hlpPassing /\c\(pass\w*\)/ | |
syn match hlpError /\c\(error\|bad\|fatal\|UVM_FATAL\|UVM_ERROR\|fail\w*\|not pass\w*\)/ | |
syn match hlpNumber "\(\<\d\+\|\)'[bB]\s*[0-1_xXzZ?]\+\>" | |
syn match hlpNumber "\(\<\d\+\|\)'[oO]\s*[0-7_xXzZ?]\+\>" | |
syn match hlpNumber "\(\<\d\+\|\)'[dD]\s*[0-9_xXzZ?]\+\>" | |
syn match hlpNumber "\(\<\d\+\|\)'[hH]\s*[0-9a-fA-F_xXzZ?]\+\>" | |
syn match hlpNumber "\<[+-]\=[0-9_]\+\(\.[0-9_]*\|\)\(e[0-9_]*\|\)\>" | |
syn match hlpDString /"[^"]\+"/ | |
syn match hlpSString /'[^']\+'/ | |
"syn region hlpDString start=+"+ skip=+\\"+ end=+"+ | |
"syn region hlpSString start=+'+ skip=+\\'+ end=+'+ | |
" Everything after the first colon is from RFC 2396, with extra | |
" backslashes to keep vim happy... Original: | |
" ^(([^:/?#]+):)?(//([^/?#]*))?([^?#]*)(\?([^#]*))?(#(.*))? | |
" | |
" Revised the pattern to exclude spaces from the URL portion of the | |
" pattern. Aaron Bieber, 2007. | |
"syn match hlpLink /"[^"]\+":\(\([^:\/?# ]\+\):\)\?\(\/\/\([^\/?# ]*\)\)\?\([^?# ]*\)\(?\([^# ]*\)\)\?\(#\([^ ]*\)\)\?/ | |
if version >= 508 || !exists("did_txt_syn_inits") | |
if version < 508 | |
let did_txt_syn_inits = 1 | |
command -nargs=+ HiLink hi link <args> | |
else | |
command -nargs=+ HiLink hi def link <args> | |
endif | |
HiLink hlpHeader PreProc | |
HiLink hlpHeader2 Comment | |
HiLink hlpBlockquote Normal | |
HiLink hlpListBullet Special | |
HiLink hlpListNumber Special | |
HiLink hlpDString Constant | |
HiLink hlpSString Constant | |
HiLink systemverilogStatement Statement | |
HiLink systemverilogOperator Special | |
HiLink systemverilogGlobal Define | |
HiLink hlpStatement Identifier | |
HiLink hlpConstant hlpHiBold | |
HiLink hlpComment Comment | |
"HiLink hlpHeading hlpHiHeading | |
HiLink hlpHeading Comment | |
HiLink hlpCodeComment Comment | |
HiLink hlpNumber Constant | |
HiLink hlpError hlpHiRed | |
HiLink hlpPassing hlpHiGreen | |
HiLink hlpAdded hlpHiGreen | |
HiLink hlpRemoved hlpHiRed | |
hi def hlpEmphasis term=underline cterm=underline gui=italic | |
hi def hlpHiBold term=bold cterm=bold gui=bold | |
delcommand HiLink | |
endif | |
let b:current_syntax = "systemverilog" | |
" vim: set ai et sw=4 : |
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
A little highlighter for my .hlp files