[PATCH] encore: overclocking changes

encore-overclocking-changes.patch

From 505a92254fa541251e2783e0cbc9334cdb9c9572 Mon Sep 17 00:00:00 2001
From: Steven Luo <[email protected]>
Date: Sun, 6 Apr 2014 01:25:07 -0700
Subject: [PATCH] encore: overclocking changes

encore: clean up overclocking config #ifdefs

* Ensure upstream defaults are used when building for non-encore boards
* Don't make DSP OPP4 available on encore with stock clocks

OMAP36xx: add DSP OPP5 for overclocking purposes

The 2.6.32 kernel for OMAP36xx defined a severely-underclocked DSP OPP5
for use with MPU OPP5, presumably because the MPU and DSP share a voltage
domain and the power demands of running the MPU and DSP at their highest
clocks simultaneously were too great.  Define the same for our present
kernel when overclocking is enabled.

encore: use lower L3 clocks for stock and 1200MHz configurations

The 2.6.32 kernel previously used on encore used L3 OPPs of 83 and 166
MHz for the OMAP3621, whereas we currently use 100 and 200 MHz (the
OMAP3630 levels).  Use the lower OPPs for CONFIG_ENCORE_MPU_STOCK to
match the stock kernel.

1200 MHz is enabled at the factory only on speed-binned OMAP3630 dies,
so it's likely that many OMAP3621s will struggle to hit that figure.
A lower L3 clock may help here, so lower the L3 clocks for
CONFIG_ENCORE_MPU_1200MHZ as well.  (It's not clear that this is a good
deal; since most of these chips can hit 1100 MHz with the higher L3
OPPs, this effectively trades a 9% CPU clock speed increase for a 20%
cut in memory bandwidth.)
---
 arch/arm/mach-omap2/opp3xxx_data.c |   16 ++++++++++++++--
 drivers/gpu/pvr/omap3/sysconfig.c  |    2 +-
 2 files changed, 15 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-omap2/opp3xxx_data.c b/arch/arm/mach-omap2/opp3xxx_data.c
index 2f762e0..fdcd78a 100644
--- a/arch/arm/mach-omap2/opp3xxx_data.c
+++ b/arch/arm/mach-omap2/opp3xxx_data.c
@@ -180,18 +180,27 @@ static struct omap_opp_def __initdata omap36xx_opp_def_list[] = {
 	/* MPU OPP5 - non-standard overclock */
 	OPP_INITIALIZER("mpu", "dpll1_ck", "mpu_iva", true,
 				ENCORE_MPU_OPP5_FREQ, OMAP3630_VDD_MPU_OPP1G_UV),
-#elif defined(CONFIG_ENCORE_MPU_1000MHZ)
+#elif !defined(CONFIG_ENCORE_MPU_STOCK)
 	/* MPU OPP4 - OPP-SB */
 	OPP_INITIALIZER("mpu", "dpll1_ck", "mpu_iva", true,
 				1000000000, OMAP3630_VDD_MPU_OPP1G_UV),
 #endif
 
+#if defined(CONFIG_ENCORE_MPU_STOCK) || defined(CONFIG_ENCORE_MPU_1200MHZ)
+	/* L3 OPP1 - OPP50 */
+	OPP_INITIALIZER("l3_main", "l3_ick", "core", true,
+				83000000, OMAP3630_VDD_CORE_OPP50_UV),
+	/* L3 OPP2 - OPP100, OPP-Turbo, OPP-SB */
+	OPP_INITIALIZER("l3_main", "l3_ick", "core", true,
+				166000000, OMAP3630_VDD_CORE_OPP100_UV),
+#else
 	/* L3 OPP1 - OPP50 */
 	OPP_INITIALIZER("l3_main", "l3_ick", "core", true,
 				100000000, OMAP3630_VDD_CORE_OPP50_UV),
 	/* L3 OPP2 - OPP100, OPP-Turbo, OPP-SB */
 	OPP_INITIALIZER("l3_main", "l3_ick", "core", true,
 				200000000, OMAP3630_VDD_CORE_OPP100_UV),
+#endif
 
 	/* DSP OPP1 - OPP50 */
 	OPP_INITIALIZER("iva", "dpll2_ck", "mpu_iva", true,  260000000, OMAP3630_VDD_MPU_OPP50_UV),
@@ -204,7 +213,10 @@ static struct omap_opp_def __initdata omap36xx_opp_def_list[] = {
 	/* DSP OPP4 - OPP-SB */
 	OPP_INITIALIZER("iva", "dpll2_ck", "mpu_iva", true,
 				800000000, OMAP3630_VDD_MPU_OPP130_UV),
-#else
+	/* DSP OPP5 - non-standard overclock */
+	OPP_INITIALIZER("iva", "dpll2_ck", "mpu_iva", true,
+				65000000, OMAP3630_VDD_MPU_OPP1G_UV),
+#elif !defined(CONFIG_ENCORE_MPU_STOCK)
 	/* DSP OPP4 - OPP-SB */
 	OPP_INITIALIZER("iva", "dpll2_ck", "mpu_iva", true,
 				800000000, OMAP3630_VDD_MPU_OPP1G_UV),
diff --git a/drivers/gpu/pvr/omap3/sysconfig.c b/drivers/gpu/pvr/omap3/sysconfig.c
index a961762..3ad0273 100644
--- a/drivers/gpu/pvr/omap3/sysconfig.c
+++ b/drivers/gpu/pvr/omap3/sysconfig.c
@@ -65,7 +65,7 @@ static IMG_CPU_VIRTADDR gsSGXRegsCPUVAddr;
 
 #ifdef SYS_OMAP3430_PIN_MEMORY_BUS_CLOCK
 extern struct platform_device *gpsPVRLDMDev;
-#if defined(SGX530) && (SGX_CORE_REV == 125)
+#if defined(SGX530) && (SGX_CORE_REV == 125) && !defined(CONFIG_ENCORE_MPU_STOCK) && !defined(CONFIG_ENCORE_MPU_1200MHZ)
 #define OMAP_MEMORY_BUS_BANDWIDTH_MAX 800000
 #else
 #define OMAP_MEMORY_BUS_BANDWIDTH_MAX 664000
-- 
1.7.10.4