Electronic Design Automation / Embedded System Abbreviations

EDA_abbreviations.txt

(GP)GPU	(General-purpose) Graphic Processing Unit
AHB	Advanced High-performance Bus
ALAP	As Late As Possible
AMAT	Average Memory Access Time
AMBA	Advanced Microcontroller Bus Architecture
APB	Advanced Peripherial Bus
APU	Application Processing Unit
ARM	{Acorns,Advanced} RISC Machines
ASAP	As Soon AS Possible
ASIC	Application Specific Integrated Circuit
ASIP	Application Specific Instruction-set Processor
AXI	Advanced eXtensible Interface Bus
BIST	Built-in Self Test
CCI	Cache Coherent Interface
CDFG	Control Data Flow Graph
CIF	Caltech Intermediate Format
CISC	Complete Instruction-set
CMOS	Complementary Metal Oxide Semiconductor
CPI	Cycles per Instruction
CPLD	Complex Programmable Logic Device
CPU	Central Processing Unit
DFM	Design for Manufacturing
DFT	Design for Testability
DMA	Direct Memory Access
DRC	Design Rule Check
DSE	Design Space Exploration
DSP	Digital Signal Processor
DVFS	Dynamic Volage Frequency Scaling
EDA	Electronic Design Automation
ES	Embedded System
ESL	Electronic System Level
EUV(L)	Extreme Ultraviolet (Lithography)
FinFET	Fin Field Effect Transistor
FPGA	Field Programmable Gate Array
FSM	Finite State Machine
GaAs	Gallium-Arsenid
GDS	II Graphical {Design Station, Data System}
GDSII	Graphical Design Station II
HDL	Hardware Description Language
HLS	High-level Synthesis
HMP	Heterogenous Multi-processing
HW	Hardware
ILP	Instruction-level Parallelism
IP	Intellectual Property
IPC	Instructions per Cycle
MP	Miss Penalty
MPSoC	Multi Processor SoC
MR	Miss Rate
NoC	Network-on-Chip
NRE	Non-recurring Engineering costs
P&R	Place & Route
PC	Program Counter
PL	Programmable Logic
PN	Petri Network
PPP	Power, Performance, Programmability
PS	Processing System
RISC	Reduced Instruction-set
RTL	Register Transfer Level
SiGe	Silicon-Germanium
SIMD	Single Instruction Multiple Data
SoC	System-on-Chip
SW	Software
TB	Testbed
TLM	Transaction Level Modelling
uC	Microcontroller
UML	Unified Modeling Language
VCD	Value Change Dump
VHDL	Very High Speed Integrated Circuit HDL
VIP	Virtual IP (Test Data)
VLIW	Very large Instruction words
VLSI	Very Large Scale Integration