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February 1, 2023 07:35
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| //This code was generated by Verilator and manually adapted to C++ | |
| //Adaptations by Victor Suarez Rovere <[email protected]> | |
| //original sources https://github.com/BrunoLevy/learn-fpga/blob/master/FemtoRV/README.md | |
| //by Bruno Levy - BSD-3-Clause license | |
| #include "cpu.h" | |
| void cpu_instance::simstep0(uint32_t mbus_rdata0) | |
| { | |
| uint5 __Vdlyvdim0__registerFile__v0; | |
| int32_t __Vdlyvval__registerFile__v0; | |
| bool __Vdlyvset__registerFile__v0; | |
| int32_t __Vdly__aluReg; | |
| uint5 __Vdly__aluShamt; | |
| int32_t __Vdly__cycles; | |
| __Vdly__cycles = __PVT__cycles; | |
| __Vdlyvset__registerFile__v0 = 0U; | |
| __Vdly__aluShamt = __PVT__aluShamt; | |
| __Vdly__aluReg = __PVT__aluReg; | |
| __Vdly__cycles = ((uint32_t)(1U) + __PVT__cycles); | |
| if ((1U & ((~ ((0x18U == (0x1fU & __PVT__instr)) | |
| | (8U == (0x1fU & __PVT__instr)))) | |
| & (uint32_t)((0U != (0xcU & (uint32_t)(__PVT__state))))))) { | |
| if ((0U != (0x1fU & (__PVT__instr >> 5U)))) { | |
| __Vdlyvval__registerFile__v0 = (((0x1cU | |
| == (0x1fU | |
| & __PVT__instr)) | |
| ? __PVT__cycles | |
| : 0U) | |
| | (((0xdU | |
| == | |
| (0x1fU | |
| & __PVT__instr)) | |
| ? | |
| (0xfffff000U | |
| & (__PVT__instr | |
| << 2U)) | |
| : 0U) | |
| | (((uint32_t)(__PVT__isALU) | |
| ? __PVT__aluOut | |
| : 0U) | |
| | (((5U | |
| == | |
| (0x1fU | |
| & __PVT__instr)) | |
| ? __PVT__PCplusImm | |
| : 0U) | |
| | (((1U | |
| & ((0x19U | |
| == | |
| (0x1fU | |
| & __PVT__instr)) | |
| | (__PVT__instr | |
| >> 1U))) | |
| ? | |
| ((uint32_t)(4U) | |
| + __PVT__PC) | |
| : 0U) | |
| | ((0U | |
| == | |
| (0x1fU | |
| & __PVT__instr)) | |
| ? | |
| ((0U | |
| == | |
| (3U | |
| & (__PVT__instr | |
| >> 0xaU))) | |
| ? | |
| (((- (uint32_t)((uint32_t)(__PVT__LOAD_sign))) | |
| << 8U) | |
| | (uint32_t)(__PVT__LOAD_byte)) | |
| : | |
| ((1U | |
| == | |
| (3U | |
| & (__PVT__instr | |
| >> 0xaU))) | |
| ? | |
| (((- (uint32_t)((uint32_t)(__PVT__LOAD_sign))) | |
| << 0x10U) | |
| | (uint32_t)(__PVT__LOAD_halfword)) | |
| : mbus_rdata0)) | |
| : 0U)))))); | |
| __Vdlyvset__registerFile__v0 = 1U; | |
| __Vdlyvdim0__registerFile__v0 = (0x1fU | |
| & (__PVT__instr | |
| >> 5U)); | |
| } | |
| } | |
| if ((((uint32_t)(__PVT__state) >> 2U) & (uint32_t)(__PVT__isALU))) { | |
| if (__PVT__funct3IsShift) { | |
| __Vdly__aluReg = __PVT__rs1; | |
| __Vdly__aluShamt = (0x1fU & __PVT__aluIn2); | |
| } | |
| } | |
| if ((0U != (uint32_t)(__PVT__aluShamt))) { | |
| __Vdly__aluShamt = (0x1fU & ((uint32_t)(__PVT__aluShamt) | |
| - (uint32_t)(1U))); | |
| __Vdly__aluReg = ((2U & ((uint32_t)(1U) << (7U | |
| & (__PVT__instr | |
| >> 0xaU)))) | |
| ? (__PVT__aluReg | |
| << 1U) : (((uint32_t)(((__PVT__instr | |
| >> 0x1cU) | |
| & (__PVT__aluReg | |
| >> 0x1fU))) | |
| << 0x1fU) | |
| | (__PVT__aluReg | |
| >> 1U))); | |
| } | |
| __PVT__mem_wdata = ((((1U & __PVT__loadstore_addr_next) | |
| ? __PVT__rs2_next | |
| : ((2U & __PVT__loadstore_addr_next) | |
| ? (__PVT__rs2_next | |
| >> 8U) : | |
| (__PVT__rs2_next | |
| >> 0x18U))) | |
| << 0x18U) | ((0xff0000U | |
| & (((2U | |
| & __PVT__loadstore_addr_next) | |
| ? __PVT__rs2_next | |
| : | |
| (__PVT__rs2_next | |
| >> 0x10U)) | |
| << 0x10U)) | |
| | ((0xff00U | |
| & (((1U | |
| & __PVT__loadstore_addr_next) | |
| ? __PVT__rs2_next | |
| : | |
| (__PVT__rs2_next | |
| >> 8U)) | |
| << 8U)) | |
| | (0xffU | |
| & __PVT__rs2_next)))); | |
| __PVT__mem_addr = ((uint32_t)((0U != (3U & (uint32_t)(__PVT__state_next)))) | |
| ? __PVT__PC_next | |
| : __PVT__loadstore_addr_next); | |
| __PVT__mem_rstrb = (1U & ((((uint32_t)(__PVT__state_next) | |
| >> 2U) & (0U | |
| == | |
| (0x1fU | |
| & __PVT__instr_next))) | |
| | (uint32_t)(__PVT__state_next))); | |
| __PVT__loadstore_addr = __PVT__loadstore_addr_next; | |
| __PVT__rs2 = __PVT__rs2_next; | |
| __PVT__cycles = __Vdly__cycles; | |
| if (__Vdlyvset__registerFile__v0) { | |
| __PVT__registerFile[__Vdlyvdim0__registerFile__v0] | |
| = __Vdlyvval__registerFile__v0; | |
| } | |
| __PVT__aluReg = __Vdly__aluReg; | |
| __PVT__aluShamt = __Vdly__aluShamt; | |
| __PVT__PC = __PVT__PC_next; | |
| __PVT__state = __PVT__state_next; | |
| __PVT__rs1 = __PVT__rs1_next; | |
| __PVT__instr = __PVT__instr_next; | |
| __PVT__isALU = ((4U == (0x1fU & __PVT__instr)) | |
| | (0xcU == (0x1fU & __PVT__instr))); | |
| __PVT__PCplusImm = (__PVT__PC + | |
| ((2U & __PVT__instr) | |
| ? (((- (uint32_t)((1U | |
| & (__PVT__instr | |
| >> 0x1dU)))) | |
| << 0x14U) | ( | |
| (0xff000U | |
| & (__PVT__instr | |
| << 2U)) | |
| | ((0x800U | |
| & (__PVT__instr | |
| >> 7U)) | |
| | (0x7feU | |
| & (__PVT__instr | |
| >> 0x12U))))) | |
| : ((4U & __PVT__instr) | |
| ? (0xfffff000U | |
| & (__PVT__instr | |
| << 2U)) | |
| : (((- (uint32_t)( | |
| (1U | |
| & (__PVT__instr | |
| >> 0x1dU)))) | |
| << 0xcU) | |
| | ((0x800U | |
| & (__PVT__instr | |
| << 6U)) | |
| | ((0x7e0U | |
| & (__PVT__instr | |
| >> 0x12U)) | |
| | (0x1eU | |
| & (__PVT__instr | |
| >> 5U)))))))); | |
| __PVT__funct3IsShift = (1U & ((0x7fU & | |
| (((uint32_t)(1U) | |
| << (7U | |
| & (__PVT__instr | |
| >> 0xaU))) | |
| >> 1U)) | |
| | (7U & ( | |
| ((uint32_t)(1U) | |
| << | |
| (7U | |
| & (__PVT__instr | |
| >> 0xaU))) | |
| >> 5U)))); | |
| _mem_wmask_OUTLET = ((- (uint32_t)((((uint32_t)(__PVT__state) | |
| >> 2U) | |
| & (8U | |
| == | |
| (0x1fU | |
| & __PVT__instr))))) | |
| & ((0U == (3U & (__PVT__instr | |
| >> 0xaU))) | |
| ? ((2U & __PVT__loadstore_addr) | |
| ? ((1U & __PVT__loadstore_addr) | |
| ? 8U : 4U) | |
| : ((1U & __PVT__loadstore_addr) | |
| ? 2U : 1U)) | |
| : ((1U == (3U | |
| & (__PVT__instr | |
| >> 0xaU))) | |
| ? ((2U & __PVT__loadstore_addr) | |
| ? 0xcU | |
| : 3U) : 0xfU))); | |
| } | |
| void cpu_instance::simstep1() | |
| { | |
| __PVT__aluIn2 = (((0xcU == (0x1fU & __PVT__instr)) | |
| | (0x18U == (0x1fU & __PVT__instr))) | |
| ? __PVT__rs2 : | |
| (((- (uint32_t)((1U & (__PVT__instr | |
| >> 0x1dU)))) | |
| << 0xbU) | (0x7ffU & | |
| (__PVT__instr | |
| >> 0x12U)))); | |
| __PVT__aluPlus = (__PVT__rs1 + __PVT__aluIn2); | |
| __PVT__aluMinus = (0x1ffffffffULL & (1ULL | |
| + | |
| ((0x100000000ULL | |
| | (uint64_t)((uint32_t)( | |
| (~ __PVT__aluIn2)))) | |
| + (uint64_t)((uint32_t)(__PVT__rs1))))); | |
| __PVT__LT = (1U & (((__PVT__rs1 | |
| ^ __PVT__aluIn2) | |
| >> 0x1fU) ? (__PVT__rs1 | |
| >> 0x1fU) | |
| : (uint32_t)((__PVT__aluMinus | |
| >> 0x20U)))); | |
| __PVT__aluOut = (((1U & ((uint32_t)(1U) << | |
| (7U & (__PVT__instr | |
| >> 0xaU)))) | |
| ? ((uint32_t)((0x10000008U | |
| == (0x10000008U | |
| & __PVT__instr))) | |
| ? (uint32_t)(__PVT__aluMinus) | |
| : __PVT__aluPlus) | |
| : 0U) | (((4U & ((uint32_t)(1U) | |
| << | |
| (7U | |
| & (__PVT__instr | |
| >> 0xaU)))) | |
| ? (uint32_t)(__PVT__LT) | |
| : 0U) | ( | |
| ((8U | |
| & ((uint32_t)(1U) | |
| << | |
| (7U | |
| & (__PVT__instr | |
| >> 0xaU)))) | |
| ? | |
| (1U | |
| & (uint32_t)( | |
| (__PVT__aluMinus | |
| >> 0x20U))) | |
| : 0U) | |
| | (((0x10U | |
| & ((uint32_t)(1U) | |
| << | |
| (7U | |
| & (__PVT__instr | |
| >> 0xaU)))) | |
| ? | |
| (__PVT__rs1 | |
| ^ __PVT__aluIn2) | |
| : 0U) | |
| | (((0x40U | |
| & ((uint32_t)(1U) | |
| << | |
| (7U | |
| & (__PVT__instr | |
| >> 0xaU)))) | |
| ? | |
| (__PVT__rs1 | |
| | __PVT__aluIn2) | |
| : 0U) | |
| | (((0x80U | |
| & ((uint32_t)(1U) | |
| << | |
| (7U | |
| & (__PVT__instr | |
| >> 0xaU)))) | |
| ? | |
| (__PVT__rs1 | |
| & __PVT__aluIn2) | |
| : 0U) | |
| | ((uint32_t)(__PVT__funct3IsShift) | |
| ? __PVT__aluReg | |
| : 0U))))))); | |
| __VdfgExtracted_h4911ff05__0 = ((0x19U | |
| == (0x1fU | |
| & __PVT__instr)) | |
| ? (0xfffffffeU | |
| & __PVT__aluPlus) | |
| : ((1U | |
| & ((__PVT__instr | |
| >> 1U) | |
| | ((0x18U | |
| == | |
| (0x1fU | |
| & __PVT__instr)) | |
| & ((((uint32_t)(1U) | |
| << | |
| (7U | |
| & (__PVT__instr | |
| >> 0xaU))) | |
| & (0U | |
| == (uint32_t)(__PVT__aluMinus))) | |
| | ((0x7fU | |
| & ((0U | |
| != (uint32_t)(__PVT__aluMinus)) | |
| & (((uint32_t)(1U) | |
| << | |
| (7U | |
| & (__PVT__instr | |
| >> 0xaU))) | |
| >> 1U))) | |
| | ((0xfU | |
| & ((((uint32_t)(1U) | |
| << | |
| (7U | |
| & (__PVT__instr | |
| >> 0xaU))) | |
| >> 4U) | |
| & (uint32_t)(__PVT__LT))) | |
| | ((7U | |
| & ((~ (uint32_t)(__PVT__LT)) | |
| & (((uint32_t)(1U) | |
| << | |
| (7U | |
| & (__PVT__instr | |
| >> 0xaU))) | |
| >> 5U))) | |
| | ((3U | |
| & ((((uint32_t)(1U) | |
| << | |
| (7U | |
| & (__PVT__instr | |
| >> 0xaU))) | |
| >> 6U) | |
| & (uint32_t)( | |
| (__PVT__aluMinus | |
| >> 0x20U)))) | |
| | (1U | |
| & ((~ (uint32_t)( | |
| (__PVT__aluMinus | |
| >> 0x20U))) | |
| & (((uint32_t)(1U) | |
| << | |
| (7U | |
| & (__PVT__instr | |
| >> 0xaU))) | |
| >> 7U))))))))))) | |
| ? __PVT__PCplusImm | |
| : | |
| ((uint32_t)(4U) | |
| + __PVT__PC))); | |
| } | |
| void cpu_instance::cpu_reset() | |
| { | |
| __PVT__PC_next = 0U; | |
| __PVT__state_next = 8U; | |
| } | |
| void cpu_instance::simstep2(uint32_t mbus_rdata0, bool mbus_rbusy, bool mbus_wbusy) | |
| { | |
| __PVT__LOAD_halfword = (0xffffU & ((2U | |
| & __PVT__loadstore_addr) | |
| ? (mbus_rdata0 | |
| >> 0x10U) | |
| : mbus_rdata0)); | |
| __PVT__PC_next = __PVT__PC; | |
| __PVT__rs2_next = __PVT__rs2; | |
| __PVT__state_next = __PVT__state; | |
| __PVT__instr_next = __PVT__instr; | |
| __PVT__rs1_next = __PVT__rs1; | |
| if ((4U & (uint32_t)(__PVT__state))) { | |
| __PVT__PC_next = __VdfgExtracted_h4911ff05__0; | |
| } | |
| if ((2U & (uint32_t)(__PVT__state))) { | |
| if ((1U & (~ (uint32_t)(mbus_rbusy)))) { | |
| __PVT__rs2_next = __PVT__registerFile | |
| [(0x1fU & (mbus_rdata0 | |
| >> 0x14U))]; | |
| __PVT__state_next = 4U; | |
| __PVT__instr_next = (mbus_rdata0 | |
| >> 2U); | |
| __PVT__rs1_next = __PVT__registerFile | |
| [(0x1fU & (mbus_rdata0 | |
| >> 0xfU))]; | |
| } | |
| } else if ((4U & (uint32_t)(__PVT__state))) { | |
| __PVT__state_next = (((0U == (0x1fU | |
| & __PVT__instr)) | |
| | ((8U == | |
| (0x1fU | |
| & __PVT__instr)) | |
| | ((uint32_t)(__PVT__isALU) | |
| & (uint32_t)(__PVT__funct3IsShift)))) | |
| ? 8U : 1U); | |
| } else if ((8U & (uint32_t)(__PVT__state))) { | |
| if ((1U & ((~ (uint32_t)((0U != (uint32_t)(__PVT__aluShamt)))) | |
| & ((~ (uint32_t)(mbus_rbusy)) | |
| & (~ (uint32_t)(mbus_wbusy)))))) { | |
| __PVT__state_next = 1U; | |
| } | |
| } else { | |
| __PVT__state_next = 2U; | |
| } | |
| __PVT__LOAD_byte = (0xffU & ((1U & __PVT__loadstore_addr) | |
| ? ((uint32_t)(__PVT__LOAD_halfword) | |
| >> 8U) | |
| : (uint32_t)(__PVT__LOAD_halfword))); | |
| __PVT__loadstore_addr_next = (__PVT__rs1_next | |
| + ((8U & __PVT__instr_next) | |
| ? (((- (uint32_t)( | |
| (1U | |
| & (__PVT__instr_next | |
| >> 0x1dU)))) | |
| << 0xbU) | |
| | ((0x7e0U | |
| & (__PVT__instr_next | |
| >> 0x12U)) | |
| | (0x1fU | |
| & (__PVT__instr_next | |
| >> 5U)))) | |
| : (((- (uint32_t)( | |
| (1U | |
| & (__PVT__instr_next | |
| >> 0x1dU)))) | |
| << 0xbU) | |
| | (0x7ffU | |
| & (__PVT__instr_next | |
| >> 0x12U))))); | |
| __PVT__LOAD_sign = (1U & ((~ (__PVT__instr | |
| >> 0xcU)) | |
| & ((0U == (3U | |
| & (__PVT__instr | |
| >> 0xaU))) | |
| ? ((uint32_t)(__PVT__LOAD_byte) | |
| >> 7U) | |
| : ((uint32_t)(__PVT__LOAD_halfword) | |
| >> 0xfU)))); | |
| } |
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