soc.py

#original source https://github.com/bl0x/learn-fpga-amaranth/blob/main/01_blink/soc.py

from amaranth import *

# Any Elaboratable class is used to generate HDL output
class SOC(Elaboratable):

    def __init__(self):

        # A Signal is usually created with its number of bits (default = 1).
        # Signals declared as instance variables (self.*) are accessible
        # from outside the class (either as input or output).
        # These signals define the external interface of the module.
        self.leds = Signal(5)

    def elaborate(self, platform):

        # Create a new Amaranth module
        m = Module()

        # This is a local signal, which will not be accessible from outside.
        count = Signal(5)

        # In the sync domain all logic is clocked at the positive edge of
        # the implicit clk signal.
        m.d.sync += count.eq(count + 1)

        # The comb domain contains logic that is unclocked and purely
        # combinatorial.
        m.d.comb += self.leds.eq(count)

        return 

soc.v

/* original source https://github.com/bl0x/learn-fpga-amaranth/blob/main/01_blink/soc.py */
/* Generated by Yosys 0.24+10 (git sha1 3ebc50dee, clang 11.0.1-2 -fPIC -Os) */

(* \amaranth.hierarchy  = "top.soc" *)
(* generator = "Amaranth" *)
module soc(rst, clk, leds);
  reg \$auto$verilog_backend.cc:2083:dump_module$1  = 0;
  (* src = "01_blink/soc.py:24" *)
  wire [5:0] \$1 ;
  (* src = "01_blink/soc.py:24" *)
  wire [5:0] \$2 ;
  (* src = "/media/vsuarez/elocaldata/SCRATCH/amaranth/amaranth/hdl/ir.py:527" *)
  input clk;
  wire clk;
  (* src = "01_blink/soc.py:20" *)
  reg [4:0] count = 5'h00;
  (* src = "01_blink/soc.py:20" *)
  reg [4:0] \count$next ;
  (* src = "01_blink/soc.py:12" *)
  output [4:0] leds;
  wire [4:0] leds;
  (* src = "/media/vsuarez/elocaldata/SCRATCH/amaranth/amaranth/hdl/ir.py:527" *)
  input rst;
  wire rst;
  assign \$2  = count + (* src = "01_blink/soc.py:24" *) 1'h1;
  always @(posedge clk)
    count <= \count$next ;
  always @* begin
    if (\$auto$verilog_backend.cc:2083:dump_module$1 ) begin end
    \count$next  = \$2 [4:0];
    (* src = "/media/vsuarez/elocaldata/SCRATCH/amaranth/amaranth/hdl/xfrm.py:516" *)
    casez (rst)
      1'h1:
          \count$next  = 5'h00;
    endcase
  end
  assign \$1  = \$2 ;
  assign leds = count;
endmodule

(* \amaranth.hierarchy  = "top" *)
(* top =  1  *)
(* generator = "Amaranth" *)
module top(clk, rst, leds);
  (* src = "/media/vsuarez/elocaldata/SCRATCH/amaranth/amaranth/hdl/ir.py:527" *)
  input clk;
  wire clk;
  (* src = "/media/vsuarez/elocaldata/SCRATCH/amaranth/amaranth/build/res.py:143" *)
  wire led_0__o;
  (* src = "/media/vsuarez/elocaldata/SCRATCH/amaranth/amaranth/build/res.py:143" *)
  wire led_1__o;
  (* src = "/media/vsuarez/elocaldata/SCRATCH/amaranth/amaranth/build/res.py:143" *)
  wire led_2__o;
  (* src = "/media/vsuarez/elocaldata/SCRATCH/amaranth/amaranth/build/res.py:143" *)
  wire led_3__o;
  (* src = "01_blink/soc.py:12" *)
  output [4:0] leds;
  wire [4:0] leds;
  (* src = "/media/vsuarez/elocaldata/SCRATCH/amaranth/amaranth/build/res.py:143" *)
  wire rgb_led_0__r__o;
  (* src = "/media/vsuarez/elocaldata/SCRATCH/amaranth/amaranth/hdl/ir.py:527" *)
  input rst;
  wire rst;
  soc soc (
    .clk(clk),
    .leds(leds),
    .rst(rst)
  );
  assign rgb_led_0__r__o = leds[4];
  assign led_3__o = leds[3];
  assign led_2__o = leds[2];
  assign led_1__o = leds[1];
  assign led_0__o = leds[0];
endmodule