lfsr.cc

//Automatically generated code

MODULE top
(   uint1 const & clk 
  , uint1 const & reset
  , uint1 & led
)
{
  uint8 var0_lfsr_7_0_;
  uint8 varshl_lfsr_v_22_2_Y;
  uint8 varternary_lfsr_v_22_3_Y;
  uint8 varxor_lfsr_v_22_4_Y;
  uint1 feedback;
  uint8 lfsr;
//-------LOOP-----------
while(always(clk))
{

  led = 1 & lfsr;
  feedback = 1 & (lfsr >> 7);

  varshl_lfsr_v_22_2_Y = lfsr << 1;
  varternary_lfsr_v_22_3_Y = feedback ? 29 : 0;
  varxor_lfsr_v_22_4_Y = varshl_lfsr_v_22_2_Y ^ varternary_lfsr_v_22_3_Y;

  var0_lfsr_7_0_ = lfsr;
  if(reset)
  {
    var0_lfsr_7_0_ = 19;
  }
  else
  {
    var0_lfsr_7_0_ = varxor_lfsr_v_22_4_Y;
  }

  lfsr = var0_lfsr_7_0_;
}
}

lfsr.v

//originally taken from https://8bitworkshop.com/v3.10.0/?platform=verilog&file=lfsr.v

module top(clk, reset, led);
  
  parameter TAPS   = 8'b11101;
  localparam NBITS  = 8;
  
  input clk, reset;
  output led;
  reg [NBITS-1:0] lfsr;

  assign led = lfsr[0];
  wire feedback = lfsr[NBITS-1];

  always @(posedge clk)
  begin
    if (reset)
      lfsr <= 8'h13;
    else
      lfsr <= (lfsr << 1) ^ (feedback ? TAPS : 8'b0);
  end

endmodule

simulator.cpp

#include <stdio.h>
#include <time.h>
#ifdef USE_VERILATOR
#include "types.h"
#include "Vtop.h"
#else
#include "dut.cc"
#endif

int main()
{
  unsigned clk_counter = 0, sum = 0;
  clock_t start_time = clock();

#ifdef USE_VERILATOR
  Vtop&  dut = *new Vtop;

  dut.clk = dut.reset = 0;
  dut.eval();
  dut.clk = dut.reset = 1;
  dut.eval();
  dut.reset = 0;

#else
  uint1 clk, reset, led;
  MODULE dut = top(clk, reset, led);
  
  clk = reset = 0;
  dut.clock();
  clk = reset = 1;
  dut.clock();
  clk = reset = 0;  
#endif

  for(;;)
  {
#ifdef USE_VERILATOR
	dut.clk = 1;
    dut.eval();
	dut.clk = 0;
    dut.eval();
    sum += dut.led;
#else
    dut.clock();
    sum += led;
#endif

    ++clk_counter;
    if(clk_counter >= 1000000000)
      break;
  }

  printf("count %d, sum %d, clock %.0f MHz\n", clk_counter, sum, clk_counter*1e-6*CLOCKS_PER_SEC/(clock()-start_time));
  return 0;
}