top.v

```// -----------------------------------------------------------------------------
// Auto-Generated by:        __   _ __      _  __
//                          / /  (_) /____ | |/_/
//                         / /__/ / __/ -_)>  <
//                        /____/_/\__/\__/_/|_|
//                     Build your hardware, easily!
//                   https://github.com/enjoy-digital/litex
//
// Filename   : digilent_arty.v
// Device     : xc7a35ticsg324-1L
// LiteX sha1 : 356847f7
// Date       : 2023-01-27 10:00:41
//------------------------------------------------------------------------------

`timescale 1ns / 1ps

//------------------------------------------------------------------------------
// Module
//------------------------------------------------------------------------------

module digilent_arty (
    output reg           serial_tx,
    input  wire          serial_rx,
    input  wire          clk100,
    input  wire          user_btn0,
    output wire          vga_hsync,
    output wire          vga_vsync,
    output wire    [3:0] vga_r,
    output wire    [3:0] vga_g,
    output wire    [3:0] vga_b
);


//------------------------------------------------------------------------------
// Signals
//------------------------------------------------------------------------------

reg           soc_rst = 1'd0;
wire          cpu_rst;
reg     [1:0] reset_storage = 2'd0;
reg           reset_re = 1'd0;
reg    [31:0] scratch_storage = 32'd305419896;
reg           scratch_re = 1'd0;
wire   [31:0] bus_errors_status;
wire          bus_errors_we;
reg           bus_errors_re = 1'd0;
reg           bus_error = 1'd0;
reg    [31:0] bus_errors = 32'd0;
reg    [29:0] ram_bus_adr = 30'd0;
reg    [31:0] ram_bus_dat_w = 32'd0;
wire   [31:0] ram_bus_dat_r;
reg     [3:0] ram_bus_sel = 4'd0;
reg           ram_bus_cyc = 1'd0;
reg           ram_bus_stb = 1'd0;
reg           ram_bus_ack = 1'd0;
reg           ram_bus_we = 1'd0;
reg           adr_burst = 1'd0;
wire   [10:0] adr;
wire   [31:0] dat_r;
reg     [3:0] we = 4'd0;
wire   [31:0] dat_w;
wire          tx_sink_valid;
reg           tx_sink_ready = 1'd0;
wire          tx_sink_first;
wire          tx_sink_last;
wire    [7:0] tx_sink_payload_data;
reg     [7:0] tx_data = 8'd0;
reg     [3:0] tx_count = 4'd0;
reg           tx_enable = 1'd0;
reg           tx_tick = 1'd0;
reg    [31:0] tx_phase = 32'd0;
reg           rx_source_valid = 1'd0;
wire          rx_source_ready;
reg           rx_source_first = 1'd0;
reg           rx_source_last = 1'd0;
reg     [7:0] rx_source_payload_data = 8'd0;
reg     [7:0] rx_data = 8'd0;
reg     [3:0] rx_count = 4'd0;
reg           rx_enable = 1'd0;
reg           rx_tick = 1'd0;
reg    [31:0] rx_phase = 32'd0;
wire          rx_rx;
reg           rx_rx_d = 1'd0;
reg           uart_rxtx_re = 1'd0;
wire    [7:0] uart_rxtx_r;
reg           uart_rxtx_we = 1'd0;
wire    [7:0] uart_rxtx_w;
wire          uart_txfull_status;
wire          uart_txfull_we;
reg           uart_txfull_re = 1'd0;
wire          uart_rxempty_status;
wire          uart_rxempty_we;
reg           uart_rxempty_re = 1'd0;
wire          uart_irq;
wire          uart_tx_status;
reg           uart_tx_pending = 1'd0;
wire          uart_tx_trigger;
reg           uart_tx_clear = 1'd0;
reg           uart_tx_trigger_d = 1'd0;
wire          uart_rx_status;
reg           uart_rx_pending = 1'd0;
wire          uart_rx_trigger;
reg           uart_rx_clear = 1'd0;
reg           uart_rx_trigger_d = 1'd0;
wire          uart_tx0;
wire          uart_rx0;
reg     [1:0] uart_status_status = 2'd0;
wire          uart_status_we;
reg           uart_status_re = 1'd0;
wire          uart_tx1;
wire          uart_rx1;
reg     [1:0] uart_pending_status = 2'd0;
wire          uart_pending_we;
reg           uart_pending_re = 1'd0;
reg     [1:0] uart_pending_r = 2'd0;
wire          uart_tx2;
wire          uart_rx2;
reg     [1:0] uart_enable_storage = 2'd0;
reg           uart_enable_re = 1'd0;
wire          uart_txempty_status;
wire          uart_txempty_we;
reg           uart_txempty_re = 1'd0;
wire          uart_rxfull_status;
wire          uart_rxfull_we;
reg           uart_rxfull_re = 1'd0;
wire          uart_uart_sink_valid;
wire          uart_uart_sink_ready;
wire          uart_uart_sink_first;
wire          uart_uart_sink_last;
wire    [7:0] uart_uart_sink_payload_data;
wire          uart_uart_source_valid;
wire          uart_uart_source_ready;
wire          uart_uart_source_first;
wire          uart_uart_source_last;
wire    [7:0] uart_uart_source_payload_data;
wire          uart_tx_fifo_sink_valid;
wire          uart_tx_fifo_sink_ready;
reg           uart_tx_fifo_sink_first = 1'd0;
reg           uart_tx_fifo_sink_last = 1'd0;
wire    [7:0] uart_tx_fifo_sink_payload_data;
wire          uart_tx_fifo_source_valid;
wire          uart_tx_fifo_source_ready;
wire          uart_tx_fifo_source_first;
wire          uart_tx_fifo_source_last;
wire    [7:0] uart_tx_fifo_source_payload_data;
wire          uart_tx_fifo_re;
reg           uart_tx_fifo_readable = 1'd0;
wire          uart_tx_fifo_syncfifo_we;
wire          uart_tx_fifo_syncfifo_writable;
wire          uart_tx_fifo_syncfifo_re;
wire          uart_tx_fifo_syncfifo_readable;
wire    [9:0] uart_tx_fifo_syncfifo_din;
wire    [9:0] uart_tx_fifo_syncfifo_dout;
reg     [4:0] uart_tx_fifo_level0 = 5'd0;
reg           uart_tx_fifo_replace = 1'd0;
reg     [3:0] uart_tx_fifo_produce = 4'd0;
reg     [3:0] uart_tx_fifo_consume = 4'd0;
reg     [3:0] uart_tx_fifo_wrport_adr = 4'd0;
wire    [9:0] uart_tx_fifo_wrport_dat_r;
wire          uart_tx_fifo_wrport_we;
wire    [9:0] uart_tx_fifo_wrport_dat_w;
wire          uart_tx_fifo_do_read;
wire    [3:0] uart_tx_fifo_rdport_adr;
wire    [9:0] uart_tx_fifo_rdport_dat_r;
wire          uart_tx_fifo_rdport_re;
wire    [4:0] uart_tx_fifo_level1;
wire    [7:0] uart_tx_fifo_fifo_in_payload_data;
wire          uart_tx_fifo_fifo_in_first;
wire          uart_tx_fifo_fifo_in_last;
wire    [7:0] uart_tx_fifo_fifo_out_payload_data;
wire          uart_tx_fifo_fifo_out_first;
wire          uart_tx_fifo_fifo_out_last;
wire          uart_rx_fifo_sink_valid;
wire          uart_rx_fifo_sink_ready;
wire          uart_rx_fifo_sink_first;
wire          uart_rx_fifo_sink_last;
wire    [7:0] uart_rx_fifo_sink_payload_data;
wire          uart_rx_fifo_source_valid;
wire          uart_rx_fifo_source_ready;
wire          uart_rx_fifo_source_first;
wire          uart_rx_fifo_source_last;
wire    [7:0] uart_rx_fifo_source_payload_data;
wire          uart_rx_fifo_re;
reg           uart_rx_fifo_readable = 1'd0;
wire          uart_rx_fifo_syncfifo_we;
wire          uart_rx_fifo_syncfifo_writable;
wire          uart_rx_fifo_syncfifo_re;
wire          uart_rx_fifo_syncfifo_readable;
wire    [9:0] uart_rx_fifo_syncfifo_din;
wire    [9:0] uart_rx_fifo_syncfifo_dout;
reg     [4:0] uart_rx_fifo_level0 = 5'd0;
reg           uart_rx_fifo_replace = 1'd0;
reg     [3:0] uart_rx_fifo_produce = 4'd0;
reg     [3:0] uart_rx_fifo_consume = 4'd0;
reg     [3:0] uart_rx_fifo_wrport_adr = 4'd0;
wire    [9:0] uart_rx_fifo_wrport_dat_r;
wire          uart_rx_fifo_wrport_we;
wire    [9:0] uart_rx_fifo_wrport_dat_w;
wire          uart_rx_fifo_do_read;
wire    [3:0] uart_rx_fifo_rdport_adr;
wire    [9:0] uart_rx_fifo_rdport_dat_r;
wire          uart_rx_fifo_rdport_re;
wire    [4:0] uart_rx_fifo_level1;
wire    [7:0] uart_rx_fifo_fifo_in_payload_data;
wire          uart_rx_fifo_fifo_in_first;
wire          uart_rx_fifo_fifo_in_last;
wire    [7:0] uart_rx_fifo_fifo_out_payload_data;
wire          uart_rx_fifo_fifo_out_first;
wire          uart_rx_fifo_fifo_out_last;
reg    [31:0] timer_load_storage = 32'd0;
reg           timer_load_re = 1'd0;
reg    [31:0] timer_reload_storage = 32'd0;
reg           timer_reload_re = 1'd0;
reg           timer_en_storage = 1'd0;
reg           timer_en_re = 1'd0;
reg           timer_update_value_storage = 1'd0;
reg           timer_update_value_re = 1'd0;
reg    [31:0] timer_value_status = 32'd0;
wire          timer_value_we;
reg           timer_value_re = 1'd0;
wire          timer_irq;
wire          timer_zero_status;
reg           timer_zero_pending = 1'd0;
wire          timer_zero_trigger;
reg           timer_zero_clear = 1'd0;
reg           timer_zero_trigger_d = 1'd0;
wire          timer_zero0;
wire          timer_status_status;
wire          timer_status_we;
reg           timer_status_re = 1'd0;
wire          timer_zero1;
wire          timer_pending_status;
wire          timer_pending_we;
reg           timer_pending_re = 1'd0;
reg           timer_pending_r = 1'd0;
wire          timer_zero2;
reg           timer_enable_storage = 1'd0;
reg           timer_enable_re = 1'd0;
reg    [31:0] timer_value = 32'd0;
reg           crg_rst = 1'd0;
wire          sys_clk;
wire          sys_rst;
wire          crg_reset;
reg           crg_power_down = 1'd0;
wire          crg_locked;
wire          crg_clkin;
wire          crg_clkout0;
wire          crg_clkout_buf0;
wire          vga_clk;
wire          vga_rst;
wire          crg_clkout1;
wire          crg_clkout_buf1;
wire          sink_valid;
wire          sink_ready;
wire          sink_first;
wire          sink_last;
wire          sink_payload_hsync;
wire          sink_payload_vsync;
wire          sink_payload_de;
wire    [7:0] sink_payload_r;
wire    [7:0] sink_payload_g;
wire    [7:0] sink_payload_b;
reg           vtg_enable_storage = 1'd1;
reg           vtg_enable_re = 1'd0;
reg    [11:0] vtg_hres_storage = 12'd640;
reg           vtg_hres_re = 1'd0;
reg    [11:0] vtg_hsync_start_storage = 12'd656;
reg           vtg_hsync_start_re = 1'd0;
reg    [11:0] vtg_hsync_end_storage = 12'd752;
reg           vtg_hsync_end_re = 1'd0;
reg    [11:0] vtg_hscan_storage = 12'd799;
reg           vtg_hscan_re = 1'd0;
reg    [11:0] vtg_vres_storage = 12'd480;
reg           vtg_vres_re = 1'd0;
reg    [11:0] vtg_vsync_start_storage = 12'd490;
reg           vtg_vsync_start_re = 1'd0;
reg    [11:0] vtg_vsync_end_storage = 12'd492;
reg           vtg_vsync_end_re = 1'd0;
reg    [11:0] vtg_vscan_storage = 12'd524;
reg           vtg_vscan_re = 1'd0;
reg           vtg_source_valid = 1'd0;
wire          vtg_source_ready;
reg           vtg_source_first = 1'd0;
reg           vtg_source_last = 1'd0;
reg           vtg_source_payload_hsync = 1'd0;
reg           vtg_source_payload_vsync = 1'd0;
wire          vtg_source_payload_de;
reg    [11:0] vtg_source_payload_hres = 12'd0;
reg    [11:0] vtg_source_payload_vres = 12'd0;
reg    [11:0] vtg_source_payload_hcount = 12'd0;
reg    [11:0] vtg_source_payload_vcount = 12'd0;
wire          vtg_enable;
wire   [11:0] vtg_hres;
wire   [11:0] vtg_hsync_start;
wire   [11:0] vtg_hsync_end;
wire   [11:0] vtg_hscan;
wire   [11:0] vtg_vres;
wire   [11:0] vtg_vsync_start;
wire   [11:0] vtg_vsync_end;
wire   [11:0] vtg_vscan;
reg           vtg_hactive = 1'd0;
reg           vtg_vactive = 1'd0;
wire          vtg_reset;
wire          graphics_vtg_sink_valid;
wire          graphics_vtg_sink_ready;
wire          graphics_vtg_sink_first;
wire          graphics_vtg_sink_last;
wire          graphics_vtg_sink_payload_hsync;
wire          graphics_vtg_sink_payload_vsync;
wire          graphics_vtg_sink_payload_de;
wire   [11:0] graphics_vtg_sink_payload_hres;
wire   [11:0] graphics_vtg_sink_payload_vres;
wire   [11:0] graphics_vtg_sink_payload_hcount;
wire   [11:0] graphics_vtg_sink_payload_vcount;
wire          graphics_source_valid;
wire          graphics_source_ready;
reg           graphics_source_first = 1'd0;
wire          graphics_source_last;
wire          graphics_source_payload_hsync;
wire          graphics_source_payload_vsync;
wire          graphics_source_payload_de;
wire    [7:0] graphics_source_payload_r;
wire    [7:0] graphics_source_payload_g;
wire    [7:0] graphics_source_payload_b;
reg    [13:0] soccore_adr = 14'd0;
reg           soccore_we = 1'd0;
reg    [31:0] soccore_dat_w = 32'd0;
wire   [31:0] soccore_dat_r;
reg    [29:0] soccore_wishbone_adr = 30'd0;
reg    [31:0] soccore_wishbone_dat_w = 32'd0;
reg    [31:0] soccore_wishbone_dat_r = 32'd0;
reg     [3:0] soccore_wishbone_sel = 4'd0;
reg           soccore_wishbone_cyc = 1'd0;
reg           soccore_wishbone_stb = 1'd0;
reg           soccore_wishbone_ack = 1'd0;
reg           soccore_wishbone_we = 1'd0;
wire   [13:0] interface0_bank_bus_adr;
wire          interface0_bank_bus_we;
wire   [31:0] interface0_bank_bus_dat_w;
reg    [31:0] interface0_bank_bus_dat_r = 32'd0;
reg           csrbank0_reset0_re = 1'd0;
wire    [1:0] csrbank0_reset0_r;
reg           csrbank0_reset0_we = 1'd0;
wire    [1:0] csrbank0_reset0_w;
reg           csrbank0_scratch0_re = 1'd0;
wire   [31:0] csrbank0_scratch0_r;
reg           csrbank0_scratch0_we = 1'd0;
wire   [31:0] csrbank0_scratch0_w;
reg           csrbank0_bus_errors_re = 1'd0;
wire   [31:0] csrbank0_bus_errors_r;
reg           csrbank0_bus_errors_we = 1'd0;
wire   [31:0] csrbank0_bus_errors_w;
wire          csrbank0_sel;
wire   [13:0] interface1_bank_bus_adr;
wire          interface1_bank_bus_we;
wire   [31:0] interface1_bank_bus_dat_w;
reg    [31:0] interface1_bank_bus_dat_r = 32'd0;
reg           csrbank1_load0_re = 1'd0;
wire   [31:0] csrbank1_load0_r;
reg           csrbank1_load0_we = 1'd0;
wire   [31:0] csrbank1_load0_w;
reg           csrbank1_reload0_re = 1'd0;
wire   [31:0] csrbank1_reload0_r;
reg           csrbank1_reload0_we = 1'd0;
wire   [31:0] csrbank1_reload0_w;
reg           csrbank1_en0_re = 1'd0;
wire          csrbank1_en0_r;
reg           csrbank1_en0_we = 1'd0;
wire          csrbank1_en0_w;
reg           csrbank1_update_value0_re = 1'd0;
wire          csrbank1_update_value0_r;
reg           csrbank1_update_value0_we = 1'd0;
wire          csrbank1_update_value0_w;
reg           csrbank1_value_re = 1'd0;
wire   [31:0] csrbank1_value_r;
reg           csrbank1_value_we = 1'd0;
wire   [31:0] csrbank1_value_w;
reg           csrbank1_ev_status_re = 1'd0;
wire          csrbank1_ev_status_r;
reg           csrbank1_ev_status_we = 1'd0;
wire          csrbank1_ev_status_w;
reg           csrbank1_ev_pending_re = 1'd0;
wire          csrbank1_ev_pending_r;
reg           csrbank1_ev_pending_we = 1'd0;
wire          csrbank1_ev_pending_w;
reg           csrbank1_ev_enable0_re = 1'd0;
wire          csrbank1_ev_enable0_r;
reg           csrbank1_ev_enable0_we = 1'd0;
wire          csrbank1_ev_enable0_w;
wire          csrbank1_sel;
wire   [13:0] interface2_bank_bus_adr;
wire          interface2_bank_bus_we;
wire   [31:0] interface2_bank_bus_dat_w;
reg    [31:0] interface2_bank_bus_dat_r = 32'd0;
reg           csrbank2_txfull_re = 1'd0;
wire          csrbank2_txfull_r;
reg           csrbank2_txfull_we = 1'd0;
wire          csrbank2_txfull_w;
reg           csrbank2_rxempty_re = 1'd0;
wire          csrbank2_rxempty_r;
reg           csrbank2_rxempty_we = 1'd0;
wire          csrbank2_rxempty_w;
reg           csrbank2_ev_status_re = 1'd0;
wire    [1:0] csrbank2_ev_status_r;
reg           csrbank2_ev_status_we = 1'd0;
wire    [1:0] csrbank2_ev_status_w;
reg           csrbank2_ev_pending_re = 1'd0;
wire    [1:0] csrbank2_ev_pending_r;
reg           csrbank2_ev_pending_we = 1'd0;
wire    [1:0] csrbank2_ev_pending_w;
reg           csrbank2_ev_enable0_re = 1'd0;
wire    [1:0] csrbank2_ev_enable0_r;
reg           csrbank2_ev_enable0_we = 1'd0;
wire    [1:0] csrbank2_ev_enable0_w;
reg           csrbank2_txempty_re = 1'd0;
wire          csrbank2_txempty_r;
reg           csrbank2_txempty_we = 1'd0;
wire          csrbank2_txempty_w;
reg           csrbank2_rxfull_re = 1'd0;
wire          csrbank2_rxfull_r;
reg           csrbank2_rxfull_we = 1'd0;
wire          csrbank2_rxfull_w;
wire          csrbank2_sel;
wire   [13:0] interface3_bank_bus_adr;
wire          interface3_bank_bus_we;
wire   [31:0] interface3_bank_bus_dat_w;
reg    [31:0] interface3_bank_bus_dat_r = 32'd0;
reg           csrbank3_enable0_re = 1'd0;
wire          csrbank3_enable0_r;
reg           csrbank3_enable0_we = 1'd0;
wire          csrbank3_enable0_w;
reg           csrbank3_hres0_re = 1'd0;
wire   [11:0] csrbank3_hres0_r;
reg           csrbank3_hres0_we = 1'd0;
wire   [11:0] csrbank3_hres0_w;
reg           csrbank3_hsync_start0_re = 1'd0;
wire   [11:0] csrbank3_hsync_start0_r;
reg           csrbank3_hsync_start0_we = 1'd0;
wire   [11:0] csrbank3_hsync_start0_w;
reg           csrbank3_hsync_end0_re = 1'd0;
wire   [11:0] csrbank3_hsync_end0_r;
reg           csrbank3_hsync_end0_we = 1'd0;
wire   [11:0] csrbank3_hsync_end0_w;
reg           csrbank3_hscan0_re = 1'd0;
wire   [11:0] csrbank3_hscan0_r;
reg           csrbank3_hscan0_we = 1'd0;
wire   [11:0] csrbank3_hscan0_w;
reg           csrbank3_vres0_re = 1'd0;
wire   [11:0] csrbank3_vres0_r;
reg           csrbank3_vres0_we = 1'd0;
wire   [11:0] csrbank3_vres0_w;
reg           csrbank3_vsync_start0_re = 1'd0;
wire   [11:0] csrbank3_vsync_start0_r;
reg           csrbank3_vsync_start0_we = 1'd0;
wire   [11:0] csrbank3_vsync_start0_w;
reg           csrbank3_vsync_end0_re = 1'd0;
wire   [11:0] csrbank3_vsync_end0_r;
reg           csrbank3_vsync_end0_we = 1'd0;
wire   [11:0] csrbank3_vsync_end0_w;
reg           csrbank3_vscan0_re = 1'd0;
wire   [11:0] csrbank3_vscan0_r;
reg           csrbank3_vscan0_we = 1'd0;
wire   [11:0] csrbank3_vscan0_w;
wire          csrbank3_sel;
wire   [13:0] csr_interconnect_adr;
wire          csr_interconnect_we;
wire   [31:0] csr_interconnect_dat_w;
wire   [31:0] csr_interconnect_dat_r;
reg           soccore_rs232phytx_state = 1'd0;
reg           soccore_rs232phytx_next_state = 1'd0;
reg     [3:0] tx_count_rs232phytx_next_value0 = 4'd0;
reg           tx_count_rs232phytx_next_value_ce0 = 1'd0;
reg           serial_tx_rs232phytx_next_value1 = 1'd0;
reg           serial_tx_rs232phytx_next_value_ce1 = 1'd0;
reg     [7:0] tx_data_rs232phytx_next_value2 = 8'd0;
reg           tx_data_rs232phytx_next_value_ce2 = 1'd0;
reg           soccore_rs232phyrx_state = 1'd0;
reg           soccore_rs232phyrx_next_state = 1'd0;
reg     [3:0] rx_count_rs232phyrx_next_value0 = 4'd0;
reg           rx_count_rs232phyrx_next_value_ce0 = 1'd0;
reg     [7:0] rx_data_rs232phyrx_next_value1 = 8'd0;
reg           rx_data_rs232phyrx_next_value_ce1 = 1'd0;
wire          soccore_reset0;
wire          soccore_reset1;
wire          soccore_reset2;
wire          soccore_reset3;
wire          soccore_reset4;
wire          soccore_reset5;
wire          soccore_reset6;
wire          soccore_reset7;
wire          soccore_pll_fb;
reg           soccore_clockdomainsrenamer_state = 1'd0;
reg           soccore_clockdomainsrenamer_next_state = 1'd0;
reg           vtg_hactive_next_value0 = 1'd0;
reg           vtg_hactive_next_value_ce0 = 1'd0;
reg           vtg_vactive_next_value1 = 1'd0;
reg           vtg_vactive_next_value_ce1 = 1'd0;
reg    [11:0] vtg_source_payload_hres_next_value2 = 12'd0;
reg           vtg_source_payload_hres_next_value_ce2 = 1'd0;
reg    [11:0] vtg_source_payload_vres_next_value3 = 12'd0;
reg           vtg_source_payload_vres_next_value_ce3 = 1'd0;
reg    [11:0] vtg_source_payload_hcount_next_value4 = 12'd0;
reg           vtg_source_payload_hcount_next_value_ce4 = 1'd0;
reg    [11:0] vtg_source_payload_vcount_next_value5 = 12'd0;
reg           vtg_source_payload_vcount_next_value_ce5 = 1'd0;
reg           vtg_source_payload_hsync_next_value6 = 1'd0;
reg           vtg_source_payload_hsync_next_value_ce6 = 1'd0;
reg           vtg_source_payload_vsync_next_value7 = 1'd0;
reg           vtg_source_payload_vsync_next_value_ce7 = 1'd0;
reg           soccore_wishbone2csr_state = 1'd0;
reg           soccore_wishbone2csr_next_state = 1'd0;
reg           xilinxmultiregimpl0_regs0 = 1'd0;
reg           xilinxmultiregimpl0_regs1 = 1'd0;
wire          xilinxasyncresetsynchronizerimpl0;
wire          xilinxasyncresetsynchronizerimpl0_rst_meta;
wire          xilinxasyncresetsynchronizerimpl1;
wire          xilinxasyncresetsynchronizerimpl1_rst_meta;
reg           xilinxmultiregimpl1_regs0 = 1'd0;
reg           xilinxmultiregimpl1_regs1 = 1'd0;
reg    [11:0] xilinxmultiregimpl2_regs0 = 12'd0;
reg    [11:0] xilinxmultiregimpl2_regs1 = 12'd0;
reg    [11:0] xilinxmultiregimpl3_regs0 = 12'd0;
reg    [11:0] xilinxmultiregimpl3_regs1 = 12'd0;
reg    [11:0] xilinxmultiregimpl4_regs0 = 12'd0;
reg    [11:0] xilinxmultiregimpl4_regs1 = 12'd0;
reg    [11:0] xilinxmultiregimpl5_regs0 = 12'd0;
reg    [11:0] xilinxmultiregimpl5_regs1 = 12'd0;
reg    [11:0] xilinxmultiregimpl6_regs0 = 12'd0;
reg    [11:0] xilinxmultiregimpl6_regs1 = 12'd0;
reg    [11:0] xilinxmultiregimpl7_regs0 = 12'd0;
reg    [11:0] xilinxmultiregimpl7_regs1 = 12'd0;
reg    [11:0] xilinxmultiregimpl8_regs0 = 12'd0;
reg    [11:0] xilinxmultiregimpl8_regs1 = 12'd0;
reg    [11:0] xilinxmultiregimpl9_regs0 = 12'd0;
reg    [11:0] xilinxmultiregimpl9_regs1 = 12'd0;

//------------------------------------------------------------------------------
// Combinatorial Logic
//------------------------------------------------------------------------------

assign graphics_vtg_sink_valid = vtg_source_valid;
assign vtg_source_ready = graphics_vtg_sink_ready;
assign graphics_vtg_sink_first = vtg_source_first;
assign graphics_vtg_sink_last = vtg_source_last;
assign graphics_vtg_sink_payload_hsync = vtg_source_payload_hsync;
assign graphics_vtg_sink_payload_vsync = vtg_source_payload_vsync;
assign graphics_vtg_sink_payload_de = vtg_source_payload_de;
assign graphics_vtg_sink_payload_hres = vtg_source_payload_hres;
assign graphics_vtg_sink_payload_vres = vtg_source_payload_vres;
assign graphics_vtg_sink_payload_hcount = vtg_source_payload_hcount;
assign graphics_vtg_sink_payload_vcount = vtg_source_payload_vcount;
assign sink_valid = graphics_source_valid;
assign graphics_source_ready = sink_ready;
assign sink_first = graphics_source_first;
assign sink_last = graphics_source_last;
assign sink_payload_hsync = graphics_source_payload_hsync;
assign sink_payload_vsync = graphics_source_payload_vsync;
assign sink_payload_de = graphics_source_payload_de;
assign sink_payload_r = graphics_source_payload_r;
assign sink_payload_g = graphics_source_payload_g;
assign sink_payload_b = graphics_source_payload_b;
always @(*) begin
    crg_rst <= 1'd0;
    if (soc_rst) begin
        crg_rst <= 1'd1;
    end
end
assign bus_errors_status = bus_errors;
always @(*) begin
    soc_rst <= 1'd0;
    if (reset_re) begin
        soc_rst <= reset_storage[0];
    end
end
assign cpu_rst = reset_storage[1];
assign csrbank0_reset0_w = reset_storage[1:0];
assign csrbank0_scratch0_w = scratch_storage[31:0];
assign csrbank0_bus_errors_w = bus_errors_status[31:0];
assign bus_errors_we = csrbank0_bus_errors_we;
always @(*) begin
    we <= 4'd0;
    we[0] <= (((ram_bus_cyc & ram_bus_stb) & ram_bus_we) & ram_bus_sel[0]);
    we[1] <= (((ram_bus_cyc & ram_bus_stb) & ram_bus_we) & ram_bus_sel[1]);
    we[2] <= (((ram_bus_cyc & ram_bus_stb) & ram_bus_we) & ram_bus_sel[2]);
    we[3] <= (((ram_bus_cyc & ram_bus_stb) & ram_bus_we) & ram_bus_sel[3]);
end
assign adr = ram_bus_adr[10:0];
assign ram_bus_dat_r = dat_r;
assign dat_w = ram_bus_dat_w;
always @(*) begin
    tx_count_rs232phytx_next_value0 <= 4'd0;
    tx_count_rs232phytx_next_value_ce0 <= 1'd0;
    serial_tx_rs232phytx_next_value1 <= 1'd0;
    serial_tx_rs232phytx_next_value_ce1 <= 1'd0;
    tx_sink_ready <= 1'd0;
    tx_data_rs232phytx_next_value2 <= 8'd0;
    tx_data_rs232phytx_next_value_ce2 <= 1'd0;
    tx_enable <= 1'd0;
    soccore_rs232phytx_next_state <= 1'd0;
    soccore_rs232phytx_next_state <= soccore_rs232phytx_state;
    case (soccore_rs232phytx_state)
        1'd1: begin
            tx_enable <= 1'd1;
            if (tx_tick) begin
                serial_tx_rs232phytx_next_value1 <= tx_data;
                serial_tx_rs232phytx_next_value_ce1 <= 1'd1;
                tx_count_rs232phytx_next_value0 <= (tx_count + 1'd1);
                tx_count_rs232phytx_next_value_ce0 <= 1'd1;
                tx_data_rs232phytx_next_value2 <= {1'd1, tx_data[7:1]};
                tx_data_rs232phytx_next_value_ce2 <= 1'd1;
                if ((tx_count == 4'd9)) begin
                    tx_sink_ready <= 1'd1;
                    soccore_rs232phytx_next_state <= 1'd0;
                end
            end
        end
        default: begin
            tx_count_rs232phytx_next_value0 <= 1'd0;
            tx_count_rs232phytx_next_value_ce0 <= 1'd1;
            serial_tx_rs232phytx_next_value1 <= 1'd1;
            serial_tx_rs232phytx_next_value_ce1 <= 1'd1;
            if (tx_sink_valid) begin
                serial_tx_rs232phytx_next_value1 <= 1'd0;
                serial_tx_rs232phytx_next_value_ce1 <= 1'd1;
                tx_data_rs232phytx_next_value2 <= tx_sink_payload_data;
                tx_data_rs232phytx_next_value_ce2 <= 1'd1;
                soccore_rs232phytx_next_state <= 1'd1;
            end
        end
    endcase
end
always @(*) begin
    soccore_rs232phyrx_next_state <= 1'd0;
    rx_count_rs232phyrx_next_value0 <= 4'd0;
    rx_count_rs232phyrx_next_value_ce0 <= 1'd0;
    rx_source_valid <= 1'd0;
    rx_data_rs232phyrx_next_value1 <= 8'd0;
    rx_data_rs232phyrx_next_value_ce1 <= 1'd0;
    rx_source_payload_data <= 8'd0;
    rx_enable <= 1'd0;
    soccore_rs232phyrx_next_state <= soccore_rs232phyrx_state;
    case (soccore_rs232phyrx_state)
        1'd1: begin
            rx_enable <= 1'd1;
            if (rx_tick) begin
                rx_count_rs232phyrx_next_value0 <= (rx_count + 1'd1);
                rx_count_rs232phyrx_next_value_ce0 <= 1'd1;
                rx_data_rs232phyrx_next_value1 <= {rx_rx, rx_data[7:1]};
                rx_data_rs232phyrx_next_value_ce1 <= 1'd1;
                if ((rx_count == 4'd9)) begin
                    rx_source_valid <= (rx_rx == 1'd1);
                    rx_source_payload_data <= rx_data;
                    soccore_rs232phyrx_next_state <= 1'd0;
                end
            end
        end
        default: begin
            rx_count_rs232phyrx_next_value0 <= 1'd0;
            rx_count_rs232phyrx_next_value_ce0 <= 1'd1;
            if (((rx_rx == 1'd0) & (rx_rx_d == 1'd1))) begin
                soccore_rs232phyrx_next_state <= 1'd1;
            end
        end
    endcase
end
assign uart_uart_sink_valid = rx_source_valid;
assign rx_source_ready = uart_uart_sink_ready;
assign uart_uart_sink_first = rx_source_first;
assign uart_uart_sink_last = rx_source_last;
assign uart_uart_sink_payload_data = rx_source_payload_data;
assign tx_sink_valid = uart_uart_source_valid;
assign uart_uart_source_ready = tx_sink_ready;
assign tx_sink_first = uart_uart_source_first;
assign tx_sink_last = uart_uart_source_last;
assign tx_sink_payload_data = uart_uart_source_payload_data;
assign uart_tx_fifo_sink_valid = uart_rxtx_re;
assign uart_tx_fifo_sink_payload_data = uart_rxtx_r;
assign uart_uart_source_valid = uart_tx_fifo_source_valid;
assign uart_tx_fifo_source_ready = uart_uart_source_ready;
assign uart_uart_source_first = uart_tx_fifo_source_first;
assign uart_uart_source_last = uart_tx_fifo_source_last;
assign uart_uart_source_payload_data = uart_tx_fifo_source_payload_data;
assign uart_txfull_status = (~uart_tx_fifo_sink_ready);
assign uart_txempty_status = (~uart_tx_fifo_source_valid);
assign uart_tx_trigger = uart_tx_fifo_sink_ready;
assign uart_rx_fifo_sink_valid = uart_uart_sink_valid;
assign uart_uart_sink_ready = uart_rx_fifo_sink_ready;
assign uart_rx_fifo_sink_first = uart_uart_sink_first;
assign uart_rx_fifo_sink_last = uart_uart_sink_last;
assign uart_rx_fifo_sink_payload_data = uart_uart_sink_payload_data;
assign uart_rxtx_w = uart_rx_fifo_source_payload_data;
assign uart_rx_fifo_source_ready = (uart_rx_clear | (1'd0 & uart_rxtx_we));
assign uart_rxempty_status = (~uart_rx_fifo_source_valid);
assign uart_rxfull_status = (~uart_rx_fifo_sink_ready);
assign uart_rx_trigger = uart_rx_fifo_source_valid;
assign uart_tx0 = uart_tx_status;
assign uart_tx1 = uart_tx_pending;
always @(*) begin
    uart_tx_clear <= 1'd0;
    if ((uart_pending_re & uart_pending_r[0])) begin
        uart_tx_clear <= 1'd1;
    end
end
assign uart_rx0 = uart_rx_status;
assign uart_rx1 = uart_rx_pending;
always @(*) begin
    uart_rx_clear <= 1'd0;
    if ((uart_pending_re & uart_pending_r[1])) begin
        uart_rx_clear <= 1'd1;
    end
end
assign uart_irq = ((uart_pending_status[0] & uart_enable_storage[0]) | (uart_pending_status[1] & uart_enable_storage[1]));
assign uart_tx_status = uart_tx_trigger;
assign uart_rx_status = uart_rx_trigger;
assign uart_tx_fifo_syncfifo_din = {uart_tx_fifo_fifo_in_last, uart_tx_fifo_fifo_in_first, uart_tx_fifo_fifo_in_payload_data};
assign {uart_tx_fifo_fifo_out_last, uart_tx_fifo_fifo_out_first, uart_tx_fifo_fifo_out_payload_data} = uart_tx_fifo_syncfifo_dout;
assign uart_tx_fifo_sink_ready = uart_tx_fifo_syncfifo_writable;
assign uart_tx_fifo_syncfifo_we = uart_tx_fifo_sink_valid;
assign uart_tx_fifo_fifo_in_first = uart_tx_fifo_sink_first;
assign uart_tx_fifo_fifo_in_last = uart_tx_fifo_sink_last;
assign uart_tx_fifo_fifo_in_payload_data = uart_tx_fifo_sink_payload_data;
assign uart_tx_fifo_source_valid = uart_tx_fifo_readable;
assign uart_tx_fifo_source_first = uart_tx_fifo_fifo_out_first;
assign uart_tx_fifo_source_last = uart_tx_fifo_fifo_out_last;
assign uart_tx_fifo_source_payload_data = uart_tx_fifo_fifo_out_payload_data;
assign uart_tx_fifo_re = uart_tx_fifo_source_ready;
assign uart_tx_fifo_syncfifo_re = (uart_tx_fifo_syncfifo_readable & ((~uart_tx_fifo_readable) | uart_tx_fifo_re));
assign uart_tx_fifo_level1 = (uart_tx_fifo_level0 + uart_tx_fifo_readable);
always @(*) begin
    uart_tx_fifo_wrport_adr <= 4'd0;
    if (uart_tx_fifo_replace) begin
        uart_tx_fifo_wrport_adr <= (uart_tx_fifo_produce - 1'd1);
    end else begin
        uart_tx_fifo_wrport_adr <= uart_tx_fifo_produce;
    end
end
assign uart_tx_fifo_wrport_dat_w = uart_tx_fifo_syncfifo_din;
assign uart_tx_fifo_wrport_we = (uart_tx_fifo_syncfifo_we & (uart_tx_fifo_syncfifo_writable | uart_tx_fifo_replace));
assign uart_tx_fifo_do_read = (uart_tx_fifo_syncfifo_readable & uart_tx_fifo_syncfifo_re);
assign uart_tx_fifo_rdport_adr = uart_tx_fifo_consume;
assign uart_tx_fifo_syncfifo_dout = uart_tx_fifo_rdport_dat_r;
assign uart_tx_fifo_rdport_re = uart_tx_fifo_do_read;
assign uart_tx_fifo_syncfifo_writable = (uart_tx_fifo_level0 != 5'd16);
assign uart_tx_fifo_syncfifo_readable = (uart_tx_fifo_level0 != 1'd0);
assign uart_rx_fifo_syncfifo_din = {uart_rx_fifo_fifo_in_last, uart_rx_fifo_fifo_in_first, uart_rx_fifo_fifo_in_payload_data};
assign {uart_rx_fifo_fifo_out_last, uart_rx_fifo_fifo_out_first, uart_rx_fifo_fifo_out_payload_data} = uart_rx_fifo_syncfifo_dout;
assign uart_rx_fifo_sink_ready = uart_rx_fifo_syncfifo_writable;
assign uart_rx_fifo_syncfifo_we = uart_rx_fifo_sink_valid;
assign uart_rx_fifo_fifo_in_first = uart_rx_fifo_sink_first;
assign uart_rx_fifo_fifo_in_last = uart_rx_fifo_sink_last;
assign uart_rx_fifo_fifo_in_payload_data = uart_rx_fifo_sink_payload_data;
assign uart_rx_fifo_source_valid = uart_rx_fifo_readable;
assign uart_rx_fifo_source_first = uart_rx_fifo_fifo_out_first;
assign uart_rx_fifo_source_last = uart_rx_fifo_fifo_out_last;
assign uart_rx_fifo_source_payload_data = uart_rx_fifo_fifo_out_payload_data;
assign uart_rx_fifo_re = uart_rx_fifo_source_ready;
assign uart_rx_fifo_syncfifo_re = (uart_rx_fifo_syncfifo_readable & ((~uart_rx_fifo_readable) | uart_rx_fifo_re));
assign uart_rx_fifo_level1 = (uart_rx_fifo_level0 + uart_rx_fifo_readable);
always @(*) begin
    uart_rx_fifo_wrport_adr <= 4'd0;
    if (uart_rx_fifo_replace) begin
        uart_rx_fifo_wrport_adr <= (uart_rx_fifo_produce - 1'd1);
    end else begin
        uart_rx_fifo_wrport_adr <= uart_rx_fifo_produce;
    end
end
assign uart_rx_fifo_wrport_dat_w = uart_rx_fifo_syncfifo_din;
assign uart_rx_fifo_wrport_we = (uart_rx_fifo_syncfifo_we & (uart_rx_fifo_syncfifo_writable | uart_rx_fifo_replace));
assign uart_rx_fifo_do_read = (uart_rx_fifo_syncfifo_readable & uart_rx_fifo_syncfifo_re);
assign uart_rx_fifo_rdport_adr = uart_rx_fifo_consume;
assign uart_rx_fifo_syncfifo_dout = uart_rx_fifo_rdport_dat_r;
assign uart_rx_fifo_rdport_re = uart_rx_fifo_do_read;
assign uart_rx_fifo_syncfifo_writable = (uart_rx_fifo_level0 != 5'd16);
assign uart_rx_fifo_syncfifo_readable = (uart_rx_fifo_level0 != 1'd0);
assign timer_zero_trigger = (timer_value == 1'd0);
assign timer_zero0 = timer_zero_status;
assign timer_zero1 = timer_zero_pending;
always @(*) begin
    timer_zero_clear <= 1'd0;
    if ((timer_pending_re & timer_pending_r)) begin
        timer_zero_clear <= 1'd1;
    end
end
assign timer_irq = (timer_pending_status & timer_enable_storage);
assign timer_zero_status = timer_zero_trigger;
assign crg_reset = (1'd0 | crg_rst);
assign crg_clkin = clk100;
assign sys_clk = crg_clkout_buf0;
assign vga_clk = crg_clkout_buf1;
assign sink_ready = 1'd1;
assign vtg_reset = (~vtg_enable);
assign vtg_source_payload_de = (vtg_hactive & vtg_vactive);
always @(*) begin
    vtg_source_valid <= 1'd0;
    soccore_clockdomainsrenamer_next_state <= 1'd0;
    vtg_hactive_next_value0 <= 1'd0;
    vtg_source_payload_vsync_next_value7 <= 1'd0;
    vtg_hactive_next_value_ce0 <= 1'd0;
    vtg_source_payload_vsync_next_value_ce7 <= 1'd0;
    vtg_vactive_next_value1 <= 1'd0;
    vtg_vactive_next_value_ce1 <= 1'd0;
    vtg_source_payload_hres_next_value2 <= 12'd0;
    vtg_source_payload_hres_next_value_ce2 <= 1'd0;
    vtg_source_payload_vres_next_value3 <= 12'd0;
    vtg_source_payload_vres_next_value_ce3 <= 1'd0;
    vtg_source_payload_hcount_next_value4 <= 12'd0;
    vtg_source_payload_hcount_next_value_ce4 <= 1'd0;
    vtg_source_payload_vcount_next_value5 <= 12'd0;
    vtg_source_payload_vcount_next_value_ce5 <= 1'd0;
    vtg_source_payload_hsync_next_value6 <= 1'd0;
    vtg_source_payload_hsync_next_value_ce6 <= 1'd0;
    soccore_clockdomainsrenamer_next_state <= soccore_clockdomainsrenamer_state;
    case (soccore_clockdomainsrenamer_state)
        1'd1: begin
            vtg_source_valid <= 1'd1;
            if (vtg_source_ready) begin
                vtg_source_payload_hcount_next_value4 <= (vtg_source_payload_hcount + 1'd1);
                vtg_source_payload_hcount_next_value_ce4 <= 1'd1;
                if ((vtg_source_payload_hcount == 1'd0)) begin
                    vtg_hactive_next_value0 <= 1'd1;
                    vtg_hactive_next_value_ce0 <= 1'd1;
                end
                if ((vtg_source_payload_hcount == vtg_hres)) begin
                    vtg_hactive_next_value0 <= 1'd0;
                    vtg_hactive_next_value_ce0 <= 1'd1;
                end
                if ((vtg_source_payload_hcount == vtg_hsync_start)) begin
                    vtg_source_payload_hsync_next_value6 <= 1'd1;
                    vtg_source_payload_hsync_next_value_ce6 <= 1'd1;
                end
                if ((vtg_source_payload_hcount == vtg_hsync_end)) begin
                    vtg_source_payload_hsync_next_value6 <= 1'd0;
                    vtg_source_payload_hsync_next_value_ce6 <= 1'd1;
                end
                if ((vtg_source_payload_hcount == vtg_hscan)) begin
                    vtg_source_payload_hcount_next_value4 <= 1'd0;
                    vtg_source_payload_hcount_next_value_ce4 <= 1'd1;
                end
                if ((vtg_source_payload_hcount == vtg_hsync_start)) begin
                    vtg_source_payload_vcount_next_value5 <= (vtg_source_payload_vcount + 1'd1);
                    vtg_source_payload_vcount_next_value_ce5 <= 1'd1;
                    if ((vtg_source_payload_vcount == 1'd0)) begin
                        vtg_vactive_next_value1 <= 1'd1;
                        vtg_vactive_next_value_ce1 <= 1'd1;
                    end
                    if ((vtg_source_payload_vcount == vtg_vres)) begin
                        vtg_vactive_next_value1 <= 1'd0;
                        vtg_vactive_next_value_ce1 <= 1'd1;
                    end
                    if ((vtg_source_payload_vcount == vtg_vsync_start)) begin
                        vtg_source_payload_vsync_next_value7 <= 1'd1;
                        vtg_source_payload_vsync_next_value_ce7 <= 1'd1;
                    end
                    if ((vtg_source_payload_vcount == vtg_vsync_end)) begin
                        vtg_source_payload_vsync_next_value7 <= 1'd0;
                        vtg_source_payload_vsync_next_value_ce7 <= 1'd1;
                    end
                    if ((vtg_source_payload_vcount == vtg_vscan)) begin
                        vtg_source_payload_vcount_next_value5 <= 1'd0;
                        vtg_source_payload_vcount_next_value_ce5 <= 1'd1;
                    end
                end
            end
        end
        default: begin
            vtg_hactive_next_value0 <= 1'd0;
            vtg_hactive_next_value_ce0 <= 1'd1;
            vtg_vactive_next_value1 <= 1'd0;
            vtg_vactive_next_value_ce1 <= 1'd1;
            vtg_source_payload_hres_next_value2 <= vtg_hres;
            vtg_source_payload_hres_next_value_ce2 <= 1'd1;
            vtg_source_payload_vres_next_value3 <= vtg_vres;
            vtg_source_payload_vres_next_value_ce3 <= 1'd1;
            vtg_source_payload_hcount_next_value4 <= 1'd0;
            vtg_source_payload_hcount_next_value_ce4 <= 1'd1;
            vtg_source_payload_vcount_next_value5 <= 1'd0;
            vtg_source_payload_vcount_next_value_ce5 <= 1'd1;
            soccore_clockdomainsrenamer_next_state <= 1'd1;
        end
    endcase
end
assign graphics_source_valid = graphics_vtg_sink_valid;
assign graphics_vtg_sink_ready = graphics_source_ready;
assign graphics_source_last = graphics_vtg_sink_last;
assign graphics_source_payload_hsync = graphics_vtg_sink_payload_hsync;
assign graphics_source_payload_vsync = graphics_vtg_sink_payload_vsync;
assign graphics_source_payload_de = graphics_vtg_sink_payload_de;
always @(*) begin
    soccore_we <= 1'd0;
    soccore_wishbone_ack <= 1'd0;
    soccore_wishbone2csr_next_state <= 1'd0;
    soccore_dat_w <= 32'd0;
    soccore_wishbone_dat_r <= 32'd0;
    soccore_adr <= 14'd0;
    soccore_wishbone2csr_next_state <= soccore_wishbone2csr_state;
    case (soccore_wishbone2csr_state)
        1'd1: begin
            soccore_wishbone_ack <= 1'd1;
            soccore_wishbone_dat_r <= soccore_dat_r;
            soccore_wishbone2csr_next_state <= 1'd0;
        end
        default: begin
            soccore_dat_w <= soccore_wishbone_dat_w;
            if ((soccore_wishbone_cyc & soccore_wishbone_stb)) begin
                soccore_adr <= soccore_wishbone_adr;
                soccore_we <= (soccore_wishbone_we & (soccore_wishbone_sel != 1'd0));
                soccore_wishbone2csr_next_state <= 1'd1;
            end
        end
    endcase
end
assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 1'd0);
assign csrbank0_reset0_r = interface0_bank_bus_dat_w[1:0];
always @(*) begin
    csrbank0_reset0_re <= 1'd0;
    csrbank0_reset0_we <= 1'd0;
    if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin
        csrbank0_reset0_re <= interface0_bank_bus_we;
        csrbank0_reset0_we <= (~interface0_bank_bus_we);
    end
end
assign csrbank0_scratch0_r = interface0_bank_bus_dat_w[31:0];
always @(*) begin
    csrbank0_scratch0_we <= 1'd0;
    csrbank0_scratch0_re <= 1'd0;
    if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin
        csrbank0_scratch0_re <= interface0_bank_bus_we;
        csrbank0_scratch0_we <= (~interface0_bank_bus_we);
    end
end
assign csrbank0_bus_errors_r = interface0_bank_bus_dat_w[31:0];
always @(*) begin
    csrbank0_bus_errors_re <= 1'd0;
    csrbank0_bus_errors_we <= 1'd0;
    if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 2'd2))) begin
        csrbank0_bus_errors_re <= interface0_bank_bus_we;
        csrbank0_bus_errors_we <= (~interface0_bank_bus_we);
    end
end
assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd1);
assign csrbank1_load0_r = interface1_bank_bus_dat_w[31:0];
always @(*) begin
    csrbank1_load0_we <= 1'd0;
    csrbank1_load0_re <= 1'd0;
    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin
        csrbank1_load0_re <= interface1_bank_bus_we;
        csrbank1_load0_we <= (~interface1_bank_bus_we);
    end
end
assign csrbank1_reload0_r = interface1_bank_bus_dat_w[31:0];
always @(*) begin
    csrbank1_reload0_re <= 1'd0;
    csrbank1_reload0_we <= 1'd0;
    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin
        csrbank1_reload0_re <= interface1_bank_bus_we;
        csrbank1_reload0_we <= (~interface1_bank_bus_we);
    end
end
assign csrbank1_en0_r = interface1_bank_bus_dat_w[0];
always @(*) begin
    csrbank1_en0_we <= 1'd0;
    csrbank1_en0_re <= 1'd0;
    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin
        csrbank1_en0_re <= interface1_bank_bus_we;
        csrbank1_en0_we <= (~interface1_bank_bus_we);
    end
end
assign csrbank1_update_value0_r = interface1_bank_bus_dat_w[0];
always @(*) begin
    csrbank1_update_value0_we <= 1'd0;
    csrbank1_update_value0_re <= 1'd0;
    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin
        csrbank1_update_value0_re <= interface1_bank_bus_we;
        csrbank1_update_value0_we <= (~interface1_bank_bus_we);
    end
end
assign csrbank1_value_r = interface1_bank_bus_dat_w[31:0];
always @(*) begin
    csrbank1_value_re <= 1'd0;
    csrbank1_value_we <= 1'd0;
    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin
        csrbank1_value_re <= interface1_bank_bus_we;
        csrbank1_value_we <= (~interface1_bank_bus_we);
    end
end
assign csrbank1_ev_status_r = interface1_bank_bus_dat_w[0];
always @(*) begin
    csrbank1_ev_status_we <= 1'd0;
    csrbank1_ev_status_re <= 1'd0;
    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin
        csrbank1_ev_status_re <= interface1_bank_bus_we;
        csrbank1_ev_status_we <= (~interface1_bank_bus_we);
    end
end
assign csrbank1_ev_pending_r = interface1_bank_bus_dat_w[0];
always @(*) begin
    csrbank1_ev_pending_we <= 1'd0;
    csrbank1_ev_pending_re <= 1'd0;
    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin
        csrbank1_ev_pending_re <= interface1_bank_bus_we;
        csrbank1_ev_pending_we <= (~interface1_bank_bus_we);
    end
end
assign csrbank1_ev_enable0_r = interface1_bank_bus_dat_w[0];
always @(*) begin
    csrbank1_ev_enable0_re <= 1'd0;
    csrbank1_ev_enable0_we <= 1'd0;
    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin
        csrbank1_ev_enable0_re <= interface1_bank_bus_we;
        csrbank1_ev_enable0_we <= (~interface1_bank_bus_we);
    end
end
assign csrbank1_load0_w = timer_load_storage[31:0];
assign csrbank1_reload0_w = timer_reload_storage[31:0];
assign csrbank1_en0_w = timer_en_storage;
assign csrbank1_update_value0_w = timer_update_value_storage;
assign csrbank1_value_w = timer_value_status[31:0];
assign timer_value_we = csrbank1_value_we;
assign timer_status_status = timer_zero0;
assign csrbank1_ev_status_w = timer_status_status;
assign timer_status_we = csrbank1_ev_status_we;
assign timer_pending_status = timer_zero1;
assign csrbank1_ev_pending_w = timer_pending_status;
assign timer_pending_we = csrbank1_ev_pending_we;
assign timer_zero2 = timer_enable_storage;
assign csrbank1_ev_enable0_w = timer_enable_storage;
assign csrbank2_sel = (interface2_bank_bus_adr[13:9] == 2'd2);
assign uart_rxtx_r = interface2_bank_bus_dat_w[7:0];
always @(*) begin
    uart_rxtx_re <= 1'd0;
    uart_rxtx_we <= 1'd0;
    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin
        uart_rxtx_re <= interface2_bank_bus_we;
        uart_rxtx_we <= (~interface2_bank_bus_we);
    end
end
assign csrbank2_txfull_r = interface2_bank_bus_dat_w[0];
always @(*) begin
    csrbank2_txfull_re <= 1'd0;
    csrbank2_txfull_we <= 1'd0;
    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin
        csrbank2_txfull_re <= interface2_bank_bus_we;
        csrbank2_txfull_we <= (~interface2_bank_bus_we);
    end
end
assign csrbank2_rxempty_r = interface2_bank_bus_dat_w[0];
always @(*) begin
    csrbank2_rxempty_we <= 1'd0;
    csrbank2_rxempty_re <= 1'd0;
    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin
        csrbank2_rxempty_re <= interface2_bank_bus_we;
        csrbank2_rxempty_we <= (~interface2_bank_bus_we);
    end
end
assign csrbank2_ev_status_r = interface2_bank_bus_dat_w[1:0];
always @(*) begin
    csrbank2_ev_status_we <= 1'd0;
    csrbank2_ev_status_re <= 1'd0;
    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin
        csrbank2_ev_status_re <= interface2_bank_bus_we;
        csrbank2_ev_status_we <= (~interface2_bank_bus_we);
    end
end
assign csrbank2_ev_pending_r = interface2_bank_bus_dat_w[1:0];
always @(*) begin
    csrbank2_ev_pending_re <= 1'd0;
    csrbank2_ev_pending_we <= 1'd0;
    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin
        csrbank2_ev_pending_re <= interface2_bank_bus_we;
        csrbank2_ev_pending_we <= (~interface2_bank_bus_we);
    end
end
assign csrbank2_ev_enable0_r = interface2_bank_bus_dat_w[1:0];
always @(*) begin
    csrbank2_ev_enable0_we <= 1'd0;
    csrbank2_ev_enable0_re <= 1'd0;
    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin
        csrbank2_ev_enable0_re <= interface2_bank_bus_we;
        csrbank2_ev_enable0_we <= (~interface2_bank_bus_we);
    end
end
assign csrbank2_txempty_r = interface2_bank_bus_dat_w[0];
always @(*) begin
    csrbank2_txempty_we <= 1'd0;
    csrbank2_txempty_re <= 1'd0;
    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin
        csrbank2_txempty_re <= interface2_bank_bus_we;
        csrbank2_txempty_we <= (~interface2_bank_bus_we);
    end
end
assign csrbank2_rxfull_r = interface2_bank_bus_dat_w[0];
always @(*) begin
    csrbank2_rxfull_re <= 1'd0;
    csrbank2_rxfull_we <= 1'd0;
    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin
        csrbank2_rxfull_re <= interface2_bank_bus_we;
        csrbank2_rxfull_we <= (~interface2_bank_bus_we);
    end
end
assign csrbank2_txfull_w = uart_txfull_status;
assign uart_txfull_we = csrbank2_txfull_we;
assign csrbank2_rxempty_w = uart_rxempty_status;
assign uart_rxempty_we = csrbank2_rxempty_we;
always @(*) begin
    uart_status_status <= 2'd0;
    uart_status_status[0] <= uart_tx0;
    uart_status_status[1] <= uart_rx0;
end
assign csrbank2_ev_status_w = uart_status_status[1:0];
assign uart_status_we = csrbank2_ev_status_we;
always @(*) begin
    uart_pending_status <= 2'd0;
    uart_pending_status[0] <= uart_tx1;
    uart_pending_status[1] <= uart_rx1;
end
assign csrbank2_ev_pending_w = uart_pending_status[1:0];
assign uart_pending_we = csrbank2_ev_pending_we;
assign uart_tx2 = uart_enable_storage[0];
assign uart_rx2 = uart_enable_storage[1];
assign csrbank2_ev_enable0_w = uart_enable_storage[1:0];
assign csrbank2_txempty_w = uart_txempty_status;
assign uart_txempty_we = csrbank2_txempty_we;
assign csrbank2_rxfull_w = uart_rxfull_status;
assign uart_rxfull_we = csrbank2_rxfull_we;
assign csrbank3_sel = (interface3_bank_bus_adr[13:9] == 2'd3);
assign csrbank3_enable0_r = interface3_bank_bus_dat_w[0];
always @(*) begin
    csrbank3_enable0_re <= 1'd0;
    csrbank3_enable0_we <= 1'd0;
    if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 1'd0))) begin
        csrbank3_enable0_re <= interface3_bank_bus_we;
        csrbank3_enable0_we <= (~interface3_bank_bus_we);
    end
end
assign csrbank3_hres0_r = interface3_bank_bus_dat_w[11:0];
always @(*) begin
    csrbank3_hres0_we <= 1'd0;
    csrbank3_hres0_re <= 1'd0;
    if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 1'd1))) begin
        csrbank3_hres0_re <= interface3_bank_bus_we;
        csrbank3_hres0_we <= (~interface3_bank_bus_we);
    end
end
assign csrbank3_hsync_start0_r = interface3_bank_bus_dat_w[11:0];
always @(*) begin
    csrbank3_hsync_start0_re <= 1'd0;
    csrbank3_hsync_start0_we <= 1'd0;
    if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 2'd2))) begin
        csrbank3_hsync_start0_re <= interface3_bank_bus_we;
        csrbank3_hsync_start0_we <= (~interface3_bank_bus_we);
    end
end
assign csrbank3_hsync_end0_r = interface3_bank_bus_dat_w[11:0];
always @(*) begin
    csrbank3_hsync_end0_re <= 1'd0;
    csrbank3_hsync_end0_we <= 1'd0;
    if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 2'd3))) begin
        csrbank3_hsync_end0_re <= interface3_bank_bus_we;
        csrbank3_hsync_end0_we <= (~interface3_bank_bus_we);
    end
end
assign csrbank3_hscan0_r = interface3_bank_bus_dat_w[11:0];
always @(*) begin
    csrbank3_hscan0_we <= 1'd0;
    csrbank3_hscan0_re <= 1'd0;
    if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 3'd4))) begin
        csrbank3_hscan0_re <= interface3_bank_bus_we;
        csrbank3_hscan0_we <= (~interface3_bank_bus_we);
    end
end
assign csrbank3_vres0_r = interface3_bank_bus_dat_w[11:0];
always @(*) begin
    csrbank3_vres0_re <= 1'd0;
    csrbank3_vres0_we <= 1'd0;
    if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 3'd5))) begin
        csrbank3_vres0_re <= interface3_bank_bus_we;
        csrbank3_vres0_we <= (~interface3_bank_bus_we);
    end
end
assign csrbank3_vsync_start0_r = interface3_bank_bus_dat_w[11:0];
always @(*) begin
    csrbank3_vsync_start0_we <= 1'd0;
    csrbank3_vsync_start0_re <= 1'd0;
    if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 3'd6))) begin
        csrbank3_vsync_start0_re <= interface3_bank_bus_we;
        csrbank3_vsync_start0_we <= (~interface3_bank_bus_we);
    end
end
assign csrbank3_vsync_end0_r = interface3_bank_bus_dat_w[11:0];
always @(*) begin
    csrbank3_vsync_end0_we <= 1'd0;
    csrbank3_vsync_end0_re <= 1'd0;
    if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 3'd7))) begin
        csrbank3_vsync_end0_re <= interface3_bank_bus_we;
        csrbank3_vsync_end0_we <= (~interface3_bank_bus_we);
    end
end
assign csrbank3_vscan0_r = interface3_bank_bus_dat_w[11:0];
always @(*) begin
    csrbank3_vscan0_re <= 1'd0;
    csrbank3_vscan0_we <= 1'd0;
    if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 4'd8))) begin
        csrbank3_vscan0_re <= interface3_bank_bus_we;
        csrbank3_vscan0_we <= (~interface3_bank_bus_we);
    end
end
assign csrbank3_enable0_w = vtg_enable_storage;
assign csrbank3_hres0_w = vtg_hres_storage[11:0];
assign csrbank3_hsync_start0_w = vtg_hsync_start_storage[11:0];
assign csrbank3_hsync_end0_w = vtg_hsync_end_storage[11:0];
assign csrbank3_hscan0_w = vtg_hscan_storage[11:0];
assign csrbank3_vres0_w = vtg_vres_storage[11:0];
assign csrbank3_vsync_start0_w = vtg_vsync_start_storage[11:0];
assign csrbank3_vsync_end0_w = vtg_vsync_end_storage[11:0];
assign csrbank3_vscan0_w = vtg_vscan_storage[11:0];
assign csr_interconnect_adr = soccore_adr;
assign csr_interconnect_we = soccore_we;
assign csr_interconnect_dat_w = soccore_dat_w;
assign soccore_dat_r = csr_interconnect_dat_r;
assign interface0_bank_bus_adr = csr_interconnect_adr;
assign interface1_bank_bus_adr = csr_interconnect_adr;
assign interface2_bank_bus_adr = csr_interconnect_adr;
assign interface3_bank_bus_adr = csr_interconnect_adr;
assign interface0_bank_bus_we = csr_interconnect_we;
assign interface1_bank_bus_we = csr_interconnect_we;
assign interface2_bank_bus_we = csr_interconnect_we;
assign interface3_bank_bus_we = csr_interconnect_we;
assign interface0_bank_bus_dat_w = csr_interconnect_dat_w;
assign interface1_bank_bus_dat_w = csr_interconnect_dat_w;
assign interface2_bank_bus_dat_w = csr_interconnect_dat_w;
assign interface3_bank_bus_dat_w = csr_interconnect_dat_w;
assign csr_interconnect_dat_r = (((interface0_bank_bus_dat_r | interface1_bank_bus_dat_r) | interface2_bank_bus_dat_r) | interface3_bank_bus_dat_r);
assign rx_rx = xilinxmultiregimpl0_regs1;
assign xilinxasyncresetsynchronizerimpl0 = (~crg_locked);
assign xilinxasyncresetsynchronizerimpl1 = (~crg_locked);
assign vtg_enable = xilinxmultiregimpl1_regs1;
assign vtg_hres = xilinxmultiregimpl2_regs1;
assign vtg_hsync_start = xilinxmultiregimpl3_regs1;
assign vtg_hsync_end = xilinxmultiregimpl4_regs1;
assign vtg_hscan = xilinxmultiregimpl5_regs1;
assign vtg_vres = xilinxmultiregimpl6_regs1;
assign vtg_vsync_start = xilinxmultiregimpl7_regs1;
assign vtg_vsync_end = xilinxmultiregimpl8_regs1;
assign vtg_vscan = xilinxmultiregimpl9_regs1;


//------------------------------------------------------------------------------
// Synchronous Logic
//------------------------------------------------------------------------------

always @(posedge sys_clk) begin
    if ((bus_errors != 32'd4294967295)) begin
        if (bus_error) begin
            bus_errors <= (bus_errors + 1'd1);
        end
    end
    if (csrbank0_reset0_re) begin
        reset_storage[1:0] <= csrbank0_reset0_r;
    end
    reset_re <= csrbank0_reset0_re;
    if (csrbank0_scratch0_re) begin
        scratch_storage[31:0] <= csrbank0_scratch0_r;
    end
    scratch_re <= csrbank0_scratch0_re;
    bus_errors_re <= csrbank0_bus_errors_re;
    ram_bus_ack <= 1'd0;
    if (((ram_bus_cyc & ram_bus_stb) & ((~ram_bus_ack) | adr_burst))) begin
        ram_bus_ack <= 1'd1;
    end
    {tx_tick, tx_phase} <= 23'd4947802;
    if (tx_enable) begin
        {tx_tick, tx_phase} <= (tx_phase + 23'd4947802);
    end
    soccore_rs232phytx_state <= soccore_rs232phytx_next_state;
    if (tx_count_rs232phytx_next_value_ce0) begin
        tx_count <= tx_count_rs232phytx_next_value0;
    end
    if (serial_tx_rs232phytx_next_value_ce1) begin
        serial_tx <= serial_tx_rs232phytx_next_value1;
    end
    if (tx_data_rs232phytx_next_value_ce2) begin
        tx_data <= tx_data_rs232phytx_next_value2;
    end
    rx_rx_d <= rx_rx;
    {rx_tick, rx_phase} <= 32'd2147483648;
    if (rx_enable) begin
        {rx_tick, rx_phase} <= (rx_phase + 23'd4947802);
    end
    soccore_rs232phyrx_state <= soccore_rs232phyrx_next_state;
    if (rx_count_rs232phyrx_next_value_ce0) begin
        rx_count <= rx_count_rs232phyrx_next_value0;
    end
    if (rx_data_rs232phyrx_next_value_ce1) begin
        rx_data <= rx_data_rs232phyrx_next_value1;
    end
    if (uart_tx_clear) begin
        uart_tx_pending <= 1'd0;
    end
    uart_tx_trigger_d <= uart_tx_trigger;
    if ((uart_tx_trigger & (~uart_tx_trigger_d))) begin
        uart_tx_pending <= 1'd1;
    end
    if (uart_rx_clear) begin
        uart_rx_pending <= 1'd0;
    end
    uart_rx_trigger_d <= uart_rx_trigger;
    if ((uart_rx_trigger & (~uart_rx_trigger_d))) begin
        uart_rx_pending <= 1'd1;
    end
    if (uart_tx_fifo_syncfifo_re) begin
        uart_tx_fifo_readable <= 1'd1;
    end else begin
        if (uart_tx_fifo_re) begin
            uart_tx_fifo_readable <= 1'd0;
        end
    end
    if (((uart_tx_fifo_syncfifo_we & uart_tx_fifo_syncfifo_writable) & (~uart_tx_fifo_replace))) begin
        uart_tx_fifo_produce <= (uart_tx_fifo_produce + 1'd1);
    end
    if (uart_tx_fifo_do_read) begin
        uart_tx_fifo_consume <= (uart_tx_fifo_consume + 1'd1);
    end
    if (((uart_tx_fifo_syncfifo_we & uart_tx_fifo_syncfifo_writable) & (~uart_tx_fifo_replace))) begin
        if ((~uart_tx_fifo_do_read)) begin
            uart_tx_fifo_level0 <= (uart_tx_fifo_level0 + 1'd1);
        end
    end else begin
        if (uart_tx_fifo_do_read) begin
            uart_tx_fifo_level0 <= (uart_tx_fifo_level0 - 1'd1);
        end
    end
    if (uart_rx_fifo_syncfifo_re) begin
        uart_rx_fifo_readable <= 1'd1;
    end else begin
        if (uart_rx_fifo_re) begin
            uart_rx_fifo_readable <= 1'd0;
        end
    end
    if (((uart_rx_fifo_syncfifo_we & uart_rx_fifo_syncfifo_writable) & (~uart_rx_fifo_replace))) begin
        uart_rx_fifo_produce <= (uart_rx_fifo_produce + 1'd1);
    end
    if (uart_rx_fifo_do_read) begin
        uart_rx_fifo_consume <= (uart_rx_fifo_consume + 1'd1);
    end
    if (((uart_rx_fifo_syncfifo_we & uart_rx_fifo_syncfifo_writable) & (~uart_rx_fifo_replace))) begin
        if ((~uart_rx_fifo_do_read)) begin
            uart_rx_fifo_level0 <= (uart_rx_fifo_level0 + 1'd1);
        end
    end else begin
        if (uart_rx_fifo_do_read) begin
            uart_rx_fifo_level0 <= (uart_rx_fifo_level0 - 1'd1);
        end
    end
    if (timer_en_storage) begin
        if ((timer_value == 1'd0)) begin
            timer_value <= timer_reload_storage;
        end else begin
            timer_value <= (timer_value - 1'd1);
        end
    end else begin
        timer_value <= timer_load_storage;
    end
    if (timer_update_value_re) begin
        timer_value_status <= timer_value;
    end
    if (timer_zero_clear) begin
        timer_zero_pending <= 1'd0;
    end
    timer_zero_trigger_d <= timer_zero_trigger;
    if ((timer_zero_trigger & (~timer_zero_trigger_d))) begin
        timer_zero_pending <= 1'd1;
    end
    soccore_wishbone2csr_state <= soccore_wishbone2csr_next_state;
    interface0_bank_bus_dat_r <= 1'd0;
    if (csrbank0_sel) begin
        case (interface0_bank_bus_adr[8:0])
            1'd0: begin
                interface0_bank_bus_dat_r <= csrbank0_reset0_w;
            end
            1'd1: begin
                interface0_bank_bus_dat_r <= csrbank0_scratch0_w;
            end
            2'd2: begin
                interface0_bank_bus_dat_r <= csrbank0_bus_errors_w;
            end
        endcase
    end
    interface1_bank_bus_dat_r <= 1'd0;
    if (csrbank1_sel) begin
        case (interface1_bank_bus_adr[8:0])
            1'd0: begin
                interface1_bank_bus_dat_r <= csrbank1_load0_w;
            end
            1'd1: begin
                interface1_bank_bus_dat_r <= csrbank1_reload0_w;
            end
            2'd2: begin
                interface1_bank_bus_dat_r <= csrbank1_en0_w;
            end
            2'd3: begin
                interface1_bank_bus_dat_r <= csrbank1_update_value0_w;
            end
            3'd4: begin
                interface1_bank_bus_dat_r <= csrbank1_value_w;
            end
            3'd5: begin
                interface1_bank_bus_dat_r <= csrbank1_ev_status_w;
            end
            3'd6: begin
                interface1_bank_bus_dat_r <= csrbank1_ev_pending_w;
            end
            3'd7: begin
                interface1_bank_bus_dat_r <= csrbank1_ev_enable0_w;
            end
        endcase
    end
    if (csrbank1_load0_re) begin
        timer_load_storage[31:0] <= csrbank1_load0_r;
    end
    timer_load_re <= csrbank1_load0_re;
    if (csrbank1_reload0_re) begin
        timer_reload_storage[31:0] <= csrbank1_reload0_r;
    end
    timer_reload_re <= csrbank1_reload0_re;
    if (csrbank1_en0_re) begin
        timer_en_storage <= csrbank1_en0_r;
    end
    timer_en_re <= csrbank1_en0_re;
    if (csrbank1_update_value0_re) begin
        timer_update_value_storage <= csrbank1_update_value0_r;
    end
    timer_update_value_re <= csrbank1_update_value0_re;
    timer_value_re <= csrbank1_value_re;
    timer_status_re <= csrbank1_ev_status_re;
    if (csrbank1_ev_pending_re) begin
        timer_pending_r <= csrbank1_ev_pending_r;
    end
    timer_pending_re <= csrbank1_ev_pending_re;
    if (csrbank1_ev_enable0_re) begin
        timer_enable_storage <= csrbank1_ev_enable0_r;
    end
    timer_enable_re <= csrbank1_ev_enable0_re;
    interface2_bank_bus_dat_r <= 1'd0;
    if (csrbank2_sel) begin
        case (interface2_bank_bus_adr[8:0])
            1'd0: begin
                interface2_bank_bus_dat_r <= uart_rxtx_w;
            end
            1'd1: begin
                interface2_bank_bus_dat_r <= csrbank2_txfull_w;
            end
            2'd2: begin
                interface2_bank_bus_dat_r <= csrbank2_rxempty_w;
            end
            2'd3: begin
                interface2_bank_bus_dat_r <= csrbank2_ev_status_w;
            end
            3'd4: begin
                interface2_bank_bus_dat_r <= csrbank2_ev_pending_w;
            end
            3'd5: begin
                interface2_bank_bus_dat_r <= csrbank2_ev_enable0_w;
            end
            3'd6: begin
                interface2_bank_bus_dat_r <= csrbank2_txempty_w;
            end
            3'd7: begin
                interface2_bank_bus_dat_r <= csrbank2_rxfull_w;
            end
        endcase
    end
    uart_txfull_re <= csrbank2_txfull_re;
    uart_rxempty_re <= csrbank2_rxempty_re;
    uart_status_re <= csrbank2_ev_status_re;
    if (csrbank2_ev_pending_re) begin
        uart_pending_r[1:0] <= csrbank2_ev_pending_r;
    end
    uart_pending_re <= csrbank2_ev_pending_re;
    if (csrbank2_ev_enable0_re) begin
        uart_enable_storage[1:0] <= csrbank2_ev_enable0_r;
    end
    uart_enable_re <= csrbank2_ev_enable0_re;
    uart_txempty_re <= csrbank2_txempty_re;
    uart_rxfull_re <= csrbank2_rxfull_re;
    interface3_bank_bus_dat_r <= 1'd0;
    if (csrbank3_sel) begin
        case (interface3_bank_bus_adr[8:0])
            1'd0: begin
                interface3_bank_bus_dat_r <= csrbank3_enable0_w;
            end
            1'd1: begin
                interface3_bank_bus_dat_r <= csrbank3_hres0_w;
            end
            2'd2: begin
                interface3_bank_bus_dat_r <= csrbank3_hsync_start0_w;
            end
            2'd3: begin
                interface3_bank_bus_dat_r <= csrbank3_hsync_end0_w;
            end
            3'd4: begin
                interface3_bank_bus_dat_r <= csrbank3_hscan0_w;
            end
            3'd5: begin
                interface3_bank_bus_dat_r <= csrbank3_vres0_w;
            end
            3'd6: begin
                interface3_bank_bus_dat_r <= csrbank3_vsync_start0_w;
            end
            3'd7: begin
                interface3_bank_bus_dat_r <= csrbank3_vsync_end0_w;
            end
            4'd8: begin
                interface3_bank_bus_dat_r <= csrbank3_vscan0_w;
            end
        endcase
    end
    if (csrbank3_enable0_re) begin
        vtg_enable_storage <= csrbank3_enable0_r;
    end
    vtg_enable_re <= csrbank3_enable0_re;
    if (csrbank3_hres0_re) begin
        vtg_hres_storage[11:0] <= csrbank3_hres0_r;
    end
    vtg_hres_re <= csrbank3_hres0_re;
    if (csrbank3_hsync_start0_re) begin
        vtg_hsync_start_storage[11:0] <= csrbank3_hsync_start0_r;
    end
    vtg_hsync_start_re <= csrbank3_hsync_start0_re;
    if (csrbank3_hsync_end0_re) begin
        vtg_hsync_end_storage[11:0] <= csrbank3_hsync_end0_r;
    end
    vtg_hsync_end_re <= csrbank3_hsync_end0_re;
    if (csrbank3_hscan0_re) begin
        vtg_hscan_storage[11:0] <= csrbank3_hscan0_r;
    end
    vtg_hscan_re <= csrbank3_hscan0_re;
    if (csrbank3_vres0_re) begin
        vtg_vres_storage[11:0] <= csrbank3_vres0_r;
    end
    vtg_vres_re <= csrbank3_vres0_re;
    if (csrbank3_vsync_start0_re) begin
        vtg_vsync_start_storage[11:0] <= csrbank3_vsync_start0_r;
    end
    vtg_vsync_start_re <= csrbank3_vsync_start0_re;
    if (csrbank3_vsync_end0_re) begin
        vtg_vsync_end_storage[11:0] <= csrbank3_vsync_end0_r;
    end
    vtg_vsync_end_re <= csrbank3_vsync_end0_re;
    if (csrbank3_vscan0_re) begin
        vtg_vscan_storage[11:0] <= csrbank3_vscan0_r;
    end
    vtg_vscan_re <= csrbank3_vscan0_re;
    if (sys_rst) begin
        reset_storage <= 2'd0;
        reset_re <= 1'd0;
        scratch_storage <= 32'd305419896;
        scratch_re <= 1'd0;
        bus_errors_re <= 1'd0;
        bus_errors <= 32'd0;
        ram_bus_ack <= 1'd0;
        serial_tx <= 1'd1;
        tx_tick <= 1'd0;
        rx_tick <= 1'd0;
        rx_rx_d <= 1'd0;
        uart_txfull_re <= 1'd0;
        uart_rxempty_re <= 1'd0;
        uart_tx_pending <= 1'd0;
        uart_tx_trigger_d <= 1'd0;
        uart_rx_pending <= 1'd0;
        uart_rx_trigger_d <= 1'd0;
        uart_status_re <= 1'd0;
        uart_pending_re <= 1'd0;
        uart_pending_r <= 2'd0;
        uart_enable_storage <= 2'd0;
        uart_enable_re <= 1'd0;
        uart_txempty_re <= 1'd0;
        uart_rxfull_re <= 1'd0;
        uart_tx_fifo_readable <= 1'd0;
        uart_tx_fifo_level0 <= 5'd0;
        uart_tx_fifo_produce <= 4'd0;
        uart_tx_fifo_consume <= 4'd0;
        uart_rx_fifo_readable <= 1'd0;
        uart_rx_fifo_level0 <= 5'd0;
        uart_rx_fifo_produce <= 4'd0;
        uart_rx_fifo_consume <= 4'd0;
        timer_load_storage <= 32'd0;
        timer_load_re <= 1'd0;
        timer_reload_storage <= 32'd0;
        timer_reload_re <= 1'd0;
        timer_en_storage <= 1'd0;
        timer_en_re <= 1'd0;
        timer_update_value_storage <= 1'd0;
        timer_update_value_re <= 1'd0;
        timer_value_status <= 32'd0;
        timer_value_re <= 1'd0;
        timer_zero_pending <= 1'd0;
        timer_zero_trigger_d <= 1'd0;
        timer_status_re <= 1'd0;
        timer_pending_re <= 1'd0;
        timer_pending_r <= 1'd0;
        timer_enable_storage <= 1'd0;
        timer_enable_re <= 1'd0;
        timer_value <= 32'd0;
        vtg_enable_storage <= 1'd1;
        vtg_enable_re <= 1'd0;
        vtg_hres_storage <= 12'd640;
        vtg_hres_re <= 1'd0;
        vtg_hsync_start_storage <= 12'd656;
        vtg_hsync_start_re <= 1'd0;
        vtg_hsync_end_storage <= 12'd752;
        vtg_hsync_end_re <= 1'd0;
        vtg_hscan_storage <= 12'd799;
        vtg_hscan_re <= 1'd0;
        vtg_vres_storage <= 12'd480;
        vtg_vres_re <= 1'd0;
        vtg_vsync_start_storage <= 12'd490;
        vtg_vsync_start_re <= 1'd0;
        vtg_vsync_end_storage <= 12'd492;
        vtg_vsync_end_re <= 1'd0;
        vtg_vscan_storage <= 12'd524;
        vtg_vscan_re <= 1'd0;
        soccore_rs232phytx_state <= 1'd0;
        soccore_rs232phyrx_state <= 1'd0;
        soccore_wishbone2csr_state <= 1'd0;
    end
    xilinxmultiregimpl0_regs0 <= serial_rx;
    xilinxmultiregimpl0_regs1 <= xilinxmultiregimpl0_regs0;
end

always @(posedge vga_clk) begin
    vtg_source_first <= ((vtg_source_payload_hcount == 1'd0) & (vtg_source_payload_vcount == 1'd0));
    vtg_source_last <= ((vtg_source_payload_hcount == vtg_hscan) & (vtg_source_payload_vcount == vtg_vscan));
    soccore_clockdomainsrenamer_state <= soccore_clockdomainsrenamer_next_state;
    if (vtg_hactive_next_value_ce0) begin
        vtg_hactive <= vtg_hactive_next_value0;
    end
    if (vtg_vactive_next_value_ce1) begin
        vtg_vactive <= vtg_vactive_next_value1;
    end
    if (vtg_source_payload_hres_next_value_ce2) begin
        vtg_source_payload_hres <= vtg_source_payload_hres_next_value2;
    end
    if (vtg_source_payload_vres_next_value_ce3) begin
        vtg_source_payload_vres <= vtg_source_payload_vres_next_value3;
    end
    if (vtg_source_payload_hcount_next_value_ce4) begin
        vtg_source_payload_hcount <= vtg_source_payload_hcount_next_value4;
    end
    if (vtg_source_payload_vcount_next_value_ce5) begin
        vtg_source_payload_vcount <= vtg_source_payload_vcount_next_value5;
    end
    if (vtg_source_payload_hsync_next_value_ce6) begin
        vtg_source_payload_hsync <= vtg_source_payload_hsync_next_value6;
    end
    if (vtg_source_payload_vsync_next_value_ce7) begin
        vtg_source_payload_vsync <= vtg_source_payload_vsync_next_value7;
    end
    if (vtg_reset) begin
        vtg_source_payload_hsync <= 1'd0;
        vtg_source_payload_vsync <= 1'd0;
        vtg_source_payload_hres <= 12'd0;
        vtg_source_payload_vres <= 12'd0;
        vtg_source_payload_hcount <= 12'd0;
        vtg_source_payload_vcount <= 12'd0;
        vtg_hactive <= 1'd0;
        vtg_vactive <= 1'd0;
        soccore_clockdomainsrenamer_state <= 1'd0;
    end
    if (vga_rst) begin
        vtg_source_payload_hsync <= 1'd0;
        vtg_source_payload_vsync <= 1'd0;
        vtg_source_payload_hres <= 12'd0;
        vtg_source_payload_vres <= 12'd0;
        vtg_source_payload_hcount <= 12'd0;
        vtg_source_payload_vcount <= 12'd0;
        vtg_hactive <= 1'd0;
        vtg_vactive <= 1'd0;
        soccore_clockdomainsrenamer_state <= 1'd0;
    end
    xilinxmultiregimpl1_regs0 <= vtg_enable_storage;
    xilinxmultiregimpl1_regs1 <= xilinxmultiregimpl1_regs0;
    xilinxmultiregimpl2_regs0 <= vtg_hres_storage;
    xilinxmultiregimpl2_regs1 <= xilinxmultiregimpl2_regs0;
    xilinxmultiregimpl3_regs0 <= vtg_hsync_start_storage;
    xilinxmultiregimpl3_regs1 <= xilinxmultiregimpl3_regs0;
    xilinxmultiregimpl4_regs0 <= vtg_hsync_end_storage;
    xilinxmultiregimpl4_regs1 <= xilinxmultiregimpl4_regs0;
    xilinxmultiregimpl5_regs0 <= vtg_hscan_storage;
    xilinxmultiregimpl5_regs1 <= xilinxmultiregimpl5_regs0;
    xilinxmultiregimpl6_regs0 <= vtg_vres_storage;
    xilinxmultiregimpl6_regs1 <= xilinxmultiregimpl6_regs0;
    xilinxmultiregimpl7_regs0 <= vtg_vsync_start_storage;
    xilinxmultiregimpl7_regs1 <= xilinxmultiregimpl7_regs0;
    xilinxmultiregimpl8_regs0 <= vtg_vsync_end_storage;
    xilinxmultiregimpl8_regs1 <= xilinxmultiregimpl8_regs0;
    xilinxmultiregimpl9_regs0 <= vtg_vscan_storage;
    xilinxmultiregimpl9_regs1 <= xilinxmultiregimpl9_regs0;
end


//------------------------------------------------------------------------------
// Specialized Logic
//------------------------------------------------------------------------------

//------------------------------------------------------------------------------
// Memory sram: 2048-words x 32-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync  | Write: Sync | Mode: Write-First | Write-Granularity: 8 
reg [31:0] sram[0:2047];
initial begin
	$readmemh("digilent_arty_sram.init", sram);
end
reg [10:0] sram_adr0;
always @(posedge sys_clk) begin
	if (we[0])
		sram[adr][7:0] <= dat_w[7:0];
	if (we[1])
		sram[adr][15:8] <= dat_w[15:8];
	if (we[2])
		sram[adr][23:16] <= dat_w[23:16];
	if (we[3])
		sram[adr][31:24] <= dat_w[31:24];
	sram_adr0 <= adr;
end
assign dat_r = sram[sram_adr0];


//------------------------------------------------------------------------------
// Memory storage: 16-words x 10-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 10 
// Port 1 | Read: Sync  | Write: ---- | 
reg [9:0] storage[0:15];
reg [9:0] storage_dat0;
reg [9:0] storage_dat1;
always @(posedge sys_clk) begin
	if (uart_tx_fifo_wrport_we)
		storage[uart_tx_fifo_wrport_adr] <= uart_tx_fifo_wrport_dat_w;
	storage_dat0 <= storage[uart_tx_fifo_wrport_adr];
end
always @(posedge sys_clk) begin
	if (uart_tx_fifo_rdport_re)
		storage_dat1 <= storage[uart_tx_fifo_rdport_adr];
end
assign uart_tx_fifo_wrport_dat_r = storage_dat0;
assign uart_tx_fifo_rdport_dat_r = storage_dat1;


//------------------------------------------------------------------------------
// Memory storage_1: 16-words x 10-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 10 
// Port 1 | Read: Sync  | Write: ---- | 
reg [9:0] storage_1[0:15];
reg [9:0] storage_1_dat0;
reg [9:0] storage_1_dat1;
always @(posedge sys_clk) begin
	if (uart_rx_fifo_wrport_we)
		storage_1[uart_rx_fifo_wrport_adr] <= uart_rx_fifo_wrport_dat_w;
	storage_1_dat0 <= storage_1[uart_rx_fifo_wrport_adr];
end
always @(posedge sys_clk) begin
	if (uart_rx_fifo_rdport_re)
		storage_1_dat1 <= storage_1[uart_rx_fifo_rdport_adr];
end
assign uart_rx_fifo_wrport_dat_r = storage_1_dat0;
assign uart_rx_fifo_rdport_dat_r = storage_1_dat1;


BUFG BUFG(
	.I(crg_clkout0),
	.O(crg_clkout_buf0)
);

BUFG BUFG_1(
	.I(crg_clkout1),
	.O(crg_clkout_buf1)
);

top top(
	.buttons_module_btn(user_btn0),
	.ext_vga_x(graphics_vtg_sink_payload_hcount),
	.ext_vga_y(graphics_vtg_sink_payload_vcount),
	.pixel_clock(vga_clk),
	.dvi_blue_DEBUG_return_output(graphics_source_payload_b),
	.dvi_green_DEBUG_return_output(graphics_source_payload_g),
	.dvi_red_DEBUG_return_output(graphics_source_payload_r)
);

FDCE FDCE(
	.C(crg_clkin),
	.CE(1'd1),
	.CLR(1'd0),
	.D(crg_reset),
	.Q(soccore_reset0)
);

FDCE FDCE_1(
	.C(crg_clkin),
	.CE(1'd1),
	.CLR(1'd0),
	.D(soccore_reset0),
	.Q(soccore_reset1)
);

FDCE FDCE_2(
	.C(crg_clkin),
	.CE(1'd1),
	.CLR(1'd0),
	.D(soccore_reset1),
	.Q(soccore_reset2)
);

FDCE FDCE_3(
	.C(crg_clkin),
	.CE(1'd1),
	.CLR(1'd0),
	.D(soccore_reset2),
	.Q(soccore_reset3)
);

FDCE FDCE_4(
	.C(crg_clkin),
	.CE(1'd1),
	.CLR(1'd0),
	.D(soccore_reset3),
	.Q(soccore_reset4)
);

FDCE FDCE_5(
	.C(crg_clkin),
	.CE(1'd1),
	.CLR(1'd0),
	.D(soccore_reset4),
	.Q(soccore_reset5)
);

FDCE FDCE_6(
	.C(crg_clkin),
	.CE(1'd1),
	.CLR(1'd0),
	.D(soccore_reset5),
	.Q(soccore_reset6)
);

FDCE FDCE_7(
	.C(crg_clkin),
	.CE(1'd1),
	.CLR(1'd0),
	.D(soccore_reset6),
	.Q(soccore_reset7)
);

PLLE2_ADV #(
	.CLKFBOUT_MULT(5'd16),
	.CLKIN1_PERIOD(10.0),
	.CLKOUT0_DIVIDE(5'd16),
	.CLKOUT0_PHASE(1'd0),
	.CLKOUT1_DIVIDE(7'd64),
	.CLKOUT1_PHASE(1'd0),
	.DIVCLK_DIVIDE(1'd1),
	.REF_JITTER1(0.01),
	.STARTUP_WAIT("FALSE")
) PLLE2_ADV (
	.CLKFBIN(soccore_pll_fb),
	.CLKIN1(crg_clkin),
	.PWRDWN(crg_power_down),
	.RST(soccore_reset7),
	.CLKFBOUT(soccore_pll_fb),
	.CLKOUT0(crg_clkout0),
	.CLKOUT1(crg_clkout1),
	.LOCKED(crg_locked)
);

FDPE #(
	.INIT(1'd1)
) FDPE (
	.C(sys_clk),
	.CE(1'd1),
	.D(1'd0),
	.PRE(xilinxasyncresetsynchronizerimpl0),
	.Q(xilinxasyncresetsynchronizerimpl0_rst_meta)
);

FDPE #(
	.INIT(1'd1)
) FDPE_1 (
	.C(sys_clk),
	.CE(1'd1),
	.D(xilinxasyncresetsynchronizerimpl0_rst_meta),
	.PRE(xilinxasyncresetsynchronizerimpl0),
	.Q(sys_rst)
);

FDPE #(
	.INIT(1'd1)
) FDPE_2 (
	.C(vga_clk),
	.CE(1'd1),
	.D(1'd0),
	.PRE(xilinxasyncresetsynchronizerimpl1),
	.Q(xilinxasyncresetsynchronizerimpl1_rst_meta)
);

FDPE #(
	.INIT(1'd1)
) FDPE_3 (
	.C(vga_clk),
	.CE(1'd1),
	.D(xilinxasyncresetsynchronizerimpl1_rst_meta),
	.PRE(xilinxasyncresetsynchronizerimpl1),
	.Q(vga_rst)
);

ODDR #(
	.DDR_CLK_EDGE("SAME_EDGE")
) ODDR (
	.C(vga_clk),
	.CE(1'd1),
	.D1(sink_payload_hsync),
	.D2(sink_payload_hsync),
	.R(1'd0),
	.S(1'd0),
	.Q(vga_hsync)
);

ODDR #(
	.DDR_CLK_EDGE("SAME_EDGE")
) ODDR_1 (
	.C(vga_clk),
	.CE(1'd1),
	.D1(sink_payload_vsync),
	.D2(sink_payload_vsync),
	.R(1'd0),
	.S(1'd0),
	.Q(vga_vsync)
);

ODDR #(
	.DDR_CLK_EDGE("SAME_EDGE")
) ODDR_2 (
	.C(vga_clk),
	.CE(1'd1),
	.D1((sink_payload_r[4] & sink_payload_de)),
	.D2((sink_payload_r[4] & sink_payload_de)),
	.R(1'd0),
	.S(1'd0),
	.Q(vga_r[0])
);

ODDR #(
	.DDR_CLK_EDGE("SAME_EDGE")
) ODDR_3 (
	.C(vga_clk),
	.CE(1'd1),
	.D1((sink_payload_g[4] & sink_payload_de)),
	.D2((sink_payload_g[4] & sink_payload_de)),
	.R(1'd0),
	.S(1'd0),
	.Q(vga_g[0])
);

ODDR #(
	.DDR_CLK_EDGE("SAME_EDGE")
) ODDR_4 (
	.C(vga_clk),
	.CE(1'd1),
	.D1((sink_payload_b[4] & sink_payload_de)),
	.D2((sink_payload_b[4] & sink_payload_de)),
	.R(1'd0),
	.S(1'd0),
	.Q(vga_b[0])
);

ODDR #(
	.DDR_CLK_EDGE("SAME_EDGE")
) ODDR_5 (
	.C(vga_clk),
	.CE(1'd1),
	.D1((sink_payload_r[5] & sink_payload_de)),
	.D2((sink_payload_r[5] & sink_payload_de)),
	.R(1'd0),
	.S(1'd0),
	.Q(vga_r[1])
);

ODDR #(
	.DDR_CLK_EDGE("SAME_EDGE")
) ODDR_6 (
	.C(vga_clk),
	.CE(1'd1),
	.D1((sink_payload_g[5] & sink_payload_de)),
	.D2((sink_payload_g[5] & sink_payload_de)),
	.R(1'd0),
	.S(1'd0),
	.Q(vga_g[1])
);

ODDR #(
	.DDR_CLK_EDGE("SAME_EDGE")
) ODDR_7 (
	.C(vga_clk),
	.CE(1'd1),
	.D1((sink_payload_b[5] & sink_payload_de)),
	.D2((sink_payload_b[5] & sink_payload_de)),
	.R(1'd0),
	.S(1'd0),
	.Q(vga_b[1])
);

ODDR #(
	.DDR_CLK_EDGE("SAME_EDGE")
) ODDR_8 (
	.C(vga_clk),
	.CE(1'd1),
	.D1((sink_payload_r[6] & sink_payload_de)),
	.D2((sink_payload_r[6] & sink_payload_de)),
	.R(1'd0),
	.S(1'd0),
	.Q(vga_r[2])
);

ODDR #(
	.DDR_CLK_EDGE("SAME_EDGE")
) ODDR_9 (
	.C(vga_clk),
	.CE(1'd1),
	.D1((sink_payload_g[6] & sink_payload_de)),
	.D2((sink_payload_g[6] & sink_payload_de)),
	.R(1'd0),
	.S(1'd0),
	.Q(vga_g[2])
);

ODDR #(
	.DDR_CLK_EDGE("SAME_EDGE")
) ODDR_10 (
	.C(vga_clk),
	.CE(1'd1),
	.D1((sink_payload_b[6] & sink_payload_de)),
	.D2((sink_payload_b[6] & sink_payload_de)),
	.R(1'd0),
	.S(1'd0),
	.Q(vga_b[2])
);

ODDR #(
	.DDR_CLK_EDGE("SAME_EDGE")
) ODDR_11 (
	.C(vga_clk),
	.CE(1'd1),
	.D1((sink_payload_r[7] & sink_payload_de)),
	.D2((sink_payload_r[7] & sink_payload_de)),
	.R(1'd0),
	.S(1'd0),
	.Q(vga_r[3])
);

ODDR #(
	.DDR_CLK_EDGE("SAME_EDGE")
) ODDR_12 (
	.C(vga_clk),
	.CE(1'd1),
	.D1((sink_payload_g[7] & sink_payload_de)),
	.D2((sink_payload_g[7] & sink_payload_de)),
	.R(1'd0),
	.S(1'd0),
	.Q(vga_g[3])
);

ODDR #(
	.DDR_CLK_EDGE("SAME_EDGE")
) ODDR_13 (
	.C(vga_clk),
	.CE(1'd1),
	.D1((sink_payload_b[7] & sink_payload_de)),
	.D2((sink_payload_b[7] & sink_payload_de)),
	.R(1'd0),
	.S(1'd0),
	.Q(vga_b[3])
);

endmodule

// -----------------------------------------------------------------------------
//  Auto-Generated by LiteX on 2023-01-27 10:00:41.
//------------------------------------------------------------------------------```