suarezvictor

# This is an nmigen delay line for ECP5 FPGAs using the open source toolchain. It strings together a series of
# manually placed carry chains into a "thermometer." It returns a signal that's (length) long that represents
# the chain "snapshotted" at the primary clock domain (using the flip flops colocated in the slice).
#
# This can be used in a Time to Digital Converter (i.e. to measure the time between to events) or in
# an ADC by comparing (with LVDS) a signal to a reference signal.
#
# Note that the bit precision (read: delay per carry element) varies as a function of temperature. On 
# a LFE5U-25F-8MG285C, I've measure delay times of approximately 43ps on average. Due to assorted reasons,
# the delay time will vary between bits and due to variations in routing (even when manually places), you might 

suarezvictor

# This is an nmigen delay line for ECP5 FPGAs using the open source toolchain. It strings together a series of
# manually placed carry chains into a "thermometer." It returns a signal that's (length) long that represents
# the chain "snapshotted" at the primary clock domain (using the flip flops colocated in the slice).
#
# This can be used in a Time to Digital Converter (i.e. to measure the time between to events) or in
# an ADC by comparing (with LVDS) a signal to a reference signal.
#
# Note that the bit precision (read: delay per carry element) varies as a function of temperature. On 
# a LFE5U-25F-8MG285C, I've measure delay times of approximately 43ps on average. Due to assorted reasons,
# the delay time will vary between bits and due to variations in routing (even when manually places), you might