SoC Voltage: 1.25V
MEM_VDD: 1.35V
CPU_VDDIO: 1.35V
MEM_VDDQ: 1.35V
VDDIO / MVDD / MVDDQ: 1.35V
VSOC: 1.25V
tCL: 30
tRCD: 36 (RD & WR)
tRP: 36
tCL: just use EXPO
tRCD: just use EXPO
tRP: just use EXPO
tRAS: 126* (Use 76 from EXPO for this memory)
tRC: 68
tWR: 48
tREFI: 50000
tRFC: 500
tRFC2: 400
tRFC4: 300
tRTP: 12
tRRD_L: 8 // Some hynix A-die really really sucks at tRRD_L
tRRD_S: 4
tFAW: 20
tWTR_L: 16
tWTR_S: 6
tRDRDSCL: 4
tRDRDSC: 1
tRDRDSD: AUTO (only relevant for dual rank)
tRDRDDD: AUTO (only relevant for multi rank)
tWRWRSCL: 4
tWRWRSC: 1
tWRWRSD: AUTO (only relevant for dual rank)
tWRWRDD: AUTO (only relevant for multi rank)
tWRRD: 2
tRDWR: 16
FCLK: 2000
UCLK DIV1 Mode: UCLK=MEMCLK (1:1 Mode)
Power Down Enable: Disabled
Memory Context Restore: Disabled
*This was previously 30. (There were stability issues and screen flickering whilie using igpu...)
Buildzoid: "as far as I can tell. Setting tRAS to 126 has no effect on performance. While setting tRAS too low can cause stability issues. Also AMD's memory controller doesn't follow the JEDEC spec of tRC = tRAS+tRP. So setting tRC really low even to the register limit of 32 actually gains performance even when tRAS and tRP are set to 126 and 36 (which according to JEDEC would be a tRC of 162). IDK if tRC 32 is good idea(as in stable)."