intended op mapping

intended-mapping.json

{
  "llvm.add": "add",
  "llvm.fadd": "fadd",
  "llvm.sub": "sub",
  "llvm.fsub": "fsub",
  "llvm.mul": "mul",
  "llvm.fmul": "fmul",
  "llvm.udiv": "udiv",
  "llvm.sdiv": "sdiv",
  "llvm.fdiv": "fdiv",
  "llvm.urem": "urem",
  "llvm.srem": "srem",
  "llvm.frem": "frem",
  "llvm.shl": "shl",
  "llvm.lshr": "lshr",
  "llvm.ashr": "ashr",
  "llvm.and": "and_",
  "llvm.or": "or_",
  "llvm.xor": "xor",
  "llvm.alloca": "alloca",
  "llvm.load": "load",
  "llvm.store": "store",
  "llvm.getelementptr": "gep",
  "llvm.trunc": "trunc",
  "llvm.zext": "zext",
  "llvm.sext": "sext",
  "llvm.fpext": "fpext",
  "llvm.sitofp": "sitofp",
  "llvm.ptrtoint": "ptrtoint",
  "llvm.inttoptr": "inttoptr",
  "llvm.bitcast": "bitcast",
  "llvm.extractvalue": "extract_value",
  "llvm.insertvalue": "insert_value",
  "llvm.call": "call",
  "llvm.return": "ret",
  "llvm.unreachable": "unreachable",
  "llvm.inline_asm": "asm",
  "llvm.icmp": null,
  "llvm.mlir.addressof": null,
  "llvm.mlir.constant": null,
  "llvm.mlir.global": null,
  "llvm.mlir.null": null,
  "llvm.mlir.undef": null,
  "llvm.mlir.zero": null,
  "llvm.func": null,
  "llvm.call_intrinsic": null,
  "cf.br": "branch",
  "cf.cond_br": "cbranch",
  "cf.switch": "switch",
  "vector.extractelement": "extract_element",
  "vector.insertelement": "insert_element",
  "vector.shuffle": "shuffle_vector",
  "vector.fma": "fma",
  "vector.bitcast": "bitcast"
}

output.txt

-------------------- xDSL Builtin Ops
        ModuleOp (builtin.module)
        UnrealizedConversionCastOp (builtin.unrealized_conversion_cast)
        UnregisteredOp (builtin.unregistered)
-------------------- xDSL LLVM Ops
        AShrOp (llvm.ashr)
        AddOp (llvm.add)
        AddressOfOp (llvm.mlir.addressof)
        AllocaOp (llvm.alloca)
        AndOp (llvm.and)
        BitcastOp (llvm.bitcast)
        CallIntrinsicOp (llvm.call_intrinsic)
        CallOp (llvm.call)
        ConstantOp (llvm.mlir.constant)
        ExtractValueOp (llvm.extractvalue)
        FAddOp (llvm.fadd)
        FDivOp (llvm.fdiv)
        FMulOp (llvm.fmul)
        FPExtOp (llvm.fpext)
        FRemOp (llvm.frem)
        FSubOp (llvm.fsub)
        FuncOp (llvm.func)
        GEPOp (llvm.getelementptr)
        GlobalOp (llvm.mlir.global)
        ICmpOp (llvm.icmp)
        InlineAsmOp (llvm.inline_asm)
        InsertValueOp (llvm.insertvalue)
        IntToPtrOp (llvm.inttoptr)
        LShrOp (llvm.lshr)
        LoadOp (llvm.load)
        MulOp (llvm.mul)
        NullOp (llvm.mlir.null)
        OrOp (llvm.or)
        PtrToIntOp (llvm.ptrtoint)
        ReturnOp (llvm.return)
        SDivOp (llvm.sdiv)
        SExtOp (llvm.sext)
        SIToFPOp (llvm.sitofp)
        SRemOp (llvm.srem)
        ShlOp (llvm.shl)
        StoreOp (llvm.store)
        SubOp (llvm.sub)
        TruncOp (llvm.trunc)
        UDivOp (llvm.udiv)
        URemOp (llvm.urem)
        UndefOp (llvm.mlir.undef)
        UnreachableOp (llvm.unreachable)
        XOrOp (llvm.xor)
        ZExtOp (llvm.zext)
        ZeroOp (llvm.mlir.zero)
-------------------- xDSL Control Flow (cf) Ops
        AssertOp (cf.assert)
        BranchOp (cf.br)
        ConditionalBranchOp (cf.cond_br)
        SwitchOp (cf.switch)
-------------------- xDSL Func Ops
        CallOp (func.call)
        FuncOp (func.func)
        ReturnOp (func.return)
-------------------- xDSL Vector Ops
        BitcastOp (vector.bitcast)
        BroadcastOp (vector.broadcast)
        CreateMaskOp (vector.create_mask)
        ExtractElementOp (vector.extractelement)
        ExtractOp (vector.extract)
        FMAOp (vector.fma)
        InsertElementOp (vector.insertelement)
        InsertOp (vector.insert)
        LoadOp (vector.load)
        MaskedLoadOp (vector.maskedload)
        MaskedStoreOp (vector.maskedstore)
        PrintOp (vector.print)
        ReductionOp (vector.reduction)
        ShuffleOp (vector.shuffle)
        StoreOp (vector.store)
        TransferReadOp (vector.transfer_read)
        TransferWriteOp (vector.transfer_write)
-------------------- xDSL GPU Ops
        AllReduceOp (gpu.all_reduce)
        AllocOp (gpu.alloc)
        BarrierOp (gpu.barrier)
        BlockDimOp (gpu.block_dim)
        BlockIdOp (gpu.block_id)
        DeallocOp (gpu.dealloc)
        FuncOp (gpu.func)
        GlobalIdOp (gpu.global_id)
        GridDimOp (gpu.grid_dim)
        HostRegisterOp (gpu.host_register)
        HostUnregisterOp (gpu.host_unregister)
        LaneIdOp (gpu.lane_id)
        LaunchFuncOp (gpu.launch_func)
        LaunchOp (gpu.launch)
        MemcpyOp (gpu.memcpy)
        ModuleOp (gpu.module)
        NumSubgroupsOp (gpu.num_subgroups)
        ReturnOp (gpu.return)
        SetDefaultDeviceOp (gpu.set_default_device)
        SubgroupIdOp (gpu.subgroup_id)
        SubgroupSizeOp (gpu.subgroup_size)
        TerminatorOp (gpu.terminator)
        ThreadIdOp (gpu.thread_id)
        WaitOp (gpu.wait)
        YieldOp (gpu.yield)
-------------------- xDSL OpenMP (omp) Ops
        DeclareReductionOp (omp.declare_reduction)
        DistributeOp (omp.distribute)
        LoopNestOp (omp.loop_nest)
        MapBoundsOp (omp.map.bounds)
        MapInfoOp (omp.map.info)
        ParallelOp (omp.parallel)
        PrivateClauseOp (omp.private)
        SimdOp (omp.simd)
        TargetDataOp (omp.target_data)
        TargetEnterDataOp (omp.target_enter_data)
        TargetExitDataOp (omp.target_exit_data)
        TargetOp (omp.target)
        TargetUpdateOp (omp.target_update)
        TeamsOp (omp.teams)
        TerminatorOp (omp.terminator)
        WsLoopOp (omp.wsloop)
        YieldOp (omp.yield)
-------------------- llvmlite ops (builder methods)
        add
        addrspacecast
        alloca
        and_
        ashr
        asm
        assume
        atomic_rmw
        bitcast
        bitreverse
        branch
        branch_indirect
        bswap
        call
        cbranch
        cmpxchg
        comment
        convert_from_fp16
        convert_to_fp16
        ctlz
        ctpop
        cttz
        extract_element
        extract_value
        fadd
        fcmp_ordered
        fcmp_unordered
        fdiv
        fence
        fma
        fmul
        fneg
        fpext
        fptosi
        fptoui
        fptrunc
        frem
        fsub
        gep
        icmp_signed
        icmp_unsigned
        insert_element
        insert_value
        inttoptr
        invoke
        landingpad
        load
        load_atomic
        load_reg
        lshr
        mul
        neg
        not_
        or_
        phi
        ptrtoint
        resume
        ret
        ret_void
        sadd_with_overflow
        sdiv
        select
        sext
        shl
        shuffle_vector
        sitofp
        smul_with_overflow
        srem
        ssub_with_overflow
        store
        store_atomic
        store_reg
        sub
        switch
        trunc
        uadd_with_overflow
        udiv
        uitofp
        umul_with_overflow
        unreachable
        urem
        usub_with_overflow
        xor
        zext
-------------------- llvmlite structure classes
        Block
        Function
        GlobalVariable
        MetaDataString
        Module
        NamedMetaData

script.py

from xdsl.dialects import builtin, llvm, cf, func, vector, gpu, omp
from xdsl.ir import Operation
import inspect
import llvmlite.ir as ir

print_section = lambda title: print(f"{'-' * 20} {title}")

# xdsl distributes llvm functionality across specific dialects
dialects = [
    (builtin, "xDSL Builtin Ops"),
    (llvm, "xDSL LLVM Ops"),
    (cf, "xDSL Control Flow (cf) Ops"),
    (func, "xDSL Func Ops"),
    (vector, "xDSL Vector Ops"),
    (gpu, "xDSL GPU Ops"),
    (omp, "xDSL OpenMP (omp) Ops"),
]

for mod, title in dialects:
    print_section(title)
    # verify 'name' to exclude abstract bases and mixins
    ops = [
        (n, o)
        for n, o in inspect.getmembers(mod)
        if inspect.isclass(o)
        and issubclass(o, Operation)
        and o is not Operation
        and hasattr(o, "name")
        and o.name
    ]
    for name, cls in sorted(ops):
        print(f"\t{name} ({cls.name})")

print_section("llvmlite ops (builder methods)")

# exclude helpers that have no direct llvm instruction equivalent
blacklist = {
    "append_basic_block",
    "position_at_start",
    "position_at_end",
    "position_before",
    "position_after",
    "goto_block",
    "goto_entry_block",
    "if_else",
    "if_then",
    "remove",
}

# llvmlite exposes instructions as builder methods
builder_methods = [
    n
    for n, o in inspect.getmembers(ir.IRBuilder)
    if inspect.isfunction(o) and not n.startswith("_") and n not in blacklist
]

for name in sorted(builder_methods):
    print(f"\t{name}")

print_section("llvmlite structure classes")

# core constructs not created via builder
structure_classes = {
    "Module",
    "Function",
    "GlobalVariable",
    "Block",
    "MetaDataString",
    "NamedMetaData",
}
ir_classes = [
    n
    for n, o in inspect.getmembers(ir)
    if inspect.isclass(o) and n in structure_classes
]

for name in sorted(ir_classes):
    print(f"\t{name}")

llvm only mapping:

{
  "unmatched_xdsl": [
    "llvm.call_intrinsic",
    "llvm.mlir.addressof",
    "llvm.mlir.constant",
    "llvm.mlir.global",
    "llvm.mlir.null",
    "llvm.mlir.undef",
    "llvm.mlir.zero"
  ],
  "unmatched_llvmlite": [
    "addrspacecast",
    "append_basic_block",
    "assume",
    "atomic_rmw",
    "basic_block",
    "bitreverse",
    "block",
    "branch",
    "branch_indirect",
    "bswap",
    "cbranch",
    "cmpxchg",
    "comment",
    "convert_from_fp16",
    "convert_to_fp16",
    "ctlz",
    "ctpop",
    "cttz",
    "extract_element",
    "fcmp_ordered",
    "fcmp_unordered",
    "fence",
    "fma",
    "fneg",
    "fptosi",
    "fptoui",
    "fptrunc",
    "goto_block",
    "goto_entry_block",
    "icmp_unsigned",
    "if_else",
    "if_then",
    "insert_element",
    "invoke",
    "landingpad",
    "load_atomic",
    "load_reg",
    "module",
    "neg",
    "not_",
    "phi",
    "position_after",
    "position_at_end",
    "position_at_start",
    "position_before",
    "remove",
    "resume",
    "ret_void",
    "sadd_with_overflow",
    "select",
    "shuffle_vector",
    "smul_with_overflow",
    "ssub_with_overflow",
    "store_atomic",
    "store_reg",
    "switch",
    "uadd_with_overflow",
    "uitofp",
    "umul_with_overflow",
    "usub_with_overflow"
  ],
  "mapping": {
    "llvm.add": "add",
    "llvm.alloca": "alloca",
    "llvm.and": "and_",
    "llvm.ashr": "ashr",
    "llvm.bitcast": "bitcast",
    "llvm.call": "call",
    "llvm.call_intrinsic": null,
    "llvm.extractvalue": "extract_value",
    "llvm.fadd": "fadd",
    "llvm.fdiv": "fdiv",
    "llvm.fmul": "fmul",
    "llvm.fpext": "fpext",
    "llvm.frem": "frem",
    "llvm.fsub": "fsub",
    "llvm.func": "function",
    "llvm.getelementptr": "gep",
    "llvm.icmp": "icmp_signed",
    "llvm.inline_asm": "asm",
    "llvm.insertvalue": "insert_value",
    "llvm.inttoptr": "inttoptr",
    "llvm.load": "load",
    "llvm.lshr": "lshr",
    "llvm.mlir.addressof": null,
    "llvm.mlir.constant": null,
    "llvm.mlir.global": null,
    "llvm.mlir.null": null,
    "llvm.mlir.undef": null,
    "llvm.mlir.zero": null,
    "llvm.mul": "mul",
    "llvm.or": "or_",
    "llvm.ptrtoint": "ptrtoint",
    "llvm.return": "ret",
    "llvm.sdiv": "sdiv",
    "llvm.sext": "sext",
    "llvm.shl": "shl",
    "llvm.sitofp": "sitofp",
    "llvm.srem": "srem",
    "llvm.store": "store",
    "llvm.sub": "sub",
    "llvm.trunc": "trunc",
    "llvm.udiv": "udiv",
    "llvm.unreachable": "unreachable",
    "llvm.urem": "urem",
    "llvm.xor": "xor",
    "llvm.zext": "zext"
  }
}