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Corefreq Jasper Forest Test 2021-06-26-1
Raw
00.corefreqd-cli-M
GenuineIntel [ 0]
Controller #0
Bus Rate 0 MHz Bus Speed 0 MHz DRAM Speed 0 MHz
Cha CL RCD RP RAS RRD RFC WR RTPr WTPr FAW B2B CWL CMD REFI
ddWR drWR srWR ddRW drRW srRW ddRR drRR srRR ddWW drWW srWW CKE ECC
Raw
01.corefreqk.h
/*
* CoreFreq
* Copyright (C) 2015-2021 CYRIL INGENIERIE
* Licenses: GPL2
*/
#define RDCOUNTER(_val, _cnt) \
({ \
unsigned int _lo, _hi; \
\
__asm__ volatile \
( \
"rdmsr" \
: "=a" (_lo), \
"=d" (_hi) \
: "c" (_cnt) \
); \
_val=_lo | ((unsigned long long) _hi << 32); \
})
#define WRCOUNTER(_val, _cnt) \
__asm__ volatile \
( \
"wrmsr" \
: \
: "c" (_cnt), \
"a" ((unsigned int) _val & 0xFFFFFFFF), \
"d" ((_val > 0xFFFFFFFF) ? \
(unsigned int) (_val >> 32) : 0) \
);
#define RDMSR(_data, _reg) \
({ \
unsigned int _lo, _hi; \
\
__asm__ volatile \
( \
"rdmsr" \
: "=a" (_lo), \
"=d" (_hi) \
: "c" (_reg) \
); \
_data.value=_lo | ((unsigned long long) _hi << 32); \
})
#define WRMSR(_data, _reg) \
__asm__ volatile \
( \
"wrmsr" \
: \
: "c" (_reg), \
"a" ((unsigned int) _data.value & 0xFFFFFFFF), \
"d" ((unsigned int) (_data.value >> 32)) \
);
#define RDMSR64(_data, _reg) \
__asm__ volatile \
( \
"xorq %%rax, %%rax" "\n\t" \
"xorq %%rdx, %%rdx" "\n\t" \
"movq %1,%%rcx" "\n\t" \
"rdmsr" "\n\t" \
"shlq $32, %%rdx" "\n\t" \
"orq %%rdx, %%rax" "\n\t" \
"movq %%rax, %0" \
: "=m" (_data) \
: "i" (_reg) \
: "%rax", "%rcx", "%rdx" \
)
#define WRMSR64(_data, _reg) \
__asm__ volatile \
( \
"movq %0, %%rax" "\n\t" \
"movq %%rax, %%rdx" "\n\t" \
"shrq $32, %%rdx" "\n\t" \
"movq %1, %%rcx" "\n\t" \
"wrmsr" \
: "=m" (_data) \
: "i" (_reg) \
: "%rax", "%rcx", "%rdx" \
)
#define Atomic_Read_VPMC(_lock, _dest, _src) \
{ \
__asm__ volatile \
( \
"xorq %%rax , %%rax" "\n\t" \
_lock "cmpxchg %%rax , %[src]" "\n\t" \
"movq %%rax , %[dest]" \
: [dest] "=m" (_dest) \
: [src] "m" (_src) \
: "%rax", "cc", "memory" \
); \
}
#define Atomic_Add_VPMC(_lock, _dest, _src) \
{ \
__asm__ volatile \
( \
"xorq %%rax , %%rax" "\n\t" \
_lock "cmpxchg %%rax , %[src]" "\n\t" \
"addq %%rax , %[dest]" \
: [dest] "=m" (_dest) \
: [src] "m" (_src) \
: "%rax", "cc", "memory" \
); \
}
#define ASM_CODE_RDMSR(_msr, _reg) \
"# Read MSR counter." "\n\t" \
"movq $" #_msr ", %%rcx" "\n\t" \
"rdmsr" "\n\t" \
"shlq $32, %%rdx" "\n\t" \
"orq %%rdx, %%rax" "\n\t" \
"# Save counter value." "\n\t" \
"movq %%rax, %%" #_reg "\n\t"
#define ASM_RDMSR(_msr, _reg) ASM_CODE_RDMSR(_msr, _reg)
#define ASM_COUNTERx1( _reg0, _reg1, \
_tsc_inst, mem_tsc, \
_msr1, _mem1) \
__asm__ volatile \
( \
_tsc_inst(_reg0) \
ASM_RDMSR(_msr1, _reg1) \
"# Store values into memory." "\n\t" \
"movq %%" #_reg0 ", %0" "\n\t" \
"movq %%" #_reg1 ", %1" \
: "=m" (mem_tsc), "=m" (_mem1) \
: \
: "%rax", "%rcx", "%rdx", \
"%" #_reg0"", "%" #_reg1"", \
"cc", "memory" \
);
#define ASM_COUNTERx2( _reg0, _reg1, _reg2, \
_tsc_inst, mem_tsc, \
_msr1, _mem1, _msr2, _mem2) \
__asm__ volatile \
( \
_tsc_inst(_reg0) \
ASM_RDMSR(_msr1, _reg1) \
ASM_RDMSR(_msr2, _reg2) \
"# Store values into memory." "\n\t" \
"movq %%" #_reg0 ", %0" "\n\t" \
"movq %%" #_reg1 ", %1" "\n\t" \
"movq %%" #_reg2 ", %2" \
: "=m" (mem_tsc), "=m" (_mem1), "=m" (_mem2) \
: \
: "%rax", "%rcx", "%rdx", \
"%" #_reg0"", "%" #_reg1"", "%" #_reg2"", \
"cc", "memory" \
);
#define ASM_COUNTERx3( _reg0, _reg1, _reg2, _reg3, \
_tsc_inst, mem_tsc, \
_msr1, _mem1, _msr2, _mem2, _msr3, _mem3) \
__asm__ volatile \
( \
_tsc_inst(_reg0) \
ASM_RDMSR(_msr1, _reg1) \
ASM_RDMSR(_msr2, _reg2) \
ASM_RDMSR(_msr3, _reg3) \
"# Store values into memory." "\n\t" \
"movq %%" #_reg0 ", %0" "\n\t" \
"movq %%" #_reg1 ", %1" "\n\t" \
"movq %%" #_reg2 ", %2" "\n\t" \
"movq %%" #_reg3 ", %3" \
: "=m" (mem_tsc), "=m" (_mem1), "=m" (_mem2), "=m" (_mem3) \
: \
: "%rax", "%rcx", "%rdx", \
"%" #_reg0"", "%" #_reg1"", "%" #_reg2"", "%" #_reg3"", \
"cc", "memory" \
);
#define ASM_COUNTERx4( _reg0, _reg1, _reg2, _reg3, _reg4, \
_tsc_inst, mem_tsc, \
_msr1, _mem1, _msr2, _mem2, _msr3, _mem3, \
_msr4, _mem4) \
__asm__ volatile \
( \
_tsc_inst(_reg0) \
ASM_RDMSR(_msr1, _reg1) \
ASM_RDMSR(_msr2, _reg2) \
ASM_RDMSR(_msr3, _reg3) \
ASM_RDMSR(_msr4, _reg4) \
"# Store values into memory." "\n\t" \
"movq %%" #_reg0 ", %0" "\n\t" \
"movq %%" #_reg1 ", %1" "\n\t" \
"movq %%" #_reg2 ", %2" "\n\t" \
"movq %%" #_reg3 ", %3" "\n\t" \
"movq %%" #_reg4 ", %4" \
: "=m" (mem_tsc), "=m" (_mem1), "=m" (_mem2), "=m" (_mem3), \
"=m" (_mem4) \
: \
: "%rax", "%rcx", "%rdx", \
"%" #_reg0"", "%" #_reg1"", "%" #_reg2"", "%" #_reg3"", \
"%" #_reg4"", \
"cc", "memory" \
);
#define ASM_COUNTERx5( _reg0, _reg1, _reg2, _reg3, _reg4, _reg5, \
_tsc_inst, mem_tsc, \
_msr1, _mem1, _msr2, _mem2, _msr3, _mem3, \
_msr4, _mem4, _msr5, _mem5) \
__asm__ volatile \
( \
_tsc_inst(_reg0) \
ASM_RDMSR(_msr1, _reg1) \
ASM_RDMSR(_msr2, _reg2) \
ASM_RDMSR(_msr3, _reg3) \
ASM_RDMSR(_msr4, _reg4) \
ASM_RDMSR(_msr5, _reg5) \
"# Store values into memory." "\n\t" \
"movq %%" #_reg0 ", %0" "\n\t" \
"movq %%" #_reg1 ", %1" "\n\t" \
"movq %%" #_reg2 ", %2" "\n\t" \
"movq %%" #_reg3 ", %3" "\n\t" \
"movq %%" #_reg4 ", %4" "\n\t" \
"movq %%" #_reg5 ", %5" \
: "=m" (mem_tsc), "=m" (_mem1), "=m" (_mem2), "=m" (_mem3), \
"=m" (_mem4), "=m" (_mem5) \
: \
: "%rax", "%rcx", "%rdx", \
"%" #_reg0"", "%" #_reg1"", "%" #_reg2"", "%" #_reg3"", \
"%" #_reg4"", "%" #_reg5"", \
"cc", "memory" \
);
#define ASM_COUNTERx5_STACK(_reg0, _reg1, _reg2, _reg3, \
_tsc_inst, mem_tsc, \
_msr1, _mem1, _msr2, _mem2, _msr3, _mem3, \
_msr4, _mem4, _msr5, _mem5) \
__asm__ volatile \
( \
_tsc_inst(_reg0) \
ASM_RDMSR(_msr1, _reg1) \
ASM_RDMSR(_msr2, _reg2) \
ASM_RDMSR(_msr3, _reg3) \
"pushq %%" #_reg3 "\n\t" \
ASM_RDMSR(_msr4, _reg3) \
"pushq %%" #_reg3 "\n\t" \
ASM_RDMSR(_msr5, _reg3) \
"# Store values into memory." "\n\t" \
"movq %%" #_reg0 ", %0" "\n\t" \
"movq %%" #_reg1 ", %1" "\n\t" \
"movq %%" #_reg2 ", %2" "\n\t" \
"movq %%" #_reg3 ", %5" "\n\t" \
"popq %%" #_reg3 "\n\t" \
"movq %%" #_reg3 ", %4" "\n\t" \
"popq %%" #_reg3 "\n\t" \
"movq %%" #_reg3 ", %3" \
: "=m" (mem_tsc), "=m" (_mem1), "=m" (_mem2), "=m" (_mem3), \
"=m" (_mem4), "=m" (_mem5) \
: \
: "%rax", "%rcx", "%rdx", \
"%" #_reg0"", "%" #_reg1"", "%" #_reg2"", "%" #_reg3"", \
"cc", "memory" \
);
#define ASM_COUNTERx6( _reg0, _reg1, _reg2, _reg3, _reg4, _reg5, _reg6,\
_tsc_inst, mem_tsc, \
_msr1, _mem1, _msr2, _mem2, _msr3, _mem3, \
_msr4, _mem4, _msr5, _mem5, _msr6, _mem6) \
__asm__ volatile \
( \
_tsc_inst(_reg0) \
ASM_RDMSR(_msr1, _reg1) \
ASM_RDMSR(_msr2, _reg2) \
ASM_RDMSR(_msr3, _reg3) \
ASM_RDMSR(_msr4, _reg4) \
ASM_RDMSR(_msr5, _reg5) \
ASM_RDMSR(_msr6, _reg6) \
"# Store values into memory." "\n\t" \
"movq %%" #_reg0 ", %0" "\n\t" \
"movq %%" #_reg1 ", %1" "\n\t" \
"movq %%" #_reg2 ", %2" "\n\t" \
"movq %%" #_reg3 ", %3" "\n\t" \
"movq %%" #_reg4 ", %4" "\n\t" \
"movq %%" #_reg5 ", %5" "\n\t" \
"movq %%" #_reg6 ", %6" \
: "=m" (mem_tsc), "=m" (_mem1), "=m" (_mem2), "=m" (_mem3), \
"=m" (_mem4), "=m" (_mem5), "=m" (_mem6) \
: \
: "%rax", "%rcx", "%rdx", \
"%" #_reg0"", "%" #_reg1"", "%" #_reg2"", "%" #_reg3"", \
"%" #_reg4"", "%" #_reg5"", "%" #_reg6"", \
"cc", "memory" \
);
#define ASM_COUNTERx6_STACK(_reg0, _reg1, _reg2, _reg3, \
_tsc_inst, mem_tsc, \
_msr1, _mem1, _msr2, _mem2, _msr3, _mem3, \
_msr4, _mem4, _msr5, _mem5, _msr6, _mem6) \
__asm__ volatile \
( \
_tsc_inst(_reg0) \
ASM_RDMSR(_msr1, _reg1) \
ASM_RDMSR(_msr2, _reg2) \
ASM_RDMSR(_msr3, _reg3) \
"pushq %%" #_reg3 "\n\t" \
ASM_RDMSR(_msr4, _reg3) \
"pushq %%" #_reg3 "\n\t" \
ASM_RDMSR(_msr5, _reg3) \
"pushq %%" #_reg3 "\n\t" \
ASM_RDMSR(_msr6, _reg3) \
"# Store values into memory." "\n\t" \
"movq %%" #_reg0 ", %0" "\n\t" \
"movq %%" #_reg1 ", %1" "\n\t" \
"movq %%" #_reg2 ", %2" "\n\t" \
"movq %%" #_reg3 ", %6" "\n\t" \
"popq %%" #_reg3 "\n\t" \
"movq %%" #_reg3 ", %5" "\n\t" \
"popq %%" #_reg3 "\n\t" \
"movq %%" #_reg3 ", %4" "\n\t" \
"popq %%" #_reg3 "\n\t" \
"movq %%" #_reg3 ", %3" \
: "=m" (mem_tsc), "=m" (_mem1), "=m" (_mem2), "=m" (_mem3), \
"=m" (_mem4), "=m" (_mem5), "=m" (_mem6) \
: \
: "%rax", "%rcx", "%rdx", \
"%" #_reg0"", "%" #_reg1"", "%" #_reg2"", "%" #_reg3"", \
"cc", "memory" \
);
#define ASM_COUNTERx7( _reg0, _reg1, _reg2, _reg3, \
_reg4, _reg5, _reg6, _reg7, \
_tsc_inst, mem_tsc, \
_msr1, _mem1, _msr2, _mem2, _msr3, _mem3, \
_msr4, _mem4, _msr5, _mem5, _msr6, _mem6, \
_msr7, _mem7) \
__asm__ volatile \
( \
_tsc_inst(_reg0) \
ASM_RDMSR(_msr1, _reg1) \
ASM_RDMSR(_msr2, _reg2) \
ASM_RDMSR(_msr3, _reg3) \
ASM_RDMSR(_msr4, _reg4) \
ASM_RDMSR(_msr5, _reg5) \
ASM_RDMSR(_msr6, _reg6) \
ASM_RDMSR(_msr7, _reg7) \
"# Store values into memory." "\n\t" \
"movq %%" #_reg0 ", %0" "\n\t" \
"movq %%" #_reg1 ", %1" "\n\t" \
"movq %%" #_reg2 ", %2" "\n\t" \
"movq %%" #_reg3 ", %3" "\n\t" \
"movq %%" #_reg4 ", %4" "\n\t" \
"movq %%" #_reg5 ", %5" "\n\t" \
"movq %%" #_reg6 ", %6" "\n\t" \
"movq %%" #_reg7 ", %7" \
: "=m" (mem_tsc), "=m" (_mem1), "=m" (_mem2), "=m" (_mem3), \
"=m" (_mem4), "=m" (_mem5), "=m" (_mem6), "=m" (_mem7) \
: \
: "%rax", "%rcx", "%rdx", \
"%" #_reg0"", "%" #_reg1"", "%" #_reg2"", "%" #_reg3"", \
"%" #_reg4"", "%" #_reg5"", "%" #_reg6"", "%" #_reg7"", \
"cc", "memory" \
);
#define ASM_COUNTERx7_STACK(_reg0, _reg1, _reg2, \
_tsc_inst, mem_tsc, \
_msr1, _mem1, _msr2, _mem2, _msr3, _mem3, \
_msr4, _mem4, _msr5, _mem5, _msr6, _mem6, \
_msr7, _mem7) \
__asm__ volatile \
( \
_tsc_inst(_reg0) \
ASM_RDMSR(_msr1, _reg1) \
ASM_RDMSR(_msr2, _reg2) \
"pushq %%" #_reg2 "\n\t" \
ASM_RDMSR(_msr3, _reg2) \
"pushq %%" #_reg2 "\n\t" \
ASM_RDMSR(_msr4, _reg2) \
"pushq %%" #_reg2 "\n\t" \
ASM_RDMSR(_msr5, _reg2) \
"pushq %%" #_reg2 "\n\t" \
ASM_RDMSR(_msr6, _reg2) \
"pushq %%" #_reg2 "\n\t" \
ASM_RDMSR(_msr7, _reg2) \
"# Store values into memory." "\n\t" \
"movq %%" #_reg0 ", %0" "\n\t" \
"movq %%" #_reg1 ", %1" "\n\t" \
"movq %%" #_reg2 ", %7" "\n\t" \
"popq %%" #_reg2 "\n\t" \
"movq %%" #_reg2 ", %6" "\n\t" \
"popq %%" #_reg2 "\n\t" \
"movq %%" #_reg2 ", %5" "\n\t" \
"popq %%" #_reg2 "\n\t" \
"movq %%" #_reg2 ", %4" "\n\t" \
"popq %%" #_reg2 "\n\t" \
"movq %%" #_reg2 ", %3" "\n\t" \
"popq %%" #_reg2 "\n\t" \
"movq %%" #_reg2 ", %2" \
: "=m" (mem_tsc), "=m" (_mem1), "=m" (_mem2), "=m" (_mem3), \
"=m" (_mem4), "=m" (_mem5), "=m" (_mem6), "=m" (_mem7) \
: \
: "%rax", "%rcx", "%rdx", \
"%" #_reg0"", "%" #_reg1"", "%" #_reg2"", \
"cc", "memory" \
);
#define RDTSC_COUNTERx1(mem_tsc, ...) \
ASM_COUNTERx1(r10, r11, ASM_RDTSC, mem_tsc, __VA_ARGS__)
#define RDTSCP_COUNTERx1(mem_tsc, ...) \
ASM_COUNTERx1(r10, r11, ASM_RDTSCP, mem_tsc, __VA_ARGS__)
#define RDTSC_COUNTERx2(mem_tsc, ...) \
ASM_COUNTERx2(r10, r11, r12, ASM_RDTSC, mem_tsc, __VA_ARGS__)
#define RDTSCP_COUNTERx2(mem_tsc, ...) \
ASM_COUNTERx2(r10, r11, r12, ASM_RDTSCP, mem_tsc, __VA_ARGS__)
#define RDTSC_COUNTERx3(mem_tsc, ...) \
ASM_COUNTERx3(r10, r11, r12, r13, ASM_RDTSC, mem_tsc, __VA_ARGS__)
#define RDTSCP_COUNTERx3(mem_tsc, ...) \
ASM_COUNTERx3(r10, r11, r12, r13, ASM_RDTSCP, mem_tsc, __VA_ARGS__)
#define RDTSC_COUNTERx4(mem_tsc, ...) \
ASM_COUNTERx4(r10, r11, r12, r13, r14, ASM_RDTSC, mem_tsc, __VA_ARGS__)
#define RDTSCP_COUNTERx4(mem_tsc, ...) \
ASM_COUNTERx4(r10, r11, r12, r13, r14, ASM_RDTSCP, mem_tsc, __VA_ARGS__)
#if defined(OPTIM_LVL) && OPTIM_LVL == 0
#define RDTSC_COUNTERx5(mem_tsc, ...) \
ASM_COUNTERx5_STACK(r12, r13, r14, r15, ASM_RDTSC, mem_tsc, __VA_ARGS__)
#define RDTSCP_COUNTERx5(mem_tsc, ...) \
ASM_COUNTERx5_STACK(r12, r13, r14, r15, ASM_RDTSCP, mem_tsc, __VA_ARGS__)
#define RDTSC_COUNTERx6(mem_tsc, ...) \
ASM_COUNTERx6_STACK(r12, r13, r14, r15, ASM_RDTSC, mem_tsc, __VA_ARGS__)
#define RDTSCP_COUNTERx6(mem_tsc, ...) \
ASM_COUNTERx6_STACK(r12, r13, r14, r15, ASM_RDTSCP, mem_tsc, __VA_ARGS__)
#define RDTSC_COUNTERx7(mem_tsc, ...) \
ASM_COUNTERx7_STACK(r13, r14, r15, ASM_RDTSC, mem_tsc, __VA_ARGS__)
#define RDTSCP_COUNTERx7(mem_tsc, ...) \
ASM_COUNTERx7_STACK(r13, r14, r15, ASM_RDTSCP, mem_tsc, __VA_ARGS__)
#else
/* #warning "Optimization" */
#define RDTSC_COUNTERx5(mem_tsc, ...) \
ASM_COUNTERx5(r10, r11, r12, r13, r14, r15, ASM_RDTSC, mem_tsc, __VA_ARGS__)
#define RDTSCP_COUNTERx5(mem_tsc, ...) \
ASM_COUNTERx5(r10, r11, r12, r13, r14, r15, ASM_RDTSCP, mem_tsc, __VA_ARGS__)
#define RDTSC_COUNTERx6(mem_tsc, ...) \
ASM_COUNTERx6(r10, r11, r12, r13, r14, r15, r9, ASM_RDTSC, mem_tsc, __VA_ARGS__)
#define RDTSCP_COUNTERx6(mem_tsc, ...) \
ASM_COUNTERx6(r10, r11, r12, r13, r14, r15, r9, ASM_RDTSCP, mem_tsc,__VA_ARGS__)
#define RDTSC_COUNTERx7(mem_tsc, ...) \
ASM_COUNTERx7(r10, r11, r12, r13, r14, r15,r9,r8,ASM_RDTSC,mem_tsc,__VA_ARGS__)
#define RDTSCP_COUNTERx7(mem_tsc, ...) \
ASM_COUNTERx7(r10, r11, r12, r13, r14, r15,r9,r8,ASM_RDTSCP,mem_tsc,__VA_ARGS__)
#endif
#define PCI_CONFIG_ADDRESS(bus, dev, fn, reg) \
(0x80000000 | ((bus) << 16)|((dev) << 11)|((fn) << 8)|((reg) & ~3))
#define RDPCI(_data, _reg) \
({ \
__asm__ volatile \
( \
"movl %1, %%eax" "\n\t" \
"movl $0xcf8, %%edx" "\n\t" \
"outl %%eax, %%dx" "\n\t" \
"movl $0xcfc, %%edx" "\n\t" \
"inl %%dx, %%eax" "\n\t" \
"movl %%eax, %0" \
: "=m" (_data) \
: "ir" (_reg) \
: "%rax", "%rdx", "memory" \
); \
})
#define WRPCI(_data, _reg) \
({ \
__asm__ volatile \
( \
"movl %1, %%eax" "\n\t" \
"movl $0xcf8, %%edx" "\n\t" \
"outl %%eax, %%dx" "\n\t" \
"movl %0, %%eax" "\n\t" \
"movl $0xcfc, %%edx" "\n\t" \
"outl %%eax, %%dx" \
: \
: "irm" (_data), \
"ir" (_reg) \
: "%rax", "%rdx", "memory" \
); \
})
/* Manufacturers Identifier Strings. */
#define VENDOR_INTEL "GenuineIntel"
#define VENDOR_AMD "AuthenticAMD"
#define VENDOR_HYGON "HygonGenuine"
#define VENDOR_KVM "TCGTGTCGCGTC"
#define VENDOR_VBOX "VBoxVBoxVBox"
#define VENDOR_KBOX "KVMKM"
#define VENDOR_VMWARE "VMwawarereVM"
#define VENDOR_HYPERV "Micrt Hvosof"
/* Source: Winbond W83627 and ITE IT8720F datasheets */
#define HWM_SIO_INDEX_PORT 0x295
#define HWM_SIO_DATA_PORT 0x296
#define HWM_SIO_CPUVCORE 0x20
#define RDSIO(_data, _reg, _index_port, _data_port) \
({ \
__asm__ volatile \
( \
"movw %1, %%ax" "\n\t" \
"movw %2, %%dx" "\n\t" \
"outw %%ax, %%dx" "\n\t" \
"movw %3, %%dx" "\n\t" \
"inb %%dx, %%al" "\n\t" \
"movb %%al, %0" \
: "=m" (_data) \
: "i" (_reg) , \
"i" (_index_port), \
"i" (_data_port) \
: "%ax", "%dx", "memory" \
); \
})
/* Hardware Monitoring: Super I/O chipset identifiers */
#define COMPATIBLE 0xffff
#define W83627 0x5ca3
#define IT8720 0x8720
/*
* --- Core_AMD_SMN_Read and Core_AMD_SMN_Write ---
*
* amd_smn_read() and amd_smn_write() protect any SMU access through
* mutex_[un]lock functions which must not be used in interrupt context.
*
* The high resolution timers are bound to CPUs using smp_call_function_*
* where context is interrupt; and where mutexes will freeze the kernel.
*/
#if defined(CONFIG_AMD_NB) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 20, 0))\
&& defined(LEGACY) && (LEGACY > 1)
FEAT_MSG("LEGACY Level 2: built with amd_smn_read(), amd_smn_write()")
#define Core_AMD_SMN_Read( SMN_Register, \
SMN_Address, \
SMU_IndexRegister, \
SMU_DataRegister ) \
({ \
if (PRIVATE(OF(ZenIF_dev)) != NULL) \
{ \
if (amd_smn_read(amd_pci_dev_to_node_id(PRIVATE(OF(ZenIF_dev))),\
SMN_Address, &SMN_Register.value)) \
{ \
pr_warn("CoreFreq: Failed to read amd_smn_read()\n"); \
} \
} \
})
#define Core_AMD_SMN_Write( SMN_Register, \
SMN_Address, \
SMU_IndexRegister, \
SMU_DataRegister ) \
({ \
if (PRIVATE(OF(ZenIF_dev)) != NULL) \
{ \
if (amd_smn_write(amd_pci_dev_to_node_id(PRIVATE(OF(ZenIF_dev))),\
SMN_Address, &SMN_Register.value)) \
{ \
pr_warn("CoreFreq: Failed to write amd_smn_write()\n"); \
} \
} \
})
#else
#define Core_AMD_SMN_Read( SMN_Register, \
SMN_Address, \
SMU_IndexRegister, \
SMU_DataRegister ) \
({ \
unsigned int tries = BIT_IO_RETRIES_COUNT; \
unsigned char ret; \
do { \
ret = BIT_ATOM_TRYLOCK( BUS_LOCK, \
PRIVATE(OF(AMD_SMN_LOCK)), \
ATOMIC_SEED ); \
if ( ret == 0 ) { \
udelay(BIT_IO_DELAY_INTERVAL); \
} else { \
WRPCI(SMN_Address, SMU_IndexRegister); \
RDPCI(SMN_Register.value, SMU_DataRegister); \
\
BIT_ATOM_UNLOCK(BUS_LOCK, \
PRIVATE(OF(AMD_SMN_LOCK)), \
ATOMIC_SEED); \
} \
tries--; \
} while ( (tries != 0) && (ret != 1) ); \
if (tries == 0) { \
pr_warn("CoreFreq: Core_AMD_SMN_Read(%x, %x) TryLock\n", \
SMN_Register.value, SMN_Address); \
} \
})
#define Core_AMD_SMN_Write( SMN_Register, \
SMN_Address, \
SMU_IndexRegister, \
SMU_DataRegister ) \
({ \
unsigned int tries = BIT_IO_RETRIES_COUNT; \
unsigned char ret; \
do { \
ret = BIT_ATOM_TRYLOCK( BUS_LOCK, \
PRIVATE(OF(AMD_SMN_LOCK)), \
ATOMIC_SEED ); \
if ( ret == 0 ) { \
udelay(BIT_IO_DELAY_INTERVAL); \
} else { \
WRPCI(SMN_Address, SMU_IndexRegister); \
WRPCI(SMN_Register.value, SMU_DataRegister); \
\
BIT_ATOM_UNLOCK(BUS_LOCK, \
PRIVATE(OF(AMD_SMN_LOCK)), \
ATOMIC_SEED); \
} \
tries--; \
} while ( (tries != 0) && (ret != 1) ); \
if (tries == 0) { \
pr_warn("CoreFreq: Core_AMD_SMN_Write(%x, %x) TryLock\n", \
SMN_Register.value, SMN_Address); \
} \
})
#endif /* CONFIG_AMD_NB and LEGACY */
typedef union
{
unsigned int value;
struct
{
unsigned int
bits : 32-0;
};
} HSMP_ARG;
#define AMD_HSMP_Mailbox( MSG_FUNC, \
MSG_ARG, \
HSMP_CmdRegister, \
HSMP_ArgRegister, \
HSMP_RspRegister, \
SMU_IndexRegister, \
SMU_DataRegister ) \
({ \
HSMP_ARG MSG_RSP = {.value = 0x0}; \
HSMP_ARG MSG_ID = {.value = MSG_FUNC}; \
unsigned int tries = BIT_IO_RETRIES_COUNT; \
unsigned char ret; \
do { \
ret = BIT_ATOM_TRYLOCK( BUS_LOCK, \
PRIVATE(OF(AMD_SMN_LOCK)), \
ATOMIC_SEED ); \
if ( ret == 0 ) { \
udelay(BIT_IO_DELAY_INTERVAL); \
} \
else \
{ \
unsigned int idx; \
unsigned char wait; \
\
WRPCI(HSMP_RspRegister , SMU_IndexRegister); \
WRPCI(MSG_RSP.value , SMU_DataRegister); \
\
for (idx = 0; idx < 8; idx++) { \
WRPCI(HSMP_ArgRegister + (idx << 2), SMU_IndexRegister);\
WRPCI(MSG_ARG[idx].value, SMU_DataRegister); \
} \
WRPCI(HSMP_CmdRegister , SMU_IndexRegister); \
WRPCI(MSG_ID.value , SMU_DataRegister); \
\
idx = BIT_IO_RETRIES_COUNT; \
do { \
WRPCI(HSMP_RspRegister , SMU_IndexRegister); \
RDPCI(MSG_RSP.value , SMU_DataRegister); \
\
idx--; \
wait = (idx != 0) && (MSG_RSP.value == 0x0) ? 1 : 0; \
if (wait == 1) { \
udelay(BIT_IO_DELAY_INTERVAL); \
} \
} while (wait == 1); \
if (idx == 0) { \
pr_warn("CoreFreq: AMD_HSMP_Mailbox(%x) Timeout\n", \
MSG_FUNC); \
} \
else if (MSG_RSP.value == 0x1) \
{ \
for (idx = 0; idx < 8; idx++) { \
WRPCI(HSMP_ArgRegister + (idx << 2), SMU_IndexRegister);\
RDPCI(MSG_ARG[idx].value, SMU_DataRegister); \
} \
} \
BIT_ATOM_UNLOCK(BUS_LOCK, \
PRIVATE(OF(AMD_SMN_LOCK)), \
ATOMIC_SEED); \
} \
tries--; \
} while ( (tries != 0) && (ret != 1) ); \
if (tries == 0) { \
pr_warn("CoreFreq: AMD_HSMP_Mailbox(%x) TryLock\n", MSG_FUNC); \
} \
MSG_RSP.value; \
})
/* Driver' private and public data definitions. */
enum CSTATES_CLASS {
CSTATES_NHM,
CSTATES_SNB,
CSTATES_ULT,
CSTATES_SKL,
CSTATES_SOC_SLM,
CSTATES_SOC_GDM
};
#define LATCH_NONE 0b0000
#define LATCH_TGT_RATIO_UNLOCK 0b0001 /* <T> TgtRatioUnlocked */
#define LATCH_CLK_RATIO_UNLOCK 0b0010 /* <X> ClkRatioUnlocked */
#define LATCH_TURBO_UNLOCK 0b0100 /* <B> TurboUnlocked */
#define LATCH_UNCORE_UNLOCK 0b1000 /* <U> UncoreUnlocked */
typedef struct {
char *CodeName;
} MICRO_ARCH;
typedef struct {
char **Brand;
unsigned int Boost[2];
THERMAL_PARAM Param;
unsigned int CodeNameIdx : 8-0,
TgtRatioUnlocked: 9-8, /* <T:1> */
ClkRatioUnlocked: 11-9, /* <X:2> */
TurboUnlocked : 12-11, /* <B:1> */
UncoreUnlocked : 13-12, /* <U:1> */
_UnusedSpecBits : 28-13,
Latch : 32-28; /* <U>-<B>-<X>-<T> */
} PROCESSOR_SPECIFIC;
typedef struct {
FEATURES *Features;
char *Brand;
unsigned int SMT_Count,
localProcessor;
signed int rc;
} INIT_ARG;
typedef struct { /* V[0] stores the previous TSC */
unsigned long long V[2]; /* V[1] stores the current TSC */
} TSC_STRUCT;
#define OCCURRENCES 4
/* OCCURRENCES x 2 (TSC values) needs a 64-byte cache line size. */
#define STRUCT_SIZE (OCCURRENCES * sizeof(TSC_STRUCT))
typedef struct {
TSC_STRUCT *TSC[2];
CLOCK Clock;
} COMPUTE_ARG;
typedef struct
{
PROC_RO *Proc_RO;
PROC_RW *Proc_RW;
SYSGATE_RO *Gate;
struct kmem_cache *Cache;
CORE_RO **Core_RO;
CORE_RW **Core_RW;
} KPUBLIC;
enum { CREATED, STARTED, MUSTFWD };
typedef struct
{
struct hrtimer Timer;
/*
TSM: Timer State Machine
CREATED: 1-0
STARTED: 2-1
MUSTFWD: 3-2
*/
Bit64 TSM __attribute__ ((aligned (8)));
} JOIN;
typedef struct
{
PROCESSOR_SPECIFIC *Specific;
#ifdef CONFIG_AMD_NB
struct pci_dev *ZenIF_dev;
#endif
Bit64 AMD_SMN_LOCK __attribute__ ((aligned (8)));
Bit64 AMD_FCH_LOCK __attribute__ ((aligned (8)));
struct kmem_cache *Cache;
JOIN *Join[];
} KPRIVATE;
/* Sources:
* Intel® 64 and IA-32 Architectures Software Developer’s Manual; Vol. 2A
* AMD64 Architecture Programmer’s Manual; Vol. 3
*/
static const CPUID_STRUCT CpuIDforVendor[CPUID_MAX_FUNC] = {
/* x86 */
[CPUID_00000001_00000000_INSTRUCTION_SET]
= {.func = 0x00000001, .sub = 0x00000000},
/* Intel */
[CPUID_00000002_00000000_CACHE_AND_TLB]
= {.func = 0x00000002, .sub = 0x00000000},
[CPUID_00000003_00000000_PROC_SERIAL_NUMBER]
= {.func = 0x00000003, .sub = 0x00000000},
[CPUID_00000004_00000000_CACHE_L1I]
= {.func = 0x00000004, .sub = 0x00000000},
[CPUID_00000004_00000001_CACHE_L1D]
= {.func = 0x00000004, .sub = 0x00000001},
[CPUID_00000004_00000002_CACHE_L2]
= {.func = 0x00000004, .sub = 0x00000002},
[CPUID_00000004_00000003_CACHE_L3]
= {.func = 0x00000004, .sub = 0x00000003},
/* x86 */
[CPUID_00000005_00000000_MONITOR_MWAIT]
= {.func = 0x00000005, .sub = 0x00000000},
[CPUID_00000006_00000000_POWER_AND_THERMAL_MGMT]
= {.func = 0x00000006, .sub = 0x00000000},
[CPUID_00000007_00000000_EXTENDED_FEATURES]
= {.func = 0x00000007, .sub = 0x00000000},
[CPUID_00000007_00000001_EXT_FEAT_SUB_LEAF_1]
= {.func = 0x00000007, .sub = 0x00000001},
/* Intel */
[CPUID_00000009_00000000_DIRECT_CACHE_ACCESS]
= {.func = 0x00000009, .sub = 0x00000000},
[CPUID_0000000A_00000000_PERF_MONITORING]
= {.func = 0x0000000a, .sub = 0x00000000},
/* x86 */
[CPUID_0000000B_00000000_EXT_TOPOLOGY]
= {.func = 0x0000000b, .sub = 0x00000000},
[CPUID_0000000D_00000000_EXT_STATE_MAIN_LEAF]
= {.func = 0x0000000d, .sub = 0x00000000},
[CPUID_0000000D_00000001_EXT_STATE_SUB_LEAF]
= {.func = 0x0000000d, .sub = 0x00000001},
/* AMD */
[CPUID_0000000D_00000002_EXT_STATE_SUB_LEAF]
= {.func = 0x0000000d, .sub = 0x00000002},
[CPUID_0000000D_00000003_BNDREGS_STATE]
= {.func = 0x0000000d, .sub = 0x00000003},
[CPUID_0000000D_00000004_BNDCSR_STATE]
= {.func = 0x0000000d, .sub = 0x00000004},
/* AMD Family 15h */
[CPUID_0000000D_0000003E_EXT_STATE_SUB_LEAF]
= {.func = 0x0000000d, .sub = 0x0000003e},
/* Intel */
[CPUID_0000000F_00000000_QOS_MONITORING_CAP]
= {.func = 0x0000000f, .sub = 0x00000000},
[CPUID_0000000F_00000001_L3_QOS_MONITORING]
= {.func = 0x0000000f, .sub = 0x00000001},
[CPUID_00000010_00000000_QOS_ENFORCEMENT_CAP]
= {.func = 0x00000010, .sub = 0x00000000},
[CPUID_00000010_00000001_L3_ALLOC_ENUMERATION]
= {.func = 0x00000010, .sub = 0x00000001},
[CPUID_00000010_00000002_L2_ALLOC_ENUMERATION]
= {.func = 0x00000010, .sub = 0x00000002},
[CPUID_00000010_00000003_RAM_BANDWIDTH_ENUM]
= {.func = 0x00000010, .sub = 0x00000003},
[CPUID_00000012_00000000_SGX_CAPABILITY]
= {.func = 0x00000012, .sub = 0x00000000},
[CPUID_00000012_00000001_SGX_ATTRIBUTES]
= {.func = 0x00000012, .sub = 0x00000001},
[CPUID_00000012_00000002_SGX_ENCLAVE_PAGE_CACHE]
= {.func = 0x00000012, .sub = 0x00000002},
[CPUID_00000014_00000000_PROCESSOR_TRACE]
= {.func = 0x00000014, .sub = 0x00000000},
[CPUID_00000014_00000001_PROC_TRACE_SUB_LEAF]
= {.func = 0x00000014, .sub = 0x00000001},
[CPUID_00000015_00000000_TIME_STAMP_COUNTER]
= {.func = 0x00000015, .sub = 0x00000000},
[CPUID_00000016_00000000_PROCESSOR_FREQUENCY]
= {.func = 0x00000016, .sub = 0x00000000},
[CPUID_00000017_00000000_SYSTEM_ON_CHIP]
= {.func = 0x00000017, .sub = 0x00000000},
[CPUID_00000017_00000001_SOC_ATTRIB_SUB_LEAF_1]
= {.func = 0x00000017, .sub = 0x00000001},
[CPUID_00000017_00000002_SOC_ATTRIB_SUB_LEAF_2]
= {.func = 0x00000017, .sub = 0x00000002},
[CPUID_00000017_00000003_SOC_ATTRIB_SUB_LEAF_3]
= {.func = 0x00000017, .sub = 0x00000003},
/* Intel */
[CPUID_00000018_00000000_ADDRESS_TRANSLATION]
= {.func = 0x00000018, .sub = 0x00000000},
[CPUID_00000018_00000001_DAT_SUB_LEAF_1]
= {.func = 0x00000018, .sub = 0x00000001},
[CPUID_00000019_00000000_KEY_LOCKER]
= {.func = 0x00000019, .sub = 0x00000000},
[CPUID_0000001A_00000000_HYBRID_INFORMATION]
= {.func = 0x0000001a, .sub = 0x00000000},
[CPUID_0000001B_00000000_PCONFIG_INFORMATION]
= {.func = 0x0000001b, .sub = 0x00000000},
[CPUID_0000001F_00000000_EXT_TOPOLOGY_V2]
= {.func = 0x0000001f, .sub = 0x00000000},
/* x86 */
[CPUID_80000001_00000000_EXTENDED_FEATURES]
= {.func = 0x80000001, .sub = 0x00000000},
[CPUID_80000002_00000000_PROCESSOR_NAME_ID]
= {.func = 0x80000002, .sub = 0x00000000},
[CPUID_80000003_00000000_PROCESSOR_NAME_ID]
= {.func = 0x80000003, .sub = 0x00000000},
[CPUID_80000004_00000000_PROCESSOR_NAME_ID]
= {.func = 0x80000004, .sub = 0x00000000},
/* AMD */
[CPUID_80000005_00000000_CACHES_L1D_L1I_TLB]
= {.func = 0x80000005, .sub=0x00000000},
/* x86 */
[CPUID_80000006_00000000_CACHE_L2_SIZE_WAY]
= {.func = 0x80000006, .sub = 0x00000000},
[CPUID_80000007_00000000_ADVANCED_POWER_MGMT]
= {.func = 0x80000007, .sub = 0x00000000},
[CPUID_80000008_00000000_LM_ADDRESS_SIZE]
= {.func = 0x80000008, .sub = 0x00000000},
/* AMD */
[CPUID_8000000A_00000000_SVM_REVISION]
= {.func = 0x8000000a, .sub = 0x00000000},
[CPUID_80000019_00000000_CACHES_AND_TLB_1G]
= {.func = 0x80000019, .sub = 0x00000000},
[CPUID_8000001A_00000000_PERF_OPTIMIZATION]
= {.func = 0x8000001a, .sub = 0x00000000},
[CPUID_8000001B_00000000_INST_BASED_SAMPLING]
= {.func = 0x8000001b, .sub = 0x00000000},
[CPUID_8000001C_00000000_LIGHTWEIGHT_PROFILING]
= {.func = 0x8000001c, .sub = 0x00000000},
[CPUID_8000001D_00000000_CACHE_L1D_PROPERTIES]
= {.func = 0x8000001d, .sub = 0x00000000},
[CPUID_8000001D_00000001_CACHE_L1I_PROPERTIES]
= {.func = 0x8000001d, .sub = 0x00000001},
[CPUID_8000001D_00000002_CACHE_L2_PROPERTIES]
= {.func = 0x8000001d, .sub = 0x00000002},
[CPUID_8000001D_00000003_CACHE_PROPERTIES_END]
= {.func = 0x8000001d, .sub = 0x00000003},
[CPUID_8000001E_00000000_EXTENDED_IDENTIFIERS]
= {.func = 0x8000001e, .sub = 0x00000000},
/* x86 */
[CPUID_40000000_00000000_HYPERVISOR_VENDOR]
= {.func = 0x40000000, .sub = 0x00000000},
[CPUID_40000001_00000000_HYPERVISOR_INTERFACE]
= {.func = 0x40000001, .sub = 0x00000000},
[CPUID_40000002_00000000_HYPERVISOR_VERSION]
= {.func = 0x40000002, .sub = 0x00000000},
[CPUID_40000003_00000000_HYPERVISOR_FEATURES]
= {.func = 0x40000003, .sub = 0x00000000},
[CPUID_40000004_00000000_HYPERV_REQUIREMENTS]
= {.func = 0x40000004, .sub = 0x00000000},
[CPUID_40000005_00000000_HYPERVISOR_LIMITS]
= {.func = 0x40000005, .sub = 0x00000000},
[CPUID_40000006_00000000_HYPERVISOR_EXPLOITS]
= {.func = 0x40000006, .sub = 0x00000000},
};
typedef struct {
char *Name,
Desc[CPUIDLE_NAME_LEN];
unsigned long flags;
unsigned short Latency,
Residency;
} IDLE_STATE;
typedef struct {
IDLE_STATE *IdleState;
unsigned int (*GetFreq)(unsigned int cpu);
void (*SetTarget)(void *arg);
} SYSTEM_DRIVER;
typedef struct
{
struct SIGNATURE Signature;
void (*Query)(unsigned int cpu);
void (*Update)(void *arg); /* Must be static */
void (*Start)(void *arg); /* Must be static */
void (*Stop)(void *arg); /* Must be static */
void (*Exit)(void);
void (*Timer)(unsigned int cpu);
CLOCK (*BaseClock)(unsigned int ratio);
long (*ClockMod)(CLOCK_ARG *pClockMod);
long (*TurboClock)(CLOCK_ARG *pClockMod);
enum THERMAL_FORMULAS thermalFormula;
enum VOLTAGE_FORMULAS voltageFormula;
enum POWER_FORMULAS powerFormula;
struct pci_device_id *PCI_ids;
struct {
void (*Start)(void *arg); /* Must be static */
void (*Stop)(void *arg); /* Must be static */
long (*ClockMod)(CLOCK_ARG *pClockMod);
} Uncore;
PROCESSOR_SPECIFIC *Specific;
SYSTEM_DRIVER SystemDriver;
MICRO_ARCH *Architecture;
} ARCH;
extern CLOCK BaseClock_GenuineIntel(unsigned int ratio) ;
extern CLOCK BaseClock_AuthenticAMD(unsigned int ratio) ;
extern CLOCK BaseClock_Core(unsigned int ratio) ;
extern CLOCK BaseClock_Core2(unsigned int ratio) ;
extern CLOCK BaseClock_Atom(unsigned int ratio) ;
extern CLOCK BaseClock_Airmont(unsigned int ratio) ;
extern CLOCK BaseClock_Silvermont(unsigned int ratio) ;
extern CLOCK BaseClock_Nehalem(unsigned int ratio) ;
extern CLOCK BaseClock_Westmere(unsigned int ratio) ;
extern CLOCK BaseClock_SandyBridge(unsigned int ratio) ;
extern CLOCK BaseClock_IvyBridge(unsigned int ratio) ;
extern CLOCK BaseClock_Haswell(unsigned int ratio) ;
extern CLOCK BaseClock_Skylake(unsigned int ratio) ;
extern CLOCK BaseClock_AMD_Family_17h(unsigned int ratio) ;
#define BaseClock_AMD_Family_19h BaseClock_AMD_Family_17h
extern long Intel_Turbo_Config8C(CLOCK_ARG *pClockMod) ;
extern long TurboClock_IvyBridge_EP(CLOCK_ARG *pClockMod) ;
extern long TurboClock_Haswell_EP(CLOCK_ARG *pClockMod) ;
extern long TurboClock_Broadwell_EP(CLOCK_ARG *pClockMod) ;
extern long TurboClock_Skylake_X(CLOCK_ARG *pClockMod) ;
extern long TurboClock_AMD_Zen(CLOCK_ARG *pClockMod) ;
extern long ClockMod_Core2_PPC(CLOCK_ARG *pClockMod) ;
extern long ClockMod_Nehalem_PPC(CLOCK_ARG *pClockMod) ;
extern long ClockMod_SandyBridge_PPC(CLOCK_ARG *pClockMod) ;
extern long ClockMod_Intel_HWP(CLOCK_ARG *pClockMod) ;
#define ClockMod_Broadwell_EP_HWP ClockMod_Intel_HWP
#define ClockMod_Skylake_HWP ClockMod_Intel_HWP
extern long ClockMod_AMD_Zen(CLOCK_ARG *pClockMod) ;
extern long Haswell_Uncore_Ratio(CLOCK_ARG *pClockMod) ;
extern void Query_GenuineIntel(unsigned int cpu) ;
static void PerCore_Intel_Query(void *arg) ;
static void Start_GenuineIntel(void *arg) ;
static void Stop_GenuineIntel(void *arg) ;
extern void InitTimer_GenuineIntel(unsigned int cpu) ;
extern void Query_AuthenticAMD(unsigned int cpu) ;
static void PerCore_AuthenticAMD_Query(void *arg) ;
static void Start_AuthenticAMD(void *arg) ;
static void Stop_AuthenticAMD(void *arg) ;
extern void InitTimer_AuthenticAMD(unsigned int cpu) ;
extern void Query_Core2(unsigned int cpu) ;
static void PerCore_Core2_Query(void *arg) ;
static void Start_Core2(void *arg) ;
static void Stop_Core2(void *arg) ;
extern void InitTimer_Core2(unsigned int cpu) ;
extern void Query_Silvermont(unsigned int cpu) ;
static void PerCore_Silvermont_Query(void *arg) ;
static void Start_Silvermont(void *arg) ;
static void Stop_Silvermont(void *arg) ;
extern void InitTimer_Silvermont(unsigned int cpu) ;
extern void Query_Goldmont(unsigned int cpu) ;
static void PerCore_Goldmont_Query(void *arg) ;
static void Start_Goldmont(void *arg) ;
static void Stop_Goldmont(void *arg) ;
extern void InitTimer_Goldmont(unsigned int cpu) ;
extern void Query_Airmont(unsigned int cpu) ;
static void PerCore_Airmont_Query(void *arg) ;
extern void Query_Nehalem(unsigned int cpu) ;
static void PerCore_Nehalem_Query(void *arg) ;
static void PerCore_Nehalem_EX_Query(void *arg) ;
static void Start_Nehalem(void *arg) ;
static void Stop_Nehalem(void *arg) ;
extern void InitTimer_Nehalem(unsigned int cpu) ;
static void Start_Uncore_Nehalem(void *arg) ;
static void Stop_Uncore_Nehalem(void *arg) ;
extern void Query_Nehalem_EX(unsigned int cpu) ;
extern void Query_Avoton(unsigned int cpu) ;
static void PerCore_Avoton_Query(void *arg) ;
extern void Query_SandyBridge(unsigned int cpu) ;
static void PerCore_SandyBridge_Query(void *arg) ;
static void Start_SandyBridge(void *arg) ;
static void Stop_SandyBridge(void *arg) ;
extern void InitTimer_SandyBridge(unsigned int cpu) ;
static void Start_Uncore_SandyBridge(void *arg) ;
static void Stop_Uncore_SandyBridge(void *arg) ;
extern void Query_SandyBridge_EP(unsigned int cpu) ;
static void PerCore_SandyBridge_EP_Query(void *arg) ;
static void Start_SandyBridge_EP(void *arg) ;
static void Stop_SandyBridge_EP(void *arg) ;
extern void InitTimer_SandyBridge_EP(unsigned int cpu) ;
static void Start_Uncore_SandyBridge_EP(void *arg) ;
static void Stop_Uncore_SandyBridge_EP(void *arg) ;
extern void Query_IvyBridge(unsigned int cpu) ;
static void PerCore_IvyBridge_Query(void *arg) ;
extern void Query_IvyBridge_EP(unsigned int cpu) ;
static void PerCore_IvyBridge_EP_Query(void *arg) ;
static void Start_IvyBridge_EP(void *arg) ;
#define Stop_IvyBridge_EP Stop_SandyBridge_EP
extern void InitTimer_IvyBridge_EP(unsigned int cpu) ;
static void Start_Uncore_IvyBridge_EP(void *arg) ;
static void Stop_Uncore_IvyBridge_EP(void *arg) ;
extern void Query_Haswell(unsigned int cpu) ;
static void PerCore_Haswell_Query(void *arg) ;
extern void Query_Haswell_EP(unsigned int cpu) ;
static void PerCore_Haswell_EP_Query(void *arg) ;
static void Start_Haswell_EP(void *arg) ;
static void Stop_Haswell_EP(void *arg) ;
extern void InitTimer_Haswell_EP(unsigned int cpu) ;
static void Start_Uncore_Haswell_EP(void *arg) ;
static void Stop_Uncore_Haswell_EP(void *arg) ;
extern void Query_Haswell_ULT(unsigned int cpu) ;
static void PerCore_Haswell_ULT_Query(void *arg) ;
static void Start_Haswell_ULT(void *arg) ;
static void Stop_Haswell_ULT(void *arg) ;
extern void InitTimer_Haswell_ULT(unsigned int cpu) ;
static void Start_Uncore_Haswell_ULT(void *arg) ;
static void Stop_Uncore_Haswell_ULT(void *arg) ;
extern void Query_Haswell_ULX(unsigned int cpu) ;
static void PerCore_Haswell_ULX(void *arg) ;
extern void Query_Broadwell(unsigned int cpu) ;
static void PerCore_Broadwell_Query(void *arg) ;
#define Start_Broadwell Start_SandyBridge
#define Stop_Broadwell Stop_SandyBridge
#define InitTimer_Broadwell InitTimer_SandyBridge
#define Start_Uncore_Broadwell Start_Uncore_SandyBridge
#define Stop_Uncore_Broadwell Stop_Uncore_SandyBridge
extern void Query_Broadwell_EP(unsigned int cpu) ;
extern void Query_Skylake(unsigned int cpu) ;
static void PerCore_Skylake_Query(void *arg) ;
static void Start_Skylake(void *arg) ;
static void Stop_Skylake(void *arg) ;
extern void InitTimer_Skylake(unsigned int cpu) ;
static void Start_Uncore_Skylake(void *arg) ;
static void Stop_Uncore_Skylake(void *arg) ;
extern void Query_Skylake_X(unsigned int cpu) ;
static void PerCore_Skylake_X_Query(void *arg) ;
static void Start_Skylake_X(void *arg) ;
static void Stop_Skylake_X(void *arg) ;
extern void InitTimer_Skylake_X(unsigned int cpu) ;
static void Start_Uncore_Skylake_X(void *arg) ;
static void Stop_Uncore_Skylake_X(void *arg) ;
extern void Query_Kaby_Lake(unsigned int cpu) ;
static void PerCore_Kaby_Lake_Query(void *arg) ;
extern void Query_AMD_Family_0Fh(unsigned int cpu) ;
static void PerCore_AMD_Family_0Fh_Query(void *arg) ;
static void Start_AMD_Family_0Fh(void *arg) ;
static void Stop_AMD_Family_0Fh(void *arg) ;
extern void InitTimer_AMD_Family_0Fh(unsigned int cpu) ;
extern void Query_AMD_Family_10h(unsigned int cpu) ;
static void PerCore_AMD_Family_10h_Query(void *arg) ;
static void Start_AMD_Family_10h(void *arg) ;
static void Stop_AMD_Family_10h(void *arg) ;
#define InitTimer_AMD_Family_10h InitTimer_AuthenticAMD
extern void Query_AMD_Family_11h(unsigned int cpu) ;
static void PerCore_AMD_Family_11h_Query(void *arg) ;
static void Start_AMD_Family_11h(void *arg) ;
#define Stop_AMD_Family_11h Stop_AMD_Family_10h
#define InitTimer_AMD_Family_11h InitTimer_AuthenticAMD
extern void Query_AMD_Family_12h(unsigned int cpu) ;
static void PerCore_AMD_Family_12h_Query(void *arg) ;
static void Start_AMD_Family_12h(void *arg) ;
#define Stop_AMD_Family_12h Stop_AMD_Family_10h
#define InitTimer_AMD_Family_12h InitTimer_AuthenticAMD
extern void Query_AMD_Family_14h(unsigned int cpu) ;
static void PerCore_AMD_Family_14h_Query(void *arg) ;
static void Start_AMD_Family_14h(void *arg) ;
#define Stop_AMD_Family_14h Stop_AMD_Family_10h
#define InitTimer_AMD_Family_14h InitTimer_AuthenticAMD
extern void Query_AMD_Family_15h(unsigned int cpu) ;
static void PerCore_AMD_Family_15h_Query(void *arg) ;
static void Start_AMD_Family_15h(void *arg) ;
#define Stop_AMD_Family_15h Stop_AMD_Family_10h
extern void InitTimer_AMD_Family_15h(unsigned int cpu) ;
#define Query_AMD_Family_16h Query_AMD_Family_15h
#define PerCore_AMD_Family_16h_Query PerCore_AMD_Family_15h_Query
#define Start_AMD_Family_16h Start_AMD_Family_15h
#define Stop_AMD_Family_16h Stop_AMD_Family_15h
#define InitTimer_AMD_Family_16h InitTimer_AuthenticAMD
extern void Query_AMD_Family_17h(unsigned int cpu) ;
static void PerCore_AMD_Family_17h_Query(void *arg) ;
static void Start_AMD_Family_17h(void *arg) ;
static void Stop_AMD_Family_17h(void *arg) ;
extern void InitTimer_AMD_Family_17h(unsigned int cpu) ;
extern void InitTimer_AMD_F17h_Zen(unsigned int cpu) ;
extern void InitTimer_AMD_F17h_Zen2_SP(unsigned int cpu) ;
extern void InitTimer_AMD_F17h_Zen2_MP(unsigned int cpu) ;
extern void InitTimer_AMD_F17h_Zen2_APU(unsigned int cpu) ;
void Core_AMD_F17h_No_Thermal(CORE_RO *Core)
{
UNUSED(Core);
}
void CTL_AMD_Family_17h_Temp(CORE_RO *Core) ;
void CCD_AMD_Family_17h_Zen2_Temp(CORE_RO *Core) ;
void (*Core_AMD_Family_17h_Temp)(CORE_RO*) = Core_AMD_F17h_No_Thermal;
#define Query_AMD_Family_19h Query_AMD_Family_17h
#define PerCore_AMD_Family_19h_Query PerCore_AMD_Family_17h_Query
#define Start_AMD_Family_19h Start_AMD_Family_17h
#define Stop_AMD_Family_19h Stop_AMD_Family_17h
#define InitTimer_AMD_Family_19h InitTimer_AMD_Family_17h
#define InitTimer_AMD_F17h_Zen3_SP InitTimer_AMD_F17h_Zen2_SP
#define InitTimer_AMD_F17h_Zen3_MP InitTimer_AMD_F17h_Zen2_MP
/* [Void] */
#define _Void_Signature {.ExtFamily=0x0, .Family=0x0, .ExtModel=0x0, .Model=0x0}
/* [Core] 06_0Eh (32 bits) */
#define _Core_Yonah {.ExtFamily=0x0, .Family=0x6, .ExtModel=0x0, .Model=0xE}
/* [Core2] 06_0Fh, 06_15h, 06_16h, 06_17h, 06_1Dh */
#define _Core_Conroe {.ExtFamily=0x0, .Family=0x6, .ExtModel=0x0, .Model=0xF}
#define _Core_Kentsfield \
{.ExtFamily=0x0, .Family=0x6, .ExtModel=0x1, .Model=0x5}
#define _Core_Conroe_616 \
{.ExtFamily=0x0, .Family=0x6, .ExtModel=0x1, .Model=0x6}
#define _Core_Penryn {.ExtFamily=0x0, .Family=0x6, .ExtModel=0x1, .Model=0x7}
#define _Core_Dunnington \
{.ExtFamily=0x0, .Family=0x6, .ExtModel=0x1, .Model=0xD}
/* [Atom] 06_1Ch, 06_26h, 06_27h (32bits), 06_35h (32bits), 06_36h */
#define _Atom_Bonnell {.ExtFamily=0x0, .Family=0x6, .ExtModel=0x1, .Model=0xC}
#define _Atom_Silvermont \
{.ExtFamily=0x0, .Family=0x6, .ExtModel=0x2, .Model=0x6}
#define _Atom_Lincroft {.ExtFamily=0x0, .Family=0x6, .ExtModel=0x2, .Model=0x7}
#define _Atom_Clover_Trail \
{.ExtFamily=0x0, .Family=0x6, .ExtModel=0x3, .Model=0x5}
#define _Atom_Saltwell {.ExtFamily=0x0, .Family=0x6, .ExtModel=0x3, .Model=0x6}
/* [Silvermont/Bay_Trail] 06_37h */
#define _Silvermont_Bay_Trail \
{.ExtFamily=0x0, .Family=0x6, .ExtModel=0x3, .Model=0x7}
/* [Avoton] 06_4Dh */
#define _Atom_Avoton {.ExtFamily=0x0, .Family=0x6, .ExtModel=0x4, .Model=0xD}
/* [Airmont] 06_4Ch */
#define _Atom_Airmont {.ExtFamily=0x0, .Family=0x6, .ExtModel=0x4, .Model=0xC}
/* [Goldmont] 06_5Ch */
#define _Atom_Goldmont {.ExtFamily=0x0, .Family=0x6, .ExtModel=0x5, .Model=0xC}
/* [SoFIA] 06_5Dh */
#define _Atom_Sofia {.ExtFamily=0x0, .Family=0x6, .ExtModel=0x5, .Model=0xD}
/* [Merrifield] 06_4Ah */
#define _Atom_Merrifield \
{.ExtFamily=0x0, .Family=0x6, .ExtModel=0x4, .Model=0xA}
/* [Moorefield] 06_5Ah */
#define _Atom_Moorefield \
{.ExtFamily=0x0, .Family=0x6, .ExtModel=0x5, .Model=0xA}
/* [Denverton] 06_5Fh Stepping 0={A0,A1} 1={B0,B1} */
#define _Atom_Denverton {.ExtFamily=0x0, .Family=0x6, .ExtModel=0x5, .Model=0xF}
/* [Tremont/Jacobsville] 06_86h
[Tremont/Lakefield] 06_8Ah
[Sapphire Rapids] 06_8Fh
[Tremont/Elkhart Lake] 06_96h
[Tremont/Jasper Lake] 06_9Ch
[Snow Ridge] */
#define _Tremont_Jacobsville \
{.ExtFamily=0x0, .Family=0x6, .ExtModel=0x8, .Model=0x6}
#define _Tremont_Lakefield \
{.ExtFamily=0x0, .Family=0x6, .ExtModel=0x8, .Model=0xA}
#define _Sapphire_Rapids \
{.ExtFamily=0x0, .Family=0x6, .ExtModel=0x8, .Model=0xF}
#define _Tremont_Elkhartlake \
{.ExtFamily=0x0, .Family=0x6, .ExtModel=0x9, .Model=0x6}
#define _Tremont_Jasperlake \
{.ExtFamily=0x0, .Family=0x6, .ExtModel=0x9, .Model=0xC}
/* [Nehalem] 06_1Ah, 06_1Eh, 06_1Fh, 06_2Eh */
#define _Nehalem_Bloomfield \
{.ExtFamily=0x0, .Family=0x6, .ExtModel=0x1, .Model=0xA}
#define _Nehalem_Lynnfield \
{.ExtFamily=0x0, .Family=0x6, .ExtModel=0x1, .Model=0xE}
#define _Nehalem_MB {.ExtFamily=0x0, .Family=0x6, .ExtModel=0x1, .Model=0xF}
#define _Nehalem_EX {.ExtFamily=0x0, .Family=0x6, .ExtModel=0x2, .Model=0xE}
/* [Westmere] 06_25h, 06_2Ch, 06_2Fh */
#define _Westmere {.ExtFamily=0x0, .Family=0x6, .ExtModel=0x2, .Model=0x5}
#define _Westmere_EP {.ExtFamily=0x0, .Family=0x6, .ExtModel=0x2, .Model=0xC}
#define _Westmere_EX {.ExtFamily=0x0, .Family=0x6, .ExtModel=0x2, .Model=0xF}
/* [Sandy Bridge] 06_2Ah, 06_2Dh */
#define _SandyBridge {.ExtFamily=0x0, .Family=0x6, .ExtModel=0x2, .Model=0xA}
#define _SandyBridge_EP {.ExtFamily=0x0, .Family=0x6, .ExtModel=0x2, .Model=0xD}
/* [Ivy Bridge] 06_3Ah, 06_3Eh */
#define _IvyBridge {.ExtFamily=0x0, .Family=0x6, .ExtModel=0x3, .Model=0xA}
#define _IvyBridge_EP {.ExtFamily=0x0, .Family=0x6, .ExtModel=0x3, .Model=0xE}
/* [Haswell] 06_3Ch, 06_3Fh, 06_45h, 06_46h */
#define _Haswell_DT {.ExtFamily=0x0, .Family=0x6, .ExtModel=0x3, .Model=0xC}
#define _Haswell_EP {.ExtFamily=0x0, .Family=0x6, .ExtModel=0x3, .Model=0xF}
#define _Haswell_ULT {.ExtFamily=0x0, .Family=0x6, .ExtModel=0x4, .Model=0x5}
#define _Haswell_ULX {.ExtFamily=0x0, .Family=0x6, .ExtModel=0x4, .Model=0x6}
/* [Broadwell] 06_3Dh, 06_56h, 06_47h, 06_4Fh */
#define _Broadwell {.ExtFamily=0x0, .Family=0x6, .ExtModel=0x3, .Model=0xD}
#define _Broadwell_D {.ExtFamily=0x0, .Family=0x6, .ExtModel=0x5, .Model=0x6}
#define _Broadwell_H {.ExtFamily=0x0, .Family=0x6, .ExtModel=0x4, .Model=0x7}
#define _Broadwell_EP {.ExtFamily=0x0, .Family=0x6, .ExtModel=0x4, .Model=0xF}
/* [Skylake] 06_4Eh, 06_5Eh, 06_55h */
#define _Skylake_UY {.ExtFamily=0x0, .Family=0x6, .ExtModel=0x4, .Model=0xE}
#define _Skylake_S {.ExtFamily=0x0, .Family=0x6, .ExtModel=0x5, .Model=0xE}
/* [Skylake/X] 06_55h Stepping 4
[Cascade Lake] 06_55h Stepping 7
[Cooper Lake] 06_55h Stepping 10, 11 */
#define _Skylake_X {.ExtFamily=0x0, .Family=0x6, .ExtModel=0x5, .Model=0x5}
/* [Xeon Phi] 06_57h, 06_85h */
#define _Xeon_Phi {.ExtFamily=0x0, .Family=0x6, .ExtModel=0x5, .Model=0x7}
/* [Kaby Lake] 06_9Eh Stepping 9
[Coffee Lake] 06_9Eh Stepping 10 and 11 */
#define _Kabylake {.ExtFamily=0x0, .Family=0x6, .ExtModel=0x9, .Model=0xE}
/* [Kaby Lake/UY] 06_8Eh Stepping 9
[Whiskey Lake/U] 06_8Eh Stepping 11
[Amber Lake/Y] 06_8Eh Stepping 9
[Comet Lake/U] 06_8Eh Stepping 12 */
#define _Kabylake_UY {.ExtFamily=0x0, .Family=0x6, .ExtModel=0x8, .Model=0xE}
/* [Cannon Lake] 06_66h */
#define _Cannonlake {.ExtFamily=0x0, .Family=0x6, .ExtModel=0x6, .Model=0x6}
/* [Gemini Lake] 06_7Ah */
#define _Geminilake {.ExtFamily=0x0, .Family=0x6, .ExtModel=0x7, .Model=0xA}
/* [Ice Lake] 06_7Dh
[Ice Lake/UY] 06_7Eh
[Ice Lake/X] 06_6Ah Stepping 5
[Ice Lake/D] 06_6Ch */
#define _Icelake {.ExtFamily=0x0, .Family=0x6, .ExtModel=0x7, .Model=0xD}
#define _Icelake_UY {.ExtFamily=0x0, .Family=0x6, .ExtModel=0x7, .Model=0xE}
#define _Icelake_X {.ExtFamily=0x0, .Family=0x6, .ExtModel=0x6, .Model=0xA}
#define _Icelake_D {.ExtFamily=0x0, .Family=0x6, .ExtModel=0x6, .Model=0xC}
/* [Sunny Cove] 06_9Dh */
#define _Sunny_Cove {.ExtFamily=0x0, .Family=0x6, .ExtModel=0x9, .Model=0xD}
/* [Tiger Lake] 06_8D
[Tiger Lake/U] 06_8C */
#define _Tigerlake {.ExtFamily=0x0, .Family=0x6, .ExtModel=0x8, .Model=0xD}
#define _Tigerlake_U {.ExtFamily=0x0, .Family=0x6, .ExtModel=0x8, .Model=0xC}
/* [Comet Lake] 06_A5
[Comet Lake/UL] 06_A6
[Rocket Lake] 06_A7
[Rocket Lake/U] 06_A8 */
#define _Cometlake {.ExtFamily=0x0, .Family=0x6, .ExtModel=0xA, .Model=0x5}
#define _Cometlake_UY {.ExtFamily=0x0, .Family=0x6, .ExtModel=0xA, .Model=0x6}
#define _Rocketlake {.ExtFamily=0x0, .Family=0x6, .ExtModel=0xA, .Model=0x7}
#define _Rocketlake_U {.ExtFamily=0x0, .Family=0x6, .ExtModel=0xA, .Model=0x8}
/* [AlderLake/S] 06_97h
[AlderLake/P] 06_9Ah */
#define _AlderLake_S {.ExtFamily=0x0, .Family=0x6, .ExtModel=0x9, .Model=0x7}
#define _AlderLake_P {.ExtFamily=0x0, .Family=0x6, .ExtModel=0x9, .Model=0xA}
/* [Family 0Fh] 0F_00h */
#define _AMD_Family_0Fh {.ExtFamily=0x0, .Family=0xF, .ExtModel=0x0, .Model=0x0}
/* [Family 10h] 1F_00h */
#define _AMD_Family_10h {.ExtFamily=0x1, .Family=0xF, .ExtModel=0x0, .Model=0x0}
/* [Family 11h] 2F_00h */
#define _AMD_Family_11h {.ExtFamily=0x2, .Family=0xF, .ExtModel=0x0, .Model=0x0}
/* [Family 12h] 3F_00h */
#define _AMD_Family_12h {.ExtFamily=0x3, .Family=0xF, .ExtModel=0x0, .Model=0x0}
/* [Family 14h] 5F_00h */
#define _AMD_Family_14h {.ExtFamily=0x5, .Family=0xF, .ExtModel=0x0, .Model=0x0}
/* [Family 15h] 6F_00h */
#define _AMD_Family_15h {.ExtFamily=0x6, .Family=0xF, .ExtModel=0x0, .Model=0x0}
/* [Family 16h] 7F_00h */
#define _AMD_Family_16h {.ExtFamily=0x7, .Family=0xF, .ExtModel=0x0, .Model=0x0}
/* [Family 17h] 8F_00h
[Zen/Summit Ridge] 8F_01h Stepping 1 14 nm
[Zen/Whitehaven] 8F_01h Stepping 1 14 nm HEDT
[EPYC/Naples] 8F_01h Stepping 2 14 nm SVR
[Zen+ Pinnacle Ridge] 8F_08h Stepping 2 12 nm
[Zen+ Colfax] 8F_08h Stepping 2 12 nm HEDT
[Zen/Raven Ridge] 8F_11h Stepping 0 14 nm APU
[Zen/Snowy Owl] 8F_11h Stepping 0 14 nm SOC
[Zen+ Picasso] 8F_18h Stepping 1 12 nm APU
[Zen/Dali] 8F_20h Stepping 1 14 nm APU/Raven2
[EPYC/Rome] 8F_30h Stepping 0 7 nm SVR
[Zen2/Castle Peak] 8F_31h Stepping 0 7 nm HEDT
[Zen2/Renoir] 8F_60h Stepping 1 7 nm APU
[Zen2/Matisse] 8F_71h Stepping 0 7 nm
[Zen2/Xbox 8F_74h Stepping 0 7 nm */
#define _AMD_Zen {.ExtFamily=0x8, .Family=0xF, .ExtModel=0x0, .Model=0x1}
#define _AMD_Zen_APU {.ExtFamily=0x8, .Family=0xF, .ExtModel=0x1, .Model=0x1}
#define _AMD_ZenPlus {.ExtFamily=0x8, .Family=0xF, .ExtModel=0x0, .Model=0x8}
#define _AMD_ZenPlus_APU {.ExtFamily=0x8,.Family=0xF, .ExtModel=0x1, .Model=0x8}
#define _AMD_Zen_APU_Dali {.ExtFamily=0x8,.Family=0xF,.ExtModel=0x2, .Model=0x0}
#define _AMD_EPYC_Rome {.ExtFamily=0x8, .Family=0xF, .ExtModel=0x3, .Model=0x0}
#define _AMD_Zen2_CPK {.ExtFamily=0x8, .Family=0xF, .ExtModel=0x3, .Model=0x1}
#define _AMD_Zen2_APU {.ExtFamily=0x8, .Family=0xF, .ExtModel=0x6, .Model=0x0}
#define _AMD_Zen2_MTS {.ExtFamily=0x8, .Family=0xF, .ExtModel=0x7, .Model=0x1}
#define _AMD_Zen2_Xbox {.ExtFamily=0x8, .Family=0xF, .ExtModel=0x7, .Model=0x4}
#define _AMD_Family_17h {.ExtFamily=0x8, .Family=0xF, .ExtModel=0x0, .Model=0x0}
/* [Family 18h] 9F_00h */
#define _AMD_Family_18h {.ExtFamily=0x9, .Family=0xF, .ExtModel=0x0, .Model=0x0}
/* [Family 19h] AF_00h
[Zen3/Vermeer] AF_21h Stepping 0 7 nm
[Zen3/Cezanne] AF_51h Stepping 0 7 nm
[EPYC/Milan] AF_01h Stepping 0 7 nm */
#define _AMD_Family_19h {.ExtFamily=0xa, .Family=0xF, .ExtModel=0x0, .Model=0x0}
#define _AMD_Zen3_VMR {.ExtFamily=0xa, .Family=0xF, .ExtModel=0x2, .Model=0x1}
#define _AMD_Zen3_CZN {.ExtFamily=0xa, .Family=0xF, .ExtModel=0x5, .Model=0x1}
#define _AMD_EPYC_Milan {.ExtFamily=0xa, .Family=0xF, .ExtModel=0x0, .Model=0x1}
typedef kernel_ulong_t (*PCI_CALLBACK)(struct pci_dev *);
static PCI_CALLBACK P945(struct pci_dev *dev) ;
static PCI_CALLBACK P955(struct pci_dev *dev) ;
static PCI_CALLBACK P965(struct pci_dev *dev) ;
static PCI_CALLBACK G965(struct pci_dev *dev) ;
static PCI_CALLBACK P35(struct pci_dev *dev) ;
static PCI_CALLBACK SoC_SLM(struct pci_dev *dev) ;
static PCI_CALLBACK Bloomfield_IMC(struct pci_dev *dev) ;
static PCI_CALLBACK Lynnfield_IMC(struct pci_dev *dev) ;
static PCI_CALLBACK Westmere_EP_IMC(struct pci_dev *dev) ;
static PCI_CALLBACK NHM_IMC_TR(struct pci_dev *dev) ;
static PCI_CALLBACK NHM_NON_CORE(struct pci_dev *dev) ;
static PCI_CALLBACK X58_VTD(struct pci_dev *dev) ;
static PCI_CALLBACK X58_QPI(struct pci_dev *dev) ;
static PCI_CALLBACK SNB_IMC(struct pci_dev *dev) ;
static PCI_CALLBACK IVB_IMC(struct pci_dev *dev) ;
static PCI_CALLBACK SNB_EP_HB(struct pci_dev *dev) ;
static PCI_CALLBACK SNB_EP_QPI(struct pci_dev *dev) ;
static PCI_CALLBACK SNB_EP_CAP(struct pci_dev *dev) ;
static PCI_CALLBACK SNB_EP_CTRL0(struct pci_dev *dev) ;
static PCI_CALLBACK SNB_EP_CTRL1(struct pci_dev *dev) ;
static PCI_CALLBACK SNB_EP_IMC_CTRL0_CHA0(struct pci_dev *dev) ;
static PCI_CALLBACK SNB_EP_IMC_CTRL0_CHA1(struct pci_dev *dev) ;
static PCI_CALLBACK SNB_EP_IMC_CTRL0_CHA2(struct pci_dev *dev) ;
static PCI_CALLBACK SNB_EP_IMC_CTRL0_CHA3(struct pci_dev *dev) ;
static PCI_CALLBACK SNB_EP_IMC_CTRL1_CHA0(struct pci_dev *dev) ;
static PCI_CALLBACK SNB_EP_IMC_CTRL1_CHA1(struct pci_dev *dev) ;
static PCI_CALLBACK SNB_EP_IMC_CTRL1_CHA2(struct pci_dev *dev) ;
static PCI_CALLBACK SNB_EP_IMC_CTRL1_CHA3(struct pci_dev *dev) ;
static PCI_CALLBACK SNB_EP_TAD_CTRL0_CHA0(struct pci_dev *dev) ;
static PCI_CALLBACK SNB_EP_TAD_CTRL0_CHA1(struct pci_dev *dev) ;
static PCI_CALLBACK SNB_EP_TAD_CTRL0_CHA2(struct pci_dev *dev) ;
static PCI_CALLBACK SNB_EP_TAD_CTRL0_CHA3(struct pci_dev *dev) ;
static PCI_CALLBACK SNB_EP_TAD_CTRL1_CHA0(struct pci_dev *dev) ;
static PCI_CALLBACK SNB_EP_TAD_CTRL1_CHA1(struct pci_dev *dev) ;
static PCI_CALLBACK SNB_EP_TAD_CTRL1_CHA2(struct pci_dev *dev) ;
static PCI_CALLBACK SNB_EP_TAD_CTRL1_CHA3(struct pci_dev *dev) ;
static PCI_CALLBACK HSW_IMC(struct pci_dev *dev) ;
static PCI_CALLBACK SKL_IMC(struct pci_dev *dev) ;
/* TODO:
static PCI_CALLBACK SKL_SA(struct pci_dev *dev) ;
*/
static PCI_CALLBACK CML_PCH(struct pci_dev *dev) ;
#define RKL_PCH CML_PCH
static PCI_CALLBACK RKL_IMC(struct pci_dev *dev) ;
static PCI_CALLBACK TGL_IMC(struct pci_dev *dev) ;
static PCI_CALLBACK AMD_0Fh_MCH(struct pci_dev *dev) ;
static PCI_CALLBACK AMD_0Fh_HTT(struct pci_dev *dev) ;
#ifdef CONFIG_AMD_NB
static PCI_CALLBACK AMD_17h_ZenIF(struct pci_dev *dev) ;
#define AMD_19h_ZenIF AMD_17h_ZenIF
#endif
static PCI_CALLBACK AMD_Zen_IOMMU(struct pci_dev *dev) ;
static PCI_CALLBACK AMD_17h_UMC(struct pci_dev *dev) ;
#define AMD_19h_UMC AMD_17h_UMC
static struct pci_device_id PCI_Void_ids[] = {
{0, }
};
static struct pci_device_id PCI_Core2_ids[] = {
{ /* 82945G - Lakeport */
PCI_VDEVICE(INTEL, DID_INTEL_82945P_HB),
.driver_data = (kernel_ulong_t) P945
},
{ /* 82945GM - Calistoga */
PCI_VDEVICE(INTEL, DID_INTEL_82945GM_HB),
.driver_data = (kernel_ulong_t) P945
},
{ /* 82945GME/SE - Calistoga */
PCI_VDEVICE(INTEL, DID_INTEL_82945GME_HB),
.driver_data = (kernel_ulong_t) P945
},
{ /* 82955X - Lakeport-X */
PCI_VDEVICE(INTEL, DID_INTEL_82955_HB),
.driver_data = (kernel_ulong_t) P955
},
{ /* 946PL/946GZ - Lakeport-PL/GZ */
PCI_VDEVICE(INTEL, DID_INTEL_82946GZ_HB),
.driver_data = (kernel_ulong_t) P965
},
{ /* Q963/Q965 - Broadwater */
PCI_VDEVICE(INTEL, DID_INTEL_82965Q_HB),
.driver_data = (kernel_ulong_t) P965
},
{ /* P965/G965 - Broadwater */
PCI_VDEVICE(INTEL, DID_INTEL_82965G_HB),
.driver_data = (kernel_ulong_t) P965
},
{ /* GM965 - Crestline */
PCI_VDEVICE(INTEL, DID_INTEL_82965GM_HB),
.driver_data = (kernel_ulong_t) G965
},
{ /* GME965 - Crestline */
PCI_VDEVICE(INTEL, DID_INTEL_82965GME_HB),
.driver_data = (kernel_ulong_t) G965
},
{ /* GM45 - Cantiga */
PCI_VDEVICE(INTEL, DID_INTEL_GM45_HB),
.driver_data = (kernel_ulong_t) G965
},
{ /* Q35 - Bearlake-Q */
PCI_VDEVICE(INTEL, DID_INTEL_Q35_HB),
.driver_data = (kernel_ulong_t) P35
},
{ /* P35/G33 - Bearlake-PG+ */
PCI_VDEVICE(INTEL, DID_INTEL_G33_HB),
.driver_data = (kernel_ulong_t) P35
},
{ /* Q33 - Bearlake-QF */
PCI_VDEVICE(INTEL, DID_INTEL_Q33_HB),
.driver_data = (kernel_ulong_t) P35
},
{ /* X38/X48 - Bearlake-X */
PCI_VDEVICE(INTEL, DID_INTEL_X38_HB),
.driver_data = (kernel_ulong_t) P35
},
{ /* 3200/3210 - Intel 3200 */
PCI_VDEVICE(INTEL, DID_INTEL_3200_HB),
.driver_data = (kernel_ulong_t) P35
},
{ /* Q45/Q43 - Eaglelake-Q */
PCI_VDEVICE(INTEL, DID_INTEL_Q45_HB),
.driver_data = (kernel_ulong_t) P35
},
{ /* P45/G45 - Eaglelake-P */
PCI_VDEVICE(INTEL, DID_INTEL_G45_HB),
.driver_data = (kernel_ulong_t) P35
},
{ /* G41 - Eaglelake-G */
PCI_VDEVICE(INTEL, DID_INTEL_G41_HB),
.driver_data = (kernel_ulong_t) P35
},
{0, }
};
static struct pci_device_id PCI_SoC_ids[] = {
{ /* 82945G - Lakeport */
PCI_VDEVICE(INTEL, DID_INTEL_SLM_PTR),
.driver_data = (kernel_ulong_t) SoC_SLM
},
{0, }
};
/* 1st Generation */
static struct pci_device_id PCI_Nehalem_QPI_ids[] = {
{ /* Bloomfield IMC */
PCI_VDEVICE(INTEL, DID_INTEL_I7_MCR),
.driver_data = (kernel_ulong_t) Bloomfield_IMC
},
{ /* Bloomfield IMC Test Registers */
PCI_VDEVICE(INTEL, DID_INTEL_I7_MC_TEST),
.driver_data = (kernel_ulong_t) NHM_IMC_TR
},
{ /* Nehalem Control Status and RAS Registers */
PCI_VDEVICE(INTEL, DID_INTEL_X58_HUB_CTRL),
.driver_data = (kernel_ulong_t) X58_QPI
},
{
PCI_VDEVICE(INTEL, DID_INTEL_X58_HUB_CORE),
.driver_data = (kernel_ulong_t) X58_VTD
},
{ /* Nehalem Bloomfield/Xeon C3500: Non-Core Registers */
PCI_VDEVICE(INTEL, DID_INTEL_BLOOMFIELD_NON_CORE),
.driver_data = (kernel_ulong_t) NHM_NON_CORE
},
{ /* Nehalem EP Xeon C5500: Non-Core Registers */
PCI_VDEVICE(INTEL, DID_INTEL_C5500_NON_CORE),
.driver_data = (kernel_ulong_t) NHM_NON_CORE
},
{0, }
};
static struct pci_device_id PCI_Nehalem_DMI_ids[] = {
{ /* Lynnfield IMC */
PCI_VDEVICE(INTEL, DID_INTEL_LYNNFIELD_MCR),
.driver_data = (kernel_ulong_t) Lynnfield_IMC
},
{ /* Lynnfield IMC Test Registers */
PCI_VDEVICE(INTEL, DID_INTEL_LYNNFIELD_MC_TEST),
.driver_data = (kernel_ulong_t) NHM_IMC_TR
},
{ /* Lynnfield QuickPath Architecture Generic Non-core Registers */
PCI_VDEVICE(INTEL, DID_INTEL_LYNNFIELD_NON_CORE),
.driver_data = (kernel_ulong_t) NHM_NON_CORE
},
{ /* Clarksfield Processor Uncore Device 0, Function 0 */
PCI_VDEVICE(INTEL, DID_INTEL_CLARKSFIELD_NON_CORE),
.driver_data = (kernel_ulong_t) NHM_NON_CORE
},
{ /* Westmere/Clarkdale QuickPath Architecture Non-core Registers */
PCI_VDEVICE(INTEL, DID_INTEL_CLARKDALE_NON_CORE),
.driver_data = (kernel_ulong_t) NHM_NON_CORE
},
{ /* Jasper Forest IMC */
PCI_VDEVICE(INTEL, 0x2cd8),
.driver_data = (kernel_ulong_t) Lynnfield_IMC
},
{0, }
};
static struct pci_device_id PCI_Westmere_EP_ids[] = {
{ /* Westmere EP IMC */
PCI_VDEVICE(INTEL, DID_INTEL_NHM_EP_MCR),
.driver_data = (kernel_ulong_t) Westmere_EP_IMC
},
{ /* Westmere EP IMC Test Registers */
PCI_VDEVICE(INTEL, DID_INTEL_NHM_EP_MC_TEST),
.driver_data = (kernel_ulong_t) NHM_IMC_TR
},
{ /* Nehalem Control Status and RAS Registers */
PCI_VDEVICE(INTEL, DID_INTEL_X58_HUB_CTRL),
.driver_data = (kernel_ulong_t) X58_QPI
},
{
PCI_VDEVICE(INTEL, DID_INTEL_X58_HUB_CORE),
.driver_data = (kernel_ulong_t) X58_VTD
},
{ /* Westmere EP: Non-Core Registers */
PCI_VDEVICE(INTEL, DID_INTEL_NHM_EP_NON_CORE),
.driver_data = (kernel_ulong_t) NHM_NON_CORE
},
{0, }
};
/* 2nd Generation
Sandy Bridge ix-2xxx, Xeon E3-E5: IMC_HA=0x3ca0 / IMC_TA=0x3ca8
TA0=0x3caa, TA1=0x3cab / TA2=0x3cac / TA3=0x3cad / TA4=0x3cae */
static struct pci_device_id PCI_SandyBridge_ids[] = {
{
PCI_VDEVICE(INTEL, DID_INTEL_SNB_IMC_HA0),
.driver_data = (kernel_ulong_t) SNB_IMC
},
{ /* Desktop: IMC_SystemAgent=0x0100,0x0104 */
PCI_VDEVICE(INTEL, DID_INTEL_SNB_IMC_SA),
.driver_data = (kernel_ulong_t) SNB_IMC
},
{
PCI_VDEVICE(INTEL, DID_INTEL_SNB_IMC_0104),
.driver_data = (kernel_ulong_t) SNB_IMC
},
{0, }
};
/* 3rd Generation
Ivy Bridge ix-3xxx, Xeon E7/E5 v2: IMC_HA=0x0ea0 / IMC_TA=0x0ea8
TA0=0x0eaa / TA1=0x0eab / TA2=0x0eac / TA3=0x0ead */
static struct pci_device_id PCI_IvyBridge_ids[] = {
{ /* Desktop: IMC_SystemAgent=0x0150 */
PCI_VDEVICE(INTEL, DID_INTEL_IVB_IMC_SA),
.driver_data = (kernel_ulong_t) IVB_IMC
},
{ /* Mobile i5-3337U: IMC=0x0154 */
PCI_VDEVICE(INTEL, DID_INTEL_IVB_IMC_0154),
.driver_data = (kernel_ulong_t) IVB_IMC
},
{0, }
};
static struct pci_device_id PCI_SandyBridge_EP_ids[] = {
{
PCI_VDEVICE(INTEL, DID_INTEL_IVB_EP_HOST_BRIDGE),
.driver_data = (kernel_ulong_t) SNB_EP_HB
},
{
/* QPIMISCSTAT */
PCI_VDEVICE(INTEL, DID_INTEL_IVB_EP_QPI_LINK0),
.driver_data = (kernel_ulong_t) SNB_EP_QPI
},
{
/* Power Control Unit */
PCI_VDEVICE(INTEL, DID_INTEL_IVB_EP_CAPABILITY),
.driver_data = (kernel_ulong_t) SNB_EP_CAP
},
{
/* Integrated Memory Controller # : General and MemHot Registers */
PCI_VDEVICE(INTEL, DID_INTEL_IVB_EP_IMC_CTRL0_CPGC),
.driver_data = (kernel_ulong_t) SNB_EP_CTRL0
},
{
PCI_VDEVICE(INTEL, DID_INTEL_IVB_EP_IMC_CTRL1_CPGC),
.driver_data = (kernel_ulong_t) SNB_EP_CTRL1
},
{
/* Integrated Memory Controller # : Channel [m-M] Thermal Registers*/
PCI_VDEVICE(INTEL, DID_INTEL_IVB_EP_IMC_CTRL0_CH0),
.driver_data = (kernel_ulong_t) SNB_EP_IMC_CTRL0_CHA0
},
{
PCI_VDEVICE(INTEL, DID_INTEL_IVB_EP_IMC_CTRL0_CH1),
.driver_data = (kernel_ulong_t) SNB_EP_IMC_CTRL0_CHA1
},
{
PCI_VDEVICE(INTEL, DID_INTEL_IVB_EP_IMC_CTRL0_CH2),
.driver_data = (kernel_ulong_t) SNB_EP_IMC_CTRL0_CHA2
},
{
PCI_VDEVICE(INTEL, DID_INTEL_IVB_EP_IMC_CTRL0_CH3),
.driver_data = (kernel_ulong_t) SNB_EP_IMC_CTRL0_CHA3
},
{
PCI_VDEVICE(INTEL, DID_INTEL_IVB_EP_IMC_CTRL1_CH0),
.driver_data = (kernel_ulong_t) SNB_EP_IMC_CTRL1_CHA0
},
{
PCI_VDEVICE(INTEL ,DID_INTEL_IVB_EP_IMC_CTRL1_CH1),
.driver_data = (kernel_ulong_t) SNB_EP_IMC_CTRL1_CHA1
},
{
PCI_VDEVICE(INTEL, DID_INTEL_IVB_EP_IMC_CTRL1_CH2),
.driver_data = (kernel_ulong_t) SNB_EP_IMC_CTRL1_CHA2
},
{
PCI_VDEVICE(INTEL, DID_INTEL_IVB_EP_IMC_CTRL1_CH3),
.driver_data = (kernel_ulong_t) SNB_EP_IMC_CTRL1_CHA3
},
/* Integrated Memory Controller 0 : Channel # TAD Registers */
{
PCI_VDEVICE(INTEL, DID_INTEL_IVB_EP_TAD_CTRL0_CH0),
.driver_data = (kernel_ulong_t) SNB_EP_TAD_CTRL0_CHA0
},
{
PCI_VDEVICE(INTEL, DID_INTEL_IVB_EP_TAD_CTRL0_CH1),
.driver_data = (kernel_ulong_t) SNB_EP_TAD_CTRL0_CHA1
},
{
PCI_VDEVICE(INTEL, DID_INTEL_IVB_EP_TAD_CTRL0_CH2),
.driver_data = (kernel_ulong_t) SNB_EP_TAD_CTRL0_CHA2
},
{
PCI_VDEVICE(INTEL, DID_INTEL_IVB_EP_TAD_CTRL0_CH3),
.driver_data = (kernel_ulong_t) SNB_EP_TAD_CTRL0_CHA3
},
{
/* Integrated Memory Controller 1 : Channel # TAD Registers */
PCI_VDEVICE(INTEL, DID_INTEL_IVB_EP_TAD_CTRL1_CH0),
.driver_data = (kernel_ulong_t) SNB_EP_TAD_CTRL1_CHA0
},
{
PCI_VDEVICE(INTEL, DID_INTEL_IVB_EP_TAD_CTRL1_CH1),
.driver_data = (kernel_ulong_t) SNB_EP_TAD_CTRL1_CHA1
},
{
PCI_VDEVICE(INTEL, DID_INTEL_IVB_EP_TAD_CTRL1_CH2),
.driver_data = (kernel_ulong_t) SNB_EP_TAD_CTRL1_CHA2
},
{
PCI_VDEVICE(INTEL, DID_INTEL_IVB_EP_TAD_CTRL1_CH3),
.driver_data = (kernel_ulong_t) SNB_EP_TAD_CTRL1_CHA3
},
{0, }
};
/* 4th Generation
Haswell ix-4xxx, Xeon E7/E5 v3: IMC_HA0=0x2fa0 / IMC_HA0_TA=0x2fa8
TAD0=0x2faa / TAD1=0x2fab / TAD2=0x2fac / TAD3=0x2fad */
static struct pci_device_id PCI_Haswell_ids[] = {
{
PCI_VDEVICE(INTEL, DID_INTEL_HASWELL_IMC_HA0),
.driver_data = (kernel_ulong_t) HSW_IMC
},
{ /* Desktop: IMC_SystemAgent=0x0c00 */
PCI_VDEVICE(INTEL, DID_INTEL_HASWELL_IMC_SA),
.driver_data = (kernel_ulong_t) HSW_IMC
},
{ /* Mobile M/H: Host Agent=0x0c04 */
PCI_VDEVICE(INTEL, DID_INTEL_HASWELL_MH_IMC_HA0),
.driver_data = (kernel_ulong_t) HSW_IMC
},
{ /* Mobile U/Y: Host Agent=0x0a04 */
PCI_VDEVICE(INTEL, DID_INTEL_HASWELL_UY_IMC_HA0),
.driver_data = (kernel_ulong_t) HSW_IMC
},
{0, }
};
/* 5th Generation
Broadwell ix-5xxx: IMC_HA0=0x1604 / 0x1614 */
static struct pci_device_id PCI_Broadwell_ids[] = {
{
PCI_VDEVICE(INTEL, DID_INTEL_BROADWELL_IMC_HA0),
.driver_data = (kernel_ulong_t) HSW_IMC
},
{
PCI_VDEVICE(INTEL, DID_INTEL_BROADWELL_D_IMC_HA0),
.driver_data = (kernel_ulong_t) HSW_IMC
},
{
PCI_VDEVICE(INTEL, DID_INTEL_BROADWELL_H_IMC_HA0),
.driver_data = (kernel_ulong_t) HSW_IMC
},
{ /* Desktop: IMC_SystemAgent=0x0c00 */
PCI_VDEVICE(INTEL, DID_INTEL_HASWELL_IMC_SA),
.driver_data = (kernel_ulong_t) HSW_IMC
},
{0, }
};
/* 6th Generation */
static struct pci_device_id PCI_Skylake_ids[] = {
{
PCI_VDEVICE(INTEL, DID_INTEL_SKYLAKE_U_IMC_HA),
.driver_data = (kernel_ulong_t) SKL_IMC
},
{
PCI_VDEVICE(INTEL, DID_INTEL_SKYLAKE_Y_IMC_HA),
.driver_data = (kernel_ulong_t) SKL_IMC
},
{
PCI_VDEVICE(INTEL, DID_INTEL_SKYLAKE_S_IMC_HAD),
.driver_data = (kernel_ulong_t) SKL_IMC
},
{
PCI_VDEVICE(INTEL, DID_INTEL_SKYLAKE_S_IMC_HAQ),
.driver_data = (kernel_ulong_t) SKL_IMC
},
{
PCI_VDEVICE(INTEL, DID_INTEL_SKYLAKE_H_IMC_HAD),
.driver_data = (kernel_ulong_t) SKL_IMC
},
{
PCI_VDEVICE(INTEL, DID_INTEL_SKYLAKE_H_IMC_HAQ),
.driver_data = (kernel_ulong_t) SKL_IMC
},
{
PCI_VDEVICE(INTEL, DID_INTEL_SKYLAKE_DT_IMC_HA),
.driver_data = (kernel_ulong_t) SKL_IMC
},
{0, }
};
static struct pci_device_id PCI_Skylake_X_ids[] = {
{0, }
};
/* 7th & 8th up to 11th Generation: Chipsets might cross generations */
static struct pci_device_id PCI_Kabylake_ids[] = {
{
PCI_VDEVICE(INTEL, DID_INTEL_KABYLAKE_H_IMC_HAD),
.driver_data = (kernel_ulong_t) SKL_IMC
},
{
PCI_VDEVICE(INTEL, DID_INTEL_KABYLAKE_U_IMC_HA),
.driver_data = (kernel_ulong_t) SKL_IMC
},
{
PCI_VDEVICE(INTEL, DID_INTEL_KABYLAKE_Y_IMC_HA),
.driver_data = (kernel_ulong_t) SKL_IMC
},
{
PCI_VDEVICE(INTEL, DID_INTEL_KABYLAKE_Y_IMC_HQ),
.driver_data = (kernel_ulong_t) SKL_IMC
},
{
PCI_VDEVICE(INTEL, DID_INTEL_KABYLAKE_S_IMC_HAD),
.driver_data = (kernel_ulong_t) SKL_IMC
},
{
PCI_VDEVICE(INTEL, DID_INTEL_KABYLAKE_H_IMC_HAQ),
.driver_data = (kernel_ulong_t) SKL_IMC
},
{
PCI_VDEVICE(INTEL, DID_INTEL_KABYLAKE_DT_IMC_HA),
.driver_data = (kernel_ulong_t) SKL_IMC
},
{
PCI_VDEVICE(INTEL, DID_INTEL_KABYLAKE_U_IMC_HAQ),
.driver_data = (kernel_ulong_t) SKL_IMC
},
{
PCI_VDEVICE(INTEL, DID_INTEL_KABYLAKE_S_IMC_HAQ),
.driver_data = (kernel_ulong_t) SKL_IMC
},
{
PCI_VDEVICE(INTEL, DID_INTEL_KABYLAKE_X_IMC_HAQ),
.driver_data = (kernel_ulong_t) SKL_IMC
},
{
PCI_VDEVICE(INTEL, DID_INTEL_COFFEELAKE_S_IMC_HAQ),
.driver_data = (kernel_ulong_t) SKL_IMC
},
{
PCI_VDEVICE(INTEL, DID_INTEL_COFFEELAKE_S_IMC_HAS),
.driver_data = (kernel_ulong_t) SKL_IMC
},
{
PCI_VDEVICE(INTEL, DID_INTEL_COFFEELAKE_R_S_IMC_HAD),
.driver_data = (kernel_ulong_t) SKL_IMC
},
{
PCI_VDEVICE(INTEL, DID_INTEL_COFFEELAKE_R_U_IMC_HAD),
.driver_data = (kernel_ulong_t) SKL_IMC
},
{
PCI_VDEVICE(INTEL, DID_INTEL_COFFEELAKE_R_U_IMC_HAQ),
.driver_data = (kernel_ulong_t) SKL_IMC
},
{
PCI_VDEVICE(INTEL, DID_INTEL_COFFEELAKE_R_H_IMC_HAQ),
.driver_data = (kernel_ulong_t) SKL_IMC
},
{
PCI_VDEVICE(INTEL, DID_INTEL_COFFEELAKE_R_H_IMC_HAS),
.driver_data = (kernel_ulong_t) SKL_IMC
},
{
PCI_VDEVICE(INTEL, DID_INTEL_COFFEELAKE_R_H_IMC_HAO),
.driver_data = (kernel_ulong_t) SKL_IMC
},
{
PCI_VDEVICE(INTEL, DID_INTEL_COFFEELAKE_R_W_IMC_HAQ),
.driver_data = (kernel_ulong_t) SKL_IMC
},
{
PCI_VDEVICE(INTEL, DID_INTEL_COFFEELAKE_R_W_IMC_HAS),
.driver_data = (kernel_ulong_t) SKL_IMC
},
{
PCI_VDEVICE(INTEL, DID_INTEL_COFFEELAKE_R_W_IMC_HAO),
.driver_data = (kernel_ulong_t) SKL_IMC
},
{
PCI_VDEVICE(INTEL, DID_INTEL_COFFEELAKE_R_S_IMC_HAQ),
.driver_data = (kernel_ulong_t) SKL_IMC
},
{
PCI_VDEVICE(INTEL, DID_INTEL_COFFEELAKE_R_S_IMC_HAS),
.driver_data = (kernel_ulong_t) SKL_IMC
},
{
PCI_VDEVICE(INTEL, DID_INTEL_COFFEELAKE_R_S_IMC_HAO),
.driver_data = (kernel_ulong_t) SKL_IMC
},
{
PCI_VDEVICE(INTEL, DID_INTEL_WHISKEYLAKE_U_IMC_HAD),
.driver_data = (kernel_ulong_t) SKL_IMC
},
{
PCI_VDEVICE(INTEL, DID_INTEL_WHISKEYLAKE_U_IMC_HAQ),
.driver_data = (kernel_ulong_t) SKL_IMC
},
{
PCI_VDEVICE(INTEL, DID_INTEL_COMETLAKE_S_IMC_6C),
.driver_data = (kernel_ulong_t) SKL_IMC
},
{
PCI_VDEVICE(INTEL, DID_INTEL_COMETLAKE_S_IMC_10C),
.driver_data = (kernel_ulong_t) SKL_IMC
},
{
PCI_VDEVICE(INTEL, DID_INTEL_COMETLAKE_H_IMC_10C),
.driver_data = (kernel_ulong_t) SKL_IMC
},
{
PCI_VDEVICE(INTEL, DID_INTEL_COMETLAKE_W_IMC_10C),
.driver_data = (kernel_ulong_t) SKL_IMC
},
{
PCI_VDEVICE(INTEL, DID_INTEL_COMETLAKE_M_IMC_6C),
.driver_data = (kernel_ulong_t) SKL_IMC
},
{
PCI_VDEVICE(INTEL, DID_INTEL_COMETLAKE_U_IMC_HB),
.driver_data = (kernel_ulong_t) RKL_IMC
},
{
PCI_VDEVICE(INTEL, DID_INTEL_COMETLAKE_U1_IMC),
.driver_data = (kernel_ulong_t) RKL_IMC
},
{
PCI_VDEVICE(INTEL, DID_INTEL_COMETLAKE_U3_IMC),
.driver_data = (kernel_ulong_t) RKL_IMC
},
{
PCI_VDEVICE(INTEL, DID_INTEL_COMETLAKE_S1_IMC),
.driver_data = (kernel_ulong_t) SKL_IMC
},
{
PCI_VDEVICE(INTEL, DID_INTEL_COMETLAKE_S2_IMC),
.driver_data = (kernel_ulong_t) SKL_IMC
},
{
PCI_VDEVICE(INTEL, DID_INTEL_COMETLAKE_S5_IMC),
.driver_data = (kernel_ulong_t) SKL_IMC
},
{
PCI_VDEVICE(INTEL, DID_INTEL_COMETLAKE_PREM_U_PCH),
.driver_data = (kernel_ulong_t) CML_PCH
},
{
PCI_VDEVICE(INTEL, DID_INTEL_COMETLAKE_BASE_U_PCH),
.driver_data = (kernel_ulong_t) CML_PCH
},
{
PCI_VDEVICE(INTEL, DID_INTEL_COMETLAKE_U_ES_PCH),
.driver_data = (kernel_ulong_t) CML_PCH
},
{
PCI_VDEVICE(INTEL, DID_INTEL_COMETLAKE_Y_ES_PCH),
.driver_data = (kernel_ulong_t) CML_PCH
},
{
PCI_VDEVICE(INTEL, DID_INTEL_COMETLAKE_Y_PCH),
.driver_data = (kernel_ulong_t) CML_PCH
},
{
PCI_VDEVICE(INTEL, DID_INTEL_COMETLAKE_H470_PCH),
.driver_data = (kernel_ulong_t) CML_PCH
},
{
PCI_VDEVICE(INTEL, DID_INTEL_COMETLAKE_Z490_PCH),
.driver_data = (kernel_ulong_t) CML_PCH
},
{
PCI_VDEVICE(INTEL, DID_INTEL_COMETLAKE_Q470_PCH),
.driver_data = (kernel_ulong_t) CML_PCH
},
{
PCI_VDEVICE(INTEL, DID_INTEL_COMETLAKE_HM470_PCH),
.driver_data = (kernel_ulong_t) CML_PCH
},
{
PCI_VDEVICE(INTEL, DID_INTEL_COMETLAKE_QM480_PCH),
.driver_data = (kernel_ulong_t) CML_PCH
},
{
PCI_VDEVICE(INTEL, DID_INTEL_COMETLAKE_WM490_PCH),
.driver_data = (kernel_ulong_t) CML_PCH
},
{
PCI_VDEVICE(INTEL, DID_INTEL_COMETLAKE_W480_PCH),
.driver_data = (kernel_ulong_t) CML_PCH
},
{
PCI_VDEVICE(INTEL, DID_INTEL_ICELAKE_U_PCH),
.driver_data = (kernel_ulong_t) CML_PCH
},
{
PCI_VDEVICE(INTEL, DID_INTEL_ICELAKE_U_IMC),
.driver_data = (kernel_ulong_t) SKL_IMC
},
{
PCI_VDEVICE(INTEL, DID_INTEL_ICELAKE_U_4C),
.driver_data = (kernel_ulong_t) SKL_IMC
},
{
PCI_VDEVICE(INTEL, DID_INTEL_TIGERLAKE_U1_IMC),
.driver_data = (kernel_ulong_t) TGL_IMC
},
{
PCI_VDEVICE(INTEL, DID_INTEL_TIGERLAKE_U2_IMC),
.driver_data = (kernel_ulong_t) TGL_IMC
},
{
PCI_VDEVICE(INTEL, DID_INTEL_TIGERLAKE_U3_IMC),
.driver_data = (kernel_ulong_t) TGL_IMC
},
{
PCI_VDEVICE(INTEL, DID_INTEL_TIGERLAKE_U4_IMC),
.driver_data = (kernel_ulong_t) TGL_IMC
},
{
PCI_VDEVICE(INTEL, DID_INTEL_TIGERLAKE_H_IMC),
.driver_data = (kernel_ulong_t) TGL_IMC
},
{
PCI_VDEVICE(INTEL, DID_INTEL_ROCKETLAKE_S_8C_IMC_HB),
.driver_data = (kernel_ulong_t) RKL_IMC
},
{
PCI_VDEVICE(INTEL, DID_INTEL_ROCKETLAKE_S_6C_IMC_HB),
.driver_data = (kernel_ulong_t) RKL_IMC
},
{
PCI_VDEVICE(INTEL, DID_INTEL_ROCKETLAKE_H510_PCH),
.driver_data = (kernel_ulong_t) RKL_PCH
},
{
PCI_VDEVICE(INTEL, DID_INTEL_ROCKETLAKE_B560_PCH),
.driver_data = (kernel_ulong_t) RKL_PCH
},
{
PCI_VDEVICE(INTEL, DID_INTEL_ROCKETLAKE_H570_PCH),
.driver_data = (kernel_ulong_t) RKL_PCH
},
{
PCI_VDEVICE(INTEL, DID_INTEL_ROCKETLAKE_Q570_PCH),
.driver_data = (kernel_ulong_t) RKL_PCH
},
{
PCI_VDEVICE(INTEL, DID_INTEL_ROCKETLAKE_Z590_PCH),
.driver_data = (kernel_ulong_t) RKL_PCH
},
{
PCI_VDEVICE(INTEL, DID_INTEL_ROCKETLAKE_W580_PCH),
.driver_data = (kernel_ulong_t) RKL_PCH
},
{
PCI_VDEVICE(INTEL, DID_INTEL_ALDERLAKE_1_IMC),
.driver_data = (kernel_ulong_t) RKL_IMC
},
{
PCI_VDEVICE(INTEL, DID_INTEL_ALDERLAKE_2_IMC),
.driver_data = (kernel_ulong_t) RKL_IMC
},
{0, }
};
/* AMD Family 0Fh */
static struct pci_device_id PCI_AMD_0Fh_ids[] = {
{
PCI_DEVICE(PCI_VENDOR_ID_AMD, DID_AMD_K8_NB_MEMCTL),
.driver_data = (kernel_ulong_t) AMD_0Fh_MCH
},
{
PCI_DEVICE(PCI_VENDOR_ID_AMD, DID_AMD_K8_NB),
.driver_data = (kernel_ulong_t) AMD_0Fh_HTT
},
{0, }
};
/* AMD Family 17h */
static struct pci_device_id PCI_AMD_17h_ids[] = {
#ifdef CONFIG_AMD_NB
/* Source: /drivers/hwmon/k10temp.c */
{
PCI_VDEVICE(AMD, DID_AMD_17H_ZEPPELIN_DF_F3),
.driver_data = (kernel_ulong_t) AMD_17h_ZenIF
},
{
PCI_VDEVICE(AMD, DID_AMD_17H_RAVEN_DF_F3),
.driver_data = (kernel_ulong_t) AMD_17h_ZenIF
},
{
PCI_VDEVICE(AMD, DID_AMD_17H_MATISSE_DF_F3),
.driver_data = (kernel_ulong_t) AMD_17h_ZenIF
},
{
PCI_VDEVICE(AMD, DID_AMD_17H_STARSHIP_DF_F3),
.driver_data = (kernel_ulong_t) AMD_17h_ZenIF
},
{
PCI_VDEVICE(AMD, DID_AMD_17H_RENOIR_DF_F3),
.driver_data = (kernel_ulong_t) AMD_17h_ZenIF
},
{
PCI_VDEVICE(AMD, DID_AMD_17H_ARIEL_DF_F3),
.driver_data = (kernel_ulong_t) AMD_17h_ZenIF
},
{
PCI_VDEVICE(AMD, DID_AMD_17H_FIREFLIGHT_DF_F3),
.driver_data = (kernel_ulong_t) AMD_17h_ZenIF
},
{
PCI_VDEVICE(AMD, DID_AMD_17H_ARDEN_DF_F3),
.driver_data = (kernel_ulong_t) AMD_17h_ZenIF
},
/* Source: HYGON: /arch/x86/kernel/amd_nb.c: DF_F3 = 0x1463 */
{
PCI_VDEVICE(HYGON, DID_AMD_17H_ZEPPELIN_DF_F3),
.driver_data = (kernel_ulong_t) AMD_17h_ZenIF
},
/* AMD Family 19h */
{
PCI_VDEVICE(AMD, DID_AMD_19H_VERMEER_DF_F3),
.driver_data = (kernel_ulong_t) AMD_19h_ZenIF
},
#endif /* CONFIG_AMD_NB */
{
PCI_VDEVICE(AMD, DID_AMD_17H_ZEN_PLUS_NB_IOMMU),
.driver_data = (kernel_ulong_t) AMD_Zen_IOMMU
},
{
PCI_VDEVICE(AMD, DID_AMD_17H_ZEPPELIN_NB_IOMMU),
.driver_data = (kernel_ulong_t) AMD_Zen_IOMMU
},
{
PCI_VDEVICE(AMD, DID_AMD_17H_RAVEN_NB_IOMMU),
.driver_data = (kernel_ulong_t) AMD_Zen_IOMMU
},
/* AMD Families 17h and 19h: IOMMU at 0x1481 */
{
PCI_VDEVICE(AMD, DID_AMD_17H_ZEN2_MTS_NB_IOMMU),
.driver_data = (kernel_ulong_t) AMD_Zen_IOMMU
},
{
PCI_VDEVICE(AMD, DID_AMD_17H_STARSHIP_NB_IOMMU),
.driver_data = (kernel_ulong_t) AMD_Zen_IOMMU
},
{
PCI_VDEVICE(AMD, DID_AMD_17H_RENOIR_NB_IOMMU),
.driver_data = (kernel_ulong_t) AMD_Zen_IOMMU
},
{
PCI_VDEVICE(AMD, DID_AMD_17H_ZEN_APU_NB_IOMMU),
.driver_data = (kernel_ulong_t) AMD_Zen_IOMMU
},
{
PCI_VDEVICE(AMD, DID_AMD_17H_ZEN2_APU_NB_IOMMU),
.driver_data = (kernel_ulong_t) AMD_Zen_IOMMU
},
{
PCI_VDEVICE(AMD, DID_AMD_17H_FIREFLIGHT_NB_IOMMU),
.driver_data = (kernel_ulong_t) AMD_Zen_IOMMU
},
{
PCI_VDEVICE(AMD, DID_AMD_17H_ARDEN_NB_IOMMU),
.driver_data = (kernel_ulong_t) AMD_Zen_IOMMU
},
/* Source: HYGON: PCI list */
{
PCI_VDEVICE(HYGON, DID_AMD_17H_ZEN_PLUS_NB_IOMMU),
.driver_data = (kernel_ulong_t) AMD_Zen_IOMMU
},
/* Source: SMU > Data Fabric > UMC */
{
PCI_VDEVICE(AMD, DID_AMD_17H_ZEPPELIN_DF_F3),
.driver_data = (kernel_ulong_t) AMD_17h_UMC
},
{
PCI_VDEVICE(AMD, DID_AMD_17H_RAVEN_DF_F3),
.driver_data = (kernel_ulong_t) AMD_17h_UMC
},
{
PCI_VDEVICE(AMD, DID_AMD_17H_MATISSE_DF_F3),
.driver_data = (kernel_ulong_t) AMD_17h_UMC
},
{
PCI_VDEVICE(AMD, DID_AMD_17H_STARSHIP_DF_F3),
.driver_data = (kernel_ulong_t) AMD_17h_UMC
},
{
PCI_VDEVICE(AMD, DID_AMD_17H_RENOIR_DF_F3),
.driver_data = (kernel_ulong_t) AMD_17h_UMC
},
{
PCI_VDEVICE(AMD, DID_AMD_17H_ARIEL_DF_F3),
.driver_data = (kernel_ulong_t) AMD_17h_UMC
},
{
PCI_VDEVICE(AMD, DID_AMD_17H_RAVEN2_DF_F3),
.driver_data = (kernel_ulong_t) AMD_17h_UMC
},
{
PCI_VDEVICE(AMD, DID_AMD_17H_FIREFLIGHT_DF_F3),
.driver_data = (kernel_ulong_t) AMD_17h_UMC
},
{
PCI_VDEVICE(AMD, DID_AMD_17H_ARDEN_DF_F3),
.driver_data = (kernel_ulong_t) AMD_17h_UMC
},
/* AMD Family 19h */
/* Source: SMU > Data Fabric > UMC */
{
PCI_VDEVICE(AMD, DID_AMD_19H_VERMEER_DF_F3),
.driver_data = (kernel_ulong_t) AMD_19h_UMC
},
{0, }
};
#define PCI_AMD_19h_ids PCI_AMD_17h_ids
static MICRO_ARCH Arch_Misc_Processor[] = {
{NULL}, /* Left as Void for initialization purpose. */
{"EPYC/Naples"},
{NULL}
};
static MICRO_ARCH Arch_Core_Yonah[] = {{"Core/Yonah"} , {NULL}};
static MICRO_ARCH Arch_Core_Conroe[] = {{"Core2/Conroe/Merom"},{NULL}};
static MICRO_ARCH Arch_Core_Kentsfield[]= {{"Core2/Kentsfield"} , {NULL}};
static MICRO_ARCH Arch_Core_Conroe_616[]= {{"Core2/Conroe/Yonah"},{NULL}};
enum {
CN_PENRYN,
CN_YORKFIELD,
CN_WOLFDALE
};
static MICRO_ARCH Arch_Core_Penryn[] = {
[CN_PENRYN] = {"Core2/Penryn"},
[CN_YORKFIELD] = {"Core2/Yorkfield"},
[CN_WOLFDALE] = {"Core2/Wolfdale"},
{NULL}
};
static MICRO_ARCH Arch_Core_Dunnington[]= {{"Xeon/Dunnington"} , {NULL}};
static MICRO_ARCH Arch_Atom_Bonnell[] = {{"Atom/Bonnell"} , {NULL}};
static MICRO_ARCH Arch_Atom_Silvermont[]= {{"Atom/Silvermont"} , {NULL}};
static MICRO_ARCH Arch_Atom_Lincroft[] = {{"Atom/Lincroft"} , {NULL}};
static MICRO_ARCH Arch_Atom_Clover_Trail[]={{"Atom/Clovertrail"}, {NULL}};
static MICRO_ARCH Arch_Atom_Saltwell[] = {{"Atom/Saltwell"} , {NULL}};
static MICRO_ARCH Arch_Silvermont_Bay_Trail[]={{"Silvermont/SoC"},{NULL}};
static MICRO_ARCH Arch_Atom_Avoton[] = {{"Atom/Avoton"} , {NULL}};
static MICRO_ARCH Arch_Atom_Airmont[] = {{"Atom/Airmont"} , {NULL}};
static MICRO_ARCH Arch_Atom_Goldmont[] = {{"Atom/Goldmont"} , {NULL}};
static MICRO_ARCH Arch_Atom_Sofia[] = {{"Atom/Sofia"} , {NULL}};
static MICRO_ARCH Arch_Atom_Merrifield[]= {{"Atom/Merrifield"} , {NULL}};
static MICRO_ARCH Arch_Atom_Moorefield[]= {{"Atom/Moorefield"} , {NULL}};
static MICRO_ARCH Arch_Nehalem_Bloomfield[]={{"Nehalem/Bloomfield"},{NULL}};
enum {
CN_LYNNFIELD,
CN_CLARKSFIELD
};
static MICRO_ARCH Arch_Nehalem_Lynnfield[] = {
[CN_LYNNFIELD] = {"Nehalem/Lynnfield"},
[CN_CLARKSFIELD] = {"Nehalem/Clarksfield"},
{NULL}
};
static MICRO_ARCH Arch_Nehalem_MB[] = {{"Nehalem/Mobile"} , {NULL}};
static MICRO_ARCH Arch_Nehalem_EX[] = {{"Nehalem/eXtreme.EP"},{NULL}};
static MICRO_ARCH Arch_Westmere[] = {{"Westmere"} , {NULL}};
enum {
CN_WESTMERE_EP,
CN_GULFTOWN
};
static MICRO_ARCH Arch_Westmere_EP[] = {
[CN_WESTMERE_EP] = {"Westmere/EP"},
[CN_GULFTOWN] = {"Westmere/Gulftown"},
{NULL}
};
static MICRO_ARCH Arch_Westmere_EX[] = {{"Westmere/eXtreme"} , {NULL}};
static MICRO_ARCH Arch_SandyBridge[] = {{"SandyBridge"} , {NULL}};
enum {
CN_SANDYBRIDGE_EP,
CN_SNB_ROMLEY_EP,
CN_SNB_EXTREME
};
static MICRO_ARCH Arch_SandyBridge_EP[] = {
[CN_SANDYBRIDGE_EP] = {"SandyBridge/EP"},
[CN_SNB_ROMLEY_EP] = {"SandyBridge/EP/Romley"},
[CN_SNB_EXTREME] = {"SandyBridge/eXtreme"},
{NULL}
};
static MICRO_ARCH Arch_IvyBridge[] = {{"IvyBridge"}, {NULL}};
enum {
CN_IVYBRIDGE_EP,
CN_IVB_ROMLEY_EP,
CN_IVB_EXTREME
};
static MICRO_ARCH Arch_IvyBridge_EP[] = {
[CN_IVYBRIDGE_EP] = {"IvyBridge/EP"},
[CN_IVB_ROMLEY_EP] = {"IvyBridge/EP/Romley"},
[CN_IVB_EXTREME] = {"IvyBridge/eXtreme"},
{NULL}
};
enum {
CN_HASWELL_DESKTOP,
CN_HASWELL_MOBILE_EX,
CN_HASWELL_CRYSTALWELL,
CN_HASWELL_CANYON,
CN_HASWELL_DENLOW,
CN_HASWELL_EMBEDDED,
CN_HASWELL_MOBILE
};
static MICRO_ARCH Arch_Haswell_DT[] = {
[CN_HASWELL_DESKTOP] = {"Haswell/Desktop"},
[CN_HASWELL_MOBILE_EX] = {"Haswell/Mobile/eXtreme"},
[CN_HASWELL_CRYSTALWELL]= {"Haswell/Crystal Well"},
[CN_HASWELL_CANYON] = {"Haswell/Canyon"},
[CN_HASWELL_DENLOW] = {"Haswell/Denlow"},
[CN_HASWELL_EMBEDDED] = {"Haswell/Embedded"},
[CN_HASWELL_MOBILE] = {"Haswell/Mobile"},
{NULL}
};
enum {
CN_HASWELL_EP,
CN_HSW_GRANTLEY_EP,
CN_HSW_EXTREME
};
static MICRO_ARCH Arch_Haswell_EP[] = {
[CN_HASWELL_EP] = {"Haswell/EP"},
[CN_HSW_GRANTLEY_EP] = {"Haswell/EP/Grantley"},
[CN_HSW_EXTREME] = {"Haswell/eXtreme"},
{NULL}
};
static MICRO_ARCH Arch_Haswell_ULT[] = {{"Haswell/Ultra Low TDP"},{NULL}};
static MICRO_ARCH Arch_Haswell_ULX[] ={{"Haswell/Ultra Low eXtreme"},{NULL}};
static MICRO_ARCH Arch_Broadwell[] = {{"Broadwell/Mobile"} , {NULL}};
static MICRO_ARCH Arch_Broadwell_D[] = {{"Broadwell/D"} , {NULL}};
static MICRO_ARCH Arch_Broadwell_H[] = {{"Broadwell/H"} , {NULL}};
enum {
CN_BROADWELL_EP,
CN_BDW_GRANTLEY_EP,
CN_BDW_EXTREME
};
static MICRO_ARCH Arch_Broadwell_EP[] = {
[CN_BROADWELL_EP] = {"Broadwell/EP"},
[CN_BDW_GRANTLEY_EP] = {"Broadwell/EP/Grantley"},
[CN_BDW_EXTREME] = {"Broadwell/eXtreme"},
{NULL}
};
static MICRO_ARCH Arch_Skylake_UY[] = {{"Skylake/UY"} , {NULL}};
static MICRO_ARCH Arch_Skylake_S[] = {{"Skylake/S"} , {NULL}};
enum {
CN_SKYLAKE_X,
CN_CASCADELAKE_X,
CN_COOPERLAKE_X
};
static MICRO_ARCH Arch_Skylake_X[] = {
[CN_SKYLAKE_X] = {"Skylake/X"},
[CN_CASCADELAKE_X] = {"Cascade Lake/X"},
[CN_COOPERLAKE_X] = {"Cooper Lake/X"},
{NULL}
};
static MICRO_ARCH Arch_Xeon_Phi[] = {{"Knights Landing"}, {NULL}};
enum {
CN_KABYLAKE,
CN_KABYLAKE_S,
CN_KABYLAKE_X,
CN_KABYLAKE_H,
CN_KABYLAKE_U,
CN_KABYLAKE_Y,
CN_KABYLAKE_R,
CN_KABYLAKE_G,
CN_COFFEELAKE_S,
CN_COFFEELAKE_H,
CN_COFFEELAKE_U,
CN_COFFEELAKE_R,
CN_COFFEELAKE_HR
};
static MICRO_ARCH Arch_Kabylake[] = {
[CN_KABYLAKE] = {"Kaby Lake"},
[CN_KABYLAKE_S] = {"Kaby Lake/S"},
[CN_KABYLAKE_X] = {"Kaby Lake/X"},
[CN_KABYLAKE_H] = {"Kaby Lake/H"},
[CN_KABYLAKE_U] = {"Kaby Lake/U"},
[CN_KABYLAKE_Y] = {"Kaby Lake/Y"},
[CN_KABYLAKE_R] = {"Kaby Lake/R"},
[CN_KABYLAKE_G] = {"Kaby Lake/G"},
[CN_COFFEELAKE_S] = {"Coffee Lake/S"},
[CN_COFFEELAKE_H] = {"Coffee Lake/H"},
[CN_COFFEELAKE_U] = {"Coffee Lake/U"},
[CN_COFFEELAKE_R] = {"Coffee Lake/R"},
[CN_COFFEELAKE_HR] = {"Coffee Lake/HR"},
{NULL}
};
enum {
CN_KABYLAKE_UY,
CN_WHISKEYLAKE_U,
CN_AMBERLAKE_Y,
CN_COMETLAKE_H,
CN_COMETLAKE_U
};
static MICRO_ARCH Arch_Kabylake_UY[] = {
[CN_KABYLAKE_UY] = {"Kaby Lake/UY"},
[CN_WHISKEYLAKE_U] = {"Whiskey Lake/U"},
[CN_AMBERLAKE_Y] = {"Amber Lake/Y"},
[CN_COMETLAKE_H] = {"Comet Lake/H"},
[CN_COMETLAKE_U] = {"Comet Lake/U"},
{NULL}
};
static MICRO_ARCH Arch_Cannonlake[] = {{"Cannon Lake"} , {NULL}};
static MICRO_ARCH Arch_Geminilake[] = {{"Atom/Gemini Lake"} , {NULL}};
static MICRO_ARCH Arch_Icelake[] = {{"Ice Lake"} , {NULL}};
static MICRO_ARCH Arch_Icelake_UY[] = {{"Ice Lake/UY"} , {NULL}};
static MICRO_ARCH Arch_Icelake_X[] = {{"Ice Lake/X"} , {NULL}};
static MICRO_ARCH Arch_Icelake_D[] = {{"Ice Lake/D"} , {NULL}};
static MICRO_ARCH Arch_Sunny_Cove[] = {{"Sunny Cove"} , {NULL}};
static MICRO_ARCH Arch_Tigerlake[] = {{"Tiger Lake"} , {NULL}};
static MICRO_ARCH Arch_Tigerlake_U[] = {{"Tiger Lake/U"} , {NULL}};
static MICRO_ARCH Arch_Cometlake[] = {{"Comet Lake"} , {NULL}};
static MICRO_ARCH Arch_Cometlake_UY[] = {{"Comet Lake/UY"} , {NULL}};
static MICRO_ARCH Arch_Atom_Denverton[] = {{"Atom/Denverton"} , {NULL}};
static MICRO_ARCH Arch_Tremont_Jacobsville[]={{"Tremont/Jacobsville"} ,{NULL}};
static MICRO_ARCH Arch_Tremont_Lakefield[] ={{"Tremont/Lakefield"} ,{NULL}};
static MICRO_ARCH Arch_Tremont_Elkhartlake[]={{"Tremont/Elkhart Lake"},{NULL}};
static MICRO_ARCH Arch_Tremont_Jasperlake[] ={{"Tremont/Jasper Lake"} ,{NULL}};
static MICRO_ARCH Arch_Sapphire_Rapids[] ={{"Sapphire Rapids"} , {NULL}};
static MICRO_ARCH Arch_Rocketlake[] = {{"Rocket Lake"} , {NULL}};
static MICRO_ARCH Arch_Rocketlake_U[] = {{"Rocket Lake/U"} , {NULL}};
enum {
CN_BULLDOZER,
CN_PILEDRIVER,
CN_STEAMROLLER,
CN_EXCAVATOR
};
static MICRO_ARCH Arch_AMD_Family_0Fh[] = {{"Hammer"} , {NULL}};
static MICRO_ARCH Arch_AMD_Family_10h[] = {{"K10"} , {NULL}};
static MICRO_ARCH Arch_AMD_Family_11h[] = {{"Turion"} , {NULL}};
static MICRO_ARCH Arch_AMD_Family_12h[] = {{"Fusion"} , {NULL}};
static MICRO_ARCH Arch_AMD_Family_14h[] = {{"Bobcat"} , {NULL}};
static MICRO_ARCH Arch_AMD_Family_15h[] = {
[CN_BULLDOZER] = {"Bulldozer"},
[CN_PILEDRIVER] = {"Bulldozer/Piledriver"},
[CN_STEAMROLLER] = {"Bulldozer/Steamroller"},
[CN_EXCAVATOR] = {"Bulldozer/Excavator"},
{NULL}
};
static MICRO_ARCH Arch_AMD_Family_16h[] = {{"Jaguar"}, {NULL}};
enum {
CN_SUMMIT_RIDGE,
CN_WHITEHAVEN,
CN_NAPLES
};
enum {
CN_RAVEN_RIDGE,
CN_SNOWY_OWL
};
enum {
CN_PINNACLE_RIDGE,
CN_COLFAX
};
enum {
CN_PICASSO
};
enum {
CN_DALI
};
enum {
CN_ROME
};
enum {
CN_CASTLE_PEAK
};
enum {
CN_RENOIR
};
enum {
CN_MATISSE
};
enum {
CN_VERMEER
};
enum {
CN_CEZANNE
};
enum {
CN_MILAN
};
static MICRO_ARCH Arch_AMD_Zen[] = {
[CN_SUMMIT_RIDGE] = {"Zen/Summit Ridge"},
[CN_WHITEHAVEN] = {"Zen/Whitehaven"},
[CN_NAPLES] = {"EPYC/Naples"},
{NULL}
};
static MICRO_ARCH Arch_AMD_Zen_APU[] = {
[CN_RAVEN_RIDGE] = {"Zen/Raven Ridge"},
[CN_SNOWY_OWL] = {"Zen/Snowy Owl"},
{NULL}
};
static MICRO_ARCH Arch_AMD_ZenPlus[] = {
[CN_PINNACLE_RIDGE] = {"Zen+ Pinnacle Ridge"},
[CN_COLFAX] = {"Zen+ Colfax"},
{NULL}
};
static MICRO_ARCH Arch_AMD_ZenPlus_APU[] = {
[CN_PICASSO] = {"Zen+ Picasso"},
{NULL}
};
static MICRO_ARCH Arch_AMD_Zen_APU_Dali[] = {
[CN_DALI] = {"Zen/Dali"},
{NULL}
};
static MICRO_ARCH Arch_AMD_EPYC_Rome[] = {
[CN_ROME] = {"EPYC/Rome"},
{NULL}
};
static MICRO_ARCH Arch_AMD_Zen2_CPK[] = {
[CN_CASTLE_PEAK] = {"Zen2/Castle Peak"},
{NULL}
};
static MICRO_ARCH Arch_AMD_Zen2_APU[] = {
[CN_RENOIR] = {"Zen2/Renoir"},
{NULL}
};
static MICRO_ARCH Arch_AMD_Zen2_MTS[] = {
[CN_MATISSE] = {"Zen2/Matisse"},
{NULL}
};
static MICRO_ARCH Arch_AMD_Zen3_VMR[] = {
[CN_VERMEER] = {"Zen3/Vermeer"},
{NULL}
};
static MICRO_ARCH Arch_AMD_Zen3_CZN[] = {
[CN_CEZANNE] = {"Zen3/Cezanne"},
{NULL}
};
static MICRO_ARCH Arch_AMD_EPYC_Milan[] = {
[CN_MILAN] = {"EPYC/Milan"},
{NULL}
};
static MICRO_ARCH Arch_AMD_Family_17h[] = {{"AMD Zen"}, {NULL}};
static MICRO_ARCH Arch_AMD_Family_18h[] = {{"Dhyana"}, {NULL}};
static MICRO_ARCH Arch_AMD_Family_19h[] = {{"AMD Zen3"}, {NULL}};
static PROCESSOR_SPECIFIC Void_Specific[] = { {0} };
static PROCESSOR_SPECIFIC Core_Penryn_Specific[] = {
/* Yorkfield
06_17h "Intel(R) Core(TM)2 Quad CPU Q8400"
'' "Intel(R) Core(TM)2 Quad CPU Q9400"
'' "Intel(R) Core(TM)2 Quad CPU Q9450"
'' "Intel(R) Core(TM)2 Quad CPU Q9550"
'' "Intel(R) Core(TM)2 Quad CPU Q9650"
'' Core 2 Quad Q9700
'' Core 2 Quad Q9705
'' "Intel(R) Core(TM)2 Extreme CPU X9650"
'' "Intel(R) Core(TM)2 Extreme CPU X9770"
'' "Intel(R) Core(TM)2 Extreme CPU X9775"
*/
{
.Brand = ZLIST( "Intel(R) Core(TM)2 Extreme CPU X97", \
"Intel(R) Core(TM)2 Extreme CPU X96", \
"Intel(R) Core(TM)2 Quad CPU Q96", \
"Intel(R) Core(TM)2 Quad CPU Q95", \
"Intel(R) Core(TM)2 Quad CPU Q94", \
"Intel(R) Core(TM)2 Quad CPU Q84" ),
.Boost = {0, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_YORKFIELD,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b00,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch = LATCH_TGT_RATIO_UNLOCK
},
/* Wolfdale
06_17h "Intel(R) Celeron(R) CPU E3200"
"Intel(R) Celeron(R) CPU E3300"
"Intel(R) Celeron(R) CPU E3400"
"Intel(R) Celeron(R) CPU E3500"
"Pentium(R) Dual-Core CPU E5200"
"Pentium(R) Dual-Core CPU E5300"
"Pentium(R) Dual-Core CPU E5400"
"Pentium(R) Dual-Core CPU E5500"
"Pentium(R) Dual-Core CPU E5700"
"Pentium(R) Dual-Core CPU E5800"
"Pentium(R) Dual-Core CPU E6300"
"Pentium(R) Dual-Core CPU E6500"
"Pentium(R) Dual-Core CPU E6600"
"Pentium(R) Dual-Core CPU E6700"
"Pentium(R) Dual-Core CPU E6800"
*/
{
.Brand = ZLIST( "Pentium(R) Dual-Core CPU E6", \
"Pentium(R) Dual-Core CPU E5", \
"Intel(R) Celeron(R) CPU E3" ),
.Boost = {0, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_WOLFDALE,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b00,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch = LATCH_TGT_RATIO_UNLOCK
},
/* Penryn
06_17h Celeron M 722
Celeron M 723
Celeron M 743
Celeron M 763
Core 2 Solo SU3300
06_17h Stepping[0Ah] "Intel(R) Core(TM)2 Solo CPU U3500"
'' "Genuine Intel(R) CPU U2300"
'' "Genuine Intel(R) CPU U2700"
'' "Genuine Intel(R) CPU U4100"
'' "Celeron(R) Dual-Core CPU T3100"
'' "Celeron(R) Dual-Core CPU T3300"
'' "Celeron(R) Dual-Core CPU T3500"
'' "Pentium(R) Dual-Core CPU T4200"
'' "Pentium(R) Dual-Core CPU T4300"
'' "Pentium(R) Dual-Core CPU T4400"
'' "Pentium(R) Dual-Core CPU T4500"
'' "Intel(R) Core(TM)2 Duo CPU P8400"
'' "Intel(R) Core(TM)2 Duo CPU P8600"
'' "Intel(R) Core(TM)2 Duo CPU P8800"
'' "Intel(R) Core(TM)2 Duo CPU T9550"
'' "Intel(R) Core(TM)2 Duo CPU T9600"
'' "Intel(R) Core(TM)2 Duo CPU T9900"
06_17h Stepping[06h] "Intel(R) Core(TM)2 Duo CPU T9300"
'' "Intel(R) Core(TM)2 Duo CPU T9400"
'' "Intel(R) Core(TM)2 Duo CPU T9500"
'' "Intel(R) Core(TM)2 Duo CPU P9300"
'' "Intel(R) Core(TM)2 Duo CPU P9400"
'' Core 2 Duo SP9600
'' "Intel(R) Core(TM)2 Extreme CPU X9000"
06_17h Stepping[0Ah] "Intel(R) Core(TM)2 Extreme CPU X9100"
'' "Intel(R) Core(TM)2 Quad CPU Q9000"
'' "Intel(R) Core(TM)2 Quad CPU Q9100"
'' "Intel(R) Core(TM)2 Extreme CPU Q9300"
*/
{
.Brand = ZLIST("Intel(R) Core(TM)2 Extreme CPU Q9300"),
.Boost = {+2, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_PENRYN,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b00,
.TurboUnlocked = 1,
.UncoreUnlocked = 0,
.Latch = LATCH_TGT_RATIO_UNLOCK
},
{0}
};
static PROCESSOR_SPECIFIC Silvermont_Bay_Trail_Specific[] = {
{
.Brand = ZLIST("Intel(R) Celeron(R) CPU N29"),
.Boost = {0, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = 0,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b00,
.TurboUnlocked = 1,
.UncoreUnlocked = 0,
.Latch = LATCH_TGT_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{0}
};
static PROCESSOR_SPECIFIC Nehalem_Bloomfield_Specific[] = {
{
.Brand = ZLIST("Intel(R) Core(TM) i7 CPU 920"),
.Boost = {0, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = 0,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b00,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch = LATCH_TGT_RATIO_UNLOCK|LATCH_TURBO_UNLOCK|LATCH_UNCORE_UNLOCK
},
{0}
};
static PROCESSOR_SPECIFIC Nehalem_Lynnfield_Specific[] = {
{
.Brand = ZLIST( "Intel(R) Core(TM) i7 CPU X", \
"Intel(R) Core(TM) i7 CPU Q" ),
.Boost = {0, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_CLARKSFIELD,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b00,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch = LATCH_TGT_RATIO_UNLOCK
},
{0}
};
static PROCESSOR_SPECIFIC Westmere_EP_Specific[] = {
{
.Brand = ZLIST( "Intel(R) Core(TM) i7 CPU X 990", \
"Intel(R) Core(TM) i7 CPU X 980", \
"Intel(R) Core(TM) i7 CPU 980" , \
"Intel(R) Core(TM) i7 CPU 970" ),
.Boost = {0, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_GULFTOWN,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b00,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch = LATCH_TGT_RATIO_UNLOCK
},
{
.Brand = ZLIST("Intel(R) Xeon(R) CPU W3690"),
.Boost = {0, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_GULFTOWN,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b00,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch = LATCH_TGT_RATIO_UNLOCK
},
{0}
};
static PROCESSOR_SPECIFIC SandyBridge_EP_Specific[] = {
{
.Brand = ZLIST("Intel(R) Xeon(R) CPU E5-26"),
.Boost = {0, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_SNB_ROMLEY_EP,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b00,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch = LATCH_TGT_RATIO_UNLOCK
},
{
.Brand = ZLIST( "Intel(R) Core(TM) i7-3970X", \
"Intel(R) Core(TM) i7-3960X", \
"Intel(R) Core(TM) i7-3930K", \
"Intel(R) Core(TM) i7-3820" ),
.Boost = {0, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_SNB_EXTREME,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b00,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch = LATCH_TGT_RATIO_UNLOCK
},
{0}
};
static PROCESSOR_SPECIFIC IvyBridge_EP_Specific[] = {
{
.Brand = ZLIST( "Intel(R) Xeon(R) CPU E5-1650 v2", \
"Intel(R) Xeon(R) CPU E5-1660 v2", \
"Intel(R) Xeon(R) CPU E5-1680 v2" ),
.Boost = {0, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_IVYBRIDGE_EP,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b00,
.TurboUnlocked = 1,
.UncoreUnlocked = 1,
.Latch = LATCH_TGT_RATIO_UNLOCK|LATCH_TURBO_UNLOCK|LATCH_UNCORE_UNLOCK
},
{
.Brand = ZLIST( "Intel(R) Xeon(R) CPU E5-26", \
"CPU E2697V" ),
.Boost = {0, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_IVB_ROMLEY_EP,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b00,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch = LATCH_TGT_RATIO_UNLOCK
},
{
.Brand = ZLIST( "Intel(R) Core(TM) i7-4960X", \
"Intel(R) Core(TM) i7-4930K", \
"Intel(R) Core(TM) i7-4820K" ),
.Boost = {0, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_IVB_EXTREME,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b00,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch = LATCH_TGT_RATIO_UNLOCK
},
{0}
};
static PROCESSOR_SPECIFIC Haswell_DT_Specific[] = {
{
.Brand = ZLIST( "Intel(R) Core(TM) i7-4940MX", \
"Intel(R) Core(TM) i7-4930MX" ),
.Boost = {0, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_HASWELL_MOBILE_EX,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b00,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch = LATCH_TGT_RATIO_UNLOCK
},
{
.Brand = ZLIST( "Intel(R) Core(TM) i7-4910MQ", \
"Intel(R) Core(TM) i7-4900MQ", \
"Intel(R) Core(TM) i7-4810MQ", \
"Intel(R) Core(TM) i7-4800MQ", \
"Intel(R) Core(TM) i7-4710HQ", \
"Intel(R) Core(TM) i7-4700HQ" ),
.Boost = {0, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_HASWELL_CRYSTALWELL,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b00,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch = LATCH_TGT_RATIO_UNLOCK
},
{
.Brand = ZLIST( "Intel(R) Core(TM) i7-47", \
"Intel(R) Core(TM) i5-46" ),
.Boost = {0, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_HASWELL_CANYON,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b00,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch = LATCH_TGT_RATIO_UNLOCK
},
{
.Brand = ZLIST("Intel(R) Xeon(R) CPU E3-12"),
.Boost = {0, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_HASWELL_DENLOW,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b00,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch = LATCH_TGT_RATIO_UNLOCK
},
{
.Brand = ZLIST("Intel(R) 4th Gen Core(TM) i"),
.Boost = {0, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_HASWELL_EMBEDDED,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b00,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch = LATCH_TGT_RATIO_UNLOCK
},
{
.Brand = ZLIST( "Intel(R) Core(TM) i5-4300M", \
"Intel(R) Core(TM) i5-4200H", \
"Intel(R) Core(TM) i3-4000M", \
"Intel(R) Pentium(R) CPU 3", \
"Intel(R) Celeron(R) CPU 2" ),
.Boost = {0, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_HASWELL_MOBILE,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b00,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch = LATCH_TGT_RATIO_UNLOCK
},
{0}
};
static PROCESSOR_SPECIFIC Haswell_EP_Specific[] = {
{
.Brand = ZLIST( "Intel(R) Xeon(R) CPU E5-1650 v3", \
"Intel(R) Xeon(R) CPU E5-1660 v3", \
"Intel(R) Xeon(R) CPU E5-1680 v3" ),
.Boost = {0, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_HASWELL_EP,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b00,
.TurboUnlocked = 1,
.UncoreUnlocked = 1,
.Latch = LATCH_TGT_RATIO_UNLOCK|LATCH_TURBO_UNLOCK|LATCH_UNCORE_UNLOCK
},
{
.Brand = ZLIST("Intel(R) Xeon(R) CPU E5-26"),
.Boost = {0, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_HSW_GRANTLEY_EP,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b00,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch = LATCH_TGT_RATIO_UNLOCK
},
{
.Brand = ZLIST( "Intel(R) Core(TM) i7-5960X", \
"Intel(R) Core(TM) i7-5930K", \
"Intel(R) Core(TM) i7-5820K" ),
.Boost = {0, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_HSW_EXTREME,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b00,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch = LATCH_TGT_RATIO_UNLOCK
},
{0}
};
static PROCESSOR_SPECIFIC Broadwell_EP_Specific[] = {
{
.Brand = ZLIST( "Intel(R) Xeon(R) CPU E5-26", \
"Intel(R) Xeon(R) CPU E5-46" ),
.Boost = {0, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_BDW_GRANTLEY_EP,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b00,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch = LATCH_TGT_RATIO_UNLOCK
},
{
.Brand = ZLIST( "Intel(R) Core(TM) i7-6950X", \
"Intel(R) Core(TM) i7-6900K", \
"Intel(R) Core(TM) i7-6850K", \
"Intel(R) Core(TM) i7-6800K" ),
.Boost = {0, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_BDW_EXTREME,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b00,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch = LATCH_TGT_RATIO_UNLOCK
},
{0}
};
static PROCESSOR_SPECIFIC Skylake_X_Specific[] = {
{
.Brand = ZLIST( "Intel(R) Core(TM) i9-10980XE", \
"Intel(R) Core(TM) i9-10940X" , \
"Intel(R) Core(TM) i9-10920X" , \
"Intel(R) Core(TM) i9-10900X" , \
"Intel(R) Xeon(R) Platinum 92", \
"Intel(R) Xeon(R) Platinum 82", \
"Intel(R) Xeon(R) Gold 62", \
"Intel(R) Xeon(R) Gold 52", \
"Intel(R) Xeon(R) Silver 42", \
"Intel(R) Xeon(R) Bronze 32", \
"Intel(R) Xeon(R) W-32", \
"Intel(R) Xeon(R) W-22" ),
.Boost = {0, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_CASCADELAKE_X,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b00,
.TurboUnlocked = 0,
.UncoreUnlocked = 1,
.Latch = LATCH_TGT_RATIO_UNLOCK|LATCH_UNCORE_UNLOCK
},
{0}
};
static PROCESSOR_SPECIFIC Kabylake_Specific[] = {
{
.Brand = ZLIST( "Intel(R) Core(TM) i7-7920HQ", \
"Intel(R) Core(TM) i7-7820HQ", \
"Intel(R) Core(TM) i7-7700HQ", \
"Intel(R) Core(TM) i5-7440HQ", \
"Intel(R) Core(TM) i5-7300HQ", \
"Intel(R) Core(TM) i3-7100H" ),
.Boost = {0, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_KABYLAKE_H,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0,
.TurboUnlocked = 0,
.UncoreUnlocked = 1,
.Latch = LATCH_TGT_RATIO_UNLOCK|LATCH_UNCORE_UNLOCK
},
{
.Brand = ZLIST( "Intel(R) Core(TM) i7-7740X", \
"Intel(R) Core(TM) i5-7640X" ),
.Boost = {0, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_KABYLAKE_X,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b00,
.TurboUnlocked = 0,
.UncoreUnlocked = 1,
.Latch = LATCH_TGT_RATIO_UNLOCK|LATCH_UNCORE_UNLOCK
},
{
.Brand = ZLIST( "Intel(R) Core(TM) i7-766", \
"Intel(R) Core(TM) i7-760", \
"Intel(R) Core(TM) i7-756", \
"Intel(R) Core(TM) i7-750" ),
.Boost = {0, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_KABYLAKE_U,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b00,
.TurboUnlocked = 0,
.UncoreUnlocked = 1,
.Latch = LATCH_TGT_RATIO_UNLOCK|LATCH_UNCORE_UNLOCK
},
{
.Brand = ZLIST( "Intel(R) Core(TM) i7-770" \
"Intel(R) Core(TM) i5-760", \
"Intel(R) Core(TM) i5-750", \
"Intel(R) Core(TM) i5-740" ),
.Boost = {0, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_KABYLAKE_S,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b00,
.TurboUnlocked = 0,
.UncoreUnlocked = 1,
.Latch = LATCH_TGT_RATIO_UNLOCK|LATCH_UNCORE_UNLOCK
},
{
.Brand = ZLIST( "Intel(R) Core(TM) i5-736", \
"Intel(R) Core(TM) i5-730", \
"Intel(R) Core(TM) i5-728", \
"Intel(R) Core(TM) i5-726", \
"Intel(R) Core(TM) i5-720" ),
.Boost = {0, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_KABYLAKE_U,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b00,
.TurboUnlocked = 0,
.UncoreUnlocked = 1,
.Latch = LATCH_TGT_RATIO_UNLOCK|LATCH_UNCORE_UNLOCK
},
{
.Brand = ZLIST( "Intel(R) Core(TM) i7-7Y7", \
"Intel(R) Core(TM) i5-7Y5", \
"Intel(R) Core(TM) m3-7Y3" ),
.Boost = {0, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_KABYLAKE_Y,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b00,
.TurboUnlocked = 0,
.UncoreUnlocked = 1,
.Latch = LATCH_TGT_RATIO_UNLOCK|LATCH_UNCORE_UNLOCK
},
{
.Brand = ZLIST( "Intel(R) Core(TM) i3-7167U", \
"Intel(R) Core(TM) i3-7130U", \
"Intel(R) Core(TM) i3-7100U", \
"Intel(R) Core(TM) i3-7020U" ),
.Boost = {0, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_KABYLAKE_U,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b00,
.TurboUnlocked = 0,
.UncoreUnlocked = 1,
.Latch = LATCH_TGT_RATIO_UNLOCK|LATCH_UNCORE_UNLOCK
},
{
.Brand = ZLIST( "Intel(R) Core(TM) i3-735", \
"Intel(R) Core(TM) i3-732", \
"Intel(R) Core(TM) i3-730", \
"Intel(R) Core(TM) i3-710" ),
.Boost = {0, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_KABYLAKE_S,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b00,
.TurboUnlocked = 0,
.UncoreUnlocked = 1,
.Latch = LATCH_TGT_RATIO_UNLOCK|LATCH_UNCORE_UNLOCK
},
{
.Brand = ZLIST( "Intel(R) Core(TM) i7-8650U", \
"Intel(R) Core(TM) i7-8550U", \
"Intel(R) Core(TM) i5-8350U", \
"Intel(R) Core(TM) i5-8250U", \
"Intel(R) Core(TM) i3-8130U" ),
.Boost = {0, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_KABYLAKE_R,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b00,
.TurboUnlocked = 0,
.UncoreUnlocked = 1,
.Latch = LATCH_TGT_RATIO_UNLOCK|LATCH_UNCORE_UNLOCK
},
{
.Brand = ZLIST( "Intel(R) Core(TM) i7-8809G", \
"Intel(R) Core(TM) i7-8709G", \
"Intel(R) Core(TM) i7-8706G", \
"Intel(R) Core(TM) i7-8705G", \
"Intel(R) Core(TM) i7-8305G" ),
.Boost = {0, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_KABYLAKE_G,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b00,
.TurboUnlocked = 0,
.UncoreUnlocked = 1,
.Latch = LATCH_TGT_RATIO_UNLOCK|LATCH_UNCORE_UNLOCK
},
{
.Brand = ZLIST( "Intel(R) Pentium(R) CPU G46", \
"Intel(R) Pentium(R) CPU G45", \
"Intel(R) Celeron(R) CPU G39" ),
.Boost = {0, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_KABYLAKE_S,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b00,
.TurboUnlocked = 0,
.UncoreUnlocked = 1,
.Latch = LATCH_TGT_RATIO_UNLOCK|LATCH_UNCORE_UNLOCK
},
{
.Brand = ZLIST( "Intel(R) Pentium(R) Processor 44", \
"Intel(R) Celeron(R) Processor 3965Y" ),
.Boost = {0, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_KABYLAKE_Y,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b00,
.TurboUnlocked = 0,
.UncoreUnlocked = 1,
.Latch = LATCH_TGT_RATIO_UNLOCK|LATCH_UNCORE_UNLOCK
},
{
.Brand = ZLIST( "Intel(R) Celeron(R) Processor 3965U", \
"Intel(R) Celeron(R) Processor 3865U" ),
.Boost = {0, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_KABYLAKE_U,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b00,
.TurboUnlocked = 0,
.UncoreUnlocked = 1,
.Latch = LATCH_TGT_RATIO_UNLOCK|LATCH_UNCORE_UNLOCK
},
{
.Brand = ZLIST( "Intel(R) Pentium(R) Gold G56", \
"Intel(R) Pentium(R) Gold G55", \
"Intel(R) Pentium(R) Gold G54", \
"Intel(R) Celeron(R) G49" ),
.Boost = {0, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_COFFEELAKE_S,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b00,
.TurboUnlocked = 0,
.UncoreUnlocked = 1,
.Latch = LATCH_TGT_RATIO_UNLOCK|LATCH_UNCORE_UNLOCK
},
{
.Brand = ZLIST( "Intel(R) Core(TM) i9-8950H", \
"Intel(R) Core(TM) i7-8850H", \
"Intel(R) Core(TM) i7-8750H", \
"Intel(R) Core(TM) i7-8700B", \
"Intel(R) Core(TM) i5-8500B", \
"Intel(R) Core(TM) i5-8400B", \
"Intel(R) Core(TM) i5-8400H", \
"Intel(R) Core(TM) i5-8300H", \
"Intel(R) Core(TM) i3-8100B", \
"Intel(R) Core(TM) i3-8100H" ),
.Boost = {0, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_COFFEELAKE_H,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b00,
.TurboUnlocked = 0,
.UncoreUnlocked = 1,
.Latch = LATCH_TGT_RATIO_UNLOCK|LATCH_UNCORE_UNLOCK
},
{
.Brand = ZLIST( "Intel(R) Core(TM) i7-8086K", \
"Intel(R) Core(TM) i7-8700", \
"Intel(R) Core(TM) i5-8600", \
"Intel(R) Core(TM) i5-8500", \
"Intel(R) Core(TM) i5-8400", \
"Intel(R) Core(TM) i3-8350K", \
"Intel(R) Core(TM) i3-8300", \
"Intel(R) Core(TM) i3-8100" ),
.Boost = {0, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_COFFEELAKE_S,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b00,
.TurboUnlocked = 0,
.UncoreUnlocked = 1,
.Latch = LATCH_TGT_RATIO_UNLOCK|LATCH_UNCORE_UNLOCK
},
{
.Brand = ZLIST( "Intel(R) Core(TM) i7-8569U", \
"Intel(R) Core(TM) i7-8559U", \
"Intel(R) Core(TM) i7-8557U", \
"Intel(R) Core(TM) i5-8279U", \
"Intel(R) Core(TM) i5-8269U", \
"Intel(R) Core(TM) i5-8259U", \
"Intel(R) Core(TM) i5-8257U", \
"Intel(R) Core(TM) i3-8109U" ),
.Boost = {0, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_COFFEELAKE_U,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b00,
.TurboUnlocked = 0,
.UncoreUnlocked = 1,
.Latch = LATCH_TGT_RATIO_UNLOCK|LATCH_UNCORE_UNLOCK
},
{
.Brand = ZLIST( "Intel(R) Core(TM) i9-9980H", \
"Intel(R) Core(TM) i9-9880H", \
"Intel(R) Core(TM) i7-9850H", \
"Intel(R) Core(TM) i7-9750H", \
"Intel(R) Core(TM) i5-9400H", \
"Intel(R) Core(TM) i5-9300H" ),
.Boost = {0, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_COFFEELAKE_HR,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b00,
.TurboUnlocked = 0,
.UncoreUnlocked = 1,
.Latch = LATCH_TGT_RATIO_UNLOCK|LATCH_UNCORE_UNLOCK
},
{
.Brand = ZLIST( "Intel(R) Core(TM) i9-990", \
"Intel(R) Core(TM) i7-970", \
"Intel(R) Core(TM) i5-960", \
"Intel(R) Core(TM) i5-950", \
"Intel(R) Core(TM) i5-940", \
"Intel(R) Core(TM) i3-935", \
"Intel(R) Core(TM) i3-932", \
"Intel(R) Core(TM) i3-930", \
"Intel(R) Core(TM) i3-910" ),
.Boost = {0, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_COFFEELAKE_R,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b00,
.TurboUnlocked = 0,
.UncoreUnlocked = 1,
.Latch = LATCH_TGT_RATIO_UNLOCK|LATCH_UNCORE_UNLOCK
},
{0}
};
static PROCESSOR_SPECIFIC Kabylake_UY_Specific[] = {
{
.Brand = ZLIST( "Intel(R) Core(TM) i7-8665U", \
"Intel(R) Core(TM) i7-8565U", \
"Intel(R) Core(TM) i5-8365U", \
"Intel(R) Core(TM) i5-8265U", \
"Intel(R) Core(TM) i3-8145U", \
"Intel(R) Pentium(R) CPU 5405U",\
"Intel(R) Celeron(R) CPU 4305U",\
"Intel(R) Celeron(R) CPU 4205U" ),
.Boost = {0, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_WHISKEYLAKE_U,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b00,
.TurboUnlocked = 0,
.UncoreUnlocked = 1,
.Latch = LATCH_TGT_RATIO_UNLOCK|LATCH_UNCORE_UNLOCK
},
{
.Brand = ZLIST( "Intel(R) Core(TM) i7-10510Y", \
"Intel(R) Core(TM) i5-10310Y", \
"Intel(R) Core(TM) i5-10210Y", \
"Intel(R) Core(TM) i3-10110Y", \
"Intel(R) Core(TM) i7-8500Y" , \
"Intel(R) Core(TM) i5-8310Y" , \
"Intel(R) Core(TM) i5-8210Y" , \
"Intel(R) Core(TM) i5-8200Y" , \
"Intel(R) Core(TM) m3-8100Y" ),
.Boost = {0, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_AMBERLAKE_Y,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b00,
.TurboUnlocked = 0,
.UncoreUnlocked = 1,
.Latch = LATCH_TGT_RATIO_UNLOCK|LATCH_UNCORE_UNLOCK
},
{
.Brand = ZLIST( "Intel(R) Core(TM) i9-10980HK", \
"Intel(R) Core(TM) i7-10875H", \
"Intel(R) Core(TM) i7-10850H", \
"Intel(R) Core(TM) i7-10750H", \
"Intel(R) Core(TM) i5-10400H", \
"Intel(R) Core(TM) i5-10300H" ),
.Boost = {0, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_COMETLAKE_H,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b00,
.TurboUnlocked = 0,
.UncoreUnlocked = 1,
.Latch = LATCH_TGT_RATIO_UNLOCK|LATCH_UNCORE_UNLOCK
},
{
.Brand = ZLIST( "Intel(R) Core(TM) i7-10710U", \
"Intel(R) Core(TM) i7-10510U", \
"Intel(R) Core(TM) i5-10210U", \
"Intel(R) Core(TM) i3-10110U", \
"Intel(R) Pentium(R) Gold 6405U",\
"Intel(R) Celeron(R) CPU 5205U" ),
.Boost = {0, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_COMETLAKE_U,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b00,
.TurboUnlocked = 0,
.UncoreUnlocked = 1,
.Latch = LATCH_TGT_RATIO_UNLOCK|LATCH_UNCORE_UNLOCK
},
{0}
};
/* AMD Family 17h
Remarks:Thermal Offset taken from Linux/k10temp.c
+0.5 XFR is rounded to +1 multiplier bin
*/
static PROCESSOR_SPECIFIC AMD_Zen_Specific[] = {
/* [Zen/Summit Ridge] 8F_01h Stepping 1 */
{
.Brand = ZLIST("AMD Ryzen Embedded V"),
.Boost = {+16, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_SUMMIT_RIDGE,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST("AMD Athlon Silver PRO 3125GE"),
.Boost = {+0, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_SUMMIT_RIDGE,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST("AMD Athlon Gold PRO 3150GE"),
.Boost = {+5, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_SUMMIT_RIDGE,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST("AMD Athlon Gold PRO 3150G"),
.Boost = {+4, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_SUMMIT_RIDGE,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST( "AMD Ryzen Embedded R", \
"AMD Athlon Silver", \
"AMD Athlon Gold" ),
.Boost = {+9, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_SUMMIT_RIDGE,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST("AMD Ryzen 3 PRO 1200"),
.Boost = {+3, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_SUMMIT_RIDGE,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST( "AMD Ryzen 3 PRO 1300", \
"AMD Ryzen 5 PRO 1500" ),
.Boost = {+2, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_SUMMIT_RIDGE,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST("AMD Ryzen 5 PRO 1600"),
.Boost = {+4, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_SUMMIT_RIDGE,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST("AMD Ryzen 7 PRO 1700X"),
.Boost = {+4, 0},
.Param.Offset = {0, 0, 20},
.CodeNameIdx = CN_SUMMIT_RIDGE,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST("AMD Ryzen 7 PRO 1700"),
.Boost = {+7, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_SUMMIT_RIDGE,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST( "AMD Ryzen 3 1300X", \
"AMD Ryzen 5 1500X" ),
.Boost = {+2, +2},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_SUMMIT_RIDGE,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 1,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST( "AMD Ryzen 5 1600X", \
"AMD Ryzen 7 1700X", \
"AMD Ryzen 7 1800X" ),
.Boost = {+4, +1},
.Param.Offset = {0, 0, 20},
.CodeNameIdx = CN_SUMMIT_RIDGE,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 1,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST("AMD Ryzen 3 1200"),
.Boost = {+3, +1},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_SUMMIT_RIDGE,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 1,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST("AMD Ryzen 5 1400"),
.Boost = {+2, +1},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_SUMMIT_RIDGE,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 1,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST("AMD Ryzen 5 1600"),
.Boost = {+4, +1},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_SUMMIT_RIDGE,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 1,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST("AMD Ryzen 7 1700"),
.Boost = {+7, +1},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_SUMMIT_RIDGE,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 1,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
/* [Zen/Whitehaven] 8F_01h Stepping 1 */
{
.Brand = ZLIST("AMD Ryzen Threadripper 1950X"),
.Boost = {+6, +2},
.Param.Offset = {0, 0, 27},
.CodeNameIdx = CN_WHITEHAVEN,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 1,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST("AMD Ryzen Threadripper 1920X"),
.Boost = {+5, +2},
.Param.Offset = {0, 0, 27},
.CodeNameIdx = CN_WHITEHAVEN,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 1,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST("AMD Ryzen Threadripper 1900X"),
.Boost = {+2, +2},
.Param.Offset = {0, 0, 27},
.CodeNameIdx = CN_WHITEHAVEN,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 1,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
/* [EPYC/Naples] 8F_01h Stepping 2 */
{ /* AMD EPYC Server Processors */
.Brand = ZLIST("AMD EPYC 7251"),
.Boost = {+8, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_NAPLES,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST("AMD EPYC 7261"),
.Boost = {+4, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_NAPLES,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST("AMD EPYC 7281"),
.Boost = {+6, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_NAPLES,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST( "AMD EPYC 7351P", \
"AMD EPYC 7351", \
"AMD EPYC 7301" ),
.Boost = {+5, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_NAPLES,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST( "AMD EPYC 7401P", \
"AMD EPYC 7401" ),
.Boost = {+8, +2},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_NAPLES,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST("AMD EPYC 7451"),
.Boost = {+6, +3},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_NAPLES,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST( "AMD EPYC 7551P", \
"AMD EPYC 7551", \
"AMD EPYC 7501" ),
.Boost = {+6, +4},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_NAPLES,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST("AMD EPYC 7601"),
.Boost = {+5, +5},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_NAPLES,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{0}
};
static PROCESSOR_SPECIFIC AMD_Zen_APU_Specific[] = {
/* [Zen/Raven Ridge] 8F_11h Stepping 0 */
{
.Brand = ZLIST( "AMD Athlon 240GE", \
"AMD Athlon 220GE", \
"AMD Athlon 200GE" ),
.Boost = {+0, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_RAVEN_RIDGE,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch = LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK
},
{
.Brand = ZLIST( "AMD Ryzen 3 PRO 2200GE", \
"AMD Ryzen 5 2600H" ),
.Boost = {+4, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_RAVEN_RIDGE,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST("AMD Ryzen 3 PRO 2200G"),
.Boost = {+2, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_RAVEN_RIDGE,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST("AMD Ryzen 3 2200GE"),
.Boost = {+4, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_RAVEN_RIDGE,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 1,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST("AMD Ryzen 3 2200G"),
.Boost = {+2, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_RAVEN_RIDGE,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 1,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST("AMD Ryzen 5 PRO 2400GE"),
.Boost = {+6, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_RAVEN_RIDGE,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST("AMD Ryzen 5 PRO 2400G"),
.Boost = {+3, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_RAVEN_RIDGE,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST("AMD Ryzen 5 2400GE"),
.Boost = {+6, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_RAVEN_RIDGE,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 1,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST("AMD Ryzen 5 2400G"),
.Boost = {+3, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_RAVEN_RIDGE,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 1,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST("AMD Ryzen 5 2500U"),
.Boost = {+16, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_RAVEN_RIDGE,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST("AMD Ryzen 7 2800H"),
.Boost = {+5, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_RAVEN_RIDGE,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST("AMD Ryzen 7 2700U"),
.Boost = {+16, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_RAVEN_RIDGE,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 1,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
/* [Zen/Snowy Owl] 8F_11h Stepping 0 */
{ /* AMD EPYC Embedded Processors */
.Brand = ZLIST( "AMD EPYC 31", \
"AMD EPYC 32" ),
.Boost = {+0, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_SNOWY_OWL,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{0}
};
static PROCESSOR_SPECIFIC AMD_ZenPlus_Specific[] = {
/* [Zen+ Pinnacle Ridge] 8F_08h Stepping 2 */
{
.Brand = ZLIST("AMD Athlon 3000G"),
.Boost = {+5, +1},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_PINNACLE_RIDGE,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 1,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST("AMD Athlon 300U"),
.Boost = {+9, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_PINNACLE_RIDGE,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch = LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK
},
{
.Brand = ZLIST("AMD Athlon 3"),
.Boost = {+9, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_PINNACLE_RIDGE,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 1,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST("AMD Athlon PRO"),
.Boost = {+5, +1},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_PINNACLE_RIDGE,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch = LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK
},
{
.Brand = ZLIST( "AMD Ryzen 3 2300X", \
"AMD Ryzen 5 2500X" ),
.Boost = {+4, +1},
.Param.Offset = {0, 0, 10},
.CodeNameIdx = CN_PINNACLE_RIDGE,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 1,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST("AMD Ryzen 5 2600E"),
.Boost = {+8, +1},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_PINNACLE_RIDGE,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 1,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST("AMD Ryzen 5 PRO 2600"),
.Boost = {+5, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_PINNACLE_RIDGE,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST("AMD Ryzen 5 2600"),
.Boost = {+3, +2},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_PINNACLE_RIDGE,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 1,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST("AMD Ryzen 7 PRO 2700X"),
.Boost = {+5, 0},
.Param.Offset = {0, 0, 10},
.CodeNameIdx = CN_PINNACLE_RIDGE,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST("AMD Ryzen 7 PRO 2700"),
.Boost = {+9, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_PINNACLE_RIDGE,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST( "AMD Ryzen 7 2700X", \
"AMD Ryzen 5 2600X" ),
.Boost = {+5, +2},
.Param.Offset = {0, 0, 10},
.CodeNameIdx = CN_PINNACLE_RIDGE,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 1,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST("AMD Ryzen 7 2700E"),
.Boost = {+12, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_PINNACLE_RIDGE,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 1,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST("AMD Ryzen 7 2700"),
.Boost = {+8, +2},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_PINNACLE_RIDGE,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 1,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
/* [Zen+ Colfax] 8F_08h Stepping 2 */
{
.Brand = ZLIST( "AMD Ryzen Threadripper 2990", \
"AMD Ryzen Threadripper 2970" ),
.Boost = {+12, 0},
.Param.Offset = {0, 0, 27},
.CodeNameIdx = CN_COLFAX,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 1,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST("AMD Ryzen Threadripper 2950"),
.Boost = {+9, 0},
.Param.Offset = {0, 0, 27},
.CodeNameIdx = CN_COLFAX,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 1,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST("AMD Ryzen Threadripper 2920"),
.Boost = {+8, 0},
.Param.Offset = {0, 0, 27},
.CodeNameIdx = CN_COLFAX,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 1,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{0}
};
static PROCESSOR_SPECIFIC AMD_ZenPlus_APU_Specific[] = {
/* [Zen+ Picasso] 8F_18h Stepping 1 */
{
.Brand = ZLIST("AMD Athlon PRO 300GE"),
.Boost = {+0, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_PICASSO,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST("AMD Ryzen 5 PRO 3400GE"),
.Boost = {+7, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_PICASSO,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST( "AMD Ryzen 5 PRO 3400G", \
"AMD Ryzen 3 PRO 3200GE" ),
.Boost = {+5, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_PICASSO,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST("AMD Ryzen 3 PRO 3200G"),
.Boost = {+4, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_PICASSO,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST("AMD Ryzen 5 3400GE"),
.Boost = {+7, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_PICASSO,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 1,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST( "AMD Ryzen 3 3200GE", \
"AMD Ryzen 5 3400G" ),
.Boost = {+5, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_PICASSO,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 1,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST("AMD Ryzen 3 3200G"),
.Boost = {+4, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_PICASSO,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 1,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST( "AMD Ryzen 5 3580U", \
"AMD Ryzen 5 3550H", \
"AMD Ryzen 5 3500U" ),
.Boost = {+16, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_PICASSO,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST( "AMD Ryzen 7 3780U", \
"AMD Ryzen 7 3750H", \
"AMD Ryzen 7 3700U" ),
.Boost = {+17, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_PICASSO,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{0}
};
static PROCESSOR_SPECIFIC AMD_Zen_APU_Dali_Specific[] = {
{
.Brand = ZLIST( "AMD Athlon", \
"AMD Ryzen 3"),
.Boost = {+9, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_DALI,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{0}
};
static PROCESSOR_SPECIFIC AMD_EPYC_Rome_Specific[] = {
/* [EPYC/Rome] 8F_30h Stepping 0 */
{
.Brand = ZLIST( "AMD EPYC 7232P", \
"AMD EPYC 7252" ),
.Boost = {+1, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_ROME,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST( "AMD EPYC 7262", \
"AMD EPYC 7F32" ),
.Boost = {+2, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_ROME,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST("AMD EPYC 7272"),
.Boost = {+3, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_ROME,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST( "AMD EPYC 7282", \
"AMD EPYC 7F52" ),
.Boost = {+4, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_ROME,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST( "AMD EPYC 7302P", \
"AMD EPYC 7302" ),
.Boost = {+3, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_ROME,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST( "AMD EPYC 7402P", \
"AMD EPYC 7402" ),
.Boost = {+6, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_ROME,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST( "AMD EPYC 7352", \
"AMD EPYC 7502P", \
"AMD EPYC 7502" ),
.Boost = {+9, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_ROME,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST( "AMD EPYC 7542", \
"AMD EPYC 7F72" ),
.Boost = {+5, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_ROME,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST("AMD EPYC 7552"),
.Boost = {+11, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_ROME,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST( "AMD EPYC 7452", \
"AMD EPYC 7642" ),
.Boost = {+10, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_ROME,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST("AMD EPYC 7662"),
.Boost = {+13, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_ROME,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST( "AMD EPYC 7702P", \
"AMD EPYC 7702" ),
.Boost = {+14, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_ROME,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST("AMD EPYC 7742"),
.Boost = {+12, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_ROME,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST("AMD EPYC 7H12"),
.Boost = {+7, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_ROME,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{0}
};
static PROCESSOR_SPECIFIC AMD_Zen2_CPK_Specific[] = {
/* [Zen2/Castle Peak] 8F_31h Stepping 0 */
{
.Brand = ZLIST("AMD Ryzen Threadripper 3990X"),
.Boost = {+14, +1},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_CASTLE_PEAK,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 1,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST("AMD Ryzen Threadripper 3970X"),
.Boost = {+8, +1},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_CASTLE_PEAK,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 1,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST("AMD Ryzen Threadripper 3960X"),
.Boost = {+7, +1},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_CASTLE_PEAK,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 1,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST("AMD Ryzen Threadripper PRO 3995WX"),
.Boost = {+15, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_CASTLE_PEAK,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK
},
{
.Brand = ZLIST("AMD Ryzen Threadripper PRO 3975WX"),
.Boost = {+7, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_CASTLE_PEAK,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK
},
{
.Brand = ZLIST("AMD Ryzen Threadripper PRO 3955WX"),
.Boost = {+4, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_CASTLE_PEAK,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK
},
{
.Brand = ZLIST("AMD Ryzen Threadripper PRO 3945WX"),
.Boost = {+3, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_CASTLE_PEAK,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK
},
{0}
};
static PROCESSOR_SPECIFIC AMD_Zen2_APU_Specific[] = {
/* [Zen2/Renoir] 8F_60h Stepping 1 */
{
.Brand = ZLIST( "AMD Ryzen 3 4300U", \
"AMD Ryzen 5 4600H" ),
.Boost = {+10, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_RENOIR,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST("AMD Ryzen 3 PRO 4350GE"),
.Boost = {+5, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_RENOIR,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST("AMD Ryzen 3 PRO 4350G"),
.Boost = {+2, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_RENOIR,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST("AMD Ryzen 5 4600GE"),
.Boost = {+9, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_RENOIR,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 1,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST( "AMD Ryzen 3 4300GE", \
"AMD Ryzen 5 4600G" ),
.Boost = {+5, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_RENOIR,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 1,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST("AMD Ryzen 3 4300G"),
.Boost = {+2, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_RENOIR,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 1,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST("AMD Ryzen 5 4500U"),
.Boost = {+17, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_RENOIR,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST("AMD Ryzen 5 PRO 4650GE"),
.Boost = {+9, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_RENOIR,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST("AMD Ryzen 5 PRO 4650G"),
.Boost = {+5, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_RENOIR,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST( "AMD Ryzen 5 PRO 4650U", \
"AMD Ryzen 5 4600U" ),
.Boost = {+19, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_RENOIR,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST("AMD Ryzen 7 4700U"),
.Boost = {+21, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_RENOIR,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST( "AMD Ryzen 7 PRO 4750U", \
"AMD Ryzen 7 4800U" ),
.Boost = {+24, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_RENOIR,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST( "AMD Ryzen 7 4800H", \
"AMD Ryzen 9 4900HS" ),
.Boost = {+13, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_RENOIR,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST( "AMD Ryzen 3 PRO 4450U", \
"AMD Ryzen 7 PRO 4750GE" ),
.Boost = {+12, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_RENOIR,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST("AMD Ryzen 7 4700GE"),
.Boost = {+12, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_RENOIR,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 1,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST("AMD Ryzen 7 PRO 4750G"),
.Boost = {+8, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_RENOIR,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST("AMD Ryzen 7 4700G"),
.Boost = {+8, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_RENOIR,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 1,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST("AMD Ryzen 9 4900U"),
.Boost = {+24, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_RENOIR,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST("AMD Ryzen 9 4900H"),
.Boost = {+11, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_RENOIR,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{0}
};
static PROCESSOR_SPECIFIC AMD_Zen2_MTS_Specific[] = {
/* [Zen2/Matisse] 8F_71h Stepping 0 */
{
.Brand = ZLIST("AMD Ryzen 3 3100"),
.Boost = {+3, +1},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_MATISSE,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 1,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST("AMD Ryzen 5 PRO 3600"),
.Boost = {+6, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_MATISSE,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST("AMD Ryzen 5 3600XT"),
.Boost = {+6, +1},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_MATISSE,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 1,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST( "AMD Ryzen 5 3600X", \
"AMD Ryzen 5 3600" ),
.Boost = {+5, +1},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_MATISSE,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 1,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST("AMD Ryzen 7 PRO 3700"),
.Boost = {+8, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_MATISSE,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST("AMD Ryzen 7 3800XT"),
.Boost = {+7, +1},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_MATISSE,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 1,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST( "AMD Ryzen 3 3300X", \
"AMD Ryzen 5 3500X", \
"AMD Ryzen 7 3800X" ),
.Boost = {+5, +1},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_MATISSE,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 1,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST("AMD Ryzen 9 PRO 3900"),
.Boost = {+12, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_MATISSE,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 0,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST("AMD Ryzen 9 3900XT"),
.Boost = {+8, +1},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_MATISSE,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 1,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST( "AMD Ryzen 7 3700X", \
"AMD Ryzen 9 3900X" ),
.Boost = {+7, +1},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_MATISSE,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 1,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
.Brand = ZLIST("AMD Ryzen 9 3950X"),
.Boost = {+11, +1},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_MATISSE,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 1,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{0}
};
static PROCESSOR_SPECIFIC Misc_Specific_Processor[] = {
{
.Brand = ZLIST("AMD EPYC Processor"), /* QEMU virtualized EPYC */
.Boost = {+1, +1}, /* Add one multiplier to each ratio 1C, 2C */
.Param.Offset = {0, 0, 0},
.CodeNameIdx = 1,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 1,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{0}
};
#ifdef CONFIG_CPU_FREQ
#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 19)
#define CPUFREQ_POLICY_UNKNOWN (0)
#endif
static int CoreFreqK_Policy_Exit(struct cpufreq_policy*) ;
static int CoreFreqK_Policy_Init(struct cpufreq_policy*) ;
#if ((LINUX_VERSION_CODE >= KERNEL_VERSION(5, 4, 19)) \
&& (LINUX_VERSION_CODE <= KERNEL_VERSION(5, 5, 0))) \
|| (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 5, 3))
static int CoreFreqK_Policy_Verify(struct cpufreq_policy_data*) ;
#else
static int CoreFreqK_Policy_Verify(struct cpufreq_policy*) ;
#endif
static int CoreFreqK_SetPolicy(struct cpufreq_policy*) ;
static int CoreFreqK_Bios_Limit(int, unsigned int*) ;
#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 8, 0)
static int CoreFreqK_SetBoost(struct cpufreq_policy*, int) ;
#else
static int CoreFreqK_SetBoost(int) ;
#endif
static ssize_t CoreFreqK_Show_SetSpeed(struct cpufreq_policy*, char*);
static int CoreFreqK_Store_SetSpeed(struct cpufreq_policy*, unsigned int) ;
#endif /* CONFIG_CPU_FREQ */
static unsigned int Policy_GetFreq(unsigned int cpu) ;
static void Policy_Core2_SetTarget(void *arg) ;
static void Policy_Nehalem_SetTarget(void *arg) ;
static void Policy_SandyBridge_SetTarget(void *arg) ;
static void Policy_HWP_SetTarget(void *arg) ;
#define Policy_Broadwell_EP_SetTarget Policy_HWP_SetTarget
#define Policy_Skylake_SetTarget Policy_HWP_SetTarget
static void Policy_Zen_SetTarget(void *arg) ;
#define VOID_Driver { \
.IdleState = NULL, \
.GetFreq = NULL, \
.SetTarget = NULL \
}
#define CORE2_Driver { \
.IdleState = NULL, \
.GetFreq = Policy_GetFreq, \
.SetTarget = Policy_Core2_SetTarget \
}
static IDLE_STATE SLM_IdleState[] = {
{
.Name = "C1",
.Desc = "SLM-C1",
.flags = 0x00 << 24,
.Latency = 1,
.Residency = 1
},
{
.Name = "C6N",
.Desc = "SLM-C6N",
.flags = (0x58 << 24) | CPUIDLE_FLAG_TLB_FLUSHED,
.Latency = 300,
.Residency = 275
},
{
.Name = "C6S",
.Desc = "SLM-C6S",
.flags = (0x52 << 24) | CPUIDLE_FLAG_TLB_FLUSHED,
.Latency = 500,
.Residency = 560
},
{
.Name = "C7",
.Desc = "SLM-C7",
.flags = (0x60 << 24) | CPUIDLE_FLAG_TLB_FLUSHED,
.Latency = 1200,
.Residency = 4000
},
{
.Name = "C7S",
.Desc = "SLM-C7S",
.flags = (0x64 << 24) | CPUIDLE_FLAG_TLB_FLUSHED,
.Latency = 10000,
.Residency = 20000
},
{NULL}
};
#define SLM_Driver { \
.IdleState = SLM_IdleState, \
.GetFreq = Policy_GetFreq, \
.SetTarget = Policy_Core2_SetTarget \
}
/* Source: /drivers/idle/intel_idle.c */
static IDLE_STATE NHM_IdleState[] = {
{
.Name = "C1",
.Desc = "NHM-C1",
.flags = 0x00 << 24,
.Latency = 3,
.Residency = 6
},
{
.Name = "C1E",
.Desc = "NHM-C1E",
.flags = 0x01 << 24,
.Latency = 10,
.Residency = 20
},
{
.Name = "C3",
.Desc = "NHM-C3",
.flags = (0x10 << 24) | CPUIDLE_FLAG_TLB_FLUSHED,
.Latency = 20,
.Residency = 80
},
{
.Name = "C6",
.Desc = "NHM-C6",
.flags = (0x20 << 24) | CPUIDLE_FLAG_TLB_FLUSHED,
.Latency = 200,
.Residency = 800
},
{NULL}
};
#define NHM_Driver { \
.IdleState = NHM_IdleState, \
.GetFreq = Policy_GetFreq, \
.SetTarget = Policy_Nehalem_SetTarget \
}
static IDLE_STATE SNB_IdleState[] = {
{
.Name = "C1",
.Desc = "SNB-C1",
.flags = 0x00 << 24,
.Latency = 2,
.Residency = 2
},
{
.Name = "C1E",
.Desc = "SNB-C1E",
.flags = 0x01 << 24,
.Latency = 10,
.Residency = 20
},
{
.Name = "C3",
.Desc = "SNB-C3",
.flags = (0x10 << 24) | CPUIDLE_FLAG_TLB_FLUSHED,
.Latency = 80,
.Residency = 211
},
{
.Name = "C6",
.Desc = "SNB-C6",
.flags = (0x20 << 24) | CPUIDLE_FLAG_TLB_FLUSHED,
.Latency = 104,
.Residency = 345
},
{
.Name = "C7",
.Desc = "SNB-C7",
.flags = (0x30 << 24) | CPUIDLE_FLAG_TLB_FLUSHED,
.Latency = 109,
.Residency = 345
},
{NULL}
};
#define SNB_Driver { \
.IdleState = SNB_IdleState, \
.GetFreq = Policy_GetFreq, \
.SetTarget = Policy_SandyBridge_SetTarget \
}
static IDLE_STATE IVB_IdleState[] = {
{
.Name = "C1",
.Desc = "IVB-C1",
.flags = 0x00 << 24,
.Latency = 1,
.Residency = 1
},
{
.Name = "C1E",
.Desc = "IVB-C1E",
.flags = 0x01 << 24,
.Latency = 10,
.Residency = 20
},
{
.Name = "C3",
.Desc = "IVB-C3",
.flags = (0x10 << 24) | CPUIDLE_FLAG_TLB_FLUSHED,
.Latency = 59,
.Residency = 156
},
{
.Name = "C6",
.Desc = "IVB-C6",
.flags = (0x20 << 24) | CPUIDLE_FLAG_TLB_FLUSHED,
.Latency = 80,
.Residency = 300
},
{
.Name = "C7",
.Desc = "IVB-C7",
.flags = (0x30 << 24) | CPUIDLE_FLAG_TLB_FLUSHED,
.Latency = 87,
.Residency = 300
},
{NULL}
};
#define IVB_Driver { \
.IdleState = IVB_IdleState, \
.GetFreq = Policy_GetFreq, \
.SetTarget = Policy_SandyBridge_SetTarget \
}
static IDLE_STATE HSW_IdleState[] = {
{
.Name = "C1",
.Desc = "HSW-C1",
.flags = 0x00 << 24,
.Latency = 2,
.Residency = 2
},
{
.Name = "C1E",
.Desc = "HSW-C1E",
.flags = 0x01 << 24,
.Latency = 10,
.Residency = 20
},
{
.Name = "C3",
.Desc = "HSW-C3",
.flags = (0x10 << 24) | CPUIDLE_FLAG_TLB_FLUSHED,
.Latency = 33,
.Residency = 100
},
{
.Name = "C6",
.Desc = "HSW-C6",
.flags = (0x20 << 24) | CPUIDLE_FLAG_TLB_FLUSHED,
.Latency = 133,
.Residency = 400
},
{
.Name = "C7",
.Desc = "HSW-C7",
.flags = (0x32 << 24) | CPUIDLE_FLAG_TLB_FLUSHED,
.Latency = 166,
.Residency = 500
},
{
.Name = "C8",
.Desc = "HSW-C8",
.flags = (0x40 << 24) | CPUIDLE_FLAG_TLB_FLUSHED,
.Latency = 300,
.Residency = 900
},
{
.Name = "C9",
.Desc = "HSW-C9",
.flags = (0x50 << 24) | CPUIDLE_FLAG_TLB_FLUSHED,
.Latency = 600,
.Residency = 1800
},
{
.Name = "C10",
.Desc = "HSW-C10",
.flags = (0x60 << 24) | CPUIDLE_FLAG_TLB_FLUSHED,
.Latency = 2600,
.Residency = 7700
},
{NULL}
};
#define HSW_Driver { \
.IdleState = HSW_IdleState, \
.GetFreq = Policy_GetFreq, \
.SetTarget = Policy_SandyBridge_SetTarget \
}
static IDLE_STATE BDW_IdleState[] = {
{
.Name = "C1",
.Desc = "BDW-C1",
.flags = 0x00 << 24,
.Latency = 2,
.Residency = 2
},
{
.Name = "C1E",
.Desc = "BDW-C1E",
.flags = 0x01 << 24,
.Latency = 10,
.Residency = 20
},
{
.Name = "C3",
.Desc = "BDW-C3",
.flags = (0x10 << 24) | CPUIDLE_FLAG_TLB_FLUSHED,
.Latency = 40,
.Residency = 100
},
{
.Name = "C6",
.Desc = "BDW-C6",
.flags = (0x20 << 24) | CPUIDLE_FLAG_TLB_FLUSHED,
.Latency = 133,
.Residency = 400
},
{
.Name = "C7",
.Desc = "BDW-C7",
.flags = (0x32 << 24) | CPUIDLE_FLAG_TLB_FLUSHED,
.Latency = 166,
.Residency = 500
},
{
.Name = "C8",
.Desc = "BDW-C8",
.flags = (0x40 << 24) | CPUIDLE_FLAG_TLB_FLUSHED,
.Latency = 300,
.Residency = 900
},
{
.Name = "C9",
.Desc = "BDW-C9",
.flags = (0x50 << 24) | CPUIDLE_FLAG_TLB_FLUSHED,
.Latency = 600,
.Residency = 1800
},
{
.Name = "C10",
.Desc = "BDW-C10",
.flags = (0x60 << 24) | CPUIDLE_FLAG_TLB_FLUSHED,
.Latency = 2600,
.Residency = 7700
},
{NULL}
};
#define BDW_Driver { \
.IdleState = BDW_IdleState, \
.GetFreq = Policy_GetFreq, \
.SetTarget = Policy_SandyBridge_SetTarget \
}
#define BDW_EP_Driver { \
.IdleState = BDW_IdleState, \
.GetFreq = Policy_GetFreq, \
.SetTarget = Policy_Broadwell_EP_SetTarget \
}
static IDLE_STATE SKL_IdleState[] = {
{
.Name = "C1",
.Desc = "SKL-C1",
.flags = 0x00 << 24,
.Latency = 2,
.Residency = 2
},
{
.Name = "C1E",
.Desc = "SKL-C1E",
.flags = 0x01 << 24,
.Latency = 10,
.Residency = 20
},
{
.Name = "C3",
.Desc = "SKL-C3",
.flags = (0x10 << 24) | CPUIDLE_FLAG_TLB_FLUSHED,
.Latency = 70,
.Residency = 100
},
{
.Name = "C6",
.Desc = "SKL-C6",
.flags = (0x20 << 24) | CPUIDLE_FLAG_TLB_FLUSHED,
.Latency = 85,
.Residency = 200
},
{
.Name = "C7",
.Desc = "SKL-C7",
.flags = (0x33 << 24) | CPUIDLE_FLAG_TLB_FLUSHED,
.Latency = 124,
.Residency = 800
},
{
.Name = "C8",
.Desc = "SKL-C8",
.flags = (0x40 << 24) | CPUIDLE_FLAG_TLB_FLUSHED,
.Latency = 200,
.Residency = 800
},
{
.Name = "C9",
.Desc = "SKL-C9",
.flags = (0x50 << 24) | CPUIDLE_FLAG_TLB_FLUSHED,
.Latency = 480,
.Residency = 5000
},
{
.Name = "C10",
.Desc = "SKL-C10",
.flags = (0x60 << 24) | CPUIDLE_FLAG_TLB_FLUSHED,
.Latency = 890,
.Residency = 5000
},
{NULL}
};
#define SKL_Driver { \
.IdleState = SKL_IdleState, \
.GetFreq = Policy_GetFreq, \
.SetTarget = Policy_Skylake_SetTarget \
}
static IDLE_STATE SKX_IdleState[] = {
{
.Name = "C1",
.Desc = "SKX-C1",
.flags = 0x00 << 24,
.Latency = 2,
.Residency = 2
},
{
.Name = "C1E",
.Desc = "SKX-C1E",
.flags = 0x01 << 24,
.Latency = 10,
.Residency = 20
},
{
.Name = "C6",
.Desc = "SKX-C6",
.flags = (0x20 << 24) | CPUIDLE_FLAG_TLB_FLUSHED,
.Latency = 133,
.Residency = 600
},
{NULL}
};
#define SKX_Driver { \
.IdleState = SKX_IdleState, \
.GetFreq = Policy_GetFreq, \
.SetTarget = Policy_Skylake_SetTarget \
}
#define Intel_Driver { \
.IdleState = NULL, \
.GetFreq = Policy_GetFreq, \
.SetTarget = Policy_Skylake_SetTarget \
}
static IDLE_STATE Zen_IdleState[] = {
{
.Name = "C1",
.Desc = "ZEN-C1",
.flags = 0x00 << 24,
.Latency = 1,
.Residency = 1 * 2
},
{
.Name = "C2",
.Desc = "ZEN-C2",
.flags = 0x10 << 24,
.Latency = 20,
.Residency = 20 * 2
},
{
.Name = "C3",
.Desc = "ZEN-C3",
.flags = 0x20 << 24,
.Latency = 40,
.Residency = 40 * 2
},
{
.Name = "C4",
.Desc = "ZEN-C4",
.flags = 0x30 << 24,
.Latency = 60,
.Residency = 60 * 2
},
{
.Name = "C5",
.Desc = "ZEN-C5",
.flags = 0x40 << 24,
.Latency = 80,
.Residency = 80 * 2
},
{
.Name = "C6",
.Desc = "ZEN-C6",
.flags = 0x50 << 24,
.Latency = 100,
.Residency = 100 * 2
},
{NULL}
};
#define AMD_Zen_Driver { \
.IdleState = Zen_IdleState, \
.GetFreq = Policy_GetFreq, \
.SetTarget = Policy_Zen_SetTarget \
}
static ARCH Arch[ARCHITECTURES] = {
[GenuineArch] = { /* 0*/
.Signature = _Void_Signature,
.Query = NULL,
.Update = NULL,
.Start = NULL,
.Stop = NULL,
.Exit = NULL,
.Timer = NULL,
.BaseClock = NULL,
.ClockMod = NULL,
.TurboClock = NULL,
.thermalFormula = THERMAL_FORMULA_NONE,
.voltageFormula = VOLTAGE_FORMULA_NONE,
.powerFormula = POWER_FORMULA_NONE,
.PCI_ids = PCI_Void_ids,
.Uncore = {
.Start = NULL,
.Stop = NULL,
.ClockMod = NULL
},
.Specific = Misc_Specific_Processor,
.SystemDriver = VOID_Driver,
.Architecture = Arch_Misc_Processor
},
[AMD_Family_0Fh] = { /* 1*/
.Signature = _AMD_Family_0Fh,
.Query = Query_AMD_Family_0Fh,
.Update = PerCore_AMD_Family_0Fh_Query,
.Start = Start_AMD_Family_0Fh,
.Stop = Stop_AMD_Family_0Fh,
.Exit = NULL,
.Timer = InitTimer_AMD_Family_0Fh,
.BaseClock = BaseClock_AuthenticAMD,
.ClockMod = NULL,
.TurboClock = NULL,
.thermalFormula = THERMAL_FORMULA_AMD_0Fh,
.voltageFormula = VOLTAGE_FORMULA_AMD_0Fh,
.powerFormula = POWER_FORMULA_AMD,
.PCI_ids = PCI_AMD_0Fh_ids,
.Uncore = {
.Start = NULL,
.Stop = NULL,
.ClockMod = NULL
},
.Specific = Void_Specific,
.SystemDriver = VOID_Driver,
.Architecture = Arch_AMD_Family_0Fh
},
[AMD_Family_10h] = { /* 2*/
.Signature = _AMD_Family_10h,
.Query = Query_AMD_Family_10h,
.Update = PerCore_AMD_Family_10h_Query,
.Start = Start_AMD_Family_10h,
.Stop = Stop_AMD_Family_10h,
.Exit = NULL,
.Timer = InitTimer_AMD_Family_10h,
.BaseClock = BaseClock_AuthenticAMD,
.ClockMod = NULL,
.TurboClock = NULL,
.thermalFormula = THERMAL_FORMULA_AMD,
.voltageFormula = VOLTAGE_FORMULA_AMD,
.powerFormula = POWER_FORMULA_AMD,
.PCI_ids = PCI_Void_ids,
.Uncore = {
.Start = NULL,
.Stop = NULL,
.ClockMod = NULL
},
.Specific = Void_Specific,
.SystemDriver = VOID_Driver,
.Architecture = Arch_AMD_Family_10h
},
[AMD_Family_11h] = { /* 3*/
.Signature = _AMD_Family_11h,
.Query = Query_AMD_Family_11h,
.Update = PerCore_AMD_Family_11h_Query,
.Start = Start_AMD_Family_11h,
.Stop = Stop_AMD_Family_11h,
.Exit = NULL,
.Timer = InitTimer_AMD_Family_11h,
.BaseClock = BaseClock_AuthenticAMD,
.ClockMod = NULL,
.TurboClock = NULL,
.thermalFormula = THERMAL_FORMULA_AMD,
.voltageFormula = VOLTAGE_FORMULA_AMD,
.powerFormula = POWER_FORMULA_AMD,
.PCI_ids = PCI_Void_ids,
.Uncore = {
.Start = NULL,
.Stop = NULL,
.ClockMod = NULL
},
.Specific = Void_Specific,
.SystemDriver = VOID_Driver,
.Architecture = Arch_AMD_Family_11h
},
[AMD_Family_12h] = { /* 4*/
.Signature = _AMD_Family_12h,
.Query = Query_AMD_Family_12h,
.Update = PerCore_AMD_Family_12h_Query,
.Start = Start_AMD_Family_12h,
.Stop = Stop_AMD_Family_12h,
.Exit = NULL,
.Timer = InitTimer_AMD_Family_12h,
.BaseClock = BaseClock_AuthenticAMD,
.ClockMod = NULL,
.TurboClock = NULL,
.thermalFormula = THERMAL_FORMULA_AMD,
.voltageFormula = VOLTAGE_FORMULA_AMD,
.powerFormula = POWER_FORMULA_AMD,
.PCI_ids = PCI_Void_ids,
.Uncore = {
.Start = NULL,
.Stop = NULL,
.ClockMod = NULL
},
.Specific = Void_Specific,
.SystemDriver = VOID_Driver,
.Architecture = Arch_AMD_Family_12h
},
[AMD_Family_14h] = { /* 5*/
.Signature = _AMD_Family_14h,
.Query = Query_AMD_Family_14h,
.Update = PerCore_AMD_Family_14h_Query,
.Start = Start_AMD_Family_14h,
.Stop = Stop_AMD_Family_14h,
.Exit = NULL,
.Timer = InitTimer_AMD_Family_14h,
.BaseClock = BaseClock_AuthenticAMD,
.ClockMod = NULL,
.TurboClock = NULL,
.thermalFormula = THERMAL_FORMULA_AMD,
.voltageFormula = VOLTAGE_FORMULA_AMD,
.powerFormula = POWER_FORMULA_AMD,
.PCI_ids = PCI_Void_ids,
.Uncore = {
.Start = NULL,
.Stop = NULL,
.ClockMod = NULL
},
.Specific = Void_Specific,
.SystemDriver = VOID_Driver,
.Architecture = Arch_AMD_Family_14h
},
[AMD_Family_15h] = { /* 6*/
.Signature = _AMD_Family_15h,
.Query = Query_AMD_Family_15h,
.Update = PerCore_AMD_Family_15h_Query,
.Start = Start_AMD_Family_15h,
.Stop = Stop_AMD_Family_15h,
.Exit = NULL,
.Timer = InitTimer_AMD_Family_15h,
.BaseClock = BaseClock_AuthenticAMD,
.ClockMod = NULL,
.TurboClock = NULL,
.thermalFormula = THERMAL_FORMULA_AMD_15h,
.voltageFormula = VOLTAGE_FORMULA_AMD_15h,
.powerFormula = POWER_FORMULA_AMD,
.PCI_ids = PCI_Void_ids,
.Uncore = {
.Start = NULL,
.Stop = NULL,
.ClockMod = NULL
},
.Specific = Void_Specific,
.SystemDriver = VOID_Driver,
.Architecture = Arch_AMD_Family_15h
},
[AMD_Family_16h] = { /* 7*/
.Signature = _AMD_Family_16h,
.Query = Query_AMD_Family_16h,
.Update = PerCore_AMD_Family_16h_Query,
.Start = Start_AMD_Family_16h,
.Stop = Stop_AMD_Family_16h,
.Exit = NULL,
.Timer = InitTimer_AMD_Family_16h,
.BaseClock = BaseClock_AuthenticAMD,
.ClockMod = NULL,
.TurboClock = NULL,
.thermalFormula = THERMAL_FORMULA_AMD,
.voltageFormula = VOLTAGE_FORMULA_AMD,
.powerFormula = POWER_FORMULA_AMD,
.PCI_ids = PCI_Void_ids,
.Uncore = {
.Start = NULL,
.Stop = NULL,
.ClockMod = NULL
},
.Specific = Void_Specific,
.SystemDriver = VOID_Driver,
.Architecture = Arch_AMD_Family_16h
},
[AMD_Family_17h] = { /* 8*/
.Signature = _AMD_Family_17h,
.Query = Query_AMD_Family_17h,
.Update = PerCore_AMD_Family_17h_Query,
.Start = Start_AMD_Family_17h,
.Stop = Stop_AMD_Family_17h,
.Exit = NULL,
.Timer = InitTimer_AMD_Family_17h,
.BaseClock = BaseClock_AMD_Family_17h,
.ClockMod = ClockMod_AMD_Zen,
.TurboClock = TurboClock_AMD_Zen,
.thermalFormula = THERMAL_FORMULA_AMD_17h,
.voltageFormula = VOLTAGE_FORMULA_AMD_17h,
.powerFormula = POWER_FORMULA_AMD_17h,
.PCI_ids = PCI_AMD_17h_ids,
.Uncore = {
.Start = NULL,
.Stop = NULL,
.ClockMod = NULL
},
.Specific = Void_Specific,
.SystemDriver = VOID_Driver,
.Architecture = Arch_AMD_Family_17h
},
[AMD_Family_18h] = { /* 9*/
.Signature = _AMD_Family_18h,
.Query = Query_AMD_Family_17h,
.Update = PerCore_AMD_Family_17h_Query,
.Start = Start_AMD_Family_17h,
.Stop = Stop_AMD_Family_17h,
.Exit = NULL,
.Timer = InitTimer_AMD_Family_17h,
.BaseClock = BaseClock_AMD_Family_17h,
.ClockMod = ClockMod_AMD_Zen,
.TurboClock = TurboClock_AMD_Zen,
.thermalFormula = THERMAL_FORMULA_AMD_17h,
.voltageFormula = VOLTAGE_FORMULA_AMD_17h,
.powerFormula = POWER_FORMULA_AMD_17h,
.PCI_ids = PCI_Void_ids,
.Uncore = {
.Start = NULL,
.Stop = NULL,
.ClockMod = NULL
},
.Specific = Void_Specific,
.SystemDriver = VOID_Driver,
.Architecture = Arch_AMD_Family_18h
},
[AMD_Family_19h] = { /* 10*/
.Signature = _AMD_Family_19h,
.Query = Query_AMD_Family_19h,
.Update = PerCore_AMD_Family_19h_Query,
.Start = Start_AMD_Family_19h,
.Stop = Stop_AMD_Family_19h,
.Exit = NULL,
.Timer = InitTimer_AMD_Family_19h,
.BaseClock = BaseClock_AMD_Family_19h,
.ClockMod = ClockMod_AMD_Zen,
.TurboClock = TurboClock_AMD_Zen,
.thermalFormula = THERMAL_FORMULA_AMD_19h,
.voltageFormula = VOLTAGE_FORMULA_AMD_19h,
.powerFormula = POWER_FORMULA_AMD_19h,
.PCI_ids = PCI_AMD_19h_ids,
.Uncore = {
.Start = NULL,
.Stop = NULL,
.ClockMod = NULL
},
.Specific = Void_Specific,
.SystemDriver = VOID_Driver,
.Architecture = Arch_AMD_Family_19h
},
[Core_Yonah] = { /* 11*/
.Signature = _Core_Yonah,
.Query = Query_GenuineIntel,
.Update = PerCore_Intel_Query,
.Start = Start_GenuineIntel,
.Stop = Stop_GenuineIntel,
.Exit = NULL,
.Timer = InitTimer_GenuineIntel,
.BaseClock = BaseClock_Core,
.ClockMod = NULL,
.TurboClock = NULL,
.thermalFormula = THERMAL_FORMULA_INTEL,
.voltageFormula = VOLTAGE_FORMULA_NONE,
.powerFormula = POWER_FORMULA_NONE,
.PCI_ids = PCI_Core2_ids,
.Uncore = {
.Start = NULL,
.Stop = NULL,
.ClockMod = NULL
},
.Specific = Void_Specific,
.SystemDriver = VOID_Driver,
.Architecture = Arch_Core_Yonah
},
[Core_Conroe] = { /* 12*/
.Signature = _Core_Conroe,
.Query = Query_Core2,
.Update = PerCore_Core2_Query,
.Start = Start_Core2,
.Stop = Stop_Core2,
.Exit = NULL,
.Timer = InitTimer_Core2,
.BaseClock = BaseClock_Core2,
.ClockMod = ClockMod_Core2_PPC,
.TurboClock = NULL,
.thermalFormula = THERMAL_FORMULA_INTEL,
.voltageFormula = VOLTAGE_FORMULA_INTEL_CORE2,
.powerFormula = POWER_FORMULA_NONE,
.PCI_ids = PCI_Core2_ids,
.Uncore = {
.Start = NULL,
.Stop = NULL,
.ClockMod = NULL
},
.Specific = Void_Specific,
.SystemDriver = CORE2_Driver,
.Architecture = Arch_Core_Conroe
},
[Core_Kentsfield] = { /* 13*/
.Signature = _Core_Kentsfield,
.Query = Query_Core2,
.Update = PerCore_Core2_Query,
.Start = Start_Core2,
.Stop = Stop_Core2,
.Exit = NULL,
.Timer = InitTimer_Core2,
.BaseClock = BaseClock_Core2,
.ClockMod = ClockMod_Core2_PPC,
.TurboClock = NULL,
.thermalFormula = THERMAL_FORMULA_INTEL,
.voltageFormula = VOLTAGE_FORMULA_NONE,
.powerFormula = POWER_FORMULA_NONE,
.PCI_ids = PCI_Core2_ids,
.Uncore = {
.Start = NULL,
.Stop = NULL,
.ClockMod = NULL
},
.Specific = Void_Specific,
.SystemDriver = CORE2_Driver,
.Architecture = Arch_Core_Kentsfield
},
[Core_Conroe_616] = { /* 14*/
.Signature = _Core_Conroe_616,
.Query = Query_Core2,
.Update = PerCore_Core2_Query,
.Start = Start_Core2,
.Stop = Stop_Core2,
.Exit = NULL,
.Timer = InitTimer_Core2,
.BaseClock = BaseClock_Core2,
.ClockMod = ClockMod_Core2_PPC,
.TurboClock = NULL,
.thermalFormula = THERMAL_FORMULA_INTEL,
.voltageFormula = VOLTAGE_FORMULA_NONE,
.powerFormula = POWER_FORMULA_NONE,
.PCI_ids = PCI_Core2_ids,
.Uncore = {
.Start = NULL,
.Stop = NULL,
.ClockMod = NULL
},
.Specific = Void_Specific,
.SystemDriver = CORE2_Driver,
.Architecture = Arch_Core_Conroe_616
},
[Core_Penryn] = { /* 15*/
.Signature = _Core_Penryn,
.Query = Query_Core2,
.Update = PerCore_Core2_Query,
.Start = Start_Core2,
.Stop = Stop_Core2,
.Exit = NULL,
.Timer = InitTimer_Core2,
.BaseClock = BaseClock_Core2,
.ClockMod = ClockMod_Core2_PPC,
.TurboClock = NULL,
.thermalFormula = THERMAL_FORMULA_INTEL,
.voltageFormula = VOLTAGE_FORMULA_NONE,
.powerFormula = POWER_FORMULA_NONE,
.PCI_ids = PCI_Core2_ids,
.Uncore = {
.Start = NULL,
.Stop = NULL,
.ClockMod = NULL
},
.Specific = Core_Penryn_Specific,
.SystemDriver = CORE2_Driver,
.Architecture = Arch_Core_Penryn
},
[Core_Dunnington] = { /* 16*/
.Signature = _Core_Dunnington,
.Query = Query_Core2,
.Update = PerCore_Core2_Query,
.Start = Start_Core2,
.Stop = Stop_Core2,
.Exit = NULL,
.Timer = InitTimer_Core2,
.BaseClock = BaseClock_Core2,
.ClockMod = ClockMod_Core2_PPC,
.TurboClock = NULL,
.thermalFormula = THERMAL_FORMULA_INTEL,
.voltageFormula = VOLTAGE_FORMULA_NONE,
.powerFormula = POWER_FORMULA_NONE,
.PCI_ids = PCI_Core2_ids,
.Uncore = {
.Start = NULL,
.Stop = NULL,
.ClockMod = NULL
},
.Specific = Void_Specific,
.SystemDriver = CORE2_Driver,
.Architecture = Arch_Core_Dunnington
},
[Atom_Bonnell] = { /* 17*/
.Signature = _Atom_Bonnell,
.Query = Query_Core2,
.Update = PerCore_Core2_Query,
.Start = Start_Core2,
.Stop = Stop_Core2,
.Exit = NULL,
.Timer = InitTimer_Core2,
.BaseClock = BaseClock_Atom,
.ClockMod = ClockMod_Core2_PPC,
.TurboClock = NULL,
.thermalFormula = THERMAL_FORMULA_INTEL,
.voltageFormula = VOLTAGE_FORMULA_NONE,
.powerFormula = POWER_FORMULA_NONE,
.PCI_ids = PCI_Void_ids,
.Uncore = {
.Start = NULL,
.Stop = NULL,
.ClockMod = NULL
},
.Specific = Void_Specific,
.SystemDriver = CORE2_Driver,
.Architecture = Arch_Atom_Bonnell
},
[Atom_Silvermont] = { /* 18*/
.Signature = _Atom_Silvermont,
.Query = Query_Core2,
.Update = PerCore_Core2_Query,
.Start = Start_Core2,
.Stop = Stop_Core2,
.Exit = NULL,
.Timer = InitTimer_Core2,
.BaseClock = BaseClock_Atom,
.ClockMod = ClockMod_Core2_PPC,
.TurboClock = NULL,
.thermalFormula = THERMAL_FORMULA_INTEL,
.voltageFormula = VOLTAGE_FORMULA_NONE,
.powerFormula = POWER_FORMULA_NONE,
.PCI_ids = PCI_Void_ids,
.Uncore = {
.Start = NULL,
.Stop = NULL,
.ClockMod = NULL
},
.Specific = Void_Specific,
.SystemDriver = CORE2_Driver,
.Architecture = Arch_Atom_Silvermont
},
[Atom_Lincroft] = { /* 19*/
.Signature = _Atom_Lincroft,
.Query = Query_Core2,
.Update = PerCore_Core2_Query,
.Start = Start_Core2,
.Stop = Stop_Core2,
.Exit = NULL,
.Timer = InitTimer_Core2,
.BaseClock = BaseClock_Atom,
.ClockMod = ClockMod_Core2_PPC,
.TurboClock = NULL,
.thermalFormula = THERMAL_FORMULA_INTEL,
.voltageFormula = VOLTAGE_FORMULA_NONE,
.powerFormula = POWER_FORMULA_NONE,
.PCI_ids = PCI_Void_ids,
.Uncore = {
.Start = NULL,
.Stop = NULL,
.ClockMod = NULL
},
.Specific = Void_Specific,
.SystemDriver = CORE2_Driver,
.Architecture = Arch_Atom_Lincroft
},
[Atom_Clover_Trail] = { /* 20*/
.Signature = _Atom_Clover_Trail,
.Query = Query_Core2,
.Update = PerCore_Core2_Query,
.Start = Start_Core2,
.Stop = Stop_Core2,
.Exit = NULL,
.Timer = InitTimer_Core2,
.BaseClock = BaseClock_Atom,
.ClockMod = ClockMod_Core2_PPC,
.TurboClock = NULL,
.thermalFormula = THERMAL_FORMULA_INTEL,
.voltageFormula = VOLTAGE_FORMULA_NONE,
.powerFormula = POWER_FORMULA_NONE,
.PCI_ids = PCI_Void_ids,
.Uncore = {
.Start = NULL,
.Stop = NULL,
.ClockMod = NULL
},
.Specific = Void_Specific,
.SystemDriver = CORE2_Driver,
.Architecture = Arch_Atom_Clover_Trail
},
[Atom_Saltwell] = { /* 21*/
.Signature = _Atom_Saltwell,
.Query = Query_Core2,
.Update = PerCore_Core2_Query,
.Start = Start_Core2,
.Stop = Stop_Core2,
.Exit = NULL,
.Timer = InitTimer_Core2,
.BaseClock = BaseClock_Atom,
.ClockMod = ClockMod_Core2_PPC,
.TurboClock = NULL,
.thermalFormula = THERMAL_FORMULA_INTEL,
.voltageFormula = VOLTAGE_FORMULA_NONE,
.powerFormula = POWER_FORMULA_NONE,
.PCI_ids = PCI_Void_ids,
.Uncore = {
.Start = NULL,
.Stop = NULL,
.ClockMod = NULL
},
.Specific = Void_Specific,
.SystemDriver = CORE2_Driver,
.Architecture = Arch_Atom_Saltwell
},
[Silvermont_Bay_Trail] = { /* 22*/
.Signature = _Silvermont_Bay_Trail,
.Query = Query_Silvermont,
.Update = PerCore_Silvermont_Query,
.Start = Start_Silvermont,
.Stop = Stop_Silvermont,
.Exit = NULL,
.Timer = InitTimer_Silvermont,
.BaseClock = BaseClock_Silvermont,
.ClockMod = ClockMod_Core2_PPC,
.TurboClock = Intel_Turbo_Config8C,
.thermalFormula = THERMAL_FORMULA_INTEL,
.voltageFormula = VOLTAGE_FORMULA_INTEL_SOC,
.powerFormula = POWER_FORMULA_INTEL_ATOM,
.PCI_ids = PCI_SoC_ids,
.Uncore = {
.Start = NULL,
.Stop = NULL,
.ClockMod = NULL
},
.Specific = Silvermont_Bay_Trail_Specific,
.SystemDriver = SLM_Driver,
.Architecture = Arch_Silvermont_Bay_Trail
},
[Atom_Avoton] = { /* 23*/
.Signature = _Atom_Avoton,
.Query = Query_Avoton,
.Update = PerCore_Avoton_Query,
.Start = Start_Nehalem,
.Stop = Stop_Nehalem,
.Exit = NULL,
.Timer = InitTimer_Nehalem,
.BaseClock = BaseClock_Silvermont,
.ClockMod = ClockMod_Nehalem_PPC,
.TurboClock = Intel_Turbo_Config8C,
.thermalFormula = THERMAL_FORMULA_INTEL,
.voltageFormula = VOLTAGE_FORMULA_NONE,
.powerFormula = POWER_FORMULA_INTEL_ATOM,
.PCI_ids = PCI_Void_ids,
.Uncore = {
.Start = Start_Uncore_Nehalem,
.Stop = Stop_Uncore_Nehalem,
.ClockMod = NULL
},
.Specific = Void_Specific,
.SystemDriver = VOID_Driver,
.Architecture = Arch_Atom_Avoton
},
[Atom_Airmont] = { /* 24*/
.Signature = _Atom_Airmont,
.Query = Query_Airmont,
.Update = PerCore_Airmont_Query,
.Start = Start_Silvermont,
.Stop = Stop_Silvermont,
.Exit = NULL,
.Timer = InitTimer_Silvermont,
.BaseClock = BaseClock_Airmont,
.ClockMod = ClockMod_Core2_PPC,
.TurboClock = Intel_Turbo_Config8C,
.thermalFormula = THERMAL_FORMULA_INTEL,
.voltageFormula = VOLTAGE_FORMULA_INTEL_SOC,
.powerFormula = POWER_FORMULA_INTEL_ATOM,
.PCI_ids = PCI_Void_ids,
.Uncore = {
.Start = NULL,
.Stop = NULL,
.ClockMod = NULL
},
.Specific = Void_Specific,
.SystemDriver = CORE2_Driver,
.Architecture = Arch_Atom_Airmont
},
[Atom_Goldmont] = { /* 25*/
.Signature = _Atom_Goldmont,
.Query = Query_Goldmont,
.Update = PerCore_Goldmont_Query,
.Start = Start_Goldmont,
.Stop = Stop_Goldmont,
.Exit = NULL,
.Timer = InitTimer_Goldmont,
.BaseClock = BaseClock_Haswell,
.ClockMod = ClockMod_SandyBridge_PPC,
.TurboClock = Intel_Turbo_Config8C,
.thermalFormula = THERMAL_FORMULA_INTEL,
.voltageFormula = VOLTAGE_FORMULA_INTEL_SOC,
.powerFormula = POWER_FORMULA_INTEL_ATOM,
.PCI_ids = PCI_Void_ids,
.Uncore = {
.Start = NULL,
.Stop = NULL,
.ClockMod = NULL
},
.Specific = Void_Specific,
.SystemDriver = SNB_Driver,
.Architecture = Arch_Atom_Goldmont
},
[Atom_Sofia] = { /* 26*/
.Signature = _Atom_Sofia,
.Query = Query_Core2,
.Update = PerCore_Core2_Query,
.Start = Start_Core2,
.Stop = Stop_Core2,
.Exit = NULL,
.Timer = InitTimer_Core2,
.BaseClock = BaseClock_Atom,
.ClockMod = ClockMod_Core2_PPC,
.TurboClock = NULL,
.thermalFormula = THERMAL_FORMULA_INTEL,
.voltageFormula = VOLTAGE_FORMULA_NONE,
.powerFormula = POWER_FORMULA_INTEL_ATOM,
.PCI_ids = PCI_Void_ids,
.Uncore = {
.Start = NULL,
.Stop = NULL,
.ClockMod = NULL
},
.Specific = Void_Specific,
.SystemDriver = CORE2_Driver,
.Architecture = Arch_Atom_Sofia
},
[Atom_Merrifield] = { /* 27*/
.Signature = _Atom_Merrifield,
.Query = Query_Core2,
.Update = PerCore_Core2_Query,
.Start = Start_Core2,
.Stop = Stop_Core2,
.Exit = NULL,
.Timer = InitTimer_Core2,
.BaseClock = BaseClock_Atom,
.ClockMod = ClockMod_Core2_PPC,
.TurboClock = NULL,
.thermalFormula = THERMAL_FORMULA_INTEL,
.voltageFormula = VOLTAGE_FORMULA_NONE,
.powerFormula = POWER_FORMULA_INTEL_ATOM,
.PCI_ids = PCI_Void_ids,
.Uncore = {
.Start = NULL,
.Stop = NULL,
.ClockMod = NULL
},
.Specific = Void_Specific,
.SystemDriver = CORE2_Driver,
.Architecture = Arch_Atom_Merrifield
},
[Atom_Moorefield] = { /* 28*/
.Signature = _Atom_Moorefield,
.Query = Query_Core2,
.Update = PerCore_Core2_Query,
.Start = Start_Core2,
.Stop = Stop_Core2,
.Exit = NULL,
.Timer = InitTimer_Core2,
.BaseClock = BaseClock_Atom,
.ClockMod = ClockMod_Core2_PPC,
.TurboClock = NULL,
.thermalFormula = THERMAL_FORMULA_INTEL,
.voltageFormula = VOLTAGE_FORMULA_NONE,
.powerFormula = POWER_FORMULA_INTEL_ATOM,
.PCI_ids = PCI_Void_ids,
.Uncore = {
.Start = NULL,
.Stop = NULL,
.ClockMod = NULL
},
.Specific = Void_Specific,
.SystemDriver = CORE2_Driver,
.Architecture = Arch_Atom_Moorefield
},
[Nehalem_Bloomfield] = { /* 29*/
.Signature = _Nehalem_Bloomfield,
.Query = Query_Nehalem,
.Update = PerCore_Nehalem_Query,
.Start = Start_Nehalem,
.Stop = Stop_Nehalem,
.Exit = NULL,
.Timer = InitTimer_Nehalem,
.BaseClock = BaseClock_Nehalem,
.ClockMod = ClockMod_Nehalem_PPC,
.TurboClock = Intel_Turbo_Config8C,
.thermalFormula = THERMAL_FORMULA_INTEL,
.voltageFormula = VOLTAGE_FORMULA_NONE,
#if defined(HWM_CHIPSET)
#if (HWM_CHIPSET == W83627)
.voltageFormula = VOLTAGE_FORMULA_WINBOND_IO,
#elif (HWM_CHIPSET == IT8720)
.voltageFormula = VOLTAGE_FORMULA_ITETECH_IO,
#endif
#endif
.powerFormula = POWER_FORMULA_INTEL,
.PCI_ids = PCI_Nehalem_QPI_ids,
.Uncore = {
.Start = Start_Uncore_Nehalem,
.Stop = Stop_Uncore_Nehalem,
.ClockMod = NULL
},
.Specific = Nehalem_Bloomfield_Specific,
.SystemDriver = NHM_Driver,
.Architecture = Arch_Nehalem_Bloomfield
},
[Nehalem_Lynnfield] = { /* 30*/
.Signature = _Nehalem_Lynnfield,
.Query = Query_Nehalem,
.Update = PerCore_Nehalem_Query,
.Start = Start_Nehalem,
.Stop = Stop_Nehalem,
.Exit = NULL,
.Timer = InitTimer_Nehalem,
.BaseClock = BaseClock_Nehalem,
.ClockMod = ClockMod_Nehalem_PPC,
.TurboClock = Intel_Turbo_Config8C,
.thermalFormula = THERMAL_FORMULA_INTEL,
.voltageFormula = VOLTAGE_FORMULA_NONE,
#if defined(HWM_CHIPSET)
#if (HWM_CHIPSET == W83627)
.voltageFormula = VOLTAGE_FORMULA_WINBOND_IO,
#elif (HWM_CHIPSET == IT8720)
.voltageFormula = VOLTAGE_FORMULA_ITETECH_IO,
#endif
#endif
.powerFormula = POWER_FORMULA_INTEL,
.PCI_ids = PCI_Nehalem_DMI_ids,
.Uncore = {
.Start = Start_Uncore_Nehalem,
.Stop = Stop_Uncore_Nehalem,
.ClockMod = NULL
},
.Specific = Nehalem_Lynnfield_Specific,
.SystemDriver = NHM_Driver,
.Architecture = Arch_Nehalem_Lynnfield
},
[Nehalem_MB] = { /* 31*/
.Signature = _Nehalem_MB,
.Query = Query_Nehalem,
.Update = PerCore_Nehalem_Query,
.Start = Start_Nehalem,
.Stop = Stop_Nehalem,
.Exit = NULL,
.Timer = InitTimer_Nehalem,
.BaseClock = BaseClock_Nehalem,
.ClockMod = ClockMod_Nehalem_PPC,
.TurboClock = Intel_Turbo_Config8C,
.thermalFormula = THERMAL_FORMULA_INTEL,
.voltageFormula = VOLTAGE_FORMULA_NONE,
#if defined(HWM_CHIPSET)
#if (HWM_CHIPSET == W83627)
.voltageFormula = VOLTAGE_FORMULA_WINBOND_IO,
#elif (HWM_CHIPSET == IT8720)
.voltageFormula = VOLTAGE_FORMULA_ITETECH_IO,
#endif
#endif
.powerFormula = POWER_FORMULA_INTEL,
.PCI_ids = PCI_Nehalem_DMI_ids,
.Uncore = {
.Start = Start_Uncore_Nehalem,
.Stop = Stop_Uncore_Nehalem,
.ClockMod = NULL
},
.Specific = Void_Specific,
.SystemDriver = NHM_Driver,
.Architecture = Arch_Nehalem_MB
},
[Nehalem_EX] = { /* 32*/
.Signature = _Nehalem_EX,
.Query = Query_Nehalem_EX,
.Update = PerCore_Nehalem_EX_Query,
.Start = Start_Nehalem,
.Stop = Stop_Nehalem,
.Exit = NULL,
.Timer = InitTimer_Nehalem,
.BaseClock = BaseClock_Nehalem,
.ClockMod = ClockMod_Nehalem_PPC,
.TurboClock = NULL, /* Attempt to read/write MSR 0x1ad will cause #UD */
.thermalFormula = THERMAL_FORMULA_INTEL,
.voltageFormula = VOLTAGE_FORMULA_NONE,
#if defined(HWM_CHIPSET)
#if (HWM_CHIPSET == W83627)
.voltageFormula = VOLTAGE_FORMULA_WINBOND_IO,
#elif (HWM_CHIPSET == IT8720)
.voltageFormula = VOLTAGE_FORMULA_ITETECH_IO,
#endif
#endif
.powerFormula = POWER_FORMULA_INTEL,
.PCI_ids = PCI_Nehalem_QPI_ids,
.Uncore = {
.Start = Start_Uncore_Nehalem,
.Stop = Stop_Uncore_Nehalem,
.ClockMod = NULL
},
.Specific = Void_Specific,
.SystemDriver = NHM_Driver,
.Architecture = Arch_Nehalem_EX
},
[Westmere] = { /* 33*/
.Signature = _Westmere,
.Query = Query_Nehalem,
.Update = PerCore_Nehalem_Query,
.Start = Start_Nehalem,
.Stop = Stop_Nehalem,
.Exit = NULL,
.Timer = InitTimer_Nehalem,
.BaseClock = BaseClock_Westmere,
.ClockMod = ClockMod_Nehalem_PPC,
.TurboClock = Intel_Turbo_Config8C,
.thermalFormula = THERMAL_FORMULA_INTEL,
.voltageFormula = VOLTAGE_FORMULA_NONE,
#if defined(HWM_CHIPSET)
#if (HWM_CHIPSET == W83627)
.voltageFormula = VOLTAGE_FORMULA_WINBOND_IO,
#elif (HWM_CHIPSET == IT8720)
.voltageFormula = VOLTAGE_FORMULA_ITETECH_IO,
#endif
#endif
.powerFormula = POWER_FORMULA_INTEL,
.PCI_ids = PCI_Nehalem_DMI_ids,
.Uncore = {
.Start = Start_Uncore_Nehalem,
.Stop = Stop_Uncore_Nehalem,
.ClockMod = NULL
},
.Specific = Void_Specific,
.SystemDriver = NHM_Driver,
.Architecture = Arch_Westmere
},
[Westmere_EP] = { /* 34*/
.Signature = _Westmere_EP,
.Query = Query_Nehalem,
.Update = PerCore_Nehalem_Query,
.Start = Start_Nehalem,
.Stop = Stop_Nehalem,
.Exit = NULL,
.Timer = InitTimer_Nehalem,
.BaseClock = BaseClock_Westmere,
.ClockMod = ClockMod_Nehalem_PPC,
.TurboClock = Intel_Turbo_Config8C,
.thermalFormula = THERMAL_FORMULA_INTEL,
.voltageFormula = VOLTAGE_FORMULA_NONE,
#if defined(HWM_CHIPSET)
#if (HWM_CHIPSET == W83627)
.voltageFormula = VOLTAGE_FORMULA_WINBOND_IO,
#elif (HWM_CHIPSET == IT8720)
.voltageFormula = VOLTAGE_FORMULA_ITETECH_IO,
#endif
#endif
.powerFormula = POWER_FORMULA_INTEL,
.PCI_ids = PCI_Westmere_EP_ids,
.Uncore = {
.Start = Start_Uncore_Nehalem,
.Stop = Stop_Uncore_Nehalem,
.ClockMod = NULL
},
.Specific = Westmere_EP_Specific,
.SystemDriver = NHM_Driver,
.Architecture = Arch_Westmere_EP
},
[Westmere_EX] = { /* 35*/
.Signature = _Westmere_EX,
.Query = Query_Nehalem_EX, /* Xeon 7500 series-based platform */
.Update = PerCore_Nehalem_EX_Query,
.Start = Start_Nehalem,
.Stop = Stop_Nehalem,
.Exit = NULL,
.Timer = InitTimer_Nehalem,
.BaseClock = BaseClock_Westmere,
.ClockMod = ClockMod_Nehalem_PPC,
.TurboClock = NULL, /* Attempt to read/write MSR 0x1ad will cause #UD */
.thermalFormula = THERMAL_FORMULA_INTEL,
.voltageFormula = VOLTAGE_FORMULA_NONE,
#if defined(HWM_CHIPSET)
#if (HWM_CHIPSET == W83627)
.voltageFormula = VOLTAGE_FORMULA_WINBOND_IO,
#elif (HWM_CHIPSET == IT8720)
.voltageFormula = VOLTAGE_FORMULA_ITETECH_IO,
#endif
#endif
.powerFormula = POWER_FORMULA_INTEL,
.PCI_ids = PCI_Nehalem_QPI_ids,
.Uncore = {
.Start = Start_Uncore_Nehalem,
.Stop = Stop_Uncore_Nehalem,
.ClockMod = NULL
},
.Specific = Void_Specific,
.SystemDriver = NHM_Driver,
.Architecture = Arch_Westmere_EX
},
[SandyBridge] = { /* 36*/
.Signature = _SandyBridge,
.Query = Query_SandyBridge,
.Update = PerCore_SandyBridge_Query,
.Start = Start_SandyBridge,
.Stop = Stop_SandyBridge,
.Exit = NULL,
.Timer = InitTimer_SandyBridge,
.BaseClock = BaseClock_SandyBridge,
.ClockMod = ClockMod_SandyBridge_PPC,
.TurboClock = Intel_Turbo_Config8C,
.thermalFormula = THERMAL_FORMULA_INTEL,
.voltageFormula = VOLTAGE_FORMULA_INTEL_SNB,
.powerFormula = POWER_FORMULA_INTEL,
.PCI_ids = PCI_SandyBridge_ids,
.Uncore = {
.Start = Start_Uncore_SandyBridge,
.Stop = Stop_Uncore_SandyBridge,
.ClockMod = NULL
},
.Specific = Void_Specific,
.SystemDriver = SNB_Driver,
.Architecture = Arch_SandyBridge
},
[SandyBridge_EP] = { /* 37*/
.Signature = _SandyBridge_EP,
.Query = Query_SandyBridge_EP,
.Update = PerCore_SandyBridge_EP_Query,
.Start = Start_SandyBridge_EP,
.Stop = Stop_SandyBridge_EP,
.Exit = NULL,
.Timer = InitTimer_SandyBridge_EP,
.BaseClock = BaseClock_SandyBridge,
.ClockMod = ClockMod_SandyBridge_PPC,
.TurboClock = Intel_Turbo_Config8C,
.thermalFormula = THERMAL_FORMULA_INTEL,
.voltageFormula = VOLTAGE_FORMULA_INTEL_SNB,
.powerFormula = POWER_FORMULA_INTEL,
.PCI_ids = PCI_SandyBridge_EP_ids,
.Uncore = {
.Start = Start_Uncore_SandyBridge_EP,
.Stop = Stop_Uncore_SandyBridge_EP,
.ClockMod = NULL
},
.Specific = SandyBridge_EP_Specific,
.SystemDriver = SNB_Driver,
.Architecture = Arch_SandyBridge_EP
},
[IvyBridge] = { /* 38*/
.Signature = _IvyBridge,
.Query = Query_IvyBridge,
.Update = PerCore_IvyBridge_Query,
.Start = Start_SandyBridge,
.Stop = Stop_SandyBridge,
.Exit = NULL,
.Timer = InitTimer_SandyBridge,
.BaseClock = BaseClock_IvyBridge,
.ClockMod = ClockMod_SandyBridge_PPC,
.TurboClock = Intel_Turbo_Config8C,
.thermalFormula = THERMAL_FORMULA_INTEL,
.voltageFormula = VOLTAGE_FORMULA_INTEL_SNB,
.powerFormula = POWER_FORMULA_INTEL,
.PCI_ids = PCI_IvyBridge_ids,
.Uncore = {
.Start = Start_Uncore_SandyBridge,
.Stop = Stop_Uncore_SandyBridge,
.ClockMod = NULL
},
.Specific = Void_Specific,
.SystemDriver = IVB_Driver,
.Architecture = Arch_IvyBridge
},
[IvyBridge_EP] = { /* 39*/
.Signature = _IvyBridge_EP,
.Query = Query_IvyBridge_EP,
.Update = PerCore_IvyBridge_EP_Query,
.Start = Start_IvyBridge_EP,
.Stop = Stop_IvyBridge_EP,
.Exit = NULL,
.Timer = InitTimer_IvyBridge_EP,
.BaseClock = BaseClock_IvyBridge,
.ClockMod = ClockMod_SandyBridge_PPC,
.TurboClock = TurboClock_IvyBridge_EP,
.thermalFormula = THERMAL_FORMULA_INTEL,
.voltageFormula = VOLTAGE_FORMULA_INTEL_SNB,
.powerFormula = POWER_FORMULA_INTEL,
.PCI_ids = PCI_SandyBridge_EP_ids,
.Uncore = {
.Start = Start_Uncore_IvyBridge_EP,
.Stop = Stop_Uncore_IvyBridge_EP,
.ClockMod = NULL
},
.Specific = IvyBridge_EP_Specific,
.SystemDriver = IVB_Driver,
.Architecture = Arch_IvyBridge_EP
},
[Haswell_DT] = { /* 40*/
.Signature = _Haswell_DT,
.Query = Query_Haswell,
.Update = PerCore_Haswell_Query,
.Start = Start_SandyBridge,
.Stop = Stop_SandyBridge,
.Exit = NULL,
.Timer = InitTimer_SandyBridge,
.BaseClock = BaseClock_Haswell,
.ClockMod = ClockMod_SandyBridge_PPC,
.TurboClock = Intel_Turbo_Config8C,
.thermalFormula = THERMAL_FORMULA_INTEL,
.voltageFormula = VOLTAGE_FORMULA_INTEL_SNB,
.powerFormula = POWER_FORMULA_INTEL,
.PCI_ids = PCI_Haswell_ids,
.Uncore = {
.Start = Start_Uncore_SandyBridge,
.Stop = Stop_Uncore_SandyBridge,
.ClockMod = NULL
},
.Specific = Haswell_DT_Specific,
.SystemDriver = HSW_Driver,
.Architecture = Arch_Haswell_DT
},
[Haswell_EP] = { /* 41*/
.Signature = _Haswell_EP,
.Query = Query_Haswell_EP,
.Update = PerCore_Haswell_EP_Query,
.Start = Start_Haswell_EP,
.Stop = Stop_Haswell_EP,
.Exit = NULL,
.Timer = InitTimer_Haswell_EP,
.BaseClock = BaseClock_Haswell,
.ClockMod = ClockMod_SandyBridge_PPC,
.TurboClock = TurboClock_Haswell_EP,
.thermalFormula = THERMAL_FORMULA_INTEL,
.voltageFormula = VOLTAGE_FORMULA_INTEL_SNB,
.powerFormula = POWER_FORMULA_INTEL,
.PCI_ids = PCI_Haswell_ids,
.Uncore = {
.Start = Start_Uncore_Haswell_EP,
.Stop = Stop_Uncore_Haswell_EP,
.ClockMod = Haswell_Uncore_Ratio
},
.Specific = Haswell_EP_Specific,
.SystemDriver = HSW_Driver,
.Architecture = Arch_Haswell_EP
},
[Haswell_ULT] = { /* 42*/
.Signature = _Haswell_ULT,
.Query = Query_Haswell_ULT,
.Update = PerCore_Haswell_ULT_Query,
.Start = Start_Haswell_ULT,
.Stop = Stop_Haswell_ULT,
.Exit = NULL,
.Timer = InitTimer_Haswell_ULT,
.BaseClock = BaseClock_Haswell,
.ClockMod = ClockMod_SandyBridge_PPC,
.TurboClock = Intel_Turbo_Config8C,
.thermalFormula = THERMAL_FORMULA_INTEL,
.voltageFormula = VOLTAGE_FORMULA_INTEL_SNB,
.powerFormula = POWER_FORMULA_INTEL,
.PCI_ids = PCI_Haswell_ids,
.Uncore = {
.Start = Start_Uncore_Haswell_ULT,
.Stop = Stop_Uncore_Haswell_ULT,
.ClockMod = NULL
},
.Specific = Void_Specific,
.SystemDriver = HSW_Driver,
.Architecture = Arch_Haswell_ULT
},
[Haswell_ULX] = { /* 43*/
.Signature = _Haswell_ULX,
.Query = Query_Haswell_ULX,
.Update = PerCore_Haswell_ULX,
.Start = Start_SandyBridge,
.Stop = Stop_SandyBridge,
.Exit = NULL,
.Timer = InitTimer_SandyBridge,
.BaseClock = BaseClock_Haswell,
.ClockMod = ClockMod_SandyBridge_PPC,
.TurboClock = Intel_Turbo_Config8C,
.thermalFormula = THERMAL_FORMULA_INTEL,
.voltageFormula = VOLTAGE_FORMULA_INTEL_SNB,
.powerFormula = POWER_FORMULA_INTEL,
.PCI_ids = PCI_Haswell_ids,
.Uncore = {
.Start = Start_Uncore_SandyBridge,
.Stop = Stop_Uncore_SandyBridge,
.ClockMod = NULL
},
.Specific = Void_Specific,
.SystemDriver = HSW_Driver,
.Architecture = Arch_Haswell_ULX
},
[Broadwell] = { /* 44*/
.Signature = _Broadwell,
.Query = Query_Broadwell,
.Update = PerCore_Broadwell_Query,
.Start = Start_Broadwell,
.Stop = Stop_Broadwell,
.Exit = NULL,
.Timer = InitTimer_Broadwell,
.BaseClock = BaseClock_Haswell,
.ClockMod = ClockMod_SandyBridge_PPC,
.TurboClock = Intel_Turbo_Config8C,
.thermalFormula = THERMAL_FORMULA_INTEL,
.voltageFormula = VOLTAGE_FORMULA_INTEL_SNB,
.powerFormula = POWER_FORMULA_INTEL,
.PCI_ids = PCI_Broadwell_ids,
.Uncore = {
.Start = Start_Uncore_Broadwell,
.Stop = Stop_Uncore_Broadwell,
.ClockMod = Haswell_Uncore_Ratio
},
.Specific = Void_Specific,
.SystemDriver = BDW_Driver,
.Architecture = Arch_Broadwell
},
[Broadwell_D] = { /* 45*/
.Signature = _Broadwell_D,
.Query = Query_Broadwell_EP,
.Update = PerCore_Haswell_EP_Query,
.Start = Start_Haswell_EP,
.Stop = Stop_Haswell_EP,
.Exit = NULL,
.Timer = InitTimer_Haswell_EP,
.BaseClock = BaseClock_Haswell,
.ClockMod = ClockMod_Broadwell_EP_HWP,
.TurboClock = TurboClock_Broadwell_EP,
.thermalFormula = THERMAL_FORMULA_INTEL,
.voltageFormula = VOLTAGE_FORMULA_INTEL_SNB,
.powerFormula = POWER_FORMULA_INTEL,
.PCI_ids = PCI_Broadwell_ids,
.Uncore = {
.Start = Start_Uncore_Haswell_EP,
.Stop = Stop_Uncore_Haswell_EP,
.ClockMod = Haswell_Uncore_Ratio
},
.Specific = Void_Specific,
.SystemDriver = BDW_EP_Driver,
.Architecture = Arch_Broadwell_D
},
[Broadwell_H] = { /* 46*/
.Signature = _Broadwell_H,
.Query = Query_Broadwell,
.Update = PerCore_Broadwell_Query,
.Start = Start_Broadwell,
.Stop = Stop_Broadwell,
.Exit = NULL,
.Timer = InitTimer_Broadwell,
.BaseClock = BaseClock_Haswell,
.ClockMod = ClockMod_SandyBridge_PPC,
.TurboClock = Intel_Turbo_Config8C,
.thermalFormula = THERMAL_FORMULA_INTEL,
.voltageFormula = VOLTAGE_FORMULA_INTEL_SNB,
.powerFormula = POWER_FORMULA_INTEL,
.PCI_ids = PCI_Broadwell_ids,
.Uncore = {
.Start = Start_Uncore_Broadwell,
.Stop = Stop_Uncore_Broadwell,
.ClockMod = Haswell_Uncore_Ratio
},
.Specific = Void_Specific,
.SystemDriver = BDW_Driver,
.Architecture = Arch_Broadwell_H
},
[Broadwell_EP] = { /* 47*/
.Signature = _Broadwell_EP,
.Query = Query_Broadwell_EP,
.Update = PerCore_Haswell_EP_Query,
.Start = Start_Haswell_EP,
.Stop = Stop_Haswell_EP,
.Exit = NULL,
.Timer = InitTimer_Haswell_EP,
.BaseClock = BaseClock_Haswell,
.ClockMod = ClockMod_Broadwell_EP_HWP,
.TurboClock = TurboClock_Broadwell_EP,
.thermalFormula = THERMAL_FORMULA_INTEL,
.voltageFormula = VOLTAGE_FORMULA_INTEL_SNB,
.powerFormula = POWER_FORMULA_INTEL,
.PCI_ids = PCI_Broadwell_ids,
.Uncore = {
.Start = Start_Uncore_Haswell_EP,
.Stop = Stop_Uncore_Haswell_EP,
.ClockMod = Haswell_Uncore_Ratio
},
.Specific = Broadwell_EP_Specific,
.SystemDriver = BDW_EP_Driver,
.Architecture = Arch_Broadwell_EP
},
[Skylake_UY] = { /* 48*/
.Signature = _Skylake_UY,
.Query = Query_Skylake,
.Update = PerCore_Skylake_Query,
.Start = Start_Skylake,
.Stop = Stop_Skylake,
.Exit = NULL,
.Timer = InitTimer_Skylake,
.BaseClock = BaseClock_Skylake,
.ClockMod = ClockMod_Skylake_HWP,
.TurboClock = Intel_Turbo_Config8C,
.thermalFormula = THERMAL_FORMULA_INTEL,
.voltageFormula = VOLTAGE_FORMULA_INTEL_SNB,
.powerFormula = POWER_FORMULA_INTEL,
.PCI_ids = PCI_Skylake_ids,
.Uncore = {
.Start = Start_Uncore_Skylake,
.Stop = Stop_Uncore_Skylake,
.ClockMod = Haswell_Uncore_Ratio
},
.Specific = Void_Specific,
.SystemDriver = SKL_Driver,
.Architecture = Arch_Skylake_UY
},
[Skylake_S] = { /* 49*/
.Signature = _Skylake_S,
.Query = Query_Skylake,
.Update = PerCore_Skylake_Query,
.Start = Start_Skylake,
.Stop = Stop_Skylake,
.Exit = NULL,
.Timer = InitTimer_Skylake,
.BaseClock = BaseClock_Skylake,
.ClockMod = ClockMod_Skylake_HWP,
.TurboClock = Intel_Turbo_Config8C,
.thermalFormula = THERMAL_FORMULA_INTEL,
.voltageFormula = VOLTAGE_FORMULA_INTEL_SNB,
.powerFormula = POWER_FORMULA_INTEL,
.PCI_ids = PCI_Skylake_ids,
.Uncore = {
.Start = Start_Uncore_Skylake,
.Stop = Stop_Uncore_Skylake,
.ClockMod = Haswell_Uncore_Ratio
},
.Specific = Void_Specific,
.SystemDriver = SKL_Driver,
.Architecture = Arch_Skylake_S
},
[Skylake_X] = { /* 50*/
.Signature = _Skylake_X,
.Query = Query_Skylake_X,
.Update = PerCore_Skylake_X_Query,
.Start = Start_Skylake_X,
.Stop = Stop_Skylake_X,
.Exit = NULL,
.Timer = InitTimer_Skylake_X,
.BaseClock = BaseClock_Skylake,
.ClockMod = ClockMod_Skylake_HWP,
.TurboClock = TurboClock_Skylake_X,
.thermalFormula = THERMAL_FORMULA_INTEL,
.voltageFormula = VOLTAGE_FORMULA_INTEL_SKL_X,
.powerFormula = POWER_FORMULA_INTEL,
.PCI_ids = PCI_Skylake_X_ids,
.Uncore = {
.Start = Start_Uncore_Skylake_X,
.Stop = Stop_Uncore_Skylake_X,
.ClockMod = Haswell_Uncore_Ratio
},
.Specific = Skylake_X_Specific,
.SystemDriver = SKX_Driver,
.Architecture = Arch_Skylake_X
},
[Xeon_Phi] = { /* 51*/
.Signature = _Xeon_Phi,
.Query = Query_SandyBridge_EP,
.Update = PerCore_SandyBridge_Query,
.Start = Start_SandyBridge,
.Stop = Stop_SandyBridge,
.Exit = NULL,
.Timer = InitTimer_SandyBridge,
.BaseClock = BaseClock_Skylake,
.ClockMod = ClockMod_SandyBridge_PPC,
.TurboClock = NULL,
.thermalFormula = THERMAL_FORMULA_INTEL,
.voltageFormula = VOLTAGE_FORMULA_NONE,
.powerFormula = POWER_FORMULA_INTEL,
.PCI_ids = PCI_Void_ids,
.Uncore = {
.Start = Start_Uncore_SandyBridge,
.Stop = Stop_Uncore_SandyBridge,
.ClockMod = Haswell_Uncore_Ratio
},
.Specific = Void_Specific,
.SystemDriver = VOID_Driver,
.Architecture = Arch_Xeon_Phi
},
[Kabylake] = { /* 52*/
.Signature = _Kabylake,
.Query = Query_Kaby_Lake,
.Update = PerCore_Kaby_Lake_Query,
.Start = Start_Skylake,
.Stop = Stop_Skylake,
.Exit = NULL,
.Timer = InitTimer_Skylake,
.BaseClock = BaseClock_Skylake,
.ClockMod = ClockMod_Skylake_HWP,
.TurboClock = Intel_Turbo_Config8C,
.thermalFormula = THERMAL_FORMULA_INTEL,
.voltageFormula = VOLTAGE_FORMULA_INTEL_SNB,
.powerFormula = POWER_FORMULA_INTEL,
.PCI_ids = PCI_Kabylake_ids,
.Uncore = {
.Start = Start_Uncore_Skylake,
.Stop = Stop_Uncore_Skylake,
.ClockMod = Haswell_Uncore_Ratio
},
.Specific = Kabylake_Specific,
.SystemDriver = SKL_Driver,
.Architecture = Arch_Kabylake
},
[Kabylake_UY] = { /* 53*/
.Signature = _Kabylake_UY,
.Query = Query_Skylake,
.Update = PerCore_Skylake_Query,
.Start = Start_Skylake,
.Stop = Stop_Skylake,
.Exit = NULL,
.Timer = InitTimer_Skylake,
.BaseClock = BaseClock_Skylake,
.ClockMod = ClockMod_Skylake_HWP,
.TurboClock = Intel_Turbo_Config8C,
.thermalFormula = THERMAL_FORMULA_INTEL,
.voltageFormula = VOLTAGE_FORMULA_INTEL_SNB,
.powerFormula = POWER_FORMULA_INTEL,
.PCI_ids = PCI_Kabylake_ids,
.Uncore = {
.Start = Start_Uncore_Skylake,
.Stop = Stop_Uncore_Skylake,
.ClockMod = Haswell_Uncore_Ratio
},
.Specific = Kabylake_UY_Specific,
.SystemDriver = SKL_Driver,
.Architecture = Arch_Kabylake_UY
},
[Cannonlake] = { /* 54*/
.Signature = _Cannonlake,
.Query = Query_Skylake,
.Update = PerCore_Skylake_Query,
.Start = Start_Skylake,
.Stop = Stop_Skylake,
.Exit = NULL,
.Timer = InitTimer_Skylake,
.BaseClock = BaseClock_Skylake,
.ClockMod = ClockMod_Skylake_HWP,
.TurboClock = Intel_Turbo_Config8C,
.thermalFormula = THERMAL_FORMULA_INTEL,
.voltageFormula = VOLTAGE_FORMULA_INTEL_SNB,
.powerFormula = POWER_FORMULA_INTEL,
.PCI_ids = PCI_Kabylake_ids,
.Uncore = {
.Start = Start_Uncore_Skylake,
.Stop = Stop_Uncore_Skylake,
.ClockMod = Haswell_Uncore_Ratio
},
.Specific = Void_Specific,
.SystemDriver = SKL_Driver,
.Architecture = Arch_Cannonlake
},
[Geminilake] = { /* 55*/
.Signature = _Geminilake,
.Query = Query_Goldmont,
.Update = PerCore_Goldmont_Query,
.Start = Start_Goldmont,
.Stop = Stop_Goldmont,
.Exit = NULL,
.Timer = InitTimer_Goldmont,
.BaseClock = BaseClock_Skylake,
.ClockMod = ClockMod_SandyBridge_PPC,
.TurboClock = Intel_Turbo_Config8C,
.thermalFormula = THERMAL_FORMULA_INTEL,
.voltageFormula = VOLTAGE_FORMULA_INTEL_SOC,
.powerFormula = POWER_FORMULA_INTEL_ATOM,
.PCI_ids = PCI_Void_ids,
.Uncore = {
.Start = NULL,
.Stop = NULL,
.ClockMod = NULL
},
.Specific = Void_Specific,
.SystemDriver = SNB_Driver,
.Architecture = Arch_Geminilake
},
[Icelake] = { /* 56*/
.Signature = _Icelake,
.Query = Query_Skylake,
.Update = PerCore_Skylake_Query,
.Start = Start_Skylake,
.Stop = Stop_Skylake,
.Exit = NULL,
.Timer = InitTimer_Skylake,
.BaseClock = BaseClock_Skylake,
.ClockMod = ClockMod_Skylake_HWP,
.TurboClock = Intel_Turbo_Config8C,
.thermalFormula = THERMAL_FORMULA_INTEL,
.voltageFormula = VOLTAGE_FORMULA_INTEL_SNB,
.powerFormula = POWER_FORMULA_INTEL,
.PCI_ids = PCI_Kabylake_ids,
.Uncore = {
.Start = Start_Uncore_Skylake,
.Stop = Stop_Uncore_Skylake,
.ClockMod = Haswell_Uncore_Ratio
},
.Specific = Void_Specific,
.SystemDriver = SKL_Driver,
.Architecture = Arch_Icelake
},
[Icelake_UY] = { /* 57*/
.Signature = _Icelake_UY,
.Query = Query_Skylake,
.Update = PerCore_Skylake_Query,
.Start = Start_Skylake,
.Stop = Stop_Skylake,
.Exit = NULL,
.Timer = InitTimer_Skylake,
.BaseClock = BaseClock_Skylake,
.ClockMod = ClockMod_Skylake_HWP,
.TurboClock = Intel_Turbo_Config8C,
.thermalFormula = THERMAL_FORMULA_INTEL,
.voltageFormula = VOLTAGE_FORMULA_INTEL_SNB,
.powerFormula = POWER_FORMULA_INTEL,
.PCI_ids = PCI_Kabylake_ids,
.Uncore = {
.Start = Start_Uncore_Skylake,
.Stop = Stop_Uncore_Skylake,
.ClockMod = Haswell_Uncore_Ratio
},
.Specific = Void_Specific,
.SystemDriver = SKL_Driver,
.Architecture = Arch_Icelake_UY
},
[Icelake_X] = { /* 58*/
.Signature = _Icelake_X,
.Query = Query_Kaby_Lake,
.Update = PerCore_Skylake_Query,
.Start = Start_Skylake,
.Stop = Stop_Skylake,
.Exit = NULL,
.Timer = InitTimer_Skylake,
.BaseClock = BaseClock_Skylake,
.ClockMod = ClockMod_Skylake_HWP,
.TurboClock = Intel_Turbo_Config8C,
.thermalFormula = THERMAL_FORMULA_INTEL,
.voltageFormula = VOLTAGE_FORMULA_INTEL_SNB,
.powerFormula = POWER_FORMULA_INTEL,
.PCI_ids = PCI_Kabylake_ids,
.Uncore = {
.Start = Start_Uncore_Skylake,
.Stop = Stop_Uncore_Skylake,
.ClockMod = Haswell_Uncore_Ratio
},
.Specific = Void_Specific,
.SystemDriver = SKL_Driver,
.Architecture = Arch_Icelake_X
},
[Icelake_D] = { /* 59*/
.Signature = _Icelake_D,
.Query = Query_Kaby_Lake,
.Update = PerCore_Skylake_Query,
.Start = Start_Skylake,
.Stop = Stop_Skylake,
.Exit = NULL,
.Timer = InitTimer_Skylake,
.BaseClock = BaseClock_Skylake,
.ClockMod = ClockMod_Skylake_HWP,
.TurboClock = Intel_Turbo_Config8C,
.thermalFormula = THERMAL_FORMULA_INTEL,
.voltageFormula = VOLTAGE_FORMULA_INTEL_SNB,
.powerFormula = POWER_FORMULA_INTEL,
.PCI_ids = PCI_Kabylake_ids,
.Uncore = {
.Start = Start_Uncore_Skylake,
.Stop = Stop_Uncore_Skylake,
.ClockMod = Haswell_Uncore_Ratio
},
.Specific = Void_Specific,
.SystemDriver = SKL_Driver,
.Architecture = Arch_Icelake_D
},
[Sunny_Cove] = { /* 60*/
.Signature = _Sunny_Cove,
.Query = Query_Skylake,
.Update = PerCore_Skylake_Query,
.Start = Start_Skylake,
.Stop = Stop_Skylake,
.Exit = NULL,
.Timer = InitTimer_Skylake,
.BaseClock = BaseClock_Skylake,
.ClockMod = ClockMod_Skylake_HWP,
.TurboClock = Intel_Turbo_Config8C,
.thermalFormula = THERMAL_FORMULA_INTEL,
.voltageFormula = VOLTAGE_FORMULA_INTEL_SNB,
.powerFormula = POWER_FORMULA_INTEL,
.PCI_ids = PCI_Kabylake_ids,
.Uncore = {
.Start = Start_Uncore_Skylake,
.Stop = Stop_Uncore_Skylake,
.ClockMod = Haswell_Uncore_Ratio
},
.Specific = Void_Specific,
.SystemDriver = SKL_Driver,
.Architecture = Arch_Sunny_Cove
},
[Tigerlake] = { /* 61*/
.Signature = _Tigerlake,
.Query = Query_Skylake,
.Update = PerCore_Skylake_Query,
.Start = Start_Skylake,
.Stop = Stop_Skylake,
.Exit = NULL,
.Timer = InitTimer_Skylake,
.BaseClock = BaseClock_Skylake,
.ClockMod = ClockMod_Skylake_HWP,
.TurboClock = Intel_Turbo_Config8C,
.thermalFormula = THERMAL_FORMULA_INTEL,
.voltageFormula = VOLTAGE_FORMULA_INTEL_SNB,
.powerFormula = POWER_FORMULA_INTEL,
.PCI_ids = PCI_Kabylake_ids,
.Uncore = {
.Start = Start_Uncore_Skylake,
.Stop = Stop_Uncore_Skylake,
.ClockMod = Haswell_Uncore_Ratio
},
.Specific = Void_Specific,
.SystemDriver = SKL_Driver,
.Architecture = Arch_Tigerlake
},
[Tigerlake_U] = { /* 62*/
.Signature = _Tigerlake_U,
.Query = Query_Skylake,
.Update = PerCore_Skylake_Query,
.Start = Start_Skylake,
.Stop = Stop_Skylake,
.Exit = NULL,
.Timer = InitTimer_Skylake,
.BaseClock = BaseClock_Skylake,
.ClockMod = ClockMod_Skylake_HWP,
.TurboClock = Intel_Turbo_Config8C,
.thermalFormula = THERMAL_FORMULA_INTEL,
.voltageFormula = VOLTAGE_FORMULA_INTEL_SNB,
.powerFormula = POWER_FORMULA_INTEL,
.PCI_ids = PCI_Kabylake_ids,
.Uncore = {
.Start = Start_Uncore_Skylake,
.Stop = Stop_Uncore_Skylake,
.ClockMod = Haswell_Uncore_Ratio
},
.Specific = Void_Specific,
.SystemDriver = SKL_Driver,
.Architecture = Arch_Tigerlake_U
},
[Cometlake] = { /* 63*/
.Signature = _Cometlake,
.Query = Query_Skylake,
.Update = PerCore_Skylake_Query,
.Start = Start_Skylake,
.Stop = Stop_Skylake,
.Exit = NULL,
.Timer = InitTimer_Skylake,
.BaseClock = BaseClock_Skylake,
.ClockMod = ClockMod_Skylake_HWP,
.TurboClock = Intel_Turbo_Config8C,
.thermalFormula = THERMAL_FORMULA_INTEL,
.voltageFormula = VOLTAGE_FORMULA_INTEL_SNB,
.powerFormula = POWER_FORMULA_INTEL,
.PCI_ids = PCI_Kabylake_ids,
.Uncore = {
.Start = Start_Uncore_Skylake,
.Stop = Stop_Uncore_Skylake,
.ClockMod = Haswell_Uncore_Ratio
},
.Specific = Void_Specific,
.SystemDriver = SKL_Driver,
.Architecture = Arch_Cometlake
},
[Cometlake_UY] = { /* 64*/
.Signature = _Cometlake_UY,
.Query = Query_Skylake,
.Update = PerCore_Skylake_Query,
.Start = Start_Skylake,
.Stop = Stop_Skylake,
.Exit = NULL,
.Timer = InitTimer_Skylake,
.BaseClock = BaseClock_Skylake,
.ClockMod = ClockMod_Skylake_HWP,
.TurboClock = Intel_Turbo_Config8C,
.thermalFormula = THERMAL_FORMULA_INTEL,
.voltageFormula = VOLTAGE_FORMULA_INTEL_SNB,
.powerFormula = POWER_FORMULA_INTEL,
.PCI_ids = PCI_Kabylake_ids,
.Uncore = {
.Start = Start_Uncore_Skylake,
.Stop = Stop_Uncore_Skylake,
.ClockMod = Haswell_Uncore_Ratio
},
.Specific = Void_Specific,
.SystemDriver = SKL_Driver,
.Architecture = Arch_Cometlake_UY
},
[Atom_Denverton] = { /* 65*/
.Signature = _Atom_Denverton,
.Query = Query_Goldmont,
.Update = PerCore_Goldmont_Query,
.Start = Start_Goldmont,
.Stop = Stop_Goldmont,
.Exit = NULL,
.Timer = InitTimer_Goldmont,
.BaseClock = BaseClock_Skylake,
.ClockMod = ClockMod_SandyBridge_PPC,
.TurboClock = Intel_Turbo_Config8C,
.thermalFormula = THERMAL_FORMULA_INTEL,
.voltageFormula = VOLTAGE_FORMULA_INTEL_SOC,
.powerFormula = POWER_FORMULA_INTEL_ATOM,
.PCI_ids = PCI_Void_ids,
.Uncore = {
.Start = NULL,
.Stop = NULL,
.ClockMod = NULL
},
.Specific = Void_Specific,
.SystemDriver = SNB_Driver,
.Architecture = Arch_Atom_Denverton
},
[Tremont_Jacobsville] = { /* 66*/
.Signature = _Tremont_Jacobsville,
.Query = Query_Goldmont,
.Update = PerCore_Goldmont_Query,
.Start = Start_Goldmont,
.Stop = Stop_Goldmont,
.Exit = NULL,
.Timer = InitTimer_Goldmont,
.BaseClock = BaseClock_Skylake,
.ClockMod = ClockMod_SandyBridge_PPC,
.TurboClock = Intel_Turbo_Config8C,
.thermalFormula = THERMAL_FORMULA_INTEL,
.voltageFormula = VOLTAGE_FORMULA_INTEL_SOC,
.powerFormula = POWER_FORMULA_INTEL_ATOM,
.PCI_ids = PCI_Void_ids,
.Uncore = {
.Start = NULL,
.Stop = NULL,
.ClockMod = NULL
},
.Specific = Void_Specific,
.SystemDriver = Intel_Driver,
.Architecture = Arch_Tremont_Jacobsville
},
[Tremont_Lakefield] = { /* 67*/
.Signature = _Tremont_Lakefield,
.Query = Query_Skylake,
.Update = PerCore_Skylake_Query,
.Start = Start_Skylake,
.Stop = Stop_Skylake,
.Exit = NULL,
.Timer = InitTimer_Skylake,
.BaseClock = BaseClock_Skylake,
.ClockMod = ClockMod_Skylake_HWP,
.TurboClock = Intel_Turbo_Config8C,
.thermalFormula = THERMAL_FORMULA_INTEL,
.voltageFormula = VOLTAGE_FORMULA_INTEL_SNB,
.powerFormula = POWER_FORMULA_INTEL,
.PCI_ids = PCI_Void_ids,
.Uncore = {
.Start = Start_Uncore_Skylake,
.Stop = Stop_Uncore_Skylake,
.ClockMod = Haswell_Uncore_Ratio
},
.Specific = Void_Specific,
.SystemDriver = Intel_Driver,
.Architecture = Arch_Tremont_Lakefield
},
[Tremont_Elkhartlake] = { /* 68*/
.Signature = _Tremont_Elkhartlake,
.Query = Query_Skylake,
.Update = PerCore_Skylake_Query,
.Start = Start_Skylake,
.Stop = Stop_Skylake,
.Exit = NULL,
.Timer = InitTimer_Skylake,
.BaseClock = BaseClock_Skylake,
.ClockMod = ClockMod_Skylake_HWP,
.TurboClock = Intel_Turbo_Config8C,
.thermalFormula = THERMAL_FORMULA_INTEL,
.voltageFormula = VOLTAGE_FORMULA_INTEL_SNB,
.powerFormula = POWER_FORMULA_INTEL,
.PCI_ids = PCI_Void_ids,
.Uncore = {
.Start = Start_Uncore_Skylake,
.Stop = Stop_Uncore_Skylake,
.ClockMod = Haswell_Uncore_Ratio
},
.Specific = Void_Specific,
.SystemDriver = Intel_Driver,
.Architecture = Arch_Tremont_Elkhartlake
},
[Tremont_Jasperlake] = { /* 69*/
.Signature = _Tremont_Jasperlake,
.Query = Query_Skylake,
.Update = PerCore_Skylake_Query,
.Start = Start_Skylake,
.Stop = Stop_Skylake,
.Exit = NULL,
.Timer = InitTimer_Skylake,
.BaseClock = BaseClock_Skylake,
.ClockMod = ClockMod_Skylake_HWP,
.TurboClock = Intel_Turbo_Config8C,
.thermalFormula = THERMAL_FORMULA_INTEL,
.voltageFormula = VOLTAGE_FORMULA_INTEL_SNB,
.powerFormula = POWER_FORMULA_INTEL,
.PCI_ids = PCI_Void_ids,
.Uncore = {
.Start = Start_Uncore_Skylake,
.Stop = Stop_Uncore_Skylake,
.ClockMod = Haswell_Uncore_Ratio
},
.Specific = Void_Specific,
.SystemDriver = Intel_Driver,
.Architecture = Arch_Tremont_Jasperlake
},
[Sapphire_Rapids] = { /* 70*/
.Signature = _Sapphire_Rapids,
.Query = Query_Skylake,
.Update = PerCore_Skylake_Query,
.Start = Start_Skylake,
.Stop = Stop_Skylake,
.Exit = NULL,
.Timer = InitTimer_Skylake,
.BaseClock = BaseClock_Skylake,
.ClockMod = ClockMod_Skylake_HWP,
.TurboClock = Intel_Turbo_Config8C,
.thermalFormula = THERMAL_FORMULA_INTEL,
.voltageFormula = VOLTAGE_FORMULA_INTEL_SNB,
.powerFormula = POWER_FORMULA_INTEL,
.PCI_ids = PCI_Void_ids,
.Uncore = {
.Start = Start_Uncore_Skylake,
.Stop = Stop_Uncore_Skylake,
.ClockMod = Haswell_Uncore_Ratio
},
.Specific = Void_Specific,
.SystemDriver = Intel_Driver,
.Architecture = Arch_Sapphire_Rapids
},
[Rocketlake] = { /* 71*/
.Signature = _Rocketlake,
.Query = Query_Skylake,
.Update = PerCore_Skylake_Query,
.Start = Start_Skylake,
.Stop = Stop_Skylake,
.Exit = NULL,
.Timer = InitTimer_Skylake,
.BaseClock = BaseClock_Skylake,
.ClockMod = ClockMod_Skylake_HWP,
.TurboClock = Intel_Turbo_Config8C,
.thermalFormula = THERMAL_FORMULA_INTEL,
.voltageFormula = VOLTAGE_FORMULA_INTEL_SNB,
.powerFormula = POWER_FORMULA_INTEL,
.PCI_ids = PCI_Kabylake_ids,
.Uncore = {
.Start = Start_Uncore_Skylake,
.Stop = Stop_Uncore_Skylake,
.ClockMod = Haswell_Uncore_Ratio
},
.Specific = Void_Specific,
.SystemDriver = SKL_Driver,
.Architecture = Arch_Rocketlake
},
[Rocketlake_U] = { /* 72*/
.Signature = _Rocketlake_U,
.Query = Query_Skylake,
.Update = PerCore_Skylake_Query,
.Start = Start_Skylake,
.Stop = Stop_Skylake,
.Exit = NULL,
.Timer = InitTimer_Skylake,
.BaseClock = BaseClock_Skylake,
.ClockMod = ClockMod_Skylake_HWP,
.TurboClock = Intel_Turbo_Config8C,
.thermalFormula = THERMAL_FORMULA_INTEL,
.voltageFormula = VOLTAGE_FORMULA_INTEL_SNB,
.powerFormula = POWER_FORMULA_INTEL,
.PCI_ids = PCI_Kabylake_ids,
.Uncore = {
.Start = Start_Uncore_Skylake,
.Stop = Stop_Uncore_Skylake,
.ClockMod = Haswell_Uncore_Ratio
},
.Specific = Void_Specific,
.SystemDriver = SKL_Driver,
.Architecture = Arch_Rocketlake_U
},
[AMD_Zen] = { /* 73*/
.Signature = _AMD_Zen,
.Query = Query_AMD_Family_17h,
.Update = PerCore_AMD_Family_17h_Query,
.Start = Start_AMD_Family_17h,
.Stop = Stop_AMD_Family_17h,
.Exit = NULL,
.Timer = InitTimer_AMD_F17h_Zen,
.BaseClock = BaseClock_AMD_Family_17h,
.ClockMod = ClockMod_AMD_Zen,
.TurboClock = TurboClock_AMD_Zen,
.thermalFormula = THERMAL_FORMULA_AMD_17h,
.voltageFormula = VOLTAGE_FORMULA_AMD_17h,
.powerFormula = POWER_FORMULA_AMD_17h,
.PCI_ids = PCI_AMD_17h_ids,
.Uncore = {
.Start = NULL,
.Stop = NULL,
.ClockMod = NULL
},
.Specific = AMD_Zen_Specific,
.SystemDriver = AMD_Zen_Driver,
.Architecture = Arch_AMD_Zen
},
[AMD_Zen_APU] = { /* 74*/
.Signature = _AMD_Zen_APU,
.Query = Query_AMD_Family_17h,
.Update = PerCore_AMD_Family_17h_Query,
.Start = Start_AMD_Family_17h,
.Stop = Stop_AMD_Family_17h,
.Exit = NULL,
.Timer = InitTimer_AMD_Family_17h,
.BaseClock = BaseClock_AMD_Family_17h,
.ClockMod = ClockMod_AMD_Zen,
.TurboClock = TurboClock_AMD_Zen,
.thermalFormula = THERMAL_FORMULA_AMD_17h,
.voltageFormula = VOLTAGE_FORMULA_AMD_17h,
.powerFormula = POWER_FORMULA_AMD_17h,
.PCI_ids = PCI_AMD_17h_ids,
.Uncore = {
.Start = NULL,
.Stop = NULL,
.ClockMod = NULL
},
.Specific = AMD_Zen_APU_Specific,
.SystemDriver = AMD_Zen_Driver,
.Architecture = Arch_AMD_Zen_APU
},
[AMD_ZenPlus] = { /* 75*/
.Signature = _AMD_ZenPlus,
.Query = Query_AMD_Family_17h,
.Update = PerCore_AMD_Family_17h_Query,
.Start = Start_AMD_Family_17h,
.Stop = Stop_AMD_Family_17h,
.Exit = NULL,
.Timer = InitTimer_AMD_F17h_Zen,
.BaseClock = BaseClock_AMD_Family_17h,
.ClockMod = ClockMod_AMD_Zen,
.TurboClock = TurboClock_AMD_Zen,
.thermalFormula = THERMAL_FORMULA_AMD_17h,
.voltageFormula = VOLTAGE_FORMULA_AMD_17h,
.powerFormula = POWER_FORMULA_AMD_17h,
.PCI_ids = PCI_AMD_17h_ids,
.Uncore = {
.Start = NULL,
.Stop = NULL,
.ClockMod = NULL
},
.Specific = AMD_ZenPlus_Specific,
.SystemDriver = AMD_Zen_Driver,
.Architecture = Arch_AMD_ZenPlus
},
[AMD_ZenPlus_APU] = { /* 76*/
.Signature = _AMD_ZenPlus_APU,
.Query = Query_AMD_Family_17h,
.Update = PerCore_AMD_Family_17h_Query,
.Start = Start_AMD_Family_17h,
.Stop = Stop_AMD_Family_17h,
.Exit = NULL,
.Timer = InitTimer_AMD_F17h_Zen,
.BaseClock = BaseClock_AMD_Family_17h,
.ClockMod = ClockMod_AMD_Zen,
.TurboClock = TurboClock_AMD_Zen,
.thermalFormula = THERMAL_FORMULA_AMD_17h,
.voltageFormula = VOLTAGE_FORMULA_AMD_17h,
.powerFormula = POWER_FORMULA_AMD_17h,
.PCI_ids = PCI_AMD_17h_ids,
.Uncore = {
.Start = NULL,
.Stop = NULL,
.ClockMod = NULL
},
.Specific = AMD_ZenPlus_APU_Specific,
.SystemDriver = AMD_Zen_Driver,
.Architecture = Arch_AMD_ZenPlus_APU
},
[AMD_Zen_APU_Dali] = { /* 77*/
.Signature = _AMD_Zen_APU_Dali,
.Query = Query_AMD_Family_17h,
.Update = PerCore_AMD_Family_17h_Query,
.Start = Start_AMD_Family_17h,
.Stop = Stop_AMD_Family_17h,
.Exit = NULL,
.Timer = InitTimer_AMD_Family_17h,
.BaseClock = BaseClock_AMD_Family_17h,
.ClockMod = ClockMod_AMD_Zen,
.TurboClock = TurboClock_AMD_Zen,
.thermalFormula = THERMAL_FORMULA_AMD_17h,
.voltageFormula = VOLTAGE_FORMULA_AMD_17h,
.powerFormula = POWER_FORMULA_AMD_17h,
.PCI_ids = PCI_AMD_17h_ids,
.Uncore = {
.Start = NULL,
.Stop = NULL,
.ClockMod = NULL
},
.Specific = AMD_Zen_APU_Dali_Specific,
.SystemDriver = AMD_Zen_Driver,
.Architecture = Arch_AMD_Zen_APU_Dali
},
[AMD_EPYC_Rome] = { /* 78*/
.Signature = _AMD_EPYC_Rome,
.Query = Query_AMD_Family_17h,
.Update = PerCore_AMD_Family_17h_Query,
.Start = Start_AMD_Family_17h,
.Stop = Stop_AMD_Family_17h,
.Exit = NULL,
.Timer = InitTimer_AMD_F17h_Zen2_MP,
.BaseClock = BaseClock_AMD_Family_17h,
.ClockMod = ClockMod_AMD_Zen,
.TurboClock = TurboClock_AMD_Zen,
.thermalFormula = THERMAL_FORMULA_AMD_17h,
.voltageFormula = VOLTAGE_FORMULA_AMD_17h,
.powerFormula = POWER_FORMULA_AMD_17h,
.PCI_ids = PCI_AMD_17h_ids,
.Uncore = {
.Start = NULL,
.Stop = NULL,
.ClockMod = NULL
},
.Specific = AMD_EPYC_Rome_Specific,
.SystemDriver = AMD_Zen_Driver,
.Architecture = Arch_AMD_EPYC_Rome
},
[AMD_Zen2_CPK] = { /* 79*/
.Signature = _AMD_Zen2_CPK,
.Query = Query_AMD_Family_17h,
.Update = PerCore_AMD_Family_17h_Query,
.Start = Start_AMD_Family_17h,
.Stop = Stop_AMD_Family_17h,
.Exit = NULL,
.Timer = InitTimer_AMD_F17h_Zen2_MP,
.BaseClock = BaseClock_AMD_Family_17h,
.ClockMod = ClockMod_AMD_Zen,
.TurboClock = TurboClock_AMD_Zen,
.thermalFormula = THERMAL_FORMULA_AMD_ZEN2,
.voltageFormula = VOLTAGE_FORMULA_AMD_17h,
.powerFormula = POWER_FORMULA_AMD_17h,
.PCI_ids = PCI_AMD_17h_ids,
.Uncore = {
.Start = NULL,
.Stop = NULL,
.ClockMod = NULL
},
.Specific = AMD_Zen2_CPK_Specific,
.SystemDriver = AMD_Zen_Driver,
.Architecture = Arch_AMD_Zen2_CPK
},
[AMD_Zen2_APU] = { /* 80*/
.Signature = _AMD_Zen2_APU,
.Query = Query_AMD_Family_17h,
.Update = PerCore_AMD_Family_17h_Query,
.Start = Start_AMD_Family_17h,
.Stop = Stop_AMD_Family_17h,
.Exit = NULL,
.Timer = InitTimer_AMD_F17h_Zen2_APU,
.BaseClock = BaseClock_AMD_Family_17h,
.ClockMod = ClockMod_AMD_Zen,
.TurboClock = TurboClock_AMD_Zen,
.thermalFormula = THERMAL_FORMULA_AMD_17h,
.voltageFormula = VOLTAGE_FORMULA_AMD_17h,
.powerFormula = POWER_FORMULA_AMD_17h,
.PCI_ids = PCI_AMD_17h_ids,
.Uncore = {
.Start = NULL,
.Stop = NULL,
.ClockMod = NULL
},
.Specific = AMD_Zen2_APU_Specific,
.SystemDriver = AMD_Zen_Driver,
.Architecture = Arch_AMD_Zen2_APU
},
[AMD_Zen2_MTS] = { /* 81*/
.Signature = _AMD_Zen2_MTS,
.Query = Query_AMD_Family_17h,
.Update = PerCore_AMD_Family_17h_Query,
.Start = Start_AMD_Family_17h,
.Stop = Stop_AMD_Family_17h,
.Exit = NULL,
.Timer = InitTimer_AMD_F17h_Zen2_SP,
.BaseClock = BaseClock_AMD_Family_17h,
.ClockMod = ClockMod_AMD_Zen,
.TurboClock = TurboClock_AMD_Zen,
.thermalFormula = THERMAL_FORMULA_AMD_ZEN2,
.voltageFormula = VOLTAGE_FORMULA_AMD_17h,
.powerFormula = POWER_FORMULA_AMD_17h,
.PCI_ids = PCI_AMD_17h_ids,
.Uncore = {
.Start = NULL,
.Stop = NULL,
.ClockMod = NULL
},
.Specific = AMD_Zen2_MTS_Specific,
.SystemDriver = AMD_Zen_Driver,
.Architecture = Arch_AMD_Zen2_MTS
},
[AMD_Zen2_Xbox] = { /* 82*/
.Signature = _AMD_Zen2_Xbox,
.Query = Query_AMD_Family_17h,
.Update = PerCore_AMD_Family_17h_Query,
.Start = Start_AMD_Family_17h,
.Stop = Stop_AMD_Family_17h,
.Exit = NULL,
.Timer = InitTimer_AMD_F17h_Zen2_SP,
.BaseClock = BaseClock_AMD_Family_17h,
.ClockMod = ClockMod_AMD_Zen,
.TurboClock = TurboClock_AMD_Zen,
.thermalFormula = THERMAL_FORMULA_AMD_ZEN2,
.voltageFormula = VOLTAGE_FORMULA_AMD_17h,
.powerFormula = POWER_FORMULA_AMD_17h,
.PCI_ids = PCI_Void_ids,
.Uncore = {
.Start = NULL,
.Stop = NULL,
.ClockMod = NULL
},
.Specific = AMD_Zen2_MTS_Specific,
.SystemDriver = AMD_Zen_Driver,
.Architecture = Arch_AMD_Zen2_MTS
},
[AMD_Zen3_VMR] = { /* 83*/
.Signature = _AMD_Zen3_VMR,
.Query = Query_AMD_Family_19h,
.Update = PerCore_AMD_Family_19h_Query,
.Start = Start_AMD_Family_19h,
.Stop = Stop_AMD_Family_19h,
.Exit = NULL,
.Timer = InitTimer_AMD_F17h_Zen3_SP,
.BaseClock = BaseClock_AMD_Family_19h,
.ClockMod = ClockMod_AMD_Zen,
.TurboClock = TurboClock_AMD_Zen,
.thermalFormula = THERMAL_FORMULA_AMD_ZEN3,
.voltageFormula = VOLTAGE_FORMULA_AMD_19h,
.powerFormula = POWER_FORMULA_AMD_19h,
.PCI_ids = PCI_AMD_19h_ids,
.Uncore = {
.Start = NULL,
.Stop = NULL,
.ClockMod = NULL
},
.Specific = Void_Specific,
.SystemDriver = AMD_Zen_Driver,
.Architecture = Arch_AMD_Zen3_VMR
},
[AMD_Zen3_CZN] = { /* 84*/
.Signature = _AMD_Zen3_CZN,
.Query = Query_AMD_Family_19h,
.Update = PerCore_AMD_Family_19h_Query,
.Start = Start_AMD_Family_19h,
.Stop = Stop_AMD_Family_19h,
.Exit = NULL,
.Timer = InitTimer_AMD_F17h_Zen3_SP,
.BaseClock = BaseClock_AMD_Family_19h,
.ClockMod = ClockMod_AMD_Zen,
.TurboClock = TurboClock_AMD_Zen,
.thermalFormula = THERMAL_FORMULA_AMD_ZEN3,
.voltageFormula = VOLTAGE_FORMULA_AMD_19h,
.powerFormula = POWER_FORMULA_AMD_19h,
.PCI_ids = PCI_AMD_19h_ids,
.Uncore = {
.Start = NULL,
.Stop = NULL,
.ClockMod = NULL
},
.Specific = Void_Specific,
.SystemDriver = AMD_Zen_Driver,
.Architecture = Arch_AMD_Zen3_CZN
},
[AMD_EPYC_Milan] = { /* 85*/
.Signature = _AMD_EPYC_Milan,
.Query = Query_AMD_Family_19h,
.Update = PerCore_AMD_Family_19h_Query,
.Start = Start_AMD_Family_19h,
.Stop = Stop_AMD_Family_19h,
.Exit = NULL,
.Timer = InitTimer_AMD_F17h_Zen3_MP,
.BaseClock = BaseClock_AMD_Family_19h,
.ClockMod = ClockMod_AMD_Zen,
.TurboClock = TurboClock_AMD_Zen,
.thermalFormula = THERMAL_FORMULA_AMD_ZEN3,
.voltageFormula = VOLTAGE_FORMULA_AMD_19h,
.powerFormula = POWER_FORMULA_AMD_19h,
.PCI_ids = PCI_AMD_19h_ids,
.Uncore = {
.Start = NULL,
.Stop = NULL,
.ClockMod = NULL
},
.Specific = Void_Specific,
.SystemDriver = AMD_Zen_Driver,
.Architecture = Arch_AMD_EPYC_Milan
}
};
Raw
02.corefreqd.c
/*
* CoreFreq
* Copyright (C) 2015-2021 CYRIL INGENIERIE
* Licenses: GPL2
*/
#define _GNU_SOURCE
#include <stdlib.h>
#include <string.h>
#include <sys/mman.h>
#include <sys/ioctl.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <sys/wait.h>
#include <unistd.h>
#include <fcntl.h>
#include <time.h>
#include <stdio.h>
#include <signal.h>
#include <stdarg.h>
#include <errno.h>
#include <pthread.h>
#include "bitasm.h"
#include "amdmsr.h"
#include "intelmsr.h"
#include "coretypes.h"
#include "corefreq.h"
#include "corefreqm.h"
#include "corefreq-api.h"
#define PAGE_SIZE (sysconf(_SC_PAGESIZE))
/* §8.10.6.7 Place Locks and Semaphores in Aligned, 128-Byte Blocks of Memory */
static BitCC roomSeed __attribute__ ((aligned (16))) = InitCC(0x0);
static BitCC roomCore __attribute__ ((aligned (16))) = InitCC(0x0);
static BitCC roomClear __attribute__ ((aligned (16))) = InitCC(0x0);
static Bit64 Shutdown __attribute__ ((aligned (8))) = 0x0;
static Bit64 PendingSync __attribute__ ((aligned (8))) = 0x0;
unsigned int Quiet = 0x001, SysGateStartUp = 1;
UBENCH_DECLARE()
typedef struct
{
int Drv,
Svr;
} FD;
typedef struct {
sigset_t Signal;
pid_t CPID;
pthread_t KID;
int Started;
struct {
SLICE_FUNC Func;
unsigned long arg;
enum PATTERN pattern;
} Slice;
FD *fd;
SHM_STRUCT *Shm;
PROC_RO *Proc_RO;
PROC_RW *Proc_RW;
CORE_RO **Core_RO;
CORE_RW **Core_RW;
SYSGATE_RO *SysGate;
} REF;
void Core_ResetSensorLimits(CPU_STRUCT *Cpu)
{
RESET_SENSOR_LIMIT(THERMAL, LOWEST, Cpu->PowerThermal.Limit);
RESET_SENSOR_LIMIT(VOLTAGE, LOWEST, Cpu->Sensors.Voltage.Limit);
RESET_SENSOR_LIMIT(ENERGY, LOWEST, Cpu->Sensors.Energy.Limit);
RESET_SENSOR_LIMIT(POWER, LOWEST, Cpu->Sensors.Power.Limit);
RESET_SENSOR_LIMIT(REL_FREQ, LOWEST, Cpu->Relative.Freq);
RESET_SENSOR_LIMIT(ABS_FREQ, LOWEST, Cpu->Absolute.Freq);
RESET_SENSOR_LIMIT(THERMAL, HIGHEST, Cpu->PowerThermal.Limit);
RESET_SENSOR_LIMIT(VOLTAGE, HIGHEST, Cpu->Sensors.Voltage.Limit);
RESET_SENSOR_LIMIT(ENERGY, HIGHEST, Cpu->Sensors.Energy.Limit);
RESET_SENSOR_LIMIT(POWER, HIGHEST, Cpu->Sensors.Power.Limit);
RESET_SENSOR_LIMIT(REL_FREQ, HIGHEST, Cpu->Relative.Freq);
RESET_SENSOR_LIMIT(ABS_FREQ, HIGHEST, Cpu->Absolute.Freq);
}
void Core_ComputeThermalLimits(CPU_STRUCT *Cpu, struct FLIP_FLOP *CFlip)
{ /* Per Core, computes the Min temperature. */
TEST_AND_SET_SENSOR( THERMAL, LOWEST, CFlip->Thermal.Temp,
Cpu->PowerThermal.Limit );
/* Per Core, computes the Max temperature. */
TEST_AND_SET_SENSOR( THERMAL, HIGHEST, CFlip->Thermal.Temp,
Cpu->PowerThermal.Limit );
}
static inline void ComputeThermal_None( struct FLIP_FLOP *CFlip,
SHM_STRUCT *Shm,
unsigned int cpu )
{
UNUSED(Shm);
UNUSED(cpu);
CFlip->Thermal.Temp = 0;
}
#define ComputeThermal_None_PerSMT ComputeThermal_None
#define ComputeThermal_None_PerCore ComputeThermal_None
#define ComputeThermal_None_PerPkg ComputeThermal_None
static void (*ComputeThermal_None_Matrix[4])( struct FLIP_FLOP*,
SHM_STRUCT*,
unsigned int ) = \
{
[FORMULA_SCOPE_NONE] = ComputeThermal_None,
[FORMULA_SCOPE_SMT ] = ComputeThermal_None_PerSMT,
[FORMULA_SCOPE_CORE] = ComputeThermal_None_PerCore,
[FORMULA_SCOPE_PKG ] = ComputeThermal_None_PerPkg
};
static inline void ComputeThermal_Intel(struct FLIP_FLOP *CFlip,
SHM_STRUCT *Shm,
unsigned int cpu)
{
COMPUTE_THERMAL(INTEL,
CFlip->Thermal.Temp,
CFlip->Thermal.Param,
CFlip->Thermal.Sensor);
Core_ComputeThermalLimits(&Shm->Cpu[cpu], CFlip);
}
#define ComputeThermal_Intel_PerSMT ComputeThermal_Intel
static inline void ComputeThermal_Intel_PerCore(struct FLIP_FLOP *CFlip,
SHM_STRUCT *Shm,
unsigned int cpu)
{
if ((Shm->Cpu[cpu].Topology.ThreadID == 0)
|| (Shm->Cpu[cpu].Topology.ThreadID == -1))
{
ComputeThermal_Intel(CFlip, Shm, cpu);
}
}
static inline void ComputeThermal_Intel_PerPkg( struct FLIP_FLOP *CFlip,
SHM_STRUCT *Shm,
unsigned int cpu )
{
if (cpu == Shm->Proc.Service.Core)
{
ComputeThermal_Intel(CFlip, Shm, cpu);
}
}
static void (*ComputeThermal_Intel_Matrix[4])( struct FLIP_FLOP*,
SHM_STRUCT*,
unsigned int ) = \
{
[FORMULA_SCOPE_NONE] = ComputeThermal_None,
[FORMULA_SCOPE_SMT ] = ComputeThermal_Intel_PerSMT,
[FORMULA_SCOPE_CORE] = ComputeThermal_Intel_PerCore,
[FORMULA_SCOPE_PKG ] = ComputeThermal_Intel_PerPkg
};
static inline void ComputeThermal_AMD( struct FLIP_FLOP *CFlip,
SHM_STRUCT *Shm,
unsigned int cpu )
{
COMPUTE_THERMAL(AMD,
CFlip->Thermal.Temp,
CFlip->Thermal.Param,
CFlip->Thermal.Sensor);
Core_ComputeThermalLimits(&Shm->Cpu[cpu], CFlip);
}
#define ComputeThermal_AMD_PerSMT ComputeThermal_AMD
static inline void ComputeThermal_AMD_PerCore( struct FLIP_FLOP *CFlip,
SHM_STRUCT *Shm,
unsigned int cpu )
{
if ((Shm->Cpu[cpu].Topology.ThreadID == 0)
|| (Shm->Cpu[cpu].Topology.ThreadID == -1))
{
ComputeThermal_AMD(CFlip, Shm, cpu);
}
}
static inline void ComputeThermal_AMD_PerPkg( struct FLIP_FLOP *CFlip,
SHM_STRUCT *Shm,
unsigned int cpu )
{
if (cpu == Shm->Proc.Service.Core)
{
ComputeThermal_AMD(CFlip, Shm, cpu);
}
}
static void (*ComputeThermal_AMD_Matrix[4])( struct FLIP_FLOP*,
SHM_STRUCT*,
unsigned int ) = \
{
[FORMULA_SCOPE_NONE] = ComputeThermal_None,
[FORMULA_SCOPE_SMT ] = ComputeThermal_AMD_PerSMT,
[FORMULA_SCOPE_CORE] = ComputeThermal_AMD_PerCore,
[FORMULA_SCOPE_PKG ] = ComputeThermal_AMD_PerPkg
};
static inline void ComputeThermal_AMD_0Fh( struct FLIP_FLOP *CFlip,
SHM_STRUCT *Shm,
unsigned int cpu )
{
COMPUTE_THERMAL(AMD_0Fh,
CFlip->Thermal.Temp,
CFlip->Thermal.Param,
CFlip->Thermal.Sensor);
Core_ComputeThermalLimits(&Shm->Cpu[cpu], CFlip);
}
#define ComputeThermal_AMD_0Fh_PerSMT ComputeThermal_AMD_0Fh
static inline void ComputeThermal_AMD_0Fh_PerCore(struct FLIP_FLOP *CFlip,
SHM_STRUCT *Shm,
unsigned int cpu )
{
if ((Shm->Cpu[cpu].Topology.ThreadID == 0)
|| (Shm->Cpu[cpu].Topology.ThreadID == -1))
{
ComputeThermal_AMD_0Fh(CFlip, Shm, cpu);
}
}
static inline void ComputeThermal_AMD_0Fh_PerPkg(struct FLIP_FLOP *CFlip,
SHM_STRUCT *Shm,
unsigned int cpu )
{
if (cpu == Shm->Proc.Service.Core)
{
ComputeThermal_AMD_0Fh(CFlip, Shm, cpu);
}
}
static void (*ComputeThermal_AMD_0Fh_Matrix[4])(struct FLIP_FLOP*,
SHM_STRUCT*,
unsigned int) = \
{
[FORMULA_SCOPE_NONE] = ComputeThermal_None,
[FORMULA_SCOPE_SMT ] = ComputeThermal_AMD_0Fh_PerSMT,
[FORMULA_SCOPE_CORE] = ComputeThermal_AMD_0Fh_PerCore,
[FORMULA_SCOPE_PKG ] = ComputeThermal_AMD_0Fh_PerPkg
};
static inline void ComputeThermal_AMD_15h( struct FLIP_FLOP *CFlip,
SHM_STRUCT *Shm,
unsigned int cpu )
{
if (Shm->Cpu[cpu].Topology.CoreID == 0)
{
COMPUTE_THERMAL(AMD_15h,
CFlip->Thermal.Temp,
CFlip->Thermal.Param,
CFlip->Thermal.Sensor);
Core_ComputeThermalLimits(&Shm->Cpu[cpu], CFlip);
}
}
#define ComputeThermal_AMD_15h_PerSMT ComputeThermal_AMD_15h
static inline void ComputeThermal_AMD_15h_PerCore(struct FLIP_FLOP *CFlip,
SHM_STRUCT *Shm,
unsigned int cpu )
{
if (Shm->Cpu[cpu].Topology.CoreID == 0) /* Opteron test case */
{
ComputeThermal_AMD_15h(CFlip, Shm, cpu);
}
}
static inline void ComputeThermal_AMD_15h_PerPkg(struct FLIP_FLOP *CFlip,
SHM_STRUCT *Shm,
unsigned int cpu )
{
if (cpu == Shm->Proc.Service.Core)
{
ComputeThermal_AMD_15h(CFlip, Shm, cpu);
}
}
static void (*ComputeThermal_AMD_15h_Matrix[4])(struct FLIP_FLOP*,
SHM_STRUCT*,
unsigned int) = \
{
[FORMULA_SCOPE_NONE] = ComputeThermal_None,
[FORMULA_SCOPE_SMT ] = ComputeThermal_AMD_15h_PerSMT,
[FORMULA_SCOPE_CORE] = ComputeThermal_AMD_15h_PerCore,
[FORMULA_SCOPE_PKG ] = ComputeThermal_AMD_15h_PerPkg
};
static inline void ComputeThermal_AMD_17h( struct FLIP_FLOP *CFlip,
SHM_STRUCT *Shm,
unsigned int cpu )
{
COMPUTE_THERMAL(AMD_17h,
CFlip->Thermal.Temp,
CFlip->Thermal.Param,
CFlip->Thermal.Sensor);
Core_ComputeThermalLimits(&Shm->Cpu[cpu], CFlip);
}
#define ComputeThermal_AMD_17h_PerSMT ComputeThermal_AMD_17h
static inline void ComputeThermal_AMD_17h_PerCore(struct FLIP_FLOP *CFlip,
SHM_STRUCT *Shm,
unsigned int cpu )
{
if ((Shm->Cpu[cpu].Topology.ThreadID == 0)
|| (Shm->Cpu[cpu].Topology.ThreadID == -1))
{
ComputeThermal_AMD_17h(CFlip, Shm, cpu);
}
}
static inline void ComputeThermal_AMD_17h_PerPkg(struct FLIP_FLOP *CFlip,
SHM_STRUCT *Shm,
unsigned int cpu )
{
if (cpu == Shm->Proc.Service.Core)
{
ComputeThermal_AMD_17h(CFlip, Shm, cpu);
}
}
static void (*ComputeThermal_AMD_17h_Matrix[4])(struct FLIP_FLOP*,
SHM_STRUCT*,
unsigned int) = \
{
[FORMULA_SCOPE_NONE] = ComputeThermal_None,
[FORMULA_SCOPE_SMT ] = ComputeThermal_AMD_17h_PerSMT,
[FORMULA_SCOPE_CORE] = ComputeThermal_AMD_17h_PerCore,
[FORMULA_SCOPE_PKG ] = ComputeThermal_AMD_17h_PerPkg
};
void Core_ComputeVoltageLimits(CPU_STRUCT *Cpu, struct FLIP_FLOP *CFlip)
{ /* Per Core, computes the Min CPU voltage. */
TEST_AND_SET_SENSOR( VOLTAGE, LOWEST, CFlip->Voltage.Vcore,
Cpu->Sensors.Voltage.Limit );
/* Per Core, computes the Max CPU voltage. */
TEST_AND_SET_SENSOR( VOLTAGE, HIGHEST, CFlip->Voltage.Vcore,
Cpu->Sensors.Voltage.Limit );
}
static inline void ComputeVoltage_None( struct FLIP_FLOP *CFlip,
SHM_STRUCT *Shm,
unsigned int cpu )
{
UNUSED(CFlip);
UNUSED(Shm);
UNUSED(cpu);
}
#define ComputeVoltage_None_PerSMT ComputeVoltage_None
#define ComputeVoltage_None_PerCore ComputeVoltage_None
#define ComputeVoltage_None_PerPkg ComputeVoltage_None
static void (*ComputeVoltage_None_Matrix[4])( struct FLIP_FLOP*,
SHM_STRUCT*,
unsigned int ) = \
{
[FORMULA_SCOPE_NONE] = ComputeVoltage_None,
[FORMULA_SCOPE_SMT ] = ComputeVoltage_None_PerSMT,
[FORMULA_SCOPE_CORE] = ComputeVoltage_None_PerCore,
[FORMULA_SCOPE_PKG ] = ComputeVoltage_None_PerPkg
};
#define ComputeVoltage_Intel_Matrix ComputeVoltage_None_Matrix
static inline void ComputeVoltage_Intel_Core2( struct FLIP_FLOP *CFlip,
SHM_STRUCT *Shm,
unsigned int cpu )
{ /* Intel Core 2 Extreme Datasheet §3.3-Table 2 */
COMPUTE_VOLTAGE(INTEL_CORE2,
CFlip->Voltage.Vcore,
CFlip->Voltage.VID);
Core_ComputeVoltageLimits(&Shm->Cpu[cpu], CFlip);
}
#define ComputeVoltage_Intel_Core2_PerSMT ComputeVoltage_Intel_Core2
static inline void ComputeVoltage_Intel_Core2_PerCore( struct FLIP_FLOP *CFlip,
SHM_STRUCT *Shm,
unsigned int cpu )
{
if ((Shm->Cpu[cpu].Topology.ThreadID == 0)
|| (Shm->Cpu[cpu].Topology.ThreadID == -1))
{
ComputeVoltage_Intel_Core2(CFlip, Shm, cpu);
}
}
static inline void ComputeVoltage_Intel_Core2_PerPkg( struct FLIP_FLOP *CFlip,
SHM_STRUCT *Shm,
unsigned int cpu )
{
if (cpu == Shm->Proc.Service.Core)
{
ComputeVoltage_Intel_Core2(CFlip, Shm, cpu);
}
}
static void (*ComputeVoltage_Intel_Core2_Matrix[4])( struct FLIP_FLOP*,
SHM_STRUCT*,
unsigned int ) = \
{
[FORMULA_SCOPE_NONE] = ComputeVoltage_None,
[FORMULA_SCOPE_SMT ] = ComputeVoltage_Intel_Core2_PerSMT,
[FORMULA_SCOPE_CORE] = ComputeVoltage_Intel_Core2_PerCore,
[FORMULA_SCOPE_PKG ] = ComputeVoltage_Intel_Core2_PerPkg
};
static inline void ComputeVoltage_Intel_SoC( struct FLIP_FLOP *CFlip,
SHM_STRUCT *Shm,
unsigned int cpu )
{ /* Intel Valleyview-D/M SoC */
COMPUTE_VOLTAGE(INTEL_SOC,
CFlip->Voltage.Vcore,
CFlip->Voltage.VID);
Core_ComputeVoltageLimits(&Shm->Cpu[cpu], CFlip);
}
#define ComputeVoltage_Intel_SoC_PerSMT ComputeVoltage_Intel_SoC
static inline void ComputeVoltage_Intel_SoC_PerCore( struct FLIP_FLOP *CFlip,
SHM_STRUCT *Shm,
unsigned int cpu )
{
if ((Shm->Cpu[cpu].Topology.ThreadID == 0)
|| (Shm->Cpu[cpu].Topology.ThreadID == -1))
{
ComputeVoltage_Intel_SoC(CFlip, Shm, cpu);
}
}
static inline void ComputeVoltage_Intel_SoC_PerPkg( struct FLIP_FLOP *CFlip,
SHM_STRUCT *Shm,
unsigned int cpu )
{
if (cpu == Shm->Proc.Service.Core)
{
ComputeVoltage_Intel_SoC(CFlip, Shm, cpu);
}
}
static void (*ComputeVoltage_Intel_SoC_Matrix[4])( struct FLIP_FLOP*,
SHM_STRUCT*,
unsigned int ) = \
{
[FORMULA_SCOPE_NONE] = ComputeVoltage_None,
[FORMULA_SCOPE_SMT ] = ComputeVoltage_Intel_SoC_PerSMT,
[FORMULA_SCOPE_CORE] = ComputeVoltage_Intel_SoC_PerCore,
[FORMULA_SCOPE_PKG ] = ComputeVoltage_Intel_SoC_PerPkg
};
static inline void ComputeVoltage_Intel_SNB( struct FLIP_FLOP *CFlip,
SHM_STRUCT *Shm,
unsigned int cpu )
{
COMPUTE_VOLTAGE(INTEL_SNB,
CFlip->Voltage.Vcore,
CFlip->Voltage.VID);
Core_ComputeVoltageLimits(&Shm->Cpu[cpu], CFlip);
}
#define ComputeVoltage_Intel_SNB_PerSMT ComputeVoltage_Intel_SNB
static inline void ComputeVoltage_Intel_SNB_PerCore(struct FLIP_FLOP *CFlip,
SHM_STRUCT *Shm,
unsigned int cpu )
{
if ((Shm->Cpu[cpu].Topology.ThreadID == 0)
|| (Shm->Cpu[cpu].Topology.ThreadID == -1))
{
ComputeVoltage_Intel_SNB(CFlip, Shm, cpu);
}
}
static inline void ComputeVoltage_Intel_SNB_PerPkg(struct FLIP_FLOP *CFlip,
SHM_STRUCT *Shm,
unsigned int cpu )
{
if (cpu == Shm->Proc.Service.Core)
{
ComputeVoltage_Intel_SNB(CFlip, Shm, cpu);
}
}
static void (*ComputeVoltage_Intel_SNB_Matrix[4])( struct FLIP_FLOP*,
SHM_STRUCT*,
unsigned int ) = \
{
[FORMULA_SCOPE_NONE] = ComputeVoltage_None,
[FORMULA_SCOPE_SMT ] = ComputeVoltage_Intel_SNB_PerSMT,
[FORMULA_SCOPE_CORE] = ComputeVoltage_Intel_SNB_PerCore,
[FORMULA_SCOPE_PKG ] = ComputeVoltage_Intel_SNB_PerPkg
};
static inline void ComputeVoltage_Intel_SKL_X( struct FLIP_FLOP *CFlip,
SHM_STRUCT *Shm,
unsigned int cpu )
{
COMPUTE_VOLTAGE(INTEL_SKL_X,
CFlip->Voltage.Vcore,
CFlip->Voltage.VID);
Core_ComputeVoltageLimits(&Shm->Cpu[cpu], CFlip);
}
#define ComputeVoltage_Intel_SKL_X_PerSMT ComputeVoltage_Intel_SKL_X
static inline void ComputeVoltage_Intel_SKL_X_PerCore(struct FLIP_FLOP *CFlip,
SHM_STRUCT *Shm,
unsigned int cpu )
{
if ((Shm->Cpu[cpu].Topology.ThreadID == 0)
|| (Shm->Cpu[cpu].Topology.ThreadID == -1))
{
ComputeVoltage_Intel_SKL_X(CFlip, Shm, cpu);
}
}
static inline void ComputeVoltage_Intel_SKL_X_PerPkg(struct FLIP_FLOP *CFlip,
SHM_STRUCT *Shm,
unsigned int cpu )
{
if (cpu == Shm->Proc.Service.Core)
{
ComputeVoltage_Intel_SKL_X(CFlip, Shm, cpu);
}
}
static void (*ComputeVoltage_Intel_SKL_X_Matrix[4])( struct FLIP_FLOP*,
SHM_STRUCT*,
unsigned int ) = \
{
[FORMULA_SCOPE_NONE] = ComputeVoltage_None,
[FORMULA_SCOPE_SMT ] = ComputeVoltage_Intel_SKL_X_PerSMT,
[FORMULA_SCOPE_CORE] = ComputeVoltage_Intel_SKL_X_PerCore,
[FORMULA_SCOPE_PKG ] = ComputeVoltage_Intel_SKL_X_PerPkg
};
static inline void ComputeVoltage_AMD( struct FLIP_FLOP *CFlip,
SHM_STRUCT *Shm,
unsigned int cpu )
{
COMPUTE_VOLTAGE(AMD,
CFlip->Voltage.Vcore,
CFlip->Voltage.VID);
Core_ComputeVoltageLimits(&Shm->Cpu[cpu], CFlip);
}
#define ComputeVoltage_AMD_PerSMT ComputeVoltage_AMD
static inline void ComputeVoltage_AMD_PerCore( struct FLIP_FLOP *CFlip,
SHM_STRUCT *Shm,
unsigned int cpu )
{
if ((Shm->Cpu[cpu].Topology.ThreadID == 0)
|| (Shm->Cpu[cpu].Topology.ThreadID == -1))
{
ComputeVoltage_AMD(CFlip, Shm, cpu);
}
}
static inline void ComputeVoltage_AMD_PerPkg( struct FLIP_FLOP *CFlip,
SHM_STRUCT *Shm,
unsigned int cpu )
{
if (cpu == Shm->Proc.Service.Core)
{
ComputeVoltage_AMD(CFlip, Shm, cpu);
}
}
static void (*ComputeVoltage_AMD_Matrix[4])( struct FLIP_FLOP*,
SHM_STRUCT*,
unsigned int ) = \
{
[FORMULA_SCOPE_NONE] = ComputeVoltage_None,
[FORMULA_SCOPE_SMT ] = ComputeVoltage_AMD_PerSMT,
[FORMULA_SCOPE_CORE] = ComputeVoltage_AMD_PerCore,
[FORMULA_SCOPE_PKG ] = ComputeVoltage_AMD_PerPkg
};
static inline void ComputeVoltage_AMD_0Fh( struct FLIP_FLOP *CFlip,
SHM_STRUCT *Shm,
unsigned int cpu )
{ /* AMD BKDG Family 0Fh §10.6 Table 70 */
COMPUTE_VOLTAGE(AMD_0Fh,
CFlip->Voltage.Vcore,
CFlip->Voltage.VID);
Core_ComputeVoltageLimits(&Shm->Cpu[cpu], CFlip);
}
#define ComputeVoltage_AMD_0Fh_PerSMT ComputeVoltage_AMD_0Fh
static inline void ComputeVoltage_AMD_0Fh_PerCore(struct FLIP_FLOP *CFlip,
SHM_STRUCT *Shm,
unsigned int cpu )
{
if ((Shm->Cpu[cpu].Topology.ThreadID == 0)
|| (Shm->Cpu[cpu].Topology.ThreadID == -1))
{
ComputeVoltage_AMD_0Fh(CFlip, Shm, cpu);
}
}
static inline void ComputeVoltage_AMD_0Fh_PerPkg(struct FLIP_FLOP *CFlip,
SHM_STRUCT *Shm,
unsigned int cpu )
{
if (cpu == Shm->Proc.Service.Core)
{
ComputeVoltage_AMD_0Fh(CFlip, Shm, cpu);
}
}
static void (*ComputeVoltage_AMD_0Fh_Matrix[4])(struct FLIP_FLOP*,
SHM_STRUCT*,
unsigned int) = \
{
[FORMULA_SCOPE_NONE] = ComputeVoltage_None,
[FORMULA_SCOPE_SMT ] = ComputeVoltage_AMD_0Fh_PerSMT,
[FORMULA_SCOPE_CORE] = ComputeVoltage_AMD_0Fh_PerCore,
[FORMULA_SCOPE_PKG ] = ComputeVoltage_AMD_0Fh_PerPkg
};
static inline void ComputeVoltage_AMD_15h( struct FLIP_FLOP *CFlip,
SHM_STRUCT *Shm,
unsigned int cpu )
{
COMPUTE_VOLTAGE(AMD_15h,
CFlip->Voltage.Vcore,
CFlip->Voltage.VID);
Core_ComputeVoltageLimits(&Shm->Cpu[cpu], CFlip);
}
#define ComputeVoltage_AMD_15h_PerSMT ComputeVoltage_AMD_15h
static inline void ComputeVoltage_AMD_15h_PerCore(struct FLIP_FLOP *CFlip,
SHM_STRUCT *Shm,
unsigned int cpu )
{
if ((Shm->Cpu[cpu].Topology.ThreadID == 0)
|| (Shm->Cpu[cpu].Topology.ThreadID == -1))
{
ComputeVoltage_AMD_15h(CFlip, Shm, cpu);
}
}
static inline void ComputeVoltage_AMD_15h_PerPkg(struct FLIP_FLOP *CFlip,
SHM_STRUCT *Shm,
unsigned int cpu )
{
if (cpu == Shm->Proc.Service.Core)
{
ComputeVoltage_AMD_15h(CFlip, Shm, cpu);
}
}
static void (*ComputeVoltage_AMD_15h_Matrix[4])(struct FLIP_FLOP*,
SHM_STRUCT*,
unsigned int) = \
{
[FORMULA_SCOPE_NONE] = ComputeVoltage_None,
[FORMULA_SCOPE_SMT ] = ComputeVoltage_AMD_15h_PerSMT,
[FORMULA_SCOPE_CORE] = ComputeVoltage_AMD_15h_PerCore,
[FORMULA_SCOPE_PKG ] = ComputeVoltage_AMD_15h_PerPkg
};
static inline void ComputeVoltage_AMD_17h( struct FLIP_FLOP *CFlip,
SHM_STRUCT *Shm,
unsigned int cpu )
{
COMPUTE_VOLTAGE(AMD_17h,
CFlip->Voltage.Vcore,
CFlip->Voltage.VID);
Core_ComputeVoltageLimits(&Shm->Cpu[cpu], CFlip);
}
#define ComputeVoltage_AMD_17h_PerSMT ComputeVoltage_AMD_17h
static inline void ComputeVoltage_AMD_17h_PerCore(struct FLIP_FLOP *CFlip,
SHM_STRUCT *Shm,
unsigned int cpu )
{
if ((Shm->Cpu[cpu].Topology.ThreadID == 0)
|| (Shm->Cpu[cpu].Topology.ThreadID == -1))
{
ComputeVoltage_AMD_17h(CFlip, Shm, cpu);
}
}
static inline void ComputeVoltage_AMD_17h_PerPkg(struct FLIP_FLOP *CFlip,
SHM_STRUCT *Shm,
unsigned int cpu )
{
if (cpu == Shm->Proc.Service.Core)
{
ComputeVoltage_AMD_17h(CFlip, Shm, cpu);
}
}
static void (*ComputeVoltage_AMD_17h_Matrix[4])(struct FLIP_FLOP*,
SHM_STRUCT*,
unsigned int) = \
{
[FORMULA_SCOPE_NONE] = ComputeVoltage_None,
[FORMULA_SCOPE_SMT ] = ComputeVoltage_AMD_17h_PerSMT,
[FORMULA_SCOPE_CORE] = ComputeVoltage_AMD_17h_PerCore,
[FORMULA_SCOPE_PKG ] = ComputeVoltage_AMD_17h_PerPkg
};
static inline void ComputeVoltage_Winbond_IO( struct FLIP_FLOP *CFlip,
SHM_STRUCT *Shm,
unsigned int cpu )
{ /* Winbond W83627EHF/EF, W83627EHG,EG */
COMPUTE_VOLTAGE(WINBOND_IO,
CFlip->Voltage.Vcore,
CFlip->Voltage.VID);
Core_ComputeVoltageLimits(&Shm->Cpu[cpu], CFlip);
}
#define ComputeVoltage_Winbond_IO_PerSMT ComputeVoltage_Winbond_IO
static inline void ComputeVoltage_Winbond_IO_PerCore(struct FLIP_FLOP *CFlip,
SHM_STRUCT *Shm,
unsigned int cpu )
{
if ((Shm->Cpu[cpu].Topology.ThreadID == 0)
|| (Shm->Cpu[cpu].Topology.ThreadID == -1))
{
ComputeVoltage_Winbond_IO(CFlip, Shm, cpu);
}
}
static inline void ComputeVoltage_Winbond_IO_PerPkg(struct FLIP_FLOP *CFlip,
SHM_STRUCT *Shm,
unsigned int cpu )
{
if (cpu == Shm->Proc.Service.Core)
{
ComputeVoltage_Winbond_IO(CFlip, Shm, cpu);
}
}
static void (*ComputeVoltage_Winbond_IO_Matrix[4])( struct FLIP_FLOP*,
SHM_STRUCT*,
unsigned int ) = \
{
[FORMULA_SCOPE_NONE] = ComputeVoltage_None,
[FORMULA_SCOPE_SMT ] = ComputeVoltage_Winbond_IO_PerSMT,
[FORMULA_SCOPE_CORE] = ComputeVoltage_Winbond_IO_PerCore,
[FORMULA_SCOPE_PKG ] = ComputeVoltage_Winbond_IO_PerPkg
};
static inline void ComputeVoltage_ITE_Tech_IO( struct FLIP_FLOP *CFlip,
SHM_STRUCT *Shm,
unsigned int cpu )
{ /* ITE Tech IT8720F */
COMPUTE_VOLTAGE(ITETECH_IO,
CFlip->Voltage.Vcore,
CFlip->Voltage.VID);
Core_ComputeVoltageLimits(&Shm->Cpu[cpu], CFlip);
}
#define ComputeVoltage_ITE_Tech_IO_PerSMT ComputeVoltage_ITE_Tech_IO
static inline void ComputeVoltage_ITE_Tech_IO_PerCore(struct FLIP_FLOP *CFlip,
SHM_STRUCT *Shm,
unsigned int cpu )
{
if ((Shm->Cpu[cpu].Topology.ThreadID == 0)
|| (Shm->Cpu[cpu].Topology.ThreadID == -1))
{
ComputeVoltage_ITE_Tech_IO(CFlip, Shm, cpu);
}
}
static inline void ComputeVoltage_ITE_Tech_IO_PerPkg(struct FLIP_FLOP *CFlip,
SHM_STRUCT *Shm,
unsigned int cpu )
{
if (cpu == Shm->Proc.Service.Core)
{
ComputeVoltage_ITE_Tech_IO(CFlip, Shm, cpu);
}
}
static void (*ComputeVoltage_ITE_Tech_IO_Matrix[4])( struct FLIP_FLOP*,
SHM_STRUCT*,
unsigned int ) = \
{
[FORMULA_SCOPE_NONE] = ComputeVoltage_None,
[FORMULA_SCOPE_SMT ] = ComputeVoltage_ITE_Tech_IO_PerSMT,
[FORMULA_SCOPE_CORE] = ComputeVoltage_ITE_Tech_IO_PerCore,
[FORMULA_SCOPE_PKG ] = ComputeVoltage_ITE_Tech_IO_PerPkg
};
void Core_ComputePowerLimits(CPU_STRUCT *Cpu, struct FLIP_FLOP *CFlip)
{ /* Per Core, computes the Min CPU Energy consumed. */
TEST_AND_SET_SENSOR( ENERGY, LOWEST, CFlip->State.Energy,
Cpu->Sensors.Energy.Limit );
/* Per Core, computes the Max CPU Energy consumed. */
TEST_AND_SET_SENSOR( ENERGY, HIGHEST, CFlip->State.Energy,
Cpu->Sensors.Energy.Limit );
/* Per Core, computes the Min CPU Power consumed. */
TEST_AND_SET_SENSOR( POWER, LOWEST, CFlip->State.Power,
Cpu->Sensors.Power.Limit);
/* Per Core, computes the Max CPU Power consumed. */
TEST_AND_SET_SENSOR( POWER, HIGHEST, CFlip->State.Power,
Cpu->Sensors.Power.Limit );
}
static inline void ComputePower_None( struct FLIP_FLOP *CFlip,
SHM_STRUCT *Shm,
unsigned int cpu )
{
UNUSED(CFlip);
UNUSED(Shm);
UNUSED(cpu);
}
#define ComputePower_None_PerSMT ComputePower_None
#define ComputePower_None_PerCore ComputePower_None
#define ComputePower_None_PerPkg ComputePower_None
static void (*ComputePower_None_Matrix[4])( struct FLIP_FLOP*,
SHM_STRUCT*,
unsigned int ) = \
{
[FORMULA_SCOPE_NONE] = ComputePower_None,
[FORMULA_SCOPE_SMT ] = ComputePower_None_PerSMT,
[FORMULA_SCOPE_CORE] = ComputePower_None_PerCore,
[FORMULA_SCOPE_PKG ] = ComputePower_None_PerPkg
};
#define ComputePower_Intel_Matrix ComputePower_None_Matrix
#define ComputePower_Intel_Atom_Matrix ComputePower_None_Matrix
#define ComputePower_AMD_Matrix ComputePower_None_Matrix
static inline void ComputePower_AMD_17h(struct FLIP_FLOP *CFlip,
SHM_STRUCT *Shm,
unsigned int cpu)
{
CFlip->State.Energy = (double) CFlip->Delta.Power.ACCU
* Shm->Proc.Power.Unit.Joules;
CFlip->State.Power = (1000.0 * CFlip->State.Energy)
/ (double) Shm->Sleep.Interval;
Core_ComputePowerLimits(&Shm->Cpu[cpu], CFlip);
}
#define ComputePower_AMD_17h_PerSMT ComputePower_AMD_17h
static inline void ComputePower_AMD_17h_PerCore(struct FLIP_FLOP *CFlip,
SHM_STRUCT *Shm,
unsigned int cpu)
{
if ((Shm->Cpu[cpu].Topology.ThreadID == 0)
|| (Shm->Cpu[cpu].Topology.ThreadID == -1))
{
ComputePower_AMD_17h(CFlip, Shm, cpu);
}
}
static inline void ComputePower_AMD_17h_PerPkg( struct FLIP_FLOP *CFlip,
SHM_STRUCT *Shm,
unsigned int cpu )
{
if (cpu == Shm->Proc.Service.Core)
{
ComputePower_AMD_17h(CFlip, Shm, cpu);
}
}
static void (*ComputePower_AMD_17h_Matrix[4])( struct FLIP_FLOP*,
SHM_STRUCT*,
unsigned int ) = \
{
[FORMULA_SCOPE_NONE] = ComputePower_None,
[FORMULA_SCOPE_SMT ] = ComputePower_AMD_17h_PerSMT,
[FORMULA_SCOPE_CORE] = ComputePower_AMD_17h_PerCore,
[FORMULA_SCOPE_PKG ] = ComputePower_AMD_17h_PerPkg
};
typedef struct {
REF *Ref;
unsigned int Bind;
pthread_t TID;
} ARG;
static void *Core_Cycle(void *arg)
{
ARG *Arg = (ARG *) arg;
unsigned int cpu = Arg->Bind;
SHM_STRUCT *Shm = Arg->Ref->Shm;
CORE_RO *Core = Arg->Ref->Core_RO[cpu];
CORE_RW *Core_RW = Arg->Ref->Core_RW[cpu];
CPU_STRUCT *Cpu = &Shm->Cpu[cpu];
pthread_t tid = pthread_self();
cpu_set_t cpuset;
CPU_ZERO(&cpuset);
CPU_SET(cpu, &cpuset);
if (pthread_setaffinity_np(tid, sizeof(cpu_set_t), &cpuset) != 0) {
goto EXIT;
}
char *comm = malloc(TASK_COMM_LEN+10+1);
if (comm != NULL) {
snprintf(comm, TASK_COMM_LEN+10+1, "corefreqd/%u", cpu);
pthread_setname_np(tid, comm);
free(comm);
}
void (**ComputeThermalFormula)( struct FLIP_FLOP*,
SHM_STRUCT*,
unsigned int );
void (**ComputeVoltageFormula)( struct FLIP_FLOP*,
SHM_STRUCT*,
unsigned int );
void (**ComputePowerFormula)( struct FLIP_FLOP*,
SHM_STRUCT*,
unsigned int );
switch (KIND_OF_FORMULA(Shm->Proc.thermalFormula)) {
case THERMAL_KIND_INTEL:
ComputeThermalFormula = ComputeThermal_Intel_Matrix;
break;
case THERMAL_KIND_AMD:
ComputeThermalFormula = ComputeThermal_AMD_Matrix;
break;
case THERMAL_KIND_AMD_0Fh:
ComputeThermalFormula = ComputeThermal_AMD_0Fh_Matrix;
break;
case THERMAL_KIND_AMD_15h:
ComputeThermalFormula = ComputeThermal_AMD_15h_Matrix;
break;
case THERMAL_KIND_AMD_17h:
ComputeThermalFormula = ComputeThermal_AMD_17h_Matrix;
break;
case THERMAL_KIND_NONE:
default:
ComputeThermalFormula = ComputeThermal_None_Matrix;
break;
}
switch (KIND_OF_FORMULA(Shm->Proc.voltageFormula)) {
case VOLTAGE_KIND_INTEL:
ComputeVoltageFormula = ComputeVoltage_Intel_Matrix;
break;
case VOLTAGE_KIND_INTEL_CORE2:
ComputeVoltageFormula = ComputeVoltage_Intel_Core2_Matrix;
break;
case VOLTAGE_KIND_INTEL_SOC:
ComputeVoltageFormula = ComputeVoltage_Intel_SoC_Matrix;
break;
case VOLTAGE_KIND_INTEL_SNB:
ComputeVoltageFormula = ComputeVoltage_Intel_SNB_Matrix;
break;
case VOLTAGE_KIND_INTEL_SKL_X:
ComputeVoltageFormula = ComputeVoltage_Intel_SKL_X_Matrix;
break;
case VOLTAGE_KIND_AMD:
ComputeVoltageFormula = ComputeVoltage_AMD_Matrix;
break;
case VOLTAGE_KIND_AMD_0Fh:
ComputeVoltageFormula = ComputeVoltage_AMD_0Fh_Matrix;
break;
case VOLTAGE_KIND_AMD_15h:
ComputeVoltageFormula = ComputeVoltage_AMD_15h_Matrix;
break;
case VOLTAGE_KIND_AMD_17h:
ComputeVoltageFormula = ComputeVoltage_AMD_17h_Matrix;
break;
case VOLTAGE_KIND_WINBOND_IO:
ComputeVoltageFormula = ComputeVoltage_Winbond_IO_Matrix;
break;
case VOLTAGE_KIND_ITETECH_IO:
ComputeVoltageFormula = ComputeVoltage_ITE_Tech_IO_Matrix;
break;
case VOLTAGE_KIND_NONE:
default:
ComputeVoltageFormula = ComputeVoltage_None_Matrix;
break;
}
switch (KIND_OF_FORMULA(Shm->Proc.powerFormula)) {
case POWER_KIND_INTEL:
ComputePowerFormula = ComputePower_Intel_Matrix;
break;
case POWER_KIND_INTEL_ATOM:
ComputePowerFormula = ComputePower_Intel_Atom_Matrix;
break;
case POWER_KIND_AMD:
ComputePowerFormula = ComputePower_AMD_Matrix;
break;
case POWER_KIND_AMD_17h:
ComputePowerFormula = ComputePower_AMD_17h_Matrix;
break;
case POWER_KIND_NONE:
default:
ComputePowerFormula = ComputePower_None_Matrix;
break;
}
if (Quiet & 0x100) {
printf(" Thread [%lx] Init CYCLE %03u\n", tid, cpu);
fflush(stdout);
}
BITSET_CC(BUS_LOCK, roomSeed, cpu);
BITSET_CC(BUS_LOCK, roomCore, cpu);
do {
double dTSC, dUCC, dURC, dINST, dC3, dC6, dC7, dC1;
while (!BITCLR(LOCKLESS, Core_RW->Sync.V, NTFY)
&& !BITVAL(Shutdown, SYNC)
&& !BITVAL(Core->OffLine, OS)) {
nanosleep(&Shm->Sleep.pollingWait, NULL);
}
if (!BITVAL(Shutdown, SYNC) && !BITVAL(Core->OffLine, OS))
{
if (BITCLR_CC(BUS_LOCK, roomCore, cpu)) {
Cpu->Toggle = !Cpu->Toggle;
}
struct FLIP_FLOP *CFlip = &Cpu->FlipFlop[Cpu->Toggle];
/* Refresh this Base Clock. */
CFlip->Clock.Q = Core->Clock.Q;
CFlip->Clock.R = Core->Clock.R;
CFlip->Clock.Hz = Core->Clock.Hz;
/* Copy the Performance & C-States Counters. */
CFlip->Delta.INST = Core->Delta.INST;
CFlip->Delta.C0.UCC = Core->Delta.C0.UCC;
CFlip->Delta.C0.URC = Core->Delta.C0.URC;
CFlip->Delta.C3 = Core->Delta.C3;
CFlip->Delta.C6 = Core->Delta.C6;
CFlip->Delta.C7 = Core->Delta.C7;
CFlip->Delta.TSC = Core->Delta.TSC;
CFlip->Delta.C1 = Core->Delta.C1;
dTSC = (double) CFlip->Delta.TSC;
dUCC = (double) CFlip->Delta.C0.UCC;
dURC = (double) CFlip->Delta.C0.URC;
dINST = (double) CFlip->Delta.INST;
dC3 = (double) CFlip->Delta.C3;
dC6 = (double) CFlip->Delta.C6;
dC7 = (double) CFlip->Delta.C7;
dC1 = (double) CFlip->Delta.C1;
/* Compute IPS=Instructions per TSC */
CFlip->State.IPS = dINST / dTSC;
/* Compute IPC=Instructions per non-halted reference cycle.
( Protect against a division by zero ) */
CFlip->State.IPC = (CFlip->Delta.C0.URC != 0) ? dINST / dURC : 0.0f;
/* Compute CPI=Non-halted reference cycles per instruction.
( Protect against a division by zero ) */
CFlip->State.CPI = (CFlip->Delta.INST != 0) ? dURC / dINST : 0.0f;
/* Compute the Turbo State. */
CFlip->State.Turbo = dUCC / dTSC;
/* Compute the C-States. */
CFlip->State.C0 = dURC / dTSC;
CFlip->State.C3 = dC3 / dTSC;
CFlip->State.C6 = dC6 / dTSC;
CFlip->State.C7 = dC7 / dTSC;
CFlip->State.C1 = dC1 / dTSC;
/* Update all clock ratios. */
memcpy(Cpu->Boost, Core->Boost, (BOOST(SIZE)) * sizeof(unsigned int));
/* Relative Frequency = Relative Ratio x Bus Clock Frequency */
CFlip->Relative.Ratio = (dUCC * Cpu->Boost[BOOST(MAX)]) / dTSC;
CFlip->Relative.Freq = (double) REL_FREQ_MHz( CFlip->Relative.Ratio,
Core->Clock,
Shm->Sleep.Interval );
/* Per Core, compute the Relative Frequency limits. */
TEST_AND_SET_SENSOR( REL_FREQ, LOWEST, CFlip->Relative.Freq,
Cpu->Relative.Freq );
TEST_AND_SET_SENSOR( REL_FREQ, HIGHEST, CFlip->Relative.Freq,
Cpu->Relative.Freq );
/* Per Core, evaluate thermal properties. */
CFlip->Thermal.Sensor = Core->PowerThermal.Sensor;
CFlip->Thermal.Events = Core->PowerThermal.Events;
CFlip->Thermal.Param = Core->PowerThermal.Param;
ComputeThermalFormula[SCOPE_OF_FORMULA(Shm->Proc.thermalFormula)](
CFlip, Shm, cpu
);
/* Per Core, evaluate the voltage properties. */
CFlip->Voltage.VID = Core->PowerThermal.VID;
ComputeVoltageFormula[SCOPE_OF_FORMULA(Shm->Proc.voltageFormula)](
CFlip, Shm, cpu
);
/* Per Core, evaluate the Power properties. */
CFlip->Delta.Power.ACCU = Core->Delta.Power.ACCU;
ComputePowerFormula[SCOPE_OF_FORMULA(Shm->Proc.powerFormula)](
CFlip, Shm, cpu
);
/* Copy the Interrupts counters. */
CFlip->Counter.SMI = Core->Interrupt.SMI;
/* If driver registered, copy any NMI counter. */
if (BITVAL(Shm->Registration.NMI, BIT_NMI_LOCAL) == 1) {
CFlip->Counter.NMI.LOCAL = Core->Interrupt.NMI.LOCAL;
}
if (BITVAL(Shm->Registration.NMI, BIT_NMI_UNKNOWN) == 1) {
CFlip->Counter.NMI.UNKNOWN = Core->Interrupt.NMI.UNKNOWN;
}
if (BITVAL(Shm->Registration.NMI, BIT_NMI_SERR) == 1) {
CFlip->Counter.NMI.PCISERR = Core->Interrupt.NMI.PCISERR;
}
if (BITVAL(Shm->Registration.NMI, BIT_NMI_IO_CHECK) == 1) {
CFlip->Counter.NMI.IOCHECK = Core->Interrupt.NMI.IOCHECK;
}
CFlip->Absolute.Ratio.Perf = Core->Ratio.Perf;
CFlip->Absolute.Freq = ABS_FREQ_MHz(
__typeof__(CFlip->Absolute.Freq),
Core->Ratio.Perf, CFlip->Clock
);
/* Per Core, compute the Absolute Frequency limits. */
TEST_AND_SET_SENSOR( ABS_FREQ, LOWEST, CFlip->Absolute.Freq,
Cpu->Absolute.Freq );
TEST_AND_SET_SENSOR( ABS_FREQ, HIGHEST, CFlip->Absolute.Freq,
Cpu->Absolute.Freq );
}
} while (!BITVAL(Shutdown, SYNC) && !BITVAL(Core->OffLine, OS)) ;
BITCLR_CC(BUS_LOCK, roomCore, cpu);
BITCLR_CC(BUS_LOCK, roomSeed, cpu);
EXIT:
if (Quiet & 0x100) {
printf(" Thread [%lx] %s CYCLE %03u\n", tid,
BITVAL(Core->OffLine, OS) ? "Offline" : "Shutdown",cpu);
fflush(stdout);
}
return (NULL);
}
void SliceScheduling(SHM_STRUCT *Shm, unsigned int cpu, enum PATTERN pattern)
{
unsigned int seek;
switch (pattern) {
case RESET_CSP:
for (seek = 0; seek < Shm->Proc.CPU.Count; seek++) {
if (seek == Shm->Proc.Service.Core) {
BITSET_CC(LOCKLESS, Shm->roomSched, seek);
} else {
BITCLR_CC(LOCKLESS, Shm->roomSched, seek);
}
}
break;
case ALL_SMT:
if (cpu == Shm->Proc.Service.Core) {
BITSTOR_CC(LOCKLESS, Shm->roomSched, roomSeed);
}
break;
case RAND_SMT:
do {
seek = (unsigned int) rand();
seek = seek % Shm->Proc.CPU.Count;
} while (BITVAL(Shm->Cpu[seek].OffLine, OS));
BITCLR_CC(LOCKLESS, Shm->roomSched, cpu);
BITSET_CC(LOCKLESS, Shm->roomSched, seek);
break;
case RR_SMT:
seek = cpu;
do {
seek++;
if (seek >= Shm->Proc.CPU.Count) {
seek = 0;
}
} while (BITVAL(Shm->Cpu[seek].OffLine, OS));
BITCLR_CC(LOCKLESS, Shm->roomSched, cpu);
BITSET_CC(LOCKLESS, Shm->roomSched, seek);
break;
case USR_CPU:
/* NOP */
break;
}
}
static void *Child_Thread(void *arg)
{
ARG *Arg = (ARG *) arg;
unsigned int cpu = Arg->Bind;
SHM_STRUCT *Shm = Arg->Ref->Shm;
CPU_STRUCT *Cpu = &Shm->Cpu[cpu];
CALL_FUNC MatrixCallFunc[2][2] = {
{ CallWith_RDTSC_No_RDPMC, CallWith_RDTSC_RDPMC },
{ CallWith_RDTSCP_No_RDPMC, CallWith_RDTSCP_RDPMC }
};
const int withTSCP = ((Shm->Proc.Features.AdvPower.EDX.Inv_TSC == 1)
|| (Shm->Proc.Features.ExtInfo.EDX.RDTSCP == 1)),
withRDPMC = ((Shm->Proc.Features.Info.Vendor.CRC == CRC_INTEL)
&& (Shm->Proc.PM_version >= 1)
&& (BITVAL(Cpu->SystemRegister.CR4, CR4_PCE) == 1));
CALL_FUNC CallSliceFunc = MatrixCallFunc[withTSCP][withRDPMC];
pthread_t tid = pthread_self();
cpu_set_t cpuset;
CPU_ZERO(&cpuset);
CPU_SET(cpu, &cpuset);
if (pthread_setaffinity_np(tid, sizeof(cpu_set_t), &cpuset) != 0) {
goto EXIT;
}
char *comm = malloc(TASK_COMM_LEN+10+1);
if (comm != NULL) {
snprintf(comm, TASK_COMM_LEN+10+1, "corefreqd#%u", cpu);
pthread_setname_np(tid, comm);
free(comm);
}
if (Quiet & 0x100) {
printf(" Thread [%lx] Init CHILD %03u\n", tid, cpu);
fflush(stdout);
}
BITSET_CC(BUS_LOCK, roomSeed, cpu);
do {
while (!BITVAL(Shm->Proc.Sync, BURN)
&& !BITVAL(Shutdown, SYNC)
&& !BITVAL(Cpu->OffLine, OS)) {
nanosleep(&Shm->Sleep.sliceWaiting, NULL);
}
BITSET_CC(BUS_LOCK, roomCore, cpu);
RESET_Slice(Cpu->Slice);
while ( BITVAL(Shm->Proc.Sync, BURN)
&& !BITVAL(Shutdown, SYNC) )
{
if (BITVAL_CC(Shm->roomSched, cpu)) {
CallSliceFunc( Shm, cpu,
Arg->Ref->Slice.Func,
Arg->Ref->Slice.arg);
SliceScheduling(Shm, cpu, Arg->Ref->Slice.pattern);
if (BITVAL(Cpu->OffLine, OS)) {/* ReSchedule to Service */
SliceScheduling(Shm, Shm->Proc.Service.Core, RESET_CSP);
break;
}
} else {
nanosleep(&Shm->Sleep.sliceWaiting, NULL);
if (BITVAL(Cpu->OffLine, OS)) {
break;
}
}
}
BITCLR_CC(BUS_LOCK, roomCore, cpu);
} while (!BITVAL(Shutdown, SYNC) && !BITVAL(Cpu->OffLine, OS)) ;
BITCLR_CC(BUS_LOCK, roomSeed, cpu);
RESET_Slice(Cpu->Slice);
EXIT:
if (Quiet & 0x100) {
printf(" Thread [%lx] %s CHILD %03u\n", tid,
BITVAL(Cpu->OffLine, OS) ? "Offline" : "Shutdown",cpu);
fflush(stdout);
}
return (NULL);
}
void Architecture(SHM_STRUCT *Shm, PROC_RO *Proc_RO)
{
signed long ix;
Bit32 fTSC = Proc_RO->Features.Std.EDX.TSC,
aTSC = Proc_RO->Features.AdvPower.EDX.Inv_TSC;
/* Copy all initial CPUID features. */
memcpy(&Shm->Proc.Features, &Proc_RO->Features, sizeof(FEATURES));
/* Copy the fomula identifiers */
Shm->Proc.thermalFormula = Proc_RO->thermalFormula;
Shm->Proc.voltageFormula = Proc_RO->voltageFormula;
Shm->Proc.powerFormula = Proc_RO->powerFormula;
/* Copy the numbers of total & online CPU. */
Shm->Proc.CPU.Count = Proc_RO->CPU.Count;
Shm->Proc.CPU.OnLine = Proc_RO->CPU.OnLine;
Shm->Proc.Service.Proc = Proc_RO->Service.Proc;
/* Architecture and Hypervisor identifiers. */
Shm->Proc.ArchID = Proc_RO->ArchID;
Shm->Proc.HypervisorID = Proc_RO->HypervisorID;
/* Copy the Architecture name. */
StrCopy(Shm->Proc.Architecture, Proc_RO->Architecture, CODENAME_LEN);
/* Make the processor's brand string with no trailing spaces */
ix = BRAND_LENGTH;
do {
if ((Proc_RO->Features.Info.Brand[ix] == 0x20)
|| (Proc_RO->Features.Info.Brand[ix] == 0x0)) {
ix--;
} else {
break;
}
} while (ix != 0);
Shm->Proc.Brand[1 + ix] = '\0';
for (; ix >= 0; ix--) {
Shm->Proc.Brand[ix] = Proc_RO->Features.Info.Brand[ix];
}
/* Compute the TSC mode: None, Variant, Invariant */
Shm->Proc.Features.InvariantTSC = fTSC << aTSC;
}
void PerformanceMonitoring(SHM_STRUCT *Shm, PROC_RO *Proc_RO)
{
Shm->Proc.PM_version = Proc_RO->Features.PerfMon.EAX.Version;
}
void HyperThreading(SHM_STRUCT *Shm, PROC_RO *Proc_RO)
{ /* Update the HyperThreading state */
Shm->Proc.Features.HyperThreading = Proc_RO->Features.HTT_Enable;
}
void PowerInterface(SHM_STRUCT *Shm, PROC_RO *Proc_RO)
{
unsigned short pwrUnits = 0, pwrVal;
enum PWR_DOMAIN pw;
switch (KIND_OF_FORMULA(Proc_RO->powerFormula)) {
case POWER_KIND_INTEL:
case POWER_KIND_AMD:
case POWER_KIND_AMD_17h:
Shm->Proc.Power.Unit.Watts = Proc_RO->PowerThermal.Unit.PU > 0 ?
1.0 / (double) (1 << Proc_RO->PowerThermal.Unit.PU) : 0;
Shm->Proc.Power.Unit.Joules= Proc_RO->PowerThermal.Unit.ESU > 0 ?
1.0 / (double)(1 << Proc_RO->PowerThermal.Unit.ESU) : 0;
TIME_UNIT:
Shm->Proc.Power.Unit.Times = Proc_RO->PowerThermal.Unit.TU > 0 ?
1.0 / (double) (1 << Proc_RO->PowerThermal.Unit.TU)
: 1.0 / (double) (1 << 10);
pwrUnits = 2 << (Proc_RO->PowerThermal.Unit.PU - 1);
break;
case POWER_KIND_INTEL_ATOM:
Shm->Proc.Power.Unit.Watts = Proc_RO->PowerThermal.Unit.PU > 0 ?
0.001 / (double)(1 << Proc_RO->PowerThermal.Unit.PU) :0;
Shm->Proc.Power.Unit.Joules= Proc_RO->PowerThermal.Unit.ESU > 0 ?
0.001 / (double)(1 << Proc_RO->PowerThermal.Unit.ESU):0;
goto TIME_UNIT;
break;
case POWER_KIND_NONE:
break;
}
if ( (Shm->Proc.Features.Info.Vendor.CRC == CRC_AMD)
|| (Shm->Proc.Features.Info.Vendor.CRC == CRC_HYGON) )
{ /* AMD PowerNow */
if (Proc_RO->Features.AdvPower.EDX.FID) {
BITSET(LOCKLESS, Shm->Proc.PowerNow, 0);
} else {
BITCLR(LOCKLESS, Shm->Proc.PowerNow, 0);
}
if (Proc_RO->Features.AdvPower.EDX.VID) {
BITSET(LOCKLESS, Shm->Proc.PowerNow, 1);
} else {
BITCLR(LOCKLESS, Shm->Proc.PowerNow, 1);
}
Shm->Proc.Power.PPT = Proc_RO->PowerThermal.Zen.PWR.PPT;
Shm->Proc.Power.TDP = Proc_RO->PowerThermal.Zen.TDP.TDP;
Shm->Proc.Power.Min = Proc_RO->PowerThermal.Zen.TDP.TDP2;
Shm->Proc.Power.Max = Proc_RO->PowerThermal.Zen.TDP.TDP3;
Shm->Proc.Power.EDC = Proc_RO->PowerThermal.Zen.EDC.EDC << 2;
Shm->Proc.Power.TDC = Proc_RO->PowerThermal.Zen.EDC.TDC;
for (pw = PWR_DOMAIN(PKG); pw < PWR_DOMAIN(SIZE); pw++)
{
Shm->Proc.Power.Domain[pw].Feature[PL1].Enable = \
Proc_RO->PowerThermal.PowerLimit[pw].Enable_Limit1;
Shm->Proc.Power.Domain[pw].Feature[PL2].Enable = \
Proc_RO->PowerThermal.PowerLimit[pw].Enable_Limit2;
Shm->Proc.Power.Domain[pw].Feature[PL1].Clamping = \
Proc_RO->PowerThermal.PowerLimit[pw].Clamping1;
Shm->Proc.Power.Domain[pw].Feature[PL2].Clamping = \
Proc_RO->PowerThermal.PowerLimit[pw].Clamping2;
pwrVal = Proc_RO->PowerThermal.PowerLimit[pw].Domain_Limit1;
Shm->Proc.Power.Domain[pw].PL1 = pwrVal;
pwrVal = Proc_RO->PowerThermal.PowerLimit[pw].Domain_Limit2;
Shm->Proc.Power.Domain[pw].PL2 = pwrVal;
}
}
else if (Shm->Proc.Features.Info.Vendor.CRC == CRC_INTEL)
{
if (pwrUnits != 0)
{
for (pw = PWR_DOMAIN(PKG); pw < PWR_DOMAIN(SIZE); pw++)
{
Shm->Proc.Power.Domain[pw].Feature[PL1].Enable = \
Proc_RO->PowerThermal.PowerLimit[pw].Enable_Limit1;
Shm->Proc.Power.Domain[pw].Feature[PL2].Enable = \
Proc_RO->PowerThermal.PowerLimit[pw].Enable_Limit2;
Shm->Proc.Power.Domain[pw].Feature[PL1].Clamping = \
Proc_RO->PowerThermal.PowerLimit[pw].Clamping1;
Shm->Proc.Power.Domain[pw].Feature[PL2].Clamping = \
Proc_RO->PowerThermal.PowerLimit[pw].Clamping2;
pwrVal = Proc_RO->PowerThermal.PowerLimit[pw].Domain_Limit1 / pwrUnits;
Shm->Proc.Power.Domain[pw].PL1 = pwrVal;
pwrVal = Proc_RO->PowerThermal.PowerLimit[pw].Domain_Limit2 / pwrUnits;
Shm->Proc.Power.Domain[pw].PL2 = pwrVal;
}
pwrVal = Proc_RO->PowerThermal.PowerInfo.ThermalSpecPower / pwrUnits;
Shm->Proc.Power.TDP = pwrVal;
pwrVal = Proc_RO->PowerThermal.PowerInfo.MinimumPower / pwrUnits;
Shm->Proc.Power.Min = pwrVal;
pwrVal = Proc_RO->PowerThermal.PowerInfo.MaximumPower / pwrUnits;
Shm->Proc.Power.Max = pwrVal;
}
for (pw = PWR_DOMAIN(PKG); pw < PWR_DOMAIN(SIZE); pw++)
{
unsigned long long duration;
duration = (1 << Proc_RO->PowerThermal.PowerLimit[pw].TimeWindow1_Y);
duration *= (4 + Proc_RO->PowerThermal.PowerLimit[pw].TimeWindow1_Z);
duration = duration >> 2;
Shm->Proc.Power.Domain[pw].TW1 = Shm->Proc.Power.Unit.Times * duration;
duration = (1 << Proc_RO->PowerThermal.PowerLimit[pw].TimeWindow2_Y);
duration *= (4 + Proc_RO->PowerThermal.PowerLimit[pw].TimeWindow2_Z);
duration = duration >> 2;
Shm->Proc.Power.Domain[pw].TW2 = Shm->Proc.Power.Unit.Times * duration;
}
Shm->Proc.Power.TDC = Proc_RO->PowerThermal.TDC;
Shm->Proc.Power.Feature.TDC = Proc_RO->PowerThermal.Enable_Limit.TDC;
} else {
Shm->Proc.PowerNow = 0;
}
}
void Technology_Update(SHM_STRUCT *Shm, PROC_RO *Proc_RO, PROC_RW *Proc_RW)
{ /* Technologies aggregation. */
Shm->Proc.Technology.PowerNow = (Shm->Proc.PowerNow == 0b11);
Shm->Proc.Technology.ODCM = BITCMP_CC( LOCKLESS,
Proc_RW->ODCM,
Proc_RO->ODCM_Mask );
Shm->Proc.Technology.L1_HW_Prefetch=BITCMP_CC(LOCKLESS,
Proc_RW->L1_HW_Prefetch,
Proc_RO->DCU_Mask );
Shm->Proc.Technology.L1_HW_IP_Prefetch=BITCMP_CC(LOCKLESS,
Proc_RW->L1_HW_IP_Prefetch,
Proc_RO->DCU_Mask );
Shm->Proc.Technology.L2_HW_Prefetch = BITCMP_CC(LOCKLESS,
Proc_RW->L2_HW_Prefetch,
Proc_RO->DCU_Mask );
Shm->Proc.Technology.L2_HW_CL_Prefetch=BITCMP_CC(LOCKLESS,
Proc_RW->L2_HW_CL_Prefetch,
Proc_RO->DCU_Mask );
Shm->Proc.Technology.PowerMgmt=BITCMP_CC(LOCKLESS,
Proc_RW->PowerMgmt,
Proc_RO->PowerMgmt_Mask);
Shm->Proc.Technology.EIST = BITCMP_CC( LOCKLESS,
Proc_RW->SpeedStep,
Proc_RO->SpeedStep_Mask );
Shm->Proc.Technology.Turbo = BITWISEAND_CC(LOCKLESS,
Proc_RW->TurboBoost,
Proc_RO->TurboBoost_Mask) != 0;
Shm->Proc.Technology.C1E = BITCMP_CC( LOCKLESS,
Proc_RW->C1E,
Proc_RO->C1E_Mask );
Shm->Proc.Technology.C3A = BITCMP_CC( LOCKLESS,
Proc_RW->C3A,
Proc_RO->C3A_Mask );
Shm->Proc.Technology.C1A = BITCMP_CC( LOCKLESS,
Proc_RW->C1A,
Proc_RO->C1A_Mask );
Shm->Proc.Technology.C3U = BITCMP_CC( LOCKLESS,
Proc_RW->C3U,
Proc_RO->C3U_Mask );
Shm->Proc.Technology.C1U = BITCMP_CC( LOCKLESS,
Proc_RW->C1U,
Proc_RO->C1U_Mask );
Shm->Proc.Technology.CC6 = BITCMP_CC( LOCKLESS,
Proc_RW->CC6,
Proc_RO->CC6_Mask );
Shm->Proc.Technology.PC6 = BITCMP_CC( LOCKLESS,
Proc_RW->PC6,
Proc_RO->PC6_Mask );
Shm->Proc.Technology.SMM = BITCMP_CC( LOCKLESS,
Proc_RW->SMM,
Proc_RO->CR_Mask );
Shm->Proc.Technology.VM = BITCMP_CC( LOCKLESS,
Proc_RW->VM,
Proc_RO->CR_Mask );
Shm->Proc.Technology.WDT = BITCMP_CC( LOCKLESS,
Proc_RW->WDT,
Proc_RO->WDT_Mask );
}
void Mitigation_2nd_Stage(SHM_STRUCT *Shm, PROC_RO *Proc_RO, PROC_RW *Proc_RW)
{
unsigned short IBRS = BITCMP_CC( LOCKLESS,
Proc_RW->IBRS,
Proc_RO->SPEC_CTRL_Mask ),
STIBP = BITCMP_CC( LOCKLESS,
Proc_RW->STIBP,
Proc_RO->SPEC_CTRL_Mask ),
SSBD = BITCMP_CC( LOCKLESS,
Proc_RW->SSBD,
Proc_RO->SPEC_CTRL_Mask );
Shm->Proc.Mechanisms.IBRS += (2 * IBRS);
Shm->Proc.Mechanisms.STIBP += (2 * STIBP);
Shm->Proc.Mechanisms.SSBD += (2 * SSBD);
}
void Mitigation_1st_Stage(SHM_STRUCT *Shm, PROC_RO *Proc_RO, PROC_RW *Proc_RW)
{
if (Shm->Proc.Features.Info.Vendor.CRC == CRC_INTEL)
{
unsigned short RDCL_NO = BITCMP_CC( LOCKLESS,
Proc_RW->RDCL_NO,
Proc_RO->ARCH_CAP_Mask ),
IBRS_ALL = BITCMP_CC( LOCKLESS,
Proc_RW->RDCL_NO,
Proc_RO->ARCH_CAP_Mask ),
RSBA = BITCMP_CC( LOCKLESS,
Proc_RW->RSBA,
Proc_RO->ARCH_CAP_Mask ),
L1DFL_NO = BITCMP_CC( LOCKLESS,
Proc_RW->L1DFL_VMENTRY_NO,
Proc_RO->ARCH_CAP_Mask ),
SSB_NO = BITCMP_CC( LOCKLESS,
Proc_RW->SSB_NO,
Proc_RO->ARCH_CAP_Mask ),
MDS_NO = BITCMP_CC( LOCKLESS,
Proc_RW->MDS_NO,
Proc_RO->ARCH_CAP_Mask ),
PSCHANGE_MC_NO=BITCMP_CC(LOCKLESS,
Proc_RW->PSCHANGE_MC_NO,
Proc_RO->ARCH_CAP_Mask),
TAA_NO = BITCMP_CC( LOCKLESS,
Proc_RW->TAA_NO,
Proc_RO->ARCH_CAP_Mask );
Shm->Proc.Mechanisms.IBRS = (
Shm->Proc.Features.ExtFeature.EDX.IBRS_IBPB_Cap == 1
);
Shm->Proc.Mechanisms.STIBP = (
Shm->Proc.Features.ExtFeature.EDX.STIBP_Cap == 1
);
Shm->Proc.Mechanisms.SSBD = (
Shm->Proc.Features.ExtFeature.EDX.SSBD_Cap == 1
);
Mitigation_2nd_Stage(Shm, Proc_RO, Proc_RW);
Shm->Proc.Mechanisms.RDCL_NO = (
Shm->Proc.Features.ExtFeature.EDX.IA32_ARCH_CAP + (2 * RDCL_NO)
);
Shm->Proc.Mechanisms.IBRS_ALL = (
Shm->Proc.Features.ExtFeature.EDX.IA32_ARCH_CAP + (2 * IBRS_ALL)
);
Shm->Proc.Mechanisms.RSBA = (
Shm->Proc.Features.ExtFeature.EDX.IA32_ARCH_CAP + (2 * RSBA)
);
Shm->Proc.Mechanisms.L1DFL_VMENTRY_NO = (
Shm->Proc.Features.ExtFeature.EDX.IA32_ARCH_CAP + (2 * L1DFL_NO)
);
Shm->Proc.Mechanisms.SSB_NO = (
Shm->Proc.Features.ExtFeature.EDX.IA32_ARCH_CAP + (2 * SSB_NO)
);
Shm->Proc.Mechanisms.MDS_NO = (
Shm->Proc.Features.ExtFeature.EDX.IA32_ARCH_CAP + (2 * MDS_NO)
);
Shm->Proc.Mechanisms.PSCHANGE_MC_NO = (
Shm->Proc.Features.ExtFeature.EDX.IA32_ARCH_CAP + (2*PSCHANGE_MC_NO)
);
Shm->Proc.Mechanisms.TAA_NO = (
Shm->Proc.Features.ExtFeature.EDX.IA32_ARCH_CAP + (2 * TAA_NO)
);
Shm->Proc.Mechanisms.SPLA = BITCMP_CC( LOCKLESS,
Proc_RW->SPLA,
Proc_RO->ARCH_CAP_Mask );
}
else if ( (Shm->Proc.Features.Info.Vendor.CRC == CRC_AMD)
|| (Shm->Proc.Features.Info.Vendor.CRC == CRC_HYGON) )
{
Shm->Proc.Mechanisms.IBRS = (
Shm->Proc.Features.leaf80000008.EBX.IBRS == 1
);
Shm->Proc.Mechanisms.STIBP = (
Shm->Proc.Features.leaf80000008.EBX.STIBP == 1
);
Shm->Proc.Mechanisms.SSBD = (
Shm->Proc.Features.leaf80000008.EBX.SSBD == 1
);
Mitigation_2nd_Stage(Shm, Proc_RO, Proc_RW);
}
}
void Package_Update(SHM_STRUCT *Shm, PROC_RO *Proc_RO, PROC_RW *Proc_RW)
{ /* Copy the operational settings. */
Shm->Registration.AutoClock = Proc_RO->Registration.AutoClock;
Shm->Registration.Experimental = Proc_RO->Registration.Experimental;
Shm->Registration.HotPlug = Proc_RO->Registration.HotPlug;
Shm->Registration.PCI = Proc_RO->Registration.PCI;
BITSTOR(LOCKLESS, Shm->Registration.NMI, Proc_RO->Registration.NMI);
Shm->Registration.Driver = Proc_RO->Registration.Driver;
/* Copy the timer interval delay. */
Shm->Sleep.Interval = Proc_RO->SleepInterval;
/* Compute the polling wait time based on the timer interval. */
Shm->Sleep.pollingWait = TIMESPEC((Shm->Sleep.Interval * 1000000L)
/ WAKEUP_RATIO);
/* Copy the SysGate tick steps. */
Shm->SysGate.tickReset = Proc_RO->tickReset;
Shm->SysGate.tickStep = Proc_RO->tickStep;
Architecture(Shm, Proc_RO);
PerformanceMonitoring(Shm, Proc_RO);
HyperThreading(Shm, Proc_RO);
PowerInterface(Shm, Proc_RO);
Mitigation_1st_Stage(Shm, Proc_RO, Proc_RW);
}
typedef struct {
unsigned int Q,
R;
} RAM_Ratio;
void P945_MCH(SHM_STRUCT *Shm, PROC_RO *Proc)
{
unsigned short mc, cha, slot;
for (mc = 0; mc < Shm->Uncore.CtrlCount; mc++)
{
Shm->Uncore.MC[mc].SlotCount = Proc->Uncore.MC[mc].SlotCount;
Shm->Uncore.MC[mc].ChannelCount = Proc->Uncore.MC[mc].ChannelCount;
for (cha = 0; cha < Shm->Uncore.MC[mc].ChannelCount; cha++)
{
Shm->Uncore.MC[mc].Channel[cha].Timing.tWR =
Proc->Uncore.MC[mc].Channel[cha].P945.DRT0.tWR;
Shm->Uncore.MC[mc].Channel[cha].Timing.tRTPr =
Proc->Uncore.MC[mc].Channel[cha].P945.DRT1.tRTPr;
Shm->Uncore.MC[mc].Channel[cha].Timing.tRAS =
Proc->Uncore.MC[mc].Channel[cha].P945.DRT1.tRAS;
switch (Proc->Uncore.MC[mc].Channel[cha].P945.DRT1.tRRD) {
case 0b000:
Shm->Uncore.MC[mc].Channel[cha].Timing.tRRD = 1;
break;
case 0b001:
Shm->Uncore.MC[mc].Channel[cha].Timing.tRRD = 2;
break;
}
Shm->Uncore.MC[mc].Channel[cha].Timing.tRFC =
Proc->Uncore.MC[mc].Channel[cha].P945.DRT1.tRFC;
switch (Proc->Uncore.MC[mc].Channel[cha].P945.DRT1.tCL) {
case 0b00:
Shm->Uncore.MC[mc].Channel[cha].Timing.tCL = 5;
break;
case 0b01:
Shm->Uncore.MC[mc].Channel[cha].Timing.tCL = 4;
break;
case 0b10:
Shm->Uncore.MC[mc].Channel[cha].Timing.tCL = 3;
break;
case 0b11:
Shm->Uncore.MC[mc].Channel[cha].Timing.tCL = 6;
break;
}
Shm->Uncore.MC[mc].Channel[cha].Timing.tRCD =
Proc->Uncore.MC[mc].Channel[cha].P945.DRT1.tRCD + 2;
Shm->Uncore.MC[mc].Channel[cha].Timing.tRP =
Proc->Uncore.MC[mc].Channel[cha].P945.DRT1.tRP + 2;
for (slot = 0; slot < Shm->Uncore.MC[mc].SlotCount; slot++)
{
unsigned long long DIMM_Size;
unsigned short rank, rankCount = (cha == 0) ? 4 : 2;
for (rank = 0; rank < rankCount; rank++) {
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Ranks +=
Proc->Uncore.MC[mc].Channel[cha].P945.DRB[rank].Boundary;
}
switch (Proc->Uncore.MC[mc].Channel[cha].P945.BANK.Rank0)
{
case 0b00:
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Banks = 4;
break;
case 0b01:
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Banks = 8;
break;
}
switch (Proc->Uncore.MC[mc].Channel[cha].P945.WIDTH.Rank0)
{
case 0b00:
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Rows = 16384;
break;
case 0b01:
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Rows = 8192;
break;
}
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Cols = 1024;
DIMM_Size=Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Rows
* Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Cols
* Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Banks
* Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Ranks;
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Size=DIMM_Size >>20;
}
Shm->Uncore.MC[mc].Channel[cha].Timing.ECC = 0;
Shm->Uncore.MC[mc].Channel[cha].Timing.tCKE =
Proc->Uncore.MC[mc].Channel[cha].P945.DRT2.tCKE;
}
}
}
void P955_MCH(SHM_STRUCT *Shm, PROC_RO *Proc)
{
unsigned short mc, cha, slot;
for (mc = 0; mc < Shm->Uncore.CtrlCount; mc++)
{
Shm->Uncore.MC[mc].SlotCount = Proc->Uncore.MC[mc].SlotCount;
Shm->Uncore.MC[mc].ChannelCount = Proc->Uncore.MC[mc].ChannelCount;
for (cha = 0; cha < Shm->Uncore.MC[mc].ChannelCount; cha++)
{
Shm->Uncore.MC[mc].Channel[cha].Timing.tRAS =
Proc->Uncore.MC[mc].Channel[cha].P955.DRT1.tRAS;
switch (Proc->Uncore.MC[mc].Channel[cha].P955.DRT1.tCL) {
case 0b00:
Shm->Uncore.MC[mc].Channel[cha].Timing.tCL = 5;
break;
case 0b01:
Shm->Uncore.MC[mc].Channel[cha].Timing.tCL = 4;
break;
case 0b10:
Shm->Uncore.MC[mc].Channel[cha].Timing.tCL = 3;
break;
case 0b11:
Shm->Uncore.MC[mc].Channel[cha].Timing.tCL = 6;
break;
}
Shm->Uncore.MC[mc].Channel[cha].Timing.tRCD =
Proc->Uncore.MC[mc].Channel[cha].P955.DRT1.tRCD + 2;
Shm->Uncore.MC[mc].Channel[cha].Timing.tRP =
Proc->Uncore.MC[mc].Channel[cha].P955.DRT1.tRP + 2;
for (slot = 0; slot < Shm->Uncore.MC[mc].SlotCount; slot++)
{
unsigned long long DIMM_Size;
unsigned short rank;
for (rank = 0; rank < 4; rank++) {
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Ranks +=
Proc->Uncore.MC[mc].Channel[cha].P955.DRB[rank].Boundary;
}
switch (Proc->Uncore.MC[mc].Channel[cha].P955.BANK.Rank0)
{
case 0b00:
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Banks = 4;
break;
case 0b01:
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Banks = 8;
break;
}
switch (Proc->Uncore.MC[mc].Channel[cha].P955.WIDTH.Rank0)
{
case 0b00:
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Rows = 16384;
break;
case 0b01:
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Rows = 8192;
break;
}
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Cols = 1024;
DIMM_Size=Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Rows
* Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Cols
* Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Banks
* Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Ranks;
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Size=DIMM_Size;
}
Shm->Uncore.MC[mc].Channel[cha].Timing.ECC = 0;
}
}
}
void P945_CLK(SHM_STRUCT *Shm, PROC_RO *Proc, CORE_RO *Core)
{
RAM_Ratio Ratio = {.Q = 1, .R = 1};
switch (Proc->Uncore.Bus.ClkCfg.FSB_Select) {
case 0b000:
Shm->Uncore.Bus.Rate = 400;
switch (Proc->Uncore.Bus.ClkCfg.RAM_Select) {
default:
/* Fallthrough */
case 0b010:
Ratio.Q = 1;
Ratio.R = 1;
break;
case 0b011:
Ratio.Q = 4;
Ratio.R = 3;
break;
case 0b100:
Ratio.Q = 5;
Ratio.R = 3;
break;
}
break;
case 0b001:
Shm->Uncore.Bus.Rate = 533;
switch (Proc->Uncore.Bus.ClkCfg.RAM_Select) {
default:
/* Fallthrough */
case 0b010:
Ratio.Q = 3;
Ratio.R = 4;
break;
case 0b011:
Ratio.Q = 1;
Ratio.R = 1;
break;
case 0b001:
Ratio.Q = 5;
Ratio.R = 4;
break;
}
break;
default:
/* Fallthrough */
case 0b011:
Shm->Uncore.Bus.Rate = 667;
switch (Proc->Uncore.Bus.ClkCfg.RAM_Select) {
default:
/* Fallthrough */
case 0b010:
Ratio.Q = 3;
Ratio.R = 5;
break;
case 0b011:
Ratio.Q = 4;
Ratio.R = 5;
break;
case 0b100:
Ratio.Q = 1;
Ratio.R = 1;
break;
}
break;
}
Shm->Uncore.CtrlSpeed = (Core->Clock.Hz * Ratio.Q * 2) /* DDR2 */
/ (Ratio.R * 1000000L);
Shm->Uncore.Bus.Speed = (Core->Clock.Hz * Shm->Uncore.Bus.Rate)
/ Shm->Proc.Features.Factory.Clock.Hz;
Shm->Uncore.Unit.Bus_Rate = 0b00;
Shm->Uncore.Unit.BusSpeed = 0b00;
Shm->Uncore.Unit.DDR_Rate = 0b11;
Shm->Uncore.Unit.DDRSpeed = 0b00;
Shm->Uncore.Unit.DDR_Ver = 2;
}
void P965_MCH(SHM_STRUCT *Shm, PROC_RO *Proc)
{
unsigned short mc, cha, slot;
for (mc = 0; mc < Shm->Uncore.CtrlCount; mc++)
{
Shm->Uncore.MC[mc].SlotCount = Proc->Uncore.MC[mc].SlotCount;
Shm->Uncore.MC[mc].ChannelCount = Proc->Uncore.MC[mc].ChannelCount;
for (cha = 0; cha < Shm->Uncore.MC[mc].ChannelCount; cha++)
{
Shm->Uncore.MC[mc].Channel[cha].Timing.tCL =
Proc->Uncore.MC[mc].Channel[cha].P965.DRT0.tCL;
Shm->Uncore.MC[mc].Channel[cha].Timing.tRAS =
Proc->Uncore.MC[mc].Channel[cha].P965.DRT1.tRAS;
Shm->Uncore.MC[mc].Channel[cha].Timing.tWR =
Proc->Uncore.MC[mc].Channel[cha].P965.DRT1.tWR;
Shm->Uncore.MC[mc].Channel[cha].Timing.tRFC =
Proc->Uncore.MC[mc].Channel[cha].P965.DRT2.tRFC;
Shm->Uncore.MC[mc].Channel[cha].Timing.tRP =
Proc->Uncore.MC[mc].Channel[cha].P965.DRT2.tRP;
Shm->Uncore.MC[mc].Channel[cha].Timing.tRRD =
Proc->Uncore.MC[mc].Channel[cha].P965.DRT2.tRRD;
Shm->Uncore.MC[mc].Channel[cha].Timing.tRCD =
Proc->Uncore.MC[mc].Channel[cha].P965.DRT4.tRCD_RD;
/* TODO(Timings)
Shm->Uncore.MC[mc].Channel[cha].Timing.tFAW =
Proc->Uncore.MC[mc].Channel[cha].P965.DRT_.tFAW;
Shm->Uncore.MC[mc].Channel[cha].Timing.tRTPr =
Proc->Uncore.MC[mc].Channel[cha].P965.DRT_.tRTPr;
Shm->Uncore.MC[mc].Channel[cha].Timing.tCWL = ?
*/
Shm->Uncore.MC[mc].Channel[cha].Timing.tCL += 3;
for (slot = 0; slot < Shm->Uncore.MC[mc].SlotCount; slot++)
{
unsigned long long DIMM_Size;
/* TODO(Geometry):Hardware missing! */
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Banks = 0;
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Ranks = 0;
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Rows = 0;
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Cols = 0;
DIMM_Size = 8LLU
* Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Rows
* Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Cols
* Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Banks
* Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Ranks;
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Size=DIMM_Size >>20;
}
Shm->Uncore.MC[mc].Channel[cha].Timing.ECC = 0;
Shm->Uncore.MC[mc].Channel[cha].Timing.tCKE =
(cha == 0) ? Proc->Uncore.MC[mc].P965.CKE0.tCKE_Low
: Proc->Uncore.MC[mc].P965.CKE1.tCKE_Low;
}
}
}
void P965_CLK(SHM_STRUCT *Shm, PROC_RO *Proc, CORE_RO *Core)
{
RAM_Ratio Ratio = {.Q = 1, .R = 1};
switch (Proc->Uncore.Bus.ClkCfg.FSB_Select) {
case 0b111: /* Unknown */
/* Fallthrough */
case 0b000:
Shm->Uncore.Bus.Rate = 1066;
switch (Proc->Uncore.Bus.ClkCfg.RAM_Select) {
case 0b001:
Ratio.Q = 1;
Ratio.R = 1;
break;
case 0b010:
Ratio.Q = 5;
Ratio.R = 4;
break;
case 0b011:
Ratio.Q = 3;
Ratio.R = 2;
break;
case 0b100:
Ratio.Q = 2;
Ratio.R = 1;
break;
case 0b101:
Ratio.Q = 5;
Ratio.R = 2;
break;
}
break;
case 0b001:
Shm->Uncore.Bus.Rate = 533;
switch (Proc->Uncore.Bus.ClkCfg.RAM_Select) {
case 0b001:
Ratio.Q = 2;
Ratio.R = 1;
break;
case 0b010:
Ratio.Q = 5;
Ratio.R = 2;
break;
case 0b011:
Ratio.Q = 3;
Ratio.R = 1;
break;
}
break;
case 0b011:
Shm->Uncore.Bus.Rate = 667;
break;
case 0b100:
Shm->Uncore.Bus.Rate = 1333;
switch (Proc->Uncore.Bus.ClkCfg.RAM_Select) {
case 0b010:
Ratio.Q = 1;
Ratio.R = 1;
break;
case 0b011:
Ratio.Q = 6;
Ratio.R = 5;
break;
case 0b100:
Ratio.Q = 8;
Ratio.R = 5;
break;
case 0b101:
Ratio.Q = 2;
Ratio.R = 1;
break;
}
break;
case 0b110:
Shm->Uncore.Bus.Rate = 1600;
switch (Proc->Uncore.Bus.ClkCfg.RAM_Select) {
case 0b011:
Ratio.Q = 1;
Ratio.R = 1;
break;
case 0b100:
Ratio.Q = 4;
Ratio.R = 3;
break;
case 0b101:
Ratio.Q = 3;
Ratio.R = 2;
break;
case 0b110:
Ratio.Q = 2;
Ratio.R = 1;
break;
}
break;
default:
/* Fallthrough */
case 0b010:
Shm->Uncore.Bus.Rate = 800;
switch (Proc->Uncore.Bus.ClkCfg.RAM_Select) {
case 0b000:
Ratio.Q = 1;
Ratio.R = 1;
break;
case 0b001:
Ratio.Q = 5;
Ratio.R = 4;
break;
case 0b010:
Ratio.Q = 5;
Ratio.R = 3;
break;
case 0b011:
Ratio.Q = 2;
Ratio.R = 1;
break;
case 0b100:
Ratio.Q = 8;
Ratio.R = 3;
break;
case 0b101:
Ratio.Q = 10;
Ratio.R = 3;
break;
}
break;
}
Shm->Uncore.CtrlSpeed = (Core->Clock.Hz * Ratio.Q * 2) /* DDR2 */
/ (Ratio.R * 1000000L);
Shm->Uncore.Bus.Speed = (Core->Clock.Hz * Shm->Uncore.Bus.Rate)
/ Shm->Proc.Features.Factory.Clock.Hz;
Shm->Uncore.Unit.Bus_Rate = 0b00;
Shm->Uncore.Unit.BusSpeed = 0b00;
Shm->Uncore.Unit.DDR_Rate = 0b11;
Shm->Uncore.Unit.DDRSpeed = 0b00;
Shm->Uncore.Unit.DDR_Ver = 2;
}
void G965_MCH(SHM_STRUCT *Shm, PROC_RO *Proc)
{
unsigned short mc, cha, slot;
for (mc = 0; mc < Shm->Uncore.CtrlCount; mc++)
{
Shm->Uncore.MC[mc].SlotCount = Proc->Uncore.MC[mc].SlotCount;
Shm->Uncore.MC[mc].ChannelCount = Proc->Uncore.MC[mc].ChannelCount;
for (cha = 0; cha < Shm->Uncore.MC[mc].ChannelCount; cha++)
{
Shm->Uncore.MC[mc].Channel[cha].Timing.tWR =
Proc->Uncore.MC[mc].Channel[cha].G965.DRT0.tWR;
switch (Proc->Uncore.MC[mc].Channel[cha].G965.DRT1.tRCD) {
case 0b000:
Shm->Uncore.MC[mc].Channel[cha].Timing.tRCD = 2;
break;
case 0b001:
Shm->Uncore.MC[mc].Channel[cha].Timing.tRCD = 3;
break;
case 0b010:
Shm->Uncore.MC[mc].Channel[cha].Timing.tRCD = 4;
break;
case 0b011:
Shm->Uncore.MC[mc].Channel[cha].Timing.tRCD = 5;
break;
case 0b100:
Shm->Uncore.MC[mc].Channel[cha].Timing.tRCD = 6;
break;
case 0b101:
Shm->Uncore.MC[mc].Channel[cha].Timing.tRCD = 7;
break;
case 0b110:
Shm->Uncore.MC[mc].Channel[cha].Timing.tRCD = 8;
break;
}
switch (Proc->Uncore.MC[mc].Channel[cha].G965.DRT1.tRP) {
case 0b000:
Shm->Uncore.MC[mc].Channel[cha].Timing.tRP = 2;
break;
case 0b001:
Shm->Uncore.MC[mc].Channel[cha].Timing.tRP = 3;
break;
case 0b010:
Shm->Uncore.MC[mc].Channel[cha].Timing.tRP = 4;
break;
case 0b011:
Shm->Uncore.MC[mc].Channel[cha].Timing.tRP = 5;
break;
case 0b100:
Shm->Uncore.MC[mc].Channel[cha].Timing.tRP = 6;
break;
case 0b101:
Shm->Uncore.MC[mc].Channel[cha].Timing.tRP = 7;
break;
case 0b110:
Shm->Uncore.MC[mc].Channel[cha].Timing.tRP = 8;
break;
}
Shm->Uncore.MC[mc].Channel[cha].Timing.tRAS =
Proc->Uncore.MC[mc].Channel[cha].G965.DRT1.tRAS;
switch (Proc->Uncore.MC[mc].Channel[cha].G965.DRT1.tRRD) {
case 0b000:
Shm->Uncore.MC[mc].Channel[cha].Timing.tRRD = 2;
break;
case 0b001:
Shm->Uncore.MC[mc].Channel[cha].Timing.tRRD = 3;
break;
case 0b010:
Shm->Uncore.MC[mc].Channel[cha].Timing.tRRD = 4;
break;
case 0b011:
Shm->Uncore.MC[mc].Channel[cha].Timing.tRRD = 5;
break;
case 0b100:
Shm->Uncore.MC[mc].Channel[cha].Timing.tRRD = 6;
break;
}
Shm->Uncore.MC[mc].Channel[cha].Timing.tRTPr =
Proc->Uncore.MC[mc].Channel[cha].G965.DRT1.tRTPr;
Shm->Uncore.MC[mc].Channel[cha].Timing.tFAW =
Proc->Uncore.MC[mc].Channel[cha].G965.DRT2.tFAW;
switch (Proc->Uncore.MC[mc].Channel[cha].G965.DRT3.tCL) {
case 0b000:
Shm->Uncore.MC[mc].Channel[cha].Timing.tCL = 3;
break;
case 0b001:
Shm->Uncore.MC[mc].Channel[cha].Timing.tCL = 4;
break;
case 0b010:
Shm->Uncore.MC[mc].Channel[cha].Timing.tCL = 5;
break;
case 0b011:
Shm->Uncore.MC[mc].Channel[cha].Timing.tCL = 6;
break;
case 0b100:
Shm->Uncore.MC[mc].Channel[cha].Timing.tCL = 7;
break;
}
Shm->Uncore.MC[mc].Channel[cha].Timing.tRFC =
Proc->Uncore.MC[mc].Channel[cha].G965.DRT3.tRFC;
switch (Proc->Uncore.MC[mc].Channel[cha].G965.DRT3.tCWL) {
case 0b000:
Shm->Uncore.MC[mc].Channel[cha].Timing.tCWL = 2;
break;
case 0b001:
Shm->Uncore.MC[mc].Channel[cha].Timing.tCWL = 3;
break;
case 0b010:
Shm->Uncore.MC[mc].Channel[cha].Timing.tCWL = 4;
break;
case 0b011:
Shm->Uncore.MC[mc].Channel[cha].Timing.tCWL = 5;
break;
case 0b100:
Shm->Uncore.MC[mc].Channel[cha].Timing.tCWL = 6;
break;
default:
Shm->Uncore.MC[mc].Channel[cha].Timing.tCWL =
Shm->Uncore.MC[mc].Channel[cha].Timing.tCL - 1;
break;
}
for (slot = 0; slot < Shm->Uncore.MC[mc].SlotCount; slot++)
{
unsigned long long DIMM_Size;
switch (Proc->Uncore.MC[mc].Channel[cha].DIMM[slot].DRA.Rank1Bank)
{
case 0b00:
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Banks = 4;
break;
case 0b01:
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Banks = 8;
break;
}
switch (Proc->Uncore.MC[mc].Channel[cha].DIMM[slot].DRA.Rank0Bank)
{
case 0b00:
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Banks += 4;
break;
case 0b01:
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Banks += 8;
break;
}
switch (Proc->Uncore.MC[mc].Channel[cha].DIMM[slot].DRA.OddRank1)
{
case 0b10:
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Ranks = 1;
break;
case 0b11:
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Ranks = 2;
break;
}
switch (Proc->Uncore.MC[mc].Channel[cha].DIMM[slot].DRA.EvenRank0)
{
case 0b10:
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Ranks += 1;
break;
case 0b11:
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Ranks += 2;
break;
}
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Rows = 4096;
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Cols = 1024;
DIMM_Size = 8LLU
* Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Rows
* Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Cols
* Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Banks
* Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Ranks;
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Size=DIMM_Size >>20;
}
Shm->Uncore.MC[mc].Channel[cha].Timing.ECC = 0;
Shm->Uncore.MC[mc].Channel[cha].Timing.tCKE =
Proc->Uncore.MC[mc].Channel[cha].G965.DRT2.tCKE;
}
}
}
void G965_CLK(SHM_STRUCT *Shm, PROC_RO *Proc, CORE_RO *Core)
{
RAM_Ratio Ratio = {.Q = 1, .R = 1};
switch (Proc->Uncore.Bus.ClkCfg.FSB_Select) {
case 0b001:
Shm->Uncore.Bus.Rate = 533;
switch (Proc->Uncore.Bus.ClkCfg.RAM_Select) {
case 0b001:
Ratio.Q = 5;
Ratio.R = 4;
break;
case 0b010:
Ratio.Q = 3;
Ratio.R = 2;
break;
case 0b011:
Ratio.Q = 2;
Ratio.R = 1;
break;
}
break;
case 0b011:
Shm->Uncore.Bus.Rate = 667;
switch (Proc->Uncore.Bus.ClkCfg.RAM_Select) {
case 0b001:
Ratio.Q = 1;
Ratio.R = 1;
break;
case 0b010:
Ratio.Q = 6;
Ratio.R = 5;
break;
case 0b011:
Ratio.Q = 8;
Ratio.R = 5;
break;
case 0b100:
Ratio.Q = 2;
Ratio.R = 1;
break;
case 0b101:
Ratio.Q = 12;
Ratio.R = 5;
break;
}
break;
case 0b110:
Shm->Uncore.Bus.Rate = 1066;
switch (Proc->Uncore.Bus.ClkCfg.RAM_Select) {
case 0b101:
Ratio.Q = 3;
Ratio.R = 2;
break;
case 0b110:
Ratio.Q = 2;
Ratio.R = 1;
break;
}
break;
default:
/* Fallthrough */
case 0b010:
Shm->Uncore.Bus.Rate = 800;
switch (Proc->Uncore.Bus.ClkCfg.RAM_Select) {
case 0b001:
Ratio.Q = 5;
Ratio.R = 6;
break;
case 0b010:
Ratio.Q = 1;
Ratio.R = 1;
break;
case 0b011:
Ratio.Q = 4;
Ratio.R = 3;
break;
case 0b100:
Ratio.Q = 5;
Ratio.R = 3;
break;
case 0b101:
Ratio.Q = 2;
Ratio.R = 1;
break;
}
break;
}
Shm->Uncore.CtrlSpeed = (Core->Clock.Hz * Ratio.Q * 2) /* DDR2 */
/ (Ratio.R * 1000000L);
Shm->Uncore.Bus.Speed = (Core->Clock.Hz * Shm->Uncore.Bus.Rate)
/ Shm->Proc.Features.Factory.Clock.Hz;
Shm->Uncore.Unit.Bus_Rate = 0b00;
Shm->Uncore.Unit.BusSpeed = 0b00;
Shm->Uncore.Unit.DDR_Rate = 0b11;
Shm->Uncore.Unit.DDRSpeed = 0b00;
Shm->Uncore.Unit.DDR_Ver = 2;
}
void P3S_MCH(SHM_STRUCT *Shm,PROC_RO *Proc,unsigned short mc,unsigned short cha)
{
Shm->Uncore.MC[mc].Channel[cha].Timing.tCL =
Proc->Uncore.MC[mc].Channel[cha].P35.DRT0.tCL;
Shm->Uncore.MC[mc].Channel[cha].Timing.tWR =
Proc->Uncore.MC[mc].Channel[cha].P35.DRT1.tWR;
Shm->Uncore.MC[mc].Channel[cha].Timing.tRFC =
Proc->Uncore.MC[mc].Channel[cha].P35.DRT2.tRFC;
Shm->Uncore.MC[mc].Channel[cha].Timing.tRP =
Proc->Uncore.MC[mc].Channel[cha].P35.DRT2.tRP;
Shm->Uncore.MC[mc].Channel[cha].Timing.tRRD =
Proc->Uncore.MC[mc].Channel[cha].P35.DRT2.tRRD;
Shm->Uncore.MC[mc].Channel[cha].Timing.tRCD =
Proc->Uncore.MC[mc].Channel[cha].P35.DRT4.tRCD_RD;
Shm->Uncore.MC[mc].Channel[cha].Timing.tRAS =
Proc->Uncore.MC[mc].Channel[cha].P35.DRT5.tRAS;
/* TODO(Timings)
Shm->Uncore.MC[mc].Channel[cha].Timing.tFAW =
Proc->Uncore.MC[mc].Channel[cha].P35.DRTn.tFAW;
Shm->Uncore.MC[mc].Channel[cha].Timing.tRTPr =
Proc->Uncore.MC[mc].Channel[cha].P35.DRTn.tRTPr;
Shm->Uncore.MC[mc].Channel[cha].Timing.tWL = ?
*/
Shm->Uncore.MC[mc].Channel[cha].Timing.tCKE =
(cha == 0) ? Proc->Uncore.MC[mc].P35.CKE0.tCKE_Low
: Proc->Uncore.MC[mc].P35.CKE1.tCKE_Low;
}
void P35_MCH(SHM_STRUCT *Shm, PROC_RO *Proc)
{
unsigned short mc, cha, slot;
for (mc = 0; mc < Shm->Uncore.CtrlCount; mc++)
{
Shm->Uncore.MC[mc].SlotCount = Proc->Uncore.MC[mc].SlotCount;
Shm->Uncore.MC[mc].ChannelCount = Proc->Uncore.MC[mc].ChannelCount;
for (cha = 0; cha < Shm->Uncore.MC[mc].ChannelCount; cha++)
{
P3S_MCH(Shm, Proc, mc, cha);
Shm->Uncore.MC[mc].Channel[cha].Timing.tCL -= 9;
/* TODO(Timings) */
for (slot = 0; slot < Shm->Uncore.MC[mc].SlotCount; slot++)
{
unsigned long long DIMM_Size;
/* TODO(Geometry):Hardware missing! */
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Banks = 0;
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Ranks = 0;
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Rows = 0;
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Cols = 0;
DIMM_Size = 8LLU
* Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Rows
* Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Cols
* Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Banks
* Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Ranks;
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Size=DIMM_Size >>20;
}
Shm->Uncore.MC[mc].Channel[cha].Timing.ECC = 0;
}
}
}
void P35_CLK(SHM_STRUCT *Shm, PROC_RO *Proc, CORE_RO *Core)
{
P965_CLK(Shm, Proc, Core);
}
void P4S_MCH(SHM_STRUCT *Shm, PROC_RO *Proc)
{
unsigned short mc, cha, slot;
for (mc = 0; mc < Shm->Uncore.CtrlCount; mc++)
{
Shm->Uncore.MC[mc].SlotCount = Proc->Uncore.MC[mc].SlotCount;
Shm->Uncore.MC[mc].ChannelCount = Proc->Uncore.MC[mc].ChannelCount;
for (cha = 0; cha < Shm->Uncore.MC[mc].ChannelCount; cha++)
{
P3S_MCH(Shm, Proc, mc, cha);
Shm->Uncore.MC[mc].Channel[cha].Timing.tCL -= 6;
/* TODO(Timings) */
for (slot = 0; slot < Shm->Uncore.MC[mc].SlotCount; slot++)
{
unsigned long long DIMM_Size;
/* TODO(Geometry):Hardware missing! */
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Banks = 0;
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Ranks = 0;
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Rows = 0;
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Cols = 0;
DIMM_Size = 8LLU
* Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Rows
* Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Cols
* Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Banks
* Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Ranks;
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Size=DIMM_Size >>20;
}
Shm->Uncore.MC[mc].Channel[cha].Timing.ECC = 0;
}
}
}
void SLM_PTR(SHM_STRUCT *Shm, PROC_RO *Proc, CORE_RO *Core)
{
unsigned short mc, cha, slot;
/* BUS & DRAM frequency */
Shm->Uncore.CtrlSpeed = 800LLU + (
((2134LLU * Proc->Uncore.MC[0].SLM.DTR0.DFREQ) >> 3)
);
Shm->Uncore.Bus.Rate = 5000;
Shm->Uncore.Bus.Speed = (Core->Clock.Hz * Shm->Uncore.Bus.Rate)
/ Shm->Proc.Features.Factory.Clock.Hz;
Shm->Uncore.Unit.Bus_Rate = 0b01;
Shm->Uncore.Unit.BusSpeed = 0b01;
Shm->Uncore.Unit.DDR_Rate = 0b11;
Shm->Uncore.Unit.DDRSpeed = 0b00;
Shm->Uncore.Unit.DDR_Ver = 3;
for (mc = 0; mc < Shm->Uncore.CtrlCount; mc++)
{
Shm->Uncore.MC[mc].SlotCount = Proc->Uncore.MC[mc].SlotCount;
Shm->Uncore.MC[mc].ChannelCount = Proc->Uncore.MC[mc].ChannelCount;
for (cha = 0; cha < Shm->Uncore.MC[mc].ChannelCount; cha++)
{
/* Standard Timings */
Shm->Uncore.MC[mc].Channel[cha].Timing.tCL =
Proc->Uncore.MC[mc].SLM.DTR0.tCL + 5;
Shm->Uncore.MC[mc].Channel[cha].Timing.tRCD =
Proc->Uncore.MC[mc].SLM.DTR0.tRCD + 5;
Shm->Uncore.MC[mc].Channel[cha].Timing.tRP =
Proc->Uncore.MC[mc].SLM.DTR0.tRP + 5;
Shm->Uncore.MC[mc].Channel[cha].Timing.tRAS =
Proc->Uncore.MC[mc].SLM.DTR1.tRAS;
Shm->Uncore.MC[mc].Channel[cha].Timing.tRRD =
Proc->Uncore.MC[mc].SLM.DTR1.tRRD + 4;
Shm->Uncore.MC[mc].Channel[cha].Timing.tRFC =
Proc->Uncore.MC[mc].SLM.DTR0.tXS == 0 ? 256 : 384;
switch (Proc->Uncore.MC[mc].SLM.DRFC.tREFI) {
case 0 ... 1:
Shm->Uncore.MC[mc].Channel[cha].Timing.tREFI = 0;
break;
case 2:
Shm->Uncore.MC[mc].Channel[cha].Timing.tREFI = 39;
break;
case 3:
Shm->Uncore.MC[mc].Channel[cha].Timing.tREFI = 78;
break;
}
Shm->Uncore.MC[mc].Channel[cha].Timing.tREFI *= Shm->Uncore.CtrlSpeed;
Shm->Uncore.MC[mc].Channel[cha].Timing.tREFI /= 20;
/*TODO( Advanced Timings )
Shm->Uncore.MC[mc].Channel[cha].Timing.tCKE =
Proc->Uncore.MC[mc].Channel[cha].SLM
*/
Shm->Uncore.MC[mc].Channel[cha].Timing.tRTPr =
Proc->Uncore.MC[mc].SLM.DTR1.tRTP + 4;
Shm->Uncore.MC[mc].Channel[cha].Timing.tWTPr =
Proc->Uncore.MC[mc].SLM.DTR1.tWTP + 14;
Shm->Uncore.MC[mc].Channel[cha].Timing.B2B =
Proc->Uncore.MC[mc].SLM.DTR1.tCCD;
switch (Proc->Uncore.MC[mc].SLM.DTR1.tFAW) {
case 0 ... 1:
Shm->Uncore.MC[mc].Channel[cha].Timing.tFAW = 0;
break;
default:
Shm->Uncore.MC[mc].Channel[cha].Timing.tFAW =
10 + (Proc->Uncore.MC[mc].SLM.DTR1.tFAW << 1);
break;
}
Shm->Uncore.MC[mc].Channel[cha].Timing.tCWL =
Proc->Uncore.MC[mc].SLM.DTR1.tWCL + 3;
/* Same Rank */
/*TODO( Read to Read )
Shm->Uncore.MC[mc].Channel[cha].Timing.tsrRdTRd =
Proc->Uncore.MC[mc].SLM.DTR?.;
*/
Shm->Uncore.MC[mc].Channel[cha].Timing.tsrRdTWr = 6
+ Proc->Uncore.MC[mc].SLM.DTR3.tRWSR;
Shm->Uncore.MC[mc].Channel[cha].Timing.tsrWrTRd = 11
+ Proc->Uncore.MC[mc].SLM.DTR3.tWRSR;
/*TODO( Write to Write )
Shm->Uncore.MC[mc].Channel[cha].Timing.tsrWrTWr =
Proc->Uncore.MC[mc].Channel[cha].SLM.DTR?.;
*/
/* Different Rank */
Shm->Uncore.MC[mc].Channel[cha].Timing.tdrRdTRd =
Proc->Uncore.MC[mc].SLM.DTR2.tRRDR;
if (Shm->Uncore.MC[mc].Channel[cha].Timing.tdrRdTRd > 0) {
Shm->Uncore.MC[mc].Channel[cha].Timing.tdrRdTRd += 5;
}
Shm->Uncore.MC[mc].Channel[cha].Timing.tdrRdTWr =
+ Proc->Uncore.MC[mc].SLM.DTR2.tRWDR;
if (Shm->Uncore.MC[mc].Channel[cha].Timing.tdrRdTWr > 0) {
Shm->Uncore.MC[mc].Channel[cha].Timing.tdrRdTWr += 5;
}
Shm->Uncore.MC[mc].Channel[cha].Timing.tdrWrTRd =
+ Proc->Uncore.MC[mc].SLM.DTR3.tWRDR;
if (Shm->Uncore.MC[mc].Channel[cha].Timing.tdrWrTRd > 0) {
Shm->Uncore.MC[mc].Channel[cha].Timing.tdrWrTRd += 3;
}
Shm->Uncore.MC[mc].Channel[cha].Timing.tdrWrTWr = 4
+ Proc->Uncore.MC[mc].SLM.DTR2.tWWDR;
/* Different DIMM */
Shm->Uncore.MC[mc].Channel[cha].Timing.tddRdTRd =
+ Proc->Uncore.MC[mc].SLM.DTR2.tRRDD;
if (Shm->Uncore.MC[mc].Channel[cha].Timing.tddRdTRd > 0) {
Shm->Uncore.MC[mc].Channel[cha].Timing.tddRdTRd += 5;
}
Shm->Uncore.MC[mc].Channel[cha].Timing.tddRdTWr =
+ Proc->Uncore.MC[mc].SLM.DTR2.tRWDD;
if (Shm->Uncore.MC[mc].Channel[cha].Timing.tddRdTWr > 0) {
Shm->Uncore.MC[mc].Channel[cha].Timing.tddRdTWr += 5;
}
Shm->Uncore.MC[mc].Channel[cha].Timing.tddWrTRd = 4
+ Proc->Uncore.MC[mc].SLM.DTR3.tWRDD;
Shm->Uncore.MC[mc].Channel[cha].Timing.tddWrTWr = 4
+ Proc->Uncore.MC[mc].SLM.DTR2.tWWDD;
/* Command Rate */
Shm->Uncore.MC[mc].Channel[cha].Timing.CMD_Rate = 1
+ Proc->Uncore.MC[mc].SLM.DTR1.tCMD;
/* Topology */
for (slot = 0; slot < Shm->Uncore.MC[mc].SlotCount; slot++)
{
unsigned long long DIMM_Size;
const struct {
unsigned int Banks,
Rows,
Cols;
} DDR3L[4] = {
{ .Banks = 8, .Rows = 1<<14, .Cols = 1<<10 },
{ .Banks = 8, .Rows = 1<<15, .Cols = 1<<10 },
{ .Banks = 8, .Rows = 1<<16, .Cols = 1<<10 },
{ .Banks = 8, .Rows = 1<<14, .Cols = 1<<10 }
};
if (cha == 0) {
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Ranks =
Proc->Uncore.MC[mc].SLM.DRP.RKEN0
+ Proc->Uncore.MC[mc].SLM.DRP.RKEN1;
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Banks =
DDR3L[ Proc->Uncore.MC[mc].SLM.DRP.DIMMDDEN0 ].Banks;
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Rows =
DDR3L[ Proc->Uncore.MC[mc].SLM.DRP.DIMMDDEN0 ].Rows;
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Cols =
DDR3L[ Proc->Uncore.MC[mc].SLM.DRP.DIMMDDEN0 ].Cols;
} else {
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Ranks =
Proc->Uncore.MC[mc].SLM.DRP.RKEN2
+ Proc->Uncore.MC[mc].SLM.DRP.RKNE3;
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Banks =
DDR3L[ Proc->Uncore.MC[mc].SLM.DRP.DIMMDDEN1 ].Banks;
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Rows =
DDR3L[ Proc->Uncore.MC[mc].SLM.DRP.DIMMDDEN1 ].Rows;
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Cols =
DDR3L[ Proc->Uncore.MC[mc].SLM.DRP.DIMMDDEN1 ].Cols;
}
DIMM_Size = 8LLU
* Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Rows
* Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Cols
* Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Banks
* Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Ranks;
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Size=DIMM_Size >> 20;
}
/* Error Correcting Code */
Shm->Uncore.MC[mc].Channel[cha].Timing.ECC =
Proc->Uncore.MC[mc].SLM.BIOS_CFG.EFF_ECC_EN
| Proc->Uncore.MC[mc].SLM.BIOS_CFG.ECC_EN;
}
}
}
void NHM_IMC(SHM_STRUCT *Shm, PROC_RO *Proc)
{
unsigned short mc, cha, slot;
for (mc = 0; mc < Shm->Uncore.CtrlCount; mc++)
{
Shm->Uncore.MC[mc].SlotCount = Proc->Uncore.MC[mc].SlotCount;
Shm->Uncore.MC[mc].ChannelCount = Proc->Uncore.MC[mc].ChannelCount;
for (cha = 0; cha < Shm->Uncore.MC[mc].ChannelCount; cha++)
{
Shm->Uncore.MC[mc].Channel[cha].Timing.tCL =
Proc->Uncore.MC[mc].Channel[cha].NHM.MR0_1.tCL ?
4 + Proc->Uncore.MC[mc].Channel[cha].NHM.MR0_1.tCL : 0;
switch (Proc->Uncore.MC[mc].Channel[cha].NHM.MR0_1.tWR) {
case 0b001:
Shm->Uncore.MC[mc].Channel[cha].Timing.tWR = 5;
break;
case 0b010:
Shm->Uncore.MC[mc].Channel[cha].Timing.tWR = 6;
break;
case 0b011:
Shm->Uncore.MC[mc].Channel[cha].Timing.tWR = 7;
break;
case 0b100:
Shm->Uncore.MC[mc].Channel[cha].Timing.tWR = 8;
break;
case 0b101:
Shm->Uncore.MC[mc].Channel[cha].Timing.tWR = 10;
break;
case 0b110:
Shm->Uncore.MC[mc].Channel[cha].Timing.tWR = 12;
break;
}
Shm->Uncore.MC[mc].Channel[cha].Timing.tRCD =
Proc->Uncore.MC[mc].Channel[cha].NHM.Bank.tRCD;
Shm->Uncore.MC[mc].Channel[cha].Timing.tRP =
Proc->Uncore.MC[mc].Channel[cha].NHM.Bank.tRP;
Shm->Uncore.MC[mc].Channel[cha].Timing.tRAS =
Proc->Uncore.MC[mc].Channel[cha].NHM.Bank.tRAS;
Shm->Uncore.MC[mc].Channel[cha].Timing.tRRD =
Proc->Uncore.MC[mc].Channel[cha].NHM.Rank_B.tRRD;
Shm->Uncore.MC[mc].Channel[cha].Timing.tRFC =
Proc->Uncore.MC[mc].Channel[cha].NHM.Refresh.tRFC;
Shm->Uncore.MC[mc].Channel[cha].Timing.tREFI =
Proc->Uncore.MC[mc].Channel[cha].NHM.Refresh.tREFI_8;
Shm->Uncore.MC[mc].Channel[cha].Timing.tCKE =
Proc->Uncore.MC[mc].Channel[cha].NHM.CKE_Timing.tCKE;
Shm->Uncore.MC[mc].Channel[cha].Timing.tRTPr =
Proc->Uncore.MC[mc].Channel[cha].NHM.Bank.tRTPr;
Shm->Uncore.MC[mc].Channel[cha].Timing.tWTPr =
Proc->Uncore.MC[mc].Channel[cha].NHM.Bank.tWTPr;
switch (Proc->Uncore.MC[mc].Channel[cha].NHM.Rank_A.tsrRdTRd) {
case 0b0:
Shm->Uncore.MC[mc].Channel[cha].Timing.tsrRdTRd = 4;
break;
case 0b1:
Shm->Uncore.MC[mc].Channel[cha].Timing.tsrRdTRd = 6;
break;
}
Shm->Uncore.MC[mc].Channel[cha].Timing.tdrRdTRd = 2
+ Proc->Uncore.MC[mc].Channel[cha].NHM.Rank_A.tdrRdTRd;
Shm->Uncore.MC[mc].Channel[cha].Timing.tddRdTRd = 2
+ Proc->Uncore.MC[mc].Channel[cha].NHM.Rank_A.tddRdTRd;
Shm->Uncore.MC[mc].Channel[cha].Timing.tsrRdTWr = 2
+ Proc->Uncore.MC[mc].Channel[cha].NHM.Rank_A.tsrRdTWr;
Shm->Uncore.MC[mc].Channel[cha].Timing.tdrRdTWr = 2
+ Proc->Uncore.MC[mc].Channel[cha].NHM.Rank_A.tdrRdTWr;
Shm->Uncore.MC[mc].Channel[cha].Timing.tddRdTWr = 2
+ Proc->Uncore.MC[mc].Channel[cha].NHM.Rank_A.tddRdTWr;
Shm->Uncore.MC[mc].Channel[cha].Timing.tsrWrTRd = 10
+ Proc->Uncore.MC[mc].Channel[cha].NHM.Rank_A.tsrWrTRd;
Shm->Uncore.MC[mc].Channel[cha].Timing.tdrWrTRd = 1
+ Proc->Uncore.MC[mc].Channel[cha].NHM.Rank_A.tdrWrTRd;
Shm->Uncore.MC[mc].Channel[cha].Timing.tddWrTRd = 1
+ Proc->Uncore.MC[mc].Channel[cha].NHM.Rank_A.tddWrTRd;
switch (Proc->Uncore.MC[mc].Channel[cha].NHM.Rank_B.tsrWrTWr) {
case 0b0:
Shm->Uncore.MC[mc].Channel[cha].Timing.tsrWrTWr = 4;
break;
case 0b1:
Shm->Uncore.MC[mc].Channel[cha].Timing.tsrWrTWr = 6;
break;
}
Shm->Uncore.MC[mc].Channel[cha].Timing.tdrWrTWr = 2
+ Proc->Uncore.MC[mc].Channel[cha].NHM.Rank_B.tdrWrTWr;
Shm->Uncore.MC[mc].Channel[cha].Timing.tddWrTWr = 2
+ Proc->Uncore.MC[mc].Channel[cha].NHM.Rank_B.tddWrTWr;
Shm->Uncore.MC[mc].Channel[cha].Timing.tFAW =
Proc->Uncore.MC[mc].Channel[cha].NHM.Rank_B.tFAW;
Shm->Uncore.MC[mc].Channel[cha].Timing.B2B =
Proc->Uncore.MC[mc].Channel[cha].NHM.Rank_B.B2B;
switch (Proc->Uncore.MC[mc].Channel[cha].NHM.MR2_3.tCWL) {
case 0b000:
Shm->Uncore.MC[mc].Channel[cha].Timing.tCWL = 5;
break;
case 0b001:
Shm->Uncore.MC[mc].Channel[cha].Timing.tCWL = 6;
break;
case 0b010:
Shm->Uncore.MC[mc].Channel[cha].Timing.tCWL = 7;
break;
case 0b011:
Shm->Uncore.MC[mc].Channel[cha].Timing.tCWL = 8;
break;
}
switch (Proc->Uncore.MC[mc].Channel[cha].NHM.Params.ENABLE_2N_3N)
{
case 0b00:
Shm->Uncore.MC[mc].Channel[cha].Timing.CMD_Rate = 1;
break;
case 0b01:
Shm->Uncore.MC[mc].Channel[cha].Timing.CMD_Rate = 2;
break;
case 0b10:
Shm->Uncore.MC[mc].Channel[cha].Timing.CMD_Rate = 3;
break;
}
for (slot = 0; slot < Shm->Uncore.MC[mc].SlotCount; slot++) {
if (Proc->Uncore.MC[mc].Channel[cha].DIMM[slot].DOD.DIMMPRESENT)
{
unsigned long long DIMM_Size;
switch (Proc->Uncore.MC[mc].Channel[cha].DIMM[slot].DOD.NUMBANK)
{
case 0b00:
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Banks = 4;
break;
case 0b01:
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Banks = 8;
break;
case 0b10:
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Banks = 16;
break;
}
switch (Proc->Uncore.MC[mc].Channel[cha].DIMM[slot].DOD.NUMRANK)
{
case 0b00:
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Ranks = 1;
break;
case 0b01:
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Ranks = 2;
break;
case 0b10:
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Ranks = 4;
break;
}
switch (Proc->Uncore.MC[mc].Channel[cha].DIMM[slot].DOD.NUMROW)
{
case 0b000:
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Rows = 1<<12;
break;
case 0b001:
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Rows = 1<<13;
break;
case 0b010:
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Rows = 1<<14;
break;
case 0b011:
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Rows = 1<<15;
break;
case 0b100:
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Rows = 1<<16;
break;
}
switch (Proc->Uncore.MC[mc].Channel[cha].DIMM[slot].DOD.NUMCOL)
{
case 0b000:
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Cols = 1<<10;
break;
case 0b001:
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Cols = 1<<11;
break;
case 0b010:
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Cols = 1<<12;
break;
}
DIMM_Size = 8LLU
* Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Rows
* Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Cols
* Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Banks
* Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Ranks;
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Size=DIMM_Size >>20;
}
}
Shm->Uncore.MC[mc].Channel[cha].Timing.ECC =
Proc->Uncore.MC[mc].NHM.STATUS.ECC_ENABLED
& Proc->Uncore.MC[mc].NHM.CONTROL.ECC_ENABLED;
}
}
}
void QPI_CLK(SHM_STRUCT *Shm, PROC_RO *Proc, CORE_RO *Core)
{
switch (Proc->Uncore.Bus.DimmClock.QCLK_RATIO) {
case 0b00110:
Shm->Uncore.CtrlSpeed = 800;
break;
case 0b01000:
Shm->Uncore.CtrlSpeed = 1066;
break;
case 0b01010:
Shm->Uncore.CtrlSpeed = 1333;
break;
case 0b01100:
Shm->Uncore.CtrlSpeed = 1600;
break;
case 0b01110:
Shm->Uncore.CtrlSpeed = 1866;
break;
case 0b10000:
Shm->Uncore.CtrlSpeed = 2133;
break;
case 0b000000:
/* Fallthrough */
default:
Shm->Uncore.CtrlSpeed = 800;
break;
}
Shm->Uncore.CtrlSpeed *= Core->Clock.Hz;
Shm->Uncore.CtrlSpeed /= Shm->Proc.Features.Factory.Clock.Hz;
Shm->Uncore.Bus.Rate = Proc->Uncore.Bus.QuickPath.X58.QPIFREQSEL==0b00 ?
4800 : Proc->Uncore.Bus.QuickPath.X58.QPIFREQSEL == 0b10 ?
6400 : Proc->Uncore.Bus.QuickPath.X58.QPIFREQSEL==0b01 ?
5866 : 6400;
Shm->Uncore.Bus.Speed = (Core->Clock.Hz * Shm->Uncore.Bus.Rate)
/ Shm->Proc.Features.Factory.Clock.Hz;
Shm->Uncore.Unit.Bus_Rate = 0b01;
Shm->Uncore.Unit.BusSpeed = 0b01;
Shm->Uncore.Unit.DDR_Rate = 0b11;
Shm->Uncore.Unit.DDRSpeed = 0b00;
Shm->Uncore.Unit.DDR_Ver = 3;
}
void X58_VTD(SHM_STRUCT *Shm, PROC_RO *Proc, CORE_RO *Core)
{
UNUSED(Core);
Shm->Proc.Technology.IOMMU = !Proc->Uncore.Bus.QuickPath.X58.VT_d;
Shm->Proc.Technology.IOMMU_Ver_Major = Proc->Uncore.Bus.IOMMU_Ver.Major;
Shm->Proc.Technology.IOMMU_Ver_Minor = Proc->Uncore.Bus.IOMMU_Ver.Minor;
}
void DMI_CLK(SHM_STRUCT *Shm, PROC_RO *Proc, CORE_RO *Core)
{
switch (Proc->Uncore.Bus.DimmClock.QCLK_RATIO) {
case 0b00010:
Shm->Uncore.CtrlSpeed = 266;
break;
case 0b00100:
Shm->Uncore.CtrlSpeed = 533;
break;
case 0b00110:
Shm->Uncore.CtrlSpeed = 800;
break;
case 0b01000:
Shm->Uncore.CtrlSpeed = 1066;
break;
case 0b01010:
Shm->Uncore.CtrlSpeed = 1333;
break;
case 0b000000:
/* Fallthrough */
default:
Shm->Uncore.CtrlSpeed = 266;
break;
}
Shm->Uncore.CtrlSpeed *= Core->Clock.Hz;
Shm->Uncore.CtrlSpeed /= Shm->Proc.Features.Factory.Clock.Hz;
Shm->Uncore.Bus.Rate = 2500; /* TODO: hardwired to Lynnfield */
Shm->Uncore.Bus.Speed = (Core->Clock.Hz * Shm->Uncore.Bus.Rate)
/ Shm->Proc.Features.Factory.Clock.Hz;
Shm->Uncore.Unit.Bus_Rate = 0b01;
Shm->Uncore.Unit.BusSpeed = 0b01;
Shm->Uncore.Unit.DDR_Rate = 0b11;
Shm->Uncore.Unit.DDRSpeed = 0b00;
Shm->Uncore.Unit.DDR_Ver = 3;
}
void SNB_IMC(SHM_STRUCT *Shm, PROC_RO *Proc)
{
unsigned short mc, cha, slot;
for (mc = 0; mc < Shm->Uncore.CtrlCount; mc++)
{
unsigned short dimmSize[2][2] = {
{
Proc->Uncore.MC[mc].SNB.MAD0.Dimm_A_Size,
Proc->Uncore.MC[mc].SNB.MAD0.Dimm_B_Size
}, {
Proc->Uncore.MC[mc].SNB.MAD1.Dimm_A_Size,
Proc->Uncore.MC[mc].SNB.MAD1.Dimm_B_Size
}
};
Shm->Uncore.MC[mc].SlotCount = Proc->Uncore.MC[mc].SlotCount;
Shm->Uncore.MC[mc].ChannelCount = Proc->Uncore.MC[mc].ChannelCount;
for (cha = 0; cha < Shm->Uncore.MC[mc].ChannelCount; cha++)
{
Shm->Uncore.MC[mc].Channel[cha].Timing.tCL =
Proc->Uncore.MC[mc].Channel[cha].SNB.DBP.tCL;
Shm->Uncore.MC[mc].Channel[cha].Timing.tRCD =
Proc->Uncore.MC[mc].Channel[cha].SNB.DBP.tRCD;
Shm->Uncore.MC[mc].Channel[cha].Timing.tRP =
Proc->Uncore.MC[mc].Channel[cha].SNB.DBP.tRP;
Shm->Uncore.MC[mc].Channel[cha].Timing.tRAS =
Proc->Uncore.MC[mc].Channel[cha].SNB.DBP.tRAS;
Shm->Uncore.MC[mc].Channel[cha].Timing.tRRD =
Proc->Uncore.MC[mc].Channel[cha].SNB.RAP.tRRD;
Shm->Uncore.MC[mc].Channel[cha].Timing.tRFC =
Proc->Uncore.MC[mc].Channel[cha].SNB.RFTP.tRFC;
Shm->Uncore.MC[mc].Channel[cha].Timing.tREFI =
Proc->Uncore.MC[mc].Channel[cha].SNB.RFTP.tREFI;
Shm->Uncore.MC[mc].Channel[cha].Timing.tWR =
Proc->Uncore.MC[mc].Channel[cha].SNB.RAP.tWR;
Shm->Uncore.MC[mc].Channel[cha].Timing.tRTPr =
Proc->Uncore.MC[mc].Channel[cha].SNB.RAP.tRTPr;
Shm->Uncore.MC[mc].Channel[cha].Timing.tWTPr =
Proc->Uncore.MC[mc].Channel[cha].SNB.RAP.tWTPr;
Shm->Uncore.MC[mc].Channel[cha].Timing.tFAW =
Proc->Uncore.MC[mc].Channel[cha].SNB.RAP.tFAW;
Shm->Uncore.MC[mc].Channel[cha].Timing.tCKE =
Proc->Uncore.MC[mc].Channel[cha].SNB.RAP.tCKE;
Shm->Uncore.MC[mc].Channel[cha].Timing.tCWL =
Proc->Uncore.MC[mc].Channel[cha].SNB.DBP.tCWL;
switch (Proc->Uncore.MC[mc].Channel[cha].SNB.RAP.CMD_Stretch) {
case 0b00:
Shm->Uncore.MC[mc].Channel[cha].Timing.CMD_Rate = 1;
break;
case 0b10:
Shm->Uncore.MC[mc].Channel[cha].Timing.CMD_Rate = 2;
break;
case 0b11:
Shm->Uncore.MC[mc].Channel[cha].Timing.CMD_Rate = 3;
break;
default:
Shm->Uncore.MC[mc].Channel[cha].Timing.CMD_Rate = 0;
break;
}
for (slot = 0; slot < Shm->Uncore.MC[mc].SlotCount; slot++)
{
unsigned int width, DIMM_Banks;
if (slot == 0) {
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Ranks =
Proc->Uncore.MC[mc].SNB.MAD0.DANOR;
width = Proc->Uncore.MC[mc].SNB.MAD0.DAW;
} else {
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Ranks =
Proc->Uncore.MC[mc].SNB.MAD0.DBNOR;
width = Proc->Uncore.MC[mc].SNB.MAD0.DBW;
}
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Ranks++;
if (width == 0) {
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Rows = 1 << 14;
} else {
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Rows = 1 << 15;
}
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Cols = 1 << 10;
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Size =
dimmSize[cha][slot] * 256;
DIMM_Banks = 8 * dimmSize[cha][slot] * 1024 * 1024;
DIMM_Banks = DIMM_Banks
/ (Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Rows
* Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Cols
* Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Ranks);
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Banks = DIMM_Banks;
}
Shm->Uncore.MC[mc].Channel[cha].Timing.ECC = (cha == 0) ?
Proc->Uncore.MC[mc].SNB.MAD0.ECC
: Proc->Uncore.MC[mc].SNB.MAD1.ECC;
}
}
}
void SNB_CAP(SHM_STRUCT *Shm, PROC_RO *Proc, CORE_RO *Core)
{
switch (Proc->Uncore.Bus.SNB_Cap.DMFC) {
case 0b111:
Shm->Uncore.CtrlSpeed = 1067;
break;
case 0b110:
Shm->Uncore.CtrlSpeed = 1333;
break;
case 0b101:
Shm->Uncore.CtrlSpeed = 1600;
break;
case 0b100:
Shm->Uncore.CtrlSpeed = 1867;
break;
case 0b011:
Shm->Uncore.CtrlSpeed = 2133;
break;
case 0b010:
Shm->Uncore.CtrlSpeed = 2400;
break;
case 0b001:
Shm->Uncore.CtrlSpeed = 2667;
break;
case 0b000:
Shm->Uncore.CtrlSpeed = 2933;
break;
}
Shm->Uncore.Bus.Rate = 5000;
Shm->Uncore.Bus.Speed = (Core->Clock.Hz * Shm->Uncore.Bus.Rate)
/ Shm->Proc.Features.Factory.Clock.Hz;
Shm->Uncore.Unit.Bus_Rate = 0b01;
Shm->Uncore.Unit.BusSpeed = 0b01;
Shm->Uncore.Unit.DDR_Rate = 0b11;
Shm->Uncore.Unit.DDRSpeed = 0b00;
Shm->Uncore.Unit.DDR_Ver = 3;
Shm->Proc.Technology.IOMMU = !Proc->Uncore.Bus.SNB_Cap.VT_d;
}
void SNB_EP_IMC(SHM_STRUCT *Shm, PROC_RO *Proc)
{
unsigned short mc, cha, slot;
for (mc = 0; mc < Shm->Uncore.CtrlCount; mc++)
{
Shm->Uncore.MC[mc].SlotCount = Proc->Uncore.MC[mc].SlotCount;
Shm->Uncore.MC[mc].ChannelCount = Proc->Uncore.MC[mc].ChannelCount;
for (cha = 0; cha < Shm->Uncore.MC[mc].ChannelCount; cha++)
{
Shm->Uncore.MC[mc].Channel[cha].Timing.tCL =
Proc->Uncore.MC[mc].Channel[cha].SNB_EP.DBP.EP.tCL;
Shm->Uncore.MC[mc].Channel[cha].Timing.tRCD =
Proc->Uncore.MC[mc].Channel[cha].SNB_EP.DBP.EP.tRCD;
Shm->Uncore.MC[mc].Channel[cha].Timing.tRP =
Proc->Uncore.MC[mc].Channel[cha].SNB_EP.DBP.EP.tRP;
Shm->Uncore.MC[mc].Channel[cha].Timing.tCWL =
Proc->Uncore.MC[mc].Channel[cha].SNB_EP.DBP.EP.tCWL;
Shm->Uncore.MC[mc].Channel[cha].Timing.tRAS =
Proc->Uncore.MC[mc].Channel[cha].SNB_EP.DBP.EP.tRAS;
Shm->Uncore.MC[mc].Channel[cha].Timing.tRRD =
Proc->Uncore.MC[mc].Channel[cha].SNB_EP.RAP.EP.tRRD;
Shm->Uncore.MC[mc].Channel[cha].Timing.tRFC =
Proc->Uncore.MC[mc].Channel[cha].SNB_EP.RFTP.EP.tRFC;
Shm->Uncore.MC[mc].Channel[cha].Timing.tREFI =
Proc->Uncore.MC[mc].Channel[cha].SNB_EP.RFTP.EP.tREFI;
Shm->Uncore.MC[mc].Channel[cha].Timing.tWR =
Proc->Uncore.MC[mc].Channel[cha].SNB_EP.RAP.EP.tWR;
Shm->Uncore.MC[mc].Channel[cha].Timing.tRTPr =
Proc->Uncore.MC[mc].Channel[cha].SNB_EP.RAP.EP.tRTPr;
Shm->Uncore.MC[mc].Channel[cha].Timing.tWTPr =
Proc->Uncore.MC[mc].Channel[cha].SNB_EP.RAP.EP.tWTPr;
Shm->Uncore.MC[mc].Channel[cha].Timing.tFAW =
Proc->Uncore.MC[mc].Channel[cha].SNB_EP.RAP.EP.tFAW;
Shm->Uncore.MC[mc].Channel[cha].Timing.tCKE =
Proc->Uncore.MC[mc].Channel[cha].SNB_EP.RAP.EP.tCKE;
Shm->Uncore.MC[mc].Channel[cha].Timing.tddWrTRd =
Proc->Uncore.MC[mc].Channel[cha].SNB_EP.RWP.EP.tWRDD;
Shm->Uncore.MC[mc].Channel[cha].Timing.tdrWrTRd =
Proc->Uncore.MC[mc].Channel[cha].SNB_EP.RWP.EP.tWRDR;
Shm->Uncore.MC[mc].Channel[cha].Timing.tsrWrTRd =
4 + Proc->Uncore.MC[mc].Channel[cha].SNB_EP.DBP.EP.tCWL
+ Proc->Uncore.MC[mc].Channel[cha].SNB_EP.RAP.EP.tWTPr;
Shm->Uncore.MC[mc].Channel[cha].Timing.tddRdTWr =
Proc->Uncore.MC[mc].Channel[cha].SNB_EP.RWP.EP.tRWDD;
Shm->Uncore.MC[mc].Channel[cha].Timing.tdrRdTWr =
Proc->Uncore.MC[mc].Channel[cha].SNB_EP.RWP.EP.tRWDR;
Shm->Uncore.MC[mc].Channel[cha].Timing.tsrRdTWr =
Proc->Uncore.MC[mc].Channel[cha].SNB_EP.RWP.EP.tRWSR;
Shm->Uncore.MC[mc].Channel[cha].Timing.tddRdTRd =
Proc->Uncore.MC[mc].Channel[cha].SNB_EP.RWP.EP.tRRDD;
Shm->Uncore.MC[mc].Channel[cha].Timing.tdrRdTRd =
Proc->Uncore.MC[mc].Channel[cha].SNB_EP.RWP.EP.tRRDR;
/* TODO
Shm->Uncore.MC[mc].Channel[cha].Timing.tsrRdTRd =
Proc->Uncore.MC[mc].Channel[cha].SNB_EP.RWP.EP.tRRSR;
*/
Shm->Uncore.MC[mc].Channel[cha].Timing.tddWrTWr =
Proc->Uncore.MC[mc].Channel[cha].SNB_EP.RWP.EP.tWWDD;
Shm->Uncore.MC[mc].Channel[cha].Timing.tdrWrTWr =
Proc->Uncore.MC[mc].Channel[cha].SNB_EP.RWP.EP.tWWDR;
/* TODO
Shm->Uncore.MC[mc].Channel[cha].Timing.tsrWrTWr =
Proc->Uncore.MC[mc].Channel[cha].SNB_EP.RWP.EP.tWWSR;
*/
Shm->Uncore.MC[mc].Channel[cha].Timing.B2B =
Proc->Uncore.MC[mc].Channel[cha].SNB_EP.RWP.EP.tCCD;
switch (Proc->Uncore.MC[mc].Channel[cha].SNB_EP.RAP.EP.CMD_Stretch) {
case 0b00:
Shm->Uncore.MC[mc].Channel[cha].Timing.CMD_Rate = 1;
break;
case 0b10:
Shm->Uncore.MC[mc].Channel[cha].Timing.CMD_Rate = 2;
break;
case 0b11:
Shm->Uncore.MC[mc].Channel[cha].Timing.CMD_Rate = 3;
break;
default:
Shm->Uncore.MC[mc].Channel[cha].Timing.CMD_Rate = 0;
break;
}
for (slot = 0; slot < Shm->Uncore.MC[mc].SlotCount; slot++)
{
if (Proc->Uncore.MC[mc].Channel[cha].DIMM[slot].MTR.DIMM_POP)
{
unsigned long long DIMM_Size;
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Banks = 4 <<
Proc->Uncore.MC[mc].Channel[cha].DIMM[slot].MTR.DDR3_WIDTH;
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Ranks = 1 <<
Proc->Uncore.MC[mc].Channel[cha].DIMM[slot].MTR.RANK_CNT;
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Rows = 1 << ( 13
+ Proc->Uncore.MC[mc].Channel[cha].DIMM[slot].MTR.RA_WIDTH );
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Cols = 1 << ( 10
+ Proc->Uncore.MC[mc].Channel[cha].DIMM[slot].MTR.CA_WIDTH );
DIMM_Size = 8LLU
* Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Rows
* Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Cols
* Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Banks
* Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Ranks;
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Size=DIMM_Size >> 20;
}
}
Shm->Uncore.MC[mc].Channel[cha].Timing.ECC = \
Proc->Uncore.MC[mc].SNB_EP.TECH.ECC_EN
& !Proc->Uncore.Bus.SNB_EP_Cap3.ECC_DIS;
}
}
}
void SNB_EP_CAP(SHM_STRUCT *Shm, PROC_RO *Proc, CORE_RO *Core)
{
switch (Proc->Uncore.Bus.SNB_EP_Cap1.DMFC) {
case 0b111:
Shm->Uncore.CtrlSpeed = 1066;
break;
case 0b110:
Shm->Uncore.CtrlSpeed = 1333;
break;
case 0b101:
Shm->Uncore.CtrlSpeed = 1600;
break;
case 0b100:
Shm->Uncore.CtrlSpeed = 1866;
break;
case 0b011:
Shm->Uncore.CtrlSpeed = 2133;
break;
case 0b010:
Shm->Uncore.CtrlSpeed = 2400;
break;
case 0b001:
Shm->Uncore.CtrlSpeed = 2666;
break;
case 0b000:
Shm->Uncore.CtrlSpeed = 2933;
break;
}
Shm->Uncore.CtrlSpeed *= Core->Clock.Hz;
Shm->Uncore.CtrlSpeed /= Shm->Proc.Features.Factory.Clock.Hz;
Shm->Uncore.Bus.Rate = \
Proc->Uncore.Bus.QuickPath.IVB_EP.QPIFREQSEL == 0b010 ? 5600
: Proc->Uncore.Bus.QuickPath.IVB_EP.QPIFREQSEL == 0b011 ? 6400
: Proc->Uncore.Bus.QuickPath.IVB_EP.QPIFREQSEL == 0b100 ? 7200
: Proc->Uncore.Bus.QuickPath.IVB_EP.QPIFREQSEL == 0b101 ? 8000 : 5000;
Shm->Uncore.Bus.Speed = (Core->Clock.Hz * Shm->Uncore.Bus.Rate)
/ Shm->Proc.Features.Factory.Clock.Hz;
Shm->Uncore.Unit.Bus_Rate = 0b01;
Shm->Uncore.Unit.BusSpeed = 0b01;
Shm->Uncore.Unit.DDR_Rate = 0b11;
Shm->Uncore.Unit.DDRSpeed = 0b00;
Shm->Uncore.Unit.DDR_Ver = 3;
/* TODO */
Shm->Proc.Technology.IOMMU = 0;
}
void IVB_CAP(SHM_STRUCT *Shm, PROC_RO *Proc, CORE_RO *Core)
{
switch (Proc->Uncore.Bus.IVB_Cap.DMFC) {
case 0b111:
Shm->Uncore.CtrlSpeed = 1067;
break;
case 0b110:
Shm->Uncore.CtrlSpeed = 1333;
break;
case 0b101:
Shm->Uncore.CtrlSpeed = 1600;
break;
case 0b100:
Shm->Uncore.CtrlSpeed = 1867;
break;
case 0b011:
Shm->Uncore.CtrlSpeed = 2133;
break;
case 0b010:
Shm->Uncore.CtrlSpeed = 2400;
break;
case 0b001:
Shm->Uncore.CtrlSpeed = 2667;
break;
case 0b000:
switch (Proc->ArchID) {
case IvyBridge:
case Haswell_ULT:
Shm->Uncore.CtrlSpeed = 2933;
break;
case Haswell_DT:
case Haswell_EP:
case Haswell_ULX:
Shm->Uncore.CtrlSpeed = 2667;
break;
case Broadwell:
case Broadwell_D:
case Broadwell_H:
case Broadwell_EP:
Shm->Uncore.CtrlSpeed = 3200;
break;
}
break;
}
Shm->Uncore.Bus.Rate = 5000;
Shm->Uncore.Bus.Speed = (Core->Clock.Hz * Shm->Uncore.Bus.Rate)
/ Shm->Proc.Features.Factory.Clock.Hz;
Shm->Uncore.Unit.Bus_Rate = 0b01;
Shm->Uncore.Unit.BusSpeed = 0b01;
Shm->Uncore.Unit.DDR_Rate = 0b11;
Shm->Uncore.Unit.DDRSpeed = 0b00;
Shm->Uncore.Unit.DDR_Ver = 3;
Shm->Proc.Technology.IOMMU = !Proc->Uncore.Bus.SNB_Cap.VT_d;
}
void HSW_IMC(SHM_STRUCT *Shm, PROC_RO *Proc)
{
unsigned short mc, cha, slot;
for (mc = 0; mc < Shm->Uncore.CtrlCount; mc++)
{
unsigned short dimmSize[2][2] = {
{
Proc->Uncore.MC[mc].SNB.MAD0.Dimm_A_Size,
Proc->Uncore.MC[mc].SNB.MAD0.Dimm_B_Size
}, {
Proc->Uncore.MC[mc].SNB.MAD1.Dimm_A_Size,
Proc->Uncore.MC[mc].SNB.MAD1.Dimm_B_Size
}
};
Shm->Uncore.MC[mc].SlotCount = Proc->Uncore.MC[mc].SlotCount;
Shm->Uncore.MC[mc].ChannelCount = Proc->Uncore.MC[mc].ChannelCount;
for (cha = 0; cha < Shm->Uncore.MC[mc].ChannelCount; cha++) {
Shm->Uncore.MC[mc].Channel[cha].Timing.tCL =
Proc->Uncore.MC[mc].Channel[cha].HSW.Rank.tCL;
Shm->Uncore.MC[mc].Channel[cha].Timing.tCWL =
Proc->Uncore.MC[mc].Channel[cha].HSW.Rank.tCWL;
/*TODO(Not Found)
Shm->Uncore.MC[mc].Channel[cha].Timing.tWR =
Proc->Uncore.MC[mc].Channel[cha].HSW._.tWR;
Shm->Uncore.MC[mc].Channel[cha].Timing.tFAW =
Proc->Uncore.MC[mc].Channel[cha].HSW._.tFAW;
Shm->Uncore.MC[mc].Channel[cha].Timing.B2B =
Proc->Uncore.MC[mc].Channel[cha].HSW._.B2B;
*/
Shm->Uncore.MC[mc].Channel[cha].Timing.tRP =
Proc->Uncore.MC[mc].Channel[cha].HSW.REG4C00.tRP;
Shm->Uncore.MC[mc].Channel[cha].Timing.tRRD =
Proc->Uncore.MC[mc].Channel[cha].HSW.REG4C00.tRRD;
Shm->Uncore.MC[mc].Channel[cha].Timing.tRCD =
Proc->Uncore.MC[mc].Channel[cha].HSW.REG4C00.tRCD;
Shm->Uncore.MC[mc].Channel[cha].Timing.tRAS =
Proc->Uncore.MC[mc].Channel[cha].HSW.REG4C00.tRAS;
Shm->Uncore.MC[mc].Channel[cha].Timing.tRFC =
Proc->Uncore.MC[mc].Channel[cha].HSW.Refresh.tRFC;
Shm->Uncore.MC[mc].Channel[cha].Timing.tREFI =
Proc->Uncore.MC[mc].Channel[cha].HSW.Refresh.tREFI;
Shm->Uncore.MC[mc].Channel[cha].Timing.tsrRdTRd =
Proc->Uncore.MC[mc].Channel[cha].HSW.Timing.tsrRdTRd;
Shm->Uncore.MC[mc].Channel[cha].Timing.tdrRdTRd =
Proc->Uncore.MC[mc].Channel[cha].HSW.Timing.tdrRdTRd;
Shm->Uncore.MC[mc].Channel[cha].Timing.tddRdTRd =
Proc->Uncore.MC[mc].Channel[cha].HSW.Timing.tddRdTRd;
Shm->Uncore.MC[mc].Channel[cha].Timing.tsrWrTRd =
Proc->Uncore.MC[mc].Channel[cha].HSW.Rank_A.tsrWrTRd;
Shm->Uncore.MC[mc].Channel[cha].Timing.tdrWrTRd =
Proc->Uncore.MC[mc].Channel[cha].HSW.Rank_A.tdrWrTRd;
Shm->Uncore.MC[mc].Channel[cha].Timing.tddWrTRd =
Proc->Uncore.MC[mc].Channel[cha].HSW.Rank_A.tddWrTRd;
Shm->Uncore.MC[mc].Channel[cha].Timing.tsrWrTWr =
Proc->Uncore.MC[mc].Channel[cha].HSW.Rank_A.tsrWrTWr;
Shm->Uncore.MC[mc].Channel[cha].Timing.tdrWrTWr =
Proc->Uncore.MC[mc].Channel[cha].HSW.Rank_A.tdrWrTWr;
Shm->Uncore.MC[mc].Channel[cha].Timing.tddWrTWr =
Proc->Uncore.MC[mc].Channel[cha].HSW.Rank_A.tddWrTWr;
Shm->Uncore.MC[mc].Channel[cha].Timing.tsrRdTWr =
Proc->Uncore.MC[mc].Channel[cha].HSW.Rank_B.tsrRdTWr;
Shm->Uncore.MC[mc].Channel[cha].Timing.tdrRdTWr =
Proc->Uncore.MC[mc].Channel[cha].HSW.Rank_B.tdrRdTWr;
Shm->Uncore.MC[mc].Channel[cha].Timing.tddRdTWr =
Proc->Uncore.MC[mc].Channel[cha].HSW.Rank_B.tddRdTWr;
switch (Proc->Uncore.MC[mc].Channel[cha].HSW.Timing.CMD_Stretch) {
case 0b00:
Shm->Uncore.MC[mc].Channel[cha].Timing.CMD_Rate = 1;
break;
case 0b10:
Shm->Uncore.MC[mc].Channel[cha].Timing.CMD_Rate = 2;
break;
case 0b11:
Shm->Uncore.MC[mc].Channel[cha].Timing.CMD_Rate = 3;
break;
default:
Shm->Uncore.MC[mc].Channel[cha].Timing.CMD_Rate = 0;
break;
}
for (slot = 0; slot < Shm->Uncore.MC[mc].SlotCount; slot++)
{
unsigned int width, DIMM_Banks;
if (slot == 0) {
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Ranks =
Proc->Uncore.MC[mc].SNB.MAD0.DANOR;
width = Proc->Uncore.MC[mc].SNB.MAD0.DAW;
} else {
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Ranks =
Proc->Uncore.MC[mc].SNB.MAD0.DBNOR;
width = Proc->Uncore.MC[mc].SNB.MAD0.DBW;
}
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Ranks++;
if (width == 0) {
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Rows = 1 << 14;
} else {
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Rows = 1 << 15;
}
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Cols = 1 << 10;
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Size =
dimmSize[cha][slot] * 256;
DIMM_Banks = 8 * dimmSize[cha][slot] * 1024 * 1024;
DIMM_Banks = DIMM_Banks
/ (Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Rows
* Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Cols
* Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Ranks);
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Banks = DIMM_Banks;
}
Shm->Uncore.MC[mc].Channel[cha].Timing.ECC = (cha == 0) ?
Proc->Uncore.MC[mc].SNB.MAD0.ECC
: Proc->Uncore.MC[mc].SNB.MAD1.ECC;
}
}
}
unsigned int SKL_DimmWidthToRows(unsigned int width)
{
unsigned int rows = 0;
switch (width) {
case 0b00:
rows = 8;
break;
case 0b01:
rows = 16;
break;
case 0b10:
rows = 32;
break;
}
return (8 * 1024 * rows);
}
void SKL_IMC(SHM_STRUCT *Shm, PROC_RO *Proc)
{
unsigned short mc, cha;
for (mc = 0; mc < Shm->Uncore.CtrlCount; mc++)
{
Shm->Uncore.MC[mc].SlotCount = Proc->Uncore.MC[mc].SlotCount;
Shm->Uncore.MC[mc].ChannelCount = Proc->Uncore.MC[mc].ChannelCount;
for (cha = 0; cha < Shm->Uncore.MC[mc].ChannelCount; cha++)
{
Shm->Uncore.MC[mc].Channel[cha].Timing.tCL =
Proc->Uncore.MC[mc].Channel[cha].SKL.ODT.tCL;
Shm->Uncore.MC[mc].Channel[cha].Timing.tRCD =
Proc->Uncore.MC[mc].Channel[cha].SKL.Timing.tRP;
Shm->Uncore.MC[mc].Channel[cha].Timing.tRP =
Proc->Uncore.MC[mc].Channel[cha].SKL.Timing.tRP;
Shm->Uncore.MC[mc].Channel[cha].Timing.tRAS =
Proc->Uncore.MC[mc].Channel[cha].SKL.Timing.tRAS;
Shm->Uncore.MC[mc].Channel[cha].Timing.tRRD =
Proc->Uncore.MC[mc].Channel[cha].SKL.ACT.tRRD_SG;
Shm->Uncore.MC[mc].Channel[cha].Timing.tRFC =
Proc->Uncore.MC[mc].Channel[cha].SKL.Refresh.tRFC;
Shm->Uncore.MC[mc].Channel[cha].Timing.tREFI =
Proc->Uncore.MC[mc].Channel[cha].SKL.Refresh.tREFI;
Shm->Uncore.MC[mc].Channel[cha].Timing.tWR =
Proc->Uncore.MC[mc].Channel[cha].SKL.Timing.tWRPRE
- Proc->Uncore.MC[mc].Channel[cha].SKL.ODT.tCWL - 4;
Shm->Uncore.MC[mc].Channel[cha].Timing.tRTPr =
Proc->Uncore.MC[mc].Channel[cha].SKL.Timing.tRDPRE;
Shm->Uncore.MC[mc].Channel[cha].Timing.tWTPr =
Proc->Uncore.MC[mc].Channel[cha].SKL.Timing.tWRPRE;
Shm->Uncore.MC[mc].Channel[cha].Timing.tFAW =
Proc->Uncore.MC[mc].Channel[cha].SKL.ACT.tFAW;
Shm->Uncore.MC[mc].Channel[cha].Timing.tCWL =
Proc->Uncore.MC[mc].Channel[cha].SKL.ODT.tCWL;
Shm->Uncore.MC[mc].Channel[cha].Timing.DDR4.tRDRD_SG =
Proc->Uncore.MC[mc].Channel[cha].SKL.RDRD.tRDRD_SG;
Shm->Uncore.MC[mc].Channel[cha].Timing.DDR4.tRDRD_DG =
Proc->Uncore.MC[mc].Channel[cha].SKL.RDRD.tRDRD_DG;
Shm->Uncore.MC[mc].Channel[cha].Timing.DDR4.tRDRD_DR =
Proc->Uncore.MC[mc].Channel[cha].SKL.RDRD.tRDRD_DR;
Shm->Uncore.MC[mc].Channel[cha].Timing.DDR4.tRDRD_DD =
Proc->Uncore.MC[mc].Channel[cha].SKL.RDRD.tRDRD_DD;
Shm->Uncore.MC[mc].Channel[cha].Timing.DDR4.tRDWR_SG =
Proc->Uncore.MC[mc].Channel[cha].SKL.RDWR.tRDWR_SG;
Shm->Uncore.MC[mc].Channel[cha].Timing.DDR4.tRDWR_DG =
Proc->Uncore.MC[mc].Channel[cha].SKL.RDWR.tRDWR_DG;
Shm->Uncore.MC[mc].Channel[cha].Timing.DDR4.tRDWR_DR =
Proc->Uncore.MC[mc].Channel[cha].SKL.RDWR.tRDWR_DR;
Shm->Uncore.MC[mc].Channel[cha].Timing.DDR4.tRDWR_DD =
Proc->Uncore.MC[mc].Channel[cha].SKL.RDWR.tRDWR_DD;
Shm->Uncore.MC[mc].Channel[cha].Timing.DDR4.tWRRD_SG =
Proc->Uncore.MC[mc].Channel[cha].SKL.WRRD.tWRRD_SG;
Shm->Uncore.MC[mc].Channel[cha].Timing.DDR4.tWRRD_DG =
Proc->Uncore.MC[mc].Channel[cha].SKL.WRRD.tWRRD_DG;
Shm->Uncore.MC[mc].Channel[cha].Timing.DDR4.tWRRD_DR =
Proc->Uncore.MC[mc].Channel[cha].SKL.WRRD.tWRRD_DR;
Shm->Uncore.MC[mc].Channel[cha].Timing.DDR4.tWRRD_DD =
Proc->Uncore.MC[mc].Channel[cha].SKL.WRRD.tWRRD_DD;
Shm->Uncore.MC[mc].Channel[cha].Timing.DDR4.tWRWR_SG =
Proc->Uncore.MC[mc].Channel[cha].SKL.WRWR.tWRWR_SG;
Shm->Uncore.MC[mc].Channel[cha].Timing.DDR4.tWRWR_DG =
Proc->Uncore.MC[mc].Channel[cha].SKL.WRWR.tWRWR_DG;
Shm->Uncore.MC[mc].Channel[cha].Timing.DDR4.tWRWR_DR =
Proc->Uncore.MC[mc].Channel[cha].SKL.WRWR.tWRWR_DR;
Shm->Uncore.MC[mc].Channel[cha].Timing.DDR4.tWRWR_DD =
Proc->Uncore.MC[mc].Channel[cha].SKL.WRWR.tWRWR_DD;
switch (Proc->Uncore.MC[mc].Channel[cha].SKL.Sched.CMD_Stretch) {
case 0b00:
case 0b11:
Shm->Uncore.MC[mc].Channel[cha].Timing.CMD_Rate = 1;
break;
case 0b01:
Shm->Uncore.MC[mc].Channel[cha].Timing.CMD_Rate = 2;
break;
case 0b10:
Shm->Uncore.MC[mc].Channel[cha].Timing.CMD_Rate = 3;
break;
}
Shm->Uncore.MC[mc].Channel[cha].DIMM[0].Banks = \
Shm->Uncore.MC[mc].Channel[cha].DIMM[1].Banks = \
Proc->Uncore.MC[mc].Channel[cha].SKL.Sched.DRAM_Tech == 0b00 ? 16 : 8;
Shm->Uncore.MC[mc].Channel[cha].DIMM[0].Cols = \
Proc->Uncore.MC[mc].Channel[cha].SKL.Sched.x8_device_Dimm0 ?
1024 : 512;
Shm->Uncore.MC[mc].Channel[cha].DIMM[1].Cols = \
Proc->Uncore.MC[mc].Channel[cha].SKL.Sched.x8_device_Dimm1 ?
1024 : 512;
Shm->Uncore.MC[mc].Channel[cha].Timing.tCKE =
Proc->Uncore.MC[mc].Channel[cha].SKL.Sched.tCKE;
}
Shm->Uncore.MC[mc].Channel[0].Timing.ECC =
Proc->Uncore.MC[mc].SKL.MADC0.ECC;
Shm->Uncore.MC[mc].Channel[1].Timing.ECC =
Proc->Uncore.MC[mc].SKL.MADC1.ECC;
Shm->Uncore.MC[mc].Channel[0].DIMM[
Proc->Uncore.MC[mc].SKL.MADC0.Dimm_L_Map
].Size = 1024 * Proc->Uncore.MC[mc].SKL.MADD0.Dimm_L_Size;
Shm->Uncore.MC[mc].Channel[0].DIMM[
!Proc->Uncore.MC[mc].SKL.MADC0.Dimm_L_Map
].Size = 1024 * Proc->Uncore.MC[mc].SKL.MADD0.Dimm_S_Size;
Shm->Uncore.MC[mc].Channel[1].DIMM[
Proc->Uncore.MC[mc].SKL.MADC1.Dimm_L_Map
].Size = 1024 * Proc->Uncore.MC[mc].SKL.MADD1.Dimm_L_Size;
Shm->Uncore.MC[mc].Channel[1].DIMM[
!Proc->Uncore.MC[mc].SKL.MADC1.Dimm_L_Map
].Size = 1024 * Proc->Uncore.MC[mc].SKL.MADD1.Dimm_S_Size;
Shm->Uncore.MC[mc].Channel[0].DIMM[
Proc->Uncore.MC[mc].SKL.MADC0.Dimm_L_Map
].Ranks = 1 + Proc->Uncore.MC[mc].SKL.MADD0.DLNOR;
Shm->Uncore.MC[mc].Channel[0].DIMM[
!Proc->Uncore.MC[mc].SKL.MADC0.Dimm_L_Map
].Ranks = 1 + Proc->Uncore.MC[mc].SKL.MADD0.DSNOR;
Shm->Uncore.MC[mc].Channel[1].DIMM[
Proc->Uncore.MC[mc].SKL.MADC1.Dimm_L_Map
].Ranks = 1 + Proc->Uncore.MC[mc].SKL.MADD1.DLNOR;
Shm->Uncore.MC[mc].Channel[1].DIMM[
!Proc->Uncore.MC[mc].SKL.MADC1.Dimm_L_Map
].Ranks = 1 + Proc->Uncore.MC[mc].SKL.MADD1.DSNOR;
Shm->Uncore.MC[mc].Channel[0].DIMM[
Proc->Uncore.MC[mc].SKL.MADC0.Dimm_L_Map
].Rows = SKL_DimmWidthToRows(Proc->Uncore.MC[mc].SKL.MADD0.DLW);
Shm->Uncore.MC[mc].Channel[0].DIMM[
!Proc->Uncore.MC[mc].SKL.MADC0.Dimm_L_Map
].Rows = SKL_DimmWidthToRows(Proc->Uncore.MC[mc].SKL.MADD0.DSW);
Shm->Uncore.MC[mc].Channel[1].DIMM[
Proc->Uncore.MC[mc].SKL.MADC1.Dimm_L_Map
].Rows = SKL_DimmWidthToRows(Proc->Uncore.MC[mc].SKL.MADD1.DLW);
Shm->Uncore.MC[mc].Channel[1].DIMM[
!Proc->Uncore.MC[mc].SKL.MADC1.Dimm_L_Map
].Rows = SKL_DimmWidthToRows(Proc->Uncore.MC[mc].SKL.MADD1.DSW);
}
}
void SKL_CAP(SHM_STRUCT *Shm, PROC_RO *Proc, CORE_RO *Core)
{
unsigned int DMFC;
switch (Proc->ArchID) {
case Skylake_UY:
case Kabylake_UY:
DMFC = Proc->Uncore.Bus.SKL_Cap_B.DMFC_DDR3;
Shm->Uncore.Bus.Rate = 4000; /* 4 GT/s QPI */
break;
default:
DMFC = Proc->Uncore.Bus.SKL_Cap_C.DMFC_DDR4;
Shm->Uncore.Bus.Rate = 8000; /* 8 GT/s DMI3 */
break;
}
switch (DMFC) {
case 0b111:
Shm->Uncore.CtrlSpeed = 1067;
break;
case 0b110:
Shm->Uncore.CtrlSpeed = 1333;
break;
case 0b101:
Shm->Uncore.CtrlSpeed = 1600;
break;
case 0b100:
Shm->Uncore.CtrlSpeed = 1867;
break;
case 0b011:
Shm->Uncore.CtrlSpeed = 2133;
break;
case 0b010:
Shm->Uncore.CtrlSpeed = 2400;
break;
case 0b001:
case 0b000:
Shm->Uncore.CtrlSpeed = 2667;
break;
}
Shm->Uncore.Bus.Speed = (Core->Clock.Hz * Shm->Uncore.Bus.Rate)
/ Shm->Proc.Features.Factory.Clock.Hz;
Shm->Uncore.Unit.Bus_Rate = 0b01;
Shm->Uncore.Unit.BusSpeed = 0b01;
Shm->Uncore.Unit.DDR_Rate = 0b11;
Shm->Uncore.Unit.DDRSpeed = 0b00;
Shm->Uncore.Unit.DDR_Ver = 4;
Shm->Proc.Technology.IOMMU = !Proc->Uncore.Bus.SKL_Cap_A.VT_d;
Shm->Proc.Technology.IOMMU_Ver_Major = Proc->Uncore.Bus.IOMMU_Ver.Major;
Shm->Proc.Technology.IOMMU_Ver_Minor = Proc->Uncore.Bus.IOMMU_Ver.Minor;
}
void RKL_IMC(SHM_STRUCT *Shm, PROC_RO *Proc)
{
unsigned short mc, cha;
for (mc = 0; mc < Shm->Uncore.CtrlCount; mc++)
{
Shm->Uncore.MC[mc].SlotCount = Proc->Uncore.MC[mc].SlotCount;
Shm->Uncore.MC[mc].ChannelCount = Proc->Uncore.MC[mc].ChannelCount;
for (cha = 0; cha < Shm->Uncore.MC[mc].ChannelCount; cha++)
{
Shm->Uncore.MC[mc].Channel[cha].Timing.tCL =
Proc->Uncore.MC[mc].Channel[cha].RKL.ODT.tCL;
Shm->Uncore.MC[mc].Channel[cha].Timing.tRCD =
Proc->Uncore.MC[mc].Channel[cha].RKL.Timing.tRP;
Shm->Uncore.MC[mc].Channel[cha].Timing.tRP =
Proc->Uncore.MC[mc].Channel[cha].RKL.Timing.tRP;
Shm->Uncore.MC[mc].Channel[cha].Timing.tRAS =
Proc->Uncore.MC[mc].Channel[cha].RKL.Timing.tRAS;
Shm->Uncore.MC[mc].Channel[cha].Timing.tRRD =
Proc->Uncore.MC[mc].Channel[cha].RKL.ACT.tRRD_SG;
Shm->Uncore.MC[mc].Channel[cha].Timing.tRFC =
Proc->Uncore.MC[mc].Channel[cha].RKL.Refresh.tRFC;
Shm->Uncore.MC[mc].Channel[cha].Timing.tREFI =
Proc->Uncore.MC[mc].Channel[cha].RKL.Refresh.tREFI;
Shm->Uncore.MC[mc].Channel[cha].Timing.tWR =
Proc->Uncore.MC[mc].Channel[cha].RKL.Timing.tWRPRE
- Proc->Uncore.MC[mc].Channel[cha].RKL.ODT.tCWL - 4;
Shm->Uncore.MC[mc].Channel[cha].Timing.tRTPr =
Proc->Uncore.MC[mc].Channel[cha].RKL.Timing.tRDPRE;
Shm->Uncore.MC[mc].Channel[cha].Timing.tWTPr =
Proc->Uncore.MC[mc].Channel[cha].RKL.Timing.tWRPRE;
Shm->Uncore.MC[mc].Channel[cha].Timing.tFAW =
Proc->Uncore.MC[mc].Channel[cha].RKL.ACT.tFAW;
Shm->Uncore.MC[mc].Channel[cha].Timing.tCWL =
Proc->Uncore.MC[mc].Channel[cha].RKL.ODT.tCWL;
Shm->Uncore.MC[mc].Channel[cha].Timing.DDR4.tRDRD_SG =
Proc->Uncore.MC[mc].Channel[cha].RKL.RDRD.tRDRD_SG;
Shm->Uncore.MC[mc].Channel[cha].Timing.DDR4.tRDRD_DG =
Proc->Uncore.MC[mc].Channel[cha].RKL.RDRD.tRDRD_DG;
Shm->Uncore.MC[mc].Channel[cha].Timing.DDR4.tRDRD_DR =
Proc->Uncore.MC[mc].Channel[cha].RKL.RDRD.tRDRD_DR;
Shm->Uncore.MC[mc].Channel[cha].Timing.DDR4.tRDRD_DD =
Proc->Uncore.MC[mc].Channel[cha].RKL.RDRD.tRDRD_DD;
Shm->Uncore.MC[mc].Channel[cha].Timing.DDR4.tRDWR_SG =
Proc->Uncore.MC[mc].Channel[cha].RKL.RDWR.tRDWR_SG;
Shm->Uncore.MC[mc].Channel[cha].Timing.DDR4.tRDWR_DG =
Proc->Uncore.MC[mc].Channel[cha].RKL.RDWR.tRDWR_DG;
Shm->Uncore.MC[mc].Channel[cha].Timing.DDR4.tRDWR_DR =
Proc->Uncore.MC[mc].Channel[cha].RKL.RDWR.tRDWR_DR;
Shm->Uncore.MC[mc].Channel[cha].Timing.DDR4.tRDWR_DD =
Proc->Uncore.MC[mc].Channel[cha].RKL.RDWR.tRDWR_DD;
Shm->Uncore.MC[mc].Channel[cha].Timing.DDR4.tWRRD_SG =
Proc->Uncore.MC[mc].Channel[cha].RKL.WRRD.tWRRD_SG;
Shm->Uncore.MC[mc].Channel[cha].Timing.DDR4.tWRRD_DG =
Proc->Uncore.MC[mc].Channel[cha].RKL.WRRD.tWRRD_DG;
Shm->Uncore.MC[mc].Channel[cha].Timing.DDR4.tWRRD_DR =
Proc->Uncore.MC[mc].Channel[cha].RKL.WRRD.tWRRD_DR;
Shm->Uncore.MC[mc].Channel[cha].Timing.DDR4.tWRRD_DD =
Proc->Uncore.MC[mc].Channel[cha].RKL.WRRD.tWRRD_DD;
Shm->Uncore.MC[mc].Channel[cha].Timing.DDR4.tWRWR_SG =
Proc->Uncore.MC[mc].Channel[cha].RKL.WRWR.tWRWR_SG;
Shm->Uncore.MC[mc].Channel[cha].Timing.DDR4.tWRWR_DG =
Proc->Uncore.MC[mc].Channel[cha].RKL.WRWR.tWRWR_DG;
Shm->Uncore.MC[mc].Channel[cha].Timing.DDR4.tWRWR_DR =
Proc->Uncore.MC[mc].Channel[cha].RKL.WRWR.tWRWR_DR;
Shm->Uncore.MC[mc].Channel[cha].Timing.DDR4.tWRWR_DD =
Proc->Uncore.MC[mc].Channel[cha].RKL.WRWR.tWRWR_DD;
switch (Proc->Uncore.MC[mc].Channel[cha].RKL.Sched.CMD_Stretch) {
case 0b00:
case 0b11:
Shm->Uncore.MC[mc].Channel[cha].Timing.CMD_Rate = 1;
break;
case 0b01:
Shm->Uncore.MC[mc].Channel[cha].Timing.CMD_Rate = 2;
break;
case 0b10:
Shm->Uncore.MC[mc].Channel[cha].Timing.CMD_Rate = 3;
break;
}
Shm->Uncore.MC[mc].Channel[cha].DIMM[0].Banks = \
Shm->Uncore.MC[mc].Channel[cha].DIMM[1].Banks = \
!Proc->Uncore.MC[mc].Channel[cha].RKL.Sched.ReservedBits1 ? 16 : 8;
Shm->Uncore.MC[mc].Channel[cha].DIMM[0].Cols = \
Proc->Uncore.MC[mc].Channel[cha].RKL.Sched.x8_device_Dimm0 ?
1024 : 512;
Shm->Uncore.MC[mc].Channel[cha].DIMM[1].Cols = \
Proc->Uncore.MC[mc].Channel[cha].RKL.Sched.x8_device_Dimm1 ?
1024 : 512;
Shm->Uncore.MC[mc].Channel[cha].Timing.tCKE =
Proc->Uncore.MC[mc].Channel[cha].RKL.PWDEN.tCKE;
}
Shm->Uncore.MC[mc].Channel[0].Timing.ECC =
Proc->Uncore.MC[mc].RKL.MADC0.ECC;
Shm->Uncore.MC[mc].Channel[1].Timing.ECC =
Proc->Uncore.MC[mc].RKL.MADC1.ECC;
Shm->Uncore.MC[mc].Channel[0].DIMM[
Proc->Uncore.MC[mc].RKL.MADC0.Dimm_L_Map
].Size = 512 * Proc->Uncore.MC[mc].RKL.MADD0.Dimm_L_Size;
Shm->Uncore.MC[mc].Channel[0].DIMM[
!Proc->Uncore.MC[mc].RKL.MADC0.Dimm_L_Map
].Size = 512 * Proc->Uncore.MC[mc].RKL.MADD0.Dimm_S_Size;
Shm->Uncore.MC[mc].Channel[1].DIMM[
Proc->Uncore.MC[mc].RKL.MADC1.Dimm_L_Map
].Size = 512 * Proc->Uncore.MC[mc].RKL.MADD1.Dimm_L_Size;
Shm->Uncore.MC[mc].Channel[1].DIMM[
!Proc->Uncore.MC[mc].RKL.MADC1.Dimm_L_Map
].Size = 512 * Proc->Uncore.MC[mc].RKL.MADD1.Dimm_S_Size;
Shm->Uncore.MC[mc].Channel[0].DIMM[
Proc->Uncore.MC[mc].RKL.MADC0.Dimm_L_Map
].Ranks = 1 + Proc->Uncore.MC[mc].RKL.MADD0.DLNOR;
Shm->Uncore.MC[mc].Channel[0].DIMM[
!Proc->Uncore.MC[mc].RKL.MADC0.Dimm_L_Map
].Ranks = 1 + Proc->Uncore.MC[mc].RKL.MADD0.DSNOR;
Shm->Uncore.MC[mc].Channel[1].DIMM[
Proc->Uncore.MC[mc].RKL.MADC1.Dimm_L_Map
].Ranks = 1 + Proc->Uncore.MC[mc].RKL.MADD1.DLNOR;
Shm->Uncore.MC[mc].Channel[1].DIMM[
!Proc->Uncore.MC[mc].RKL.MADC1.Dimm_L_Map
].Ranks = 1 + Proc->Uncore.MC[mc].RKL.MADD1.DSNOR;
Shm->Uncore.MC[mc].Channel[0].DIMM[
Proc->Uncore.MC[mc].RKL.MADC0.Dimm_L_Map
].Rows = SKL_DimmWidthToRows(Proc->Uncore.MC[mc].RKL.MADD0.DLW);
Shm->Uncore.MC[mc].Channel[0].DIMM[
!Proc->Uncore.MC[mc].RKL.MADC0.Dimm_L_Map
].Rows = SKL_DimmWidthToRows(Proc->Uncore.MC[mc].RKL.MADD0.DSW);
Shm->Uncore.MC[mc].Channel[1].DIMM[
Proc->Uncore.MC[mc].RKL.MADC1.Dimm_L_Map
].Rows = SKL_DimmWidthToRows(Proc->Uncore.MC[mc].RKL.MADD1.DLW);
Shm->Uncore.MC[mc].Channel[1].DIMM[
!Proc->Uncore.MC[mc].RKL.MADC1.Dimm_L_Map
].Rows = SKL_DimmWidthToRows(Proc->Uncore.MC[mc].RKL.MADD1.DSW);
}
}
void RKL_CAP(SHM_STRUCT *Shm, PROC_RO *Proc, CORE_RO *Core)
{
unsigned int units;
Shm->Uncore.Bus.Rate = 8000;
Shm->Uncore.Bus.Speed = (Core->Clock.Hz * Shm->Uncore.Bus.Rate)
/ Shm->Proc.Features.Factory.Clock.Hz;
if (Proc->Uncore.Bus.RKL_Cap_C.LPDDR4_EN
&& !Proc->Uncore.Bus.RKL_Cap_A.DDR_OVERCLOCK) {
units = Proc->Uncore.Bus.RKL_Cap_C.DATA_RATE_LPDDR4;
} else if (Proc->Uncore.Bus.RKL_Cap_C.DDR4_EN
&& !Proc->Uncore.Bus.RKL_Cap_A.DDR_OVERCLOCK) {
units = Proc->Uncore.Bus.RKL_Cap_C.DATA_RATE_DDR4;
} else {
units = 12;
}
Shm->Uncore.CtrlSpeed = (266 * units) + ((333 * units) / 500);
Shm->Uncore.Unit.Bus_Rate = 0b01;
Shm->Uncore.Unit.BusSpeed = 0b01;
Shm->Uncore.Unit.DDR_Rate = 0b11;
Shm->Uncore.Unit.DDRSpeed = 0b00;
Shm->Uncore.Unit.DDR_Ver = Proc->Uncore.MC[0].RKL.MADCH.DDR_TYPE ? 5:4;
Shm->Proc.Technology.IOMMU = !Proc->Uncore.Bus.RKL_Cap_A.VT_d;
Shm->Proc.Technology.IOMMU_Ver_Major = Proc->Uncore.Bus.IOMMU_Ver.Major;
Shm->Proc.Technology.IOMMU_Ver_Minor = Proc->Uncore.Bus.IOMMU_Ver.Minor;
}
void TGL_IMC(SHM_STRUCT *Shm, PROC_RO *Proc)
{
unsigned short mc, cha;
for (mc = 0; mc < Shm->Uncore.CtrlCount; mc++)
{
Shm->Uncore.MC[mc].SlotCount = Proc->Uncore.MC[mc].SlotCount;
Shm->Uncore.MC[mc].ChannelCount = Proc->Uncore.MC[mc].ChannelCount;
for (cha = 0; cha < Shm->Uncore.MC[mc].ChannelCount; cha++)
{
Shm->Uncore.MC[mc].Channel[cha].Timing.tCL =
Proc->Uncore.MC[mc].Channel[cha].TGL.ODT.tCL;
Shm->Uncore.MC[mc].Channel[cha].Timing.tRCD =
Proc->Uncore.MC[mc].Channel[cha].TGL.Timing.tRP;
Shm->Uncore.MC[mc].Channel[cha].Timing.tRP =
Proc->Uncore.MC[mc].Channel[cha].TGL.Timing.tRP;
Shm->Uncore.MC[mc].Channel[cha].Timing.tRAS =
Proc->Uncore.MC[mc].Channel[cha].TGL.Timing.tRAS;
Shm->Uncore.MC[mc].Channel[cha].Timing.tRRD =
Proc->Uncore.MC[mc].Channel[cha].TGL.ACT.tRRD_SG;
Shm->Uncore.MC[mc].Channel[cha].Timing.tRFC =
Proc->Uncore.MC[mc].Channel[cha].TGL.Refresh.tRFC;
Shm->Uncore.MC[mc].Channel[cha].Timing.tREFI =
Proc->Uncore.MC[mc].Channel[cha].TGL.Refresh.tREFI;
Shm->Uncore.MC[mc].Channel[cha].Timing.tWR =
Proc->Uncore.MC[mc].Channel[cha].TGL.Timing.tWRPRE
- Proc->Uncore.MC[mc].Channel[cha].TGL.ODT.tCWL - 4;
Shm->Uncore.MC[mc].Channel[cha].Timing.tRTPr =
Proc->Uncore.MC[mc].Channel[cha].TGL.Timing.tRDPRE;
Shm->Uncore.MC[mc].Channel[cha].Timing.tWTPr =
Proc->Uncore.MC[mc].Channel[cha].TGL.Timing.tWRPRE;
Shm->Uncore.MC[mc].Channel[cha].Timing.tFAW =
Proc->Uncore.MC[mc].Channel[cha].TGL.ACT.tFAW;
Shm->Uncore.MC[mc].Channel[cha].Timing.tCWL =
Proc->Uncore.MC[mc].Channel[cha].TGL.ODT.tCWL;
Shm->Uncore.MC[mc].Channel[cha].Timing.DDR4.tRDRD_SG =
Proc->Uncore.MC[mc].Channel[cha].TGL.RDRD.tRDRD_SG;
Shm->Uncore.MC[mc].Channel[cha].Timing.DDR4.tRDRD_DG =
Proc->Uncore.MC[mc].Channel[cha].TGL.RDRD.tRDRD_DG;
Shm->Uncore.MC[mc].Channel[cha].Timing.DDR4.tRDRD_DR =
Proc->Uncore.MC[mc].Channel[cha].TGL.RDRD.tRDRD_DR;
Shm->Uncore.MC[mc].Channel[cha].Timing.DDR4.tRDRD_DD =
Proc->Uncore.MC[mc].Channel[cha].TGL.RDRD.tRDRD_DD;
Shm->Uncore.MC[mc].Channel[cha].Timing.DDR4.tRDWR_SG =
Proc->Uncore.MC[mc].Channel[cha].TGL.RDWR.tRDWR_SG;
Shm->Uncore.MC[mc].Channel[cha].Timing.DDR4.tRDWR_DG =
Proc->Uncore.MC[mc].Channel[cha].TGL.RDWR.tRDWR_DG;
Shm->Uncore.MC[mc].Channel[cha].Timing.DDR4.tRDWR_DR =
Proc->Uncore.MC[mc].Channel[cha].TGL.RDWR.tRDWR_DR;
Shm->Uncore.MC[mc].Channel[cha].Timing.DDR4.tRDWR_DD =
Proc->Uncore.MC[mc].Channel[cha].TGL.RDWR.tRDWR_DD;
Shm->Uncore.MC[mc].Channel[cha].Timing.DDR4.tWRRD_SG =
Proc->Uncore.MC[mc].Channel[cha].TGL.WRRD.tWRRD_SG;
Shm->Uncore.MC[mc].Channel[cha].Timing.DDR4.tWRRD_DG =
Proc->Uncore.MC[mc].Channel[cha].TGL.WRRD.tWRRD_DG;
Shm->Uncore.MC[mc].Channel[cha].Timing.DDR4.tWRRD_DR =
Proc->Uncore.MC[mc].Channel[cha].TGL.WRRD.tWRRD_DR;
Shm->Uncore.MC[mc].Channel[cha].Timing.DDR4.tWRRD_DD =
Proc->Uncore.MC[mc].Channel[cha].TGL.WRRD.tWRRD_DD;
Shm->Uncore.MC[mc].Channel[cha].Timing.DDR4.tWRWR_SG =
Proc->Uncore.MC[mc].Channel[cha].TGL.WRWR.tWRWR_SG;
Shm->Uncore.MC[mc].Channel[cha].Timing.DDR4.tWRWR_DG =
Proc->Uncore.MC[mc].Channel[cha].TGL.WRWR.tWRWR_DG;
Shm->Uncore.MC[mc].Channel[cha].Timing.DDR4.tWRWR_DR =
Proc->Uncore.MC[mc].Channel[cha].TGL.WRWR.tWRWR_DR;
Shm->Uncore.MC[mc].Channel[cha].Timing.DDR4.tWRWR_DD =
Proc->Uncore.MC[mc].Channel[cha].TGL.WRWR.tWRWR_DD;
switch (Proc->Uncore.MC[mc].Channel[cha].TGL.Sched.CMD_Stretch) {
case 0b00:
case 0b11:
Shm->Uncore.MC[mc].Channel[cha].Timing.CMD_Rate = 1;
break;
case 0b01:
Shm->Uncore.MC[mc].Channel[cha].Timing.CMD_Rate = 2;
break;
case 0b10:
Shm->Uncore.MC[mc].Channel[cha].Timing.CMD_Rate = 3;
break;
}
Shm->Uncore.MC[mc].Channel[cha].DIMM[0].Banks = \
Shm->Uncore.MC[mc].Channel[cha].DIMM[1].Banks = \
!Proc->Uncore.MC[mc].Channel[cha].TGL.Sched.ReservedBits1 ? 16 : 8;
Shm->Uncore.MC[mc].Channel[cha].DIMM[0].Cols = \
Proc->Uncore.MC[mc].Channel[cha].TGL.Sched.x8_device_Dimm0 ?
1024 : 512;
Shm->Uncore.MC[mc].Channel[cha].DIMM[1].Cols = \
Proc->Uncore.MC[mc].Channel[cha].TGL.Sched.x8_device_Dimm1 ?
1024 : 512;
Shm->Uncore.MC[mc].Channel[cha].Timing.tCKE =
Proc->Uncore.MC[mc].Channel[cha].TGL.PWDEN.tCKE;
}
Shm->Uncore.MC[mc].Channel[0].Timing.ECC =
Proc->Uncore.MC[mc].TGL.MADC0.ECC;
Shm->Uncore.MC[mc].Channel[1].Timing.ECC =
Proc->Uncore.MC[mc].TGL.MADC1.ECC;
Shm->Uncore.MC[mc].Channel[0].DIMM[
Proc->Uncore.MC[mc].TGL.MADC0.Dimm_L_Map
].Size = 512 * Proc->Uncore.MC[mc].TGL.MADD0.Dimm_L_Size;
Shm->Uncore.MC[mc].Channel[0].DIMM[
!Proc->Uncore.MC[mc].TGL.MADC0.Dimm_L_Map
].Size = 512 * Proc->Uncore.MC[mc].TGL.MADD0.Dimm_S_Size;
Shm->Uncore.MC[mc].Channel[1].DIMM[
Proc->Uncore.MC[mc].TGL.MADC1.Dimm_L_Map
].Size = 512 * Proc->Uncore.MC[mc].TGL.MADD1.Dimm_L_Size;
Shm->Uncore.MC[mc].Channel[1].DIMM[
!Proc->Uncore.MC[mc].TGL.MADC1.Dimm_L_Map
].Size = 512 * Proc->Uncore.MC[mc].TGL.MADD1.Dimm_S_Size;
Shm->Uncore.MC[mc].Channel[0].DIMM[
Proc->Uncore.MC[mc].TGL.MADC0.Dimm_L_Map
].Ranks = 1 + Proc->Uncore.MC[mc].TGL.MADD0.DLNOR;
Shm->Uncore.MC[mc].Channel[0].DIMM[
!Proc->Uncore.MC[mc].TGL.MADC0.Dimm_L_Map
].Ranks = 1 + Proc->Uncore.MC[mc].TGL.MADD0.DSNOR;
Shm->Uncore.MC[mc].Channel[1].DIMM[
Proc->Uncore.MC[mc].TGL.MADC1.Dimm_L_Map
].Ranks = 1 + Proc->Uncore.MC[mc].TGL.MADD1.DLNOR;
Shm->Uncore.MC[mc].Channel[1].DIMM[
!Proc->Uncore.MC[mc].TGL.MADC1.Dimm_L_Map
].Ranks = 1 + Proc->Uncore.MC[mc].TGL.MADD1.DSNOR;
Shm->Uncore.MC[mc].Channel[0].DIMM[
Proc->Uncore.MC[mc].TGL.MADC0.Dimm_L_Map
].Rows = SKL_DimmWidthToRows(Proc->Uncore.MC[mc].TGL.MADD0.DLW);
Shm->Uncore.MC[mc].Channel[0].DIMM[
!Proc->Uncore.MC[mc].TGL.MADC0.Dimm_L_Map
].Rows = SKL_DimmWidthToRows(Proc->Uncore.MC[mc].TGL.MADD0.DSW);
Shm->Uncore.MC[mc].Channel[1].DIMM[
Proc->Uncore.MC[mc].TGL.MADC1.Dimm_L_Map
].Rows = SKL_DimmWidthToRows(Proc->Uncore.MC[mc].TGL.MADD1.DLW);
Shm->Uncore.MC[mc].Channel[1].DIMM[
!Proc->Uncore.MC[mc].TGL.MADC1.Dimm_L_Map
].Rows = SKL_DimmWidthToRows(Proc->Uncore.MC[mc].TGL.MADD1.DSW);
}
}
#define TGL_CAP RKL_CAP
void AMD_0Fh_MCH(SHM_STRUCT *Shm, PROC_RO *Proc)
{
struct {
unsigned int size;
} module[] = {
{256}, {512}, {1024}, {1024},
{1024}, {2048}, {2048}, {4096},
{4096}, {8192}, {8192}, {16384},
{0}, {0}, {0}, {0}
};
unsigned int mask;
unsigned short mc, cha, slot, shift, index;
for (mc = 0; mc < Shm->Uncore.CtrlCount; mc++)
{
Shm->Uncore.MC[mc].SlotCount = Proc->Uncore.MC[mc].SlotCount;
Shm->Uncore.MC[mc].ChannelCount = Proc->Uncore.MC[mc].ChannelCount;
for (cha = 0; cha < Shm->Uncore.MC[mc].ChannelCount; cha++) {
switch (Proc->Uncore.MC[mc].Channel[cha].AMD0Fh.DTRL.tCL) {
case 0b010:
Shm->Uncore.MC[mc].Channel[cha].Timing.tCL = 3;
break;
case 0b011:
Shm->Uncore.MC[mc].Channel[cha].Timing.tCL = 4;
break;
case 0b100:
Shm->Uncore.MC[mc].Channel[cha].Timing.tCL = 5;
break;
case 0b101:
Shm->Uncore.MC[mc].Channel[cha].Timing.tCL = 6;
break;
}
switch (Proc->Uncore.MC[mc].Channel[cha].AMD0Fh.DTRL.tRCD) {
case 0b00:
Shm->Uncore.MC[mc].Channel[cha].Timing.tRCD = 3;
break;
case 0b01:
Shm->Uncore.MC[mc].Channel[cha].Timing.tRCD = 4;
break;
case 0b10:
Shm->Uncore.MC[mc].Channel[cha].Timing.tRCD = 5;
break;
case 0b11:
Shm->Uncore.MC[mc].Channel[cha].Timing.tRCD = 6;
break;
}
switch (Proc->Uncore.MC[mc].Channel[cha].AMD0Fh.DTRL.tRP) {
case 0b00:
Shm->Uncore.MC[mc].Channel[cha].Timing.tRP = 3;
break;
case 0b01:
Shm->Uncore.MC[mc].Channel[cha].Timing.tRP = 4;
break;
case 0b10:
Shm->Uncore.MC[mc].Channel[cha].Timing.tRP = 5;
break;
case 0b11:
Shm->Uncore.MC[mc].Channel[cha].Timing.tRP = 6;
break;
}
switch (Proc->Uncore.MC[mc].Channel[cha].AMD0Fh.DTRL.tRTPr) {
case 0b0:
if (Proc->Uncore.MC[mc].AMD0Fh.DCRL.BurstLength32 == 0b1) {
Shm->Uncore.MC[mc].Channel[cha].Timing.tRTPr = 2;
} else {
Shm->Uncore.MC[mc].Channel[cha].Timing.tRTPr = 4;
}
break;
case 0b1:
if (Proc->Uncore.MC[mc].AMD0Fh.DCRL.BurstLength32 == 0b1) {
Shm->Uncore.MC[mc].Channel[cha].Timing.tRTPr = 3;
} else {
Shm->Uncore.MC[mc].Channel[cha].Timing.tRTPr = 5;
}
break;
}
if (Proc->Uncore.MC[mc].Channel[cha].AMD0Fh.DTRL.tRAS >= 0b0010) {
Shm->Uncore.MC[mc].Channel[cha].Timing.tRAS =
Proc->Uncore.MC[mc].Channel[cha].AMD0Fh.DTRL.tRAS + 3;
}
Shm->Uncore.MC[mc].Channel[cha].Timing.tRFC =
Proc->Uncore.MC[mc].Channel[cha].AMD0Fh.DTRL.tRC + 11;
switch (Proc->Uncore.MC[mc].Channel[cha].AMD0Fh.DTRL.tWR) {
case 0b00:
Shm->Uncore.MC[mc].Channel[cha].Timing.tWR = 3;
break;
case 0b01:
Shm->Uncore.MC[mc].Channel[cha].Timing.tWR = 4;
break;
case 0b10:
Shm->Uncore.MC[mc].Channel[cha].Timing.tWR = 5;
break;
case 0b11:
Shm->Uncore.MC[mc].Channel[cha].Timing.tWR = 6;
break;
}
switch (Proc->Uncore.MC[mc].Channel[cha].AMD0Fh.DTRL.tRRD) {
case 0b00:
Shm->Uncore.MC[mc].Channel[cha].Timing.tRRD = 2;
break;
case 0b01:
Shm->Uncore.MC[mc].Channel[cha].Timing.tRRD = 3;
break;
case 0b10:
Shm->Uncore.MC[mc].Channel[cha].Timing.tRRD = 4;
break;
case 0b11:
Shm->Uncore.MC[mc].Channel[cha].Timing.tRRD = 5;
break;
}
if ((Proc->Uncore.MC[mc].AMD0Fh.DCRH.tFAW > 0b0000)
&& (Proc->Uncore.MC[mc].AMD0Fh.DCRH.tFAW <= 0b1101)) {
Shm->Uncore.MC[mc].Channel[cha].Timing.tFAW =
Proc->Uncore.MC[mc].AMD0Fh.DCRH.tFAW + 7;
}
if (Proc->Uncore.MC[mc].AMD0Fh.DCRH.SlowAccessMode == 0b1)
Shm->Uncore.MC[mc].Channel[cha].Timing.CMD_Rate = 2;
else
Shm->Uncore.MC[mc].Channel[cha].Timing.CMD_Rate = 1;
shift = 4 * cha;
mask = 0b1111 << shift;
for (slot = 0; slot < Shm->Uncore.MC[mc].SlotCount; slot++) {
if (Proc->Uncore.MC[mc].Channel[cha].DIMM[slot].MBA.CSEnable) {
index=(Proc->Uncore.MC[mc].MaxDIMMs.AMD0Fh.CS.value & mask) >>shift;
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Size=module[index].size;
}
}
Shm->Uncore.MC[mc].Channel[cha].Timing.ECC =
Proc->Uncore.MC[mc].AMD0Fh.DCRL.ECC_DIMM_Enable;
}
}
}
void AMD_0Fh_HTT(SHM_STRUCT *Shm, PROC_RO *Proc)
{
unsigned int link = 0;
RAM_Ratio Ratio = {.Q = 0, .R = 0};
unsigned long long HTT_Clock = 0;
switch (Proc->Uncore.MC[0].AMD0Fh.DCRH.MemClkFreq) {
case 0b000:
Ratio.Q = 200;
Ratio.R = 0;
break;
case 0b001:
Ratio.Q = 266;
Ratio.R = 1;
break;
case 0b010:
Ratio.Q = 333;
Ratio.R = 1;
break;
case 0b011:
Ratio.Q = 400;
Ratio.R = 0;
break;
}
Shm->Uncore.CtrlSpeed = (Ratio.Q * 2) + Ratio.R; /* DDR2 */
if ((link = Proc->Uncore.Bus.UnitID.McUnit) < 0b11) {
switch (Proc->Uncore.Bus.LDTi_Freq[link].LinkFreqMax)/*"MHz"*/
{
case 0b0000:
HTT_Clock = 200;
break;
case 0b0010:
HTT_Clock = 400;
break;
case 0b0100:
HTT_Clock = 600;
break;
case 0b0101:
HTT_Clock = 800;
break;
case 0b0110:
HTT_Clock = 1000;
break;
case 0b1111:
HTT_Clock = 100;
break;
}
Shm->Uncore.Bus.Rate = HTT_Clock * 2; /* "MT/s" */
Shm->Uncore.Bus.Speed = HTT_Clock * 4; /* "MB/s" */
}
Shm->Uncore.Unit.Bus_Rate = 0b01;
Shm->Uncore.Unit.BusSpeed = 0b10;
Shm->Uncore.Unit.DDR_Rate = 0b11;
Shm->Uncore.Unit.DDRSpeed = 0b00;
Shm->Uncore.Unit.DDR_Ver = 2;
}
void AMD_17h_UMC(SHM_STRUCT *Shm, PROC_RO *Proc)
{
unsigned short mc;
for (mc = 0; mc < Shm->Uncore.CtrlCount; mc++)
{
Shm->Uncore.MC[mc].ChannelCount = Proc->Uncore.MC[mc].ChannelCount;
unsigned short cha;
for (cha = 0; cha < Shm->Uncore.MC[mc].ChannelCount; cha++)
{
unsigned long long DIMM_Size = 0;
unsigned short chip, slotCount = 0;
for (chip = 0; chip < 4; chip++)
{
const unsigned short slot = chip / 2;
unsigned short sec;
for (sec = 0; sec < 2; sec++)
{
unsigned int chipSize = 0;
if (BITVAL(Proc->Uncore.MC[mc].Channel[cha] \
.AMD17h.CHIP[chip][sec].Chip.value, 0))
{
__asm__ volatile
(
"xorl %%edx, %%edx" "\n\t"
"bsrl %[base], %%ecx" "\n\t"
"jz 1f" "\n\t"
"incl %%edx" "\n\t"
"shll %%cl, %%edx" "\n\t"
"negl %%edx" "\n\t"
"notl %%edx" "\n\t"
"andl $0xfffffffe, %%edx" "\n\t"
"shrl $2, %%edx" "\n\t"
"incl %%edx" "\n\t"
"1:" "\n\t"
"movl %%edx, %[dest]"
: [dest] "=m" (chipSize)
: [base] "m"
(Proc->Uncore.MC[mc].Channel[cha].AMD17h.CHIP[chip][sec].Mask.value)
: "cc", "memory", "%ecx", "%edx"
);
DIMM_Size += chipSize;
slotCount++;
}
}
if (DIMM_Size > 0)
{
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Ranks = \
Proc->Uncore.MC[mc].Channel[cha].AMD17h.Ranks;
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Rows = 1 << 16;
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Cols = 1 << 10;
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Size = DIMM_Size >> 10;
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Banks = DIMM_Size >> 19;
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Banks = \
Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Banks
/ Shm->Uncore.MC[mc].Channel[cha].DIMM[slot].Ranks;
}
}
Shm->Uncore.MC[mc].SlotCount = slotCount;
Shm->Uncore.MC[mc].Channel[cha].Timing.tCL =
Proc->Uncore.MC[mc].Channel[cha].AMD17h.DTR1.tCL;
Shm->Uncore.MC[mc].Channel[cha].Timing.tRCD_RD =
Proc->Uncore.MC[mc].Channel[cha].AMD17h.DTR1.tRCD_RD;
Shm->Uncore.MC[mc].Channel[cha].Timing.tRCD_WR =
Proc->Uncore.MC[mc].Channel[cha].AMD17h.DTR1.tRCD_WR;
Shm->Uncore.MC[mc].Channel[cha].Timing.tRP =
Proc->Uncore.MC[mc].Channel[cha].AMD17h.DTR2.tRP;
Shm->Uncore.MC[mc].Channel[cha].Timing.tRAS =
Proc->Uncore.MC[mc].Channel[cha].AMD17h.DTR1.tRAS;
Shm->Uncore.MC[mc].Channel[cha].Timing.tRRDS =
Proc->Uncore.MC[mc].Channel[cha].AMD17h.DTR3.tRRDS;
Shm->Uncore.MC[mc].Channel[cha].Timing.tRRDL =
Proc->Uncore.MC[mc].Channel[cha].AMD17h.DTR3.tRRDL;
Shm->Uncore.MC[mc].Channel[cha].Timing.Zen.tRRDDLR =
Proc->Uncore.MC[mc].Channel[cha].AMD17h.DTR3.tRRDDLR;
Shm->Uncore.MC[mc].Channel[cha].Timing.tRC =
Proc->Uncore.MC[mc].Channel[cha].AMD17h.DTR2.tRC;
Shm->Uncore.MC[mc].Channel[cha].Timing.tRCPB =
Proc->Uncore.MC[mc].Channel[cha].AMD17h.DTR2.tRCPB;
Shm->Uncore.MC[mc].Channel[cha].Timing.tRPPB =
Proc->Uncore.MC[mc].Channel[cha].AMD17h.DTR2.tRPPB;
Shm->Uncore.MC[mc].Channel[cha].Timing.tFAW =
Proc->Uncore.MC[mc].Channel[cha].AMD17h.DTR4.tFAW;
Shm->Uncore.MC[mc].Channel[cha].Timing.tFAWSLR =
Proc->Uncore.MC[mc].Channel[cha].AMD17h.DTR4.tFAWSLR;
Shm->Uncore.MC[mc].Channel[cha].Timing.tFAWDLR =
Proc->Uncore.MC[mc].Channel[cha].AMD17h.DTR4.tFAWDLR;
Shm->Uncore.MC[mc].Channel[cha].Timing.tWTRS =
Proc->Uncore.MC[mc].Channel[cha].AMD17h.DTR5.tWTRS;
Shm->Uncore.MC[mc].Channel[cha].Timing.tWTRL =
Proc->Uncore.MC[mc].Channel[cha].AMD17h.DTR5.tWTRL;
Shm->Uncore.MC[mc].Channel[cha].Timing.tWR =
Proc->Uncore.MC[mc].Channel[cha].AMD17h.DTR6.tWR;
Shm->Uncore.MC[mc].Channel[cha].Timing.tRCPage =
Proc->Uncore.MC[mc].Channel[cha].AMD17h.DTR7.tRCPage;
Shm->Uncore.MC[mc].Channel[cha].Timing.Zen.tRdRdScl =
Proc->Uncore.MC[mc].Channel[cha].AMD17h.DTR8.tRdRdScl;
Shm->Uncore.MC[mc].Channel[cha].Timing.Zen.tWrWrScl =
Proc->Uncore.MC[mc].Channel[cha].AMD17h.DTR9.tWrWrScl;
Shm->Uncore.MC[mc].Channel[cha].Timing.Zen.tRdRdBan =
Proc->Uncore.MC[mc].Channel[cha].AMD17h.DTR8.tRdRdBan;
Shm->Uncore.MC[mc].Channel[cha].Timing.Zen.tWrWrBan =
Proc->Uncore.MC[mc].Channel[cha].AMD17h.DTR9.tWrWrBan;
Shm->Uncore.MC[mc].Channel[cha].Timing.tCWL =
Proc->Uncore.MC[mc].Channel[cha].AMD17h.DTR5.tCWL;
Shm->Uncore.MC[mc].Channel[cha].Timing.tRTP =
Proc->Uncore.MC[mc].Channel[cha].AMD17h.DTR3.tRTP;
Shm->Uncore.MC[mc].Channel[cha].Timing.Zen.tddRdTWr =
Proc->Uncore.MC[mc].Channel[cha].AMD17h.DTR10.tddRdTWr;
Shm->Uncore.MC[mc].Channel[cha].Timing.Zen.tddWrTRd =
Proc->Uncore.MC[mc].Channel[cha].AMD17h.DTR10.tddWrTRd;
Shm->Uncore.MC[mc].Channel[cha].Timing.Zen.tscWrTWr =
Proc->Uncore.MC[mc].Channel[cha].AMD17h.DTR9.tscWrTWr;
Shm->Uncore.MC[mc].Channel[cha].Timing.Zen.tsdWrTWr =
Proc->Uncore.MC[mc].Channel[cha].AMD17h.DTR9.tsdWrTWr;
Shm->Uncore.MC[mc].Channel[cha].Timing.Zen.tddWrTWr =
Proc->Uncore.MC[mc].Channel[cha].AMD17h.DTR9.tddWrTWr;
Shm->Uncore.MC[mc].Channel[cha].Timing.Zen.tscRdTRd =
Proc->Uncore.MC[mc].Channel[cha].AMD17h.DTR8.tscRdTRd;
Shm->Uncore.MC[mc].Channel[cha].Timing.Zen.tsdRdTRd =
Proc->Uncore.MC[mc].Channel[cha].AMD17h.DTR8.tsdRdTRd;
Shm->Uncore.MC[mc].Channel[cha].Timing.Zen.tddRdTRd =
Proc->Uncore.MC[mc].Channel[cha].AMD17h.DTR8.tddRdTRd;
Shm->Uncore.MC[mc].Channel[cha].Timing.Zen.tRdRdScDLR =
Proc->Uncore.MC[mc].Channel[cha].AMD17h.DTR8.tRdRdScDLR;
Shm->Uncore.MC[mc].Channel[cha].Timing.Zen.tWrWrScDLR =
Proc->Uncore.MC[mc].Channel[cha].AMD17h.DTR9.tWrWrScDLR;
Shm->Uncore.MC[mc].Channel[cha].Timing.Zen.tWrRdScDLR =
Proc->Uncore.MC[mc].Channel[cha].AMD17h.DTR10.tWrRdScDLR;
Shm->Uncore.MC[mc].Channel[cha].Timing.tCKE =
Proc->Uncore.MC[mc].Channel[cha].AMD17h.DTR54.tCKE;
Shm->Uncore.MC[mc].Channel[cha].Timing.tREFI =
Proc->Uncore.MC[mc].Channel[cha].AMD17h.DTR12.tREFI;
Shm->Uncore.MC[mc].Channel[cha].Timing.tRFC1 =
Proc->Uncore.MC[mc].Channel[cha].AMD17h.DTR60.tRFC1;
Shm->Uncore.MC[mc].Channel[cha].Timing.tRFC2 =
Proc->Uncore.MC[mc].Channel[cha].AMD17h.DTR60.tRFC2;
Shm->Uncore.MC[mc].Channel[cha].Timing.tRFC4 =
Proc->Uncore.MC[mc].Channel[cha].AMD17h.DTR60.tRFC4;
switch(Proc->Uncore.MC[mc].Channel[cha].AMD17h.MISC.CMD_Rate) {
case 0b00:
Shm->Uncore.MC[mc].Channel[cha].Timing.CMD_Rate = 1;
break;
case 0b10:
Shm->Uncore.MC[mc].Channel[cha].Timing.CMD_Rate = 2;
break;
default:
Shm->Uncore.MC[mc].Channel[cha].Timing.CMD_Rate = 0;
break;
}
Shm->Uncore.MC[mc].Channel[cha].Timing.ECC =
Proc->Uncore.MC[mc].Channel[cha].AMD17h.ECC.Enable;
Shm->Uncore.MC[mc].Channel[cha].Timing.GDM =
Proc->Uncore.MC[mc].Channel[cha].AMD17h.MISC.GearDownMode;
Shm->Uncore.MC[mc].Channel[cha].Timing.BGS =
!((Proc->Uncore.MC[mc].Channel[cha].AMD17h.BGS.value
& AMD_17_UMC_BGS_MASK_OFF) == AMD_17_UMC_BGS_MASK_OFF);
Shm->Uncore.MC[mc].Channel[cha].Timing.BGS_ALT =
(Proc->Uncore.MC[mc].Channel[cha].AMD17h.BGS_ALT.value
& AMD_17_UMC_BGS_ALT_MASK_ON) == AMD_17_UMC_BGS_ALT_MASK_ON;
}
}
}
void AMD_17h_CAP(SHM_STRUCT *Shm, PROC_RO *Proc, CORE_RO *Core)
{
Shm->Uncore.Bus.Rate=(Proc->Uncore.MC[0].Channel[0].AMD17h.MISC.MEMCLK
* Shm->Proc.Features.Factory.Clock.Q) / 3;
Shm->Uncore.Bus.Speed=(Proc->Uncore.MC[0].Channel[0].AMD17h.MISC.MEMCLK
* Core->Clock.Hz * 333333333LLU)
/ (Shm->Proc.Features.Factory.Clock.Hz
* (1000LLU * PRECISION * PRECISION));
Shm->Uncore.CtrlSpeed=(Proc->Uncore.MC[0].Channel[0].AMD17h.MISC.MEMCLK
* Core->Clock.Hz * 666666666LLU)
/ (Shm->Proc.Features.Factory.Clock.Hz
* (1000LLU * PRECISION * PRECISION));
Shm->Uncore.Unit.Bus_Rate = 0b01;
Shm->Uncore.Unit.BusSpeed = 0b00;
Shm->Uncore.Unit.DDR_Rate = 0b11;
Shm->Uncore.Unit.DDRSpeed = 0b00;
Shm->Uncore.Unit.DDR_Ver = 4;
}
void AMD_17h_IOMMU(SHM_STRUCT *Shm, PROC_RO *Proc)
{
Shm->Proc.Technology.IOMMU = Proc->Uncore.Bus.IOMMU_CR.IOMMU_En;
Shm->Proc.Technology.IOMMU_Ver_Major = \
(Proc->Uncore.Bus.IOMMU_HDR.CapRev & 0b10000) >> 5;
Shm->Proc.Technology.IOMMU_Ver_Minor = \
Proc->Uncore.Bus.IOMMU_HDR.CapRev & 0b01111;
}
static char *Chipset[CHIPSETS] = {
[IC_CHIPSET] = NULL,
[IC_LAKEPORT] = "82945/Lakeport",
[IC_LAKEPORT_P] = "82946/Lakeport-P",
[IC_LAKEPORT_X] = "82955/Lakeport-X",
[IC_CALISTOGA] = "82945/Calistoga",
[IC_BROADWATER] = "82965/Broadwater",
[IC_CRESTLINE] = "82965/Crestline",
[IC_CANTIGA] = "G45/Cantiga",
[IC_BEARLAKE_Q] = "Q35/Bearlake-Q",
[IC_BEARLAKE_P] = "G33/Bearlake-PG+",
[IC_BEARLAKE_QF] = "Q33/Bearlake-QF",
[IC_BEARLAKE_X] = "X38/Bearlake-X",
[IC_INTEL_3200] = "Intel 3200",
[IC_EAGLELAKE_Q] = "Q45/Eaglelake-Q",
[IC_EAGLELAKE_P] = "G45/Eaglelake-P",
[IC_EAGLELAKE_G] = "G41/Eaglelake-G",
[IC_BAYTRAIL] = "Bay Trail",
[IC_TYLERSBURG] = "X58/Tylersburg",
[IC_IBEXPEAK] = "P55/Ibex Peak",
[IC_IBEXPEAK_M] = "QM57/Ibex Peak-M",
[IC_COUGARPOINT] = "P67/Cougar Point",
[IC_PATSBURG] = "X79/Patsburg",
[IC_CAVECREEK] = "Cave Creek",
[IC_WELLSBURG] = "X99/Wellsburg",
[IC_PANTHERPOINT] = "Panther Point",
[IC_PANTHERPOINT_M] = "Panther Point-M",
[IC_LYNXPOINT] = "Lynx Point",
[IC_LYNXPOINT_M] = "Lynx Point-M",
[IC_WILDCATPOINT] = "Wildcat Point",
[IC_WILDCATPOINT_M] = "Wildcat Point-M",
[IC_SUNRISEPOINT] = "Sunrise Point",
[IC_UNIONPOINT] = "Union Point",
[IC_CANNONPOINT] = "Cannon Point",
[IC_400_SERIES_P] = "400 Series-Prem-U",
[IC_400_SERIES_M] = "400 Series-Base-U",
[IC_495] = "Intel 495",
[IC_H470] = "Intel H470",
[IC_Z490] = "Intel Z490",
[IC_Q470] = "Intel Q470",
[IC_HM470] = "Intel HM470",
[IC_QM480] = "Intel QM480",
[IC_WM490] = "Intel WM490",
[IC_W480] = "Intel W480",
[IC_H510] = "Intel H510",
[IC_B560] = "Intel B560",
[IC_H570] = "Intel H570",
[IC_Q570] = "Intel Q570",
[IC_Z590] = "Intel Z590",
[IC_W580] = "Intel W580",
[IC_K8] = "K8/HyperTransport",
[IC_ZEN] = "Zen UMC"
};
#define SET_CHIPSET(ic) \
({ \
Shm->Uncore.ChipID = DID; \
Shm->Uncore.Chipset.ArchID = ic; \
})
void PCI_Intel(SHM_STRUCT *Shm, PROC_RO *Proc, CORE_RO *Core,unsigned short DID)
{
switch (DID) {
case DID_INTEL_82945P_HB:
P945_CLK(Shm, Proc, Core);
P945_MCH(Shm, Proc);
SET_CHIPSET(IC_LAKEPORT);
break;
case DID_INTEL_82945GM_HB:
case DID_INTEL_82945GME_HB:
P945_CLK(Shm, Proc, Core);
P945_MCH(Shm, Proc);
SET_CHIPSET(IC_CALISTOGA);
break;
case DID_INTEL_82955_HB:
P945_CLK(Shm, Proc, Core);
P955_MCH(Shm, Proc);
SET_CHIPSET(IC_LAKEPORT_X);
break;
case DID_INTEL_82946GZ_HB:
P965_CLK(Shm, Proc, Core);
P965_MCH(Shm, Proc);
SET_CHIPSET(IC_LAKEPORT_P);
break;
case DID_INTEL_82965Q_HB:
case DID_INTEL_82965G_HB:
P965_CLK(Shm, Proc, Core);
P965_MCH(Shm, Proc);
SET_CHIPSET(IC_BROADWATER);
break;
case DID_INTEL_82965GM_HB:
case DID_INTEL_82965GME_HB:
G965_CLK(Shm, Proc, Core);
G965_MCH(Shm, Proc);
SET_CHIPSET(IC_CRESTLINE);
break;
case DID_INTEL_GM45_HB:
G965_CLK(Shm, Proc, Core);
G965_MCH(Shm, Proc);
SET_CHIPSET(IC_CANTIGA);
break;
case DID_INTEL_Q35_HB:
P35_CLK(Shm, Proc, Core);
P35_MCH(Shm, Proc);
SET_CHIPSET(IC_BEARLAKE_Q);
break;
case DID_INTEL_G33_HB:
P35_CLK(Shm, Proc, Core);
P35_MCH(Shm, Proc);
SET_CHIPSET(IC_BEARLAKE_P);
break;
case DID_INTEL_Q33_HB:
P35_CLK(Shm, Proc, Core);
P35_MCH(Shm, Proc);
SET_CHIPSET(IC_BEARLAKE_QF);
break;
case DID_INTEL_X38_HB:
P35_CLK(Shm, Proc, Core);
P35_MCH(Shm, Proc);
SET_CHIPSET(IC_BEARLAKE_X);
break;
case DID_INTEL_3200_HB:
P35_CLK(Shm, Proc, Core);
P35_MCH(Shm, Proc);
SET_CHIPSET(IC_INTEL_3200);
break;
case DID_INTEL_Q45_HB:
P35_CLK(Shm, Proc, Core);
P4S_MCH(Shm, Proc);
SET_CHIPSET(IC_EAGLELAKE_Q);
break;
case DID_INTEL_G45_HB:
P35_CLK(Shm, Proc, Core);
P4S_MCH(Shm, Proc);
SET_CHIPSET(IC_EAGLELAKE_P);
break;
case DID_INTEL_G41_HB:
P35_CLK(Shm, Proc, Core);
P4S_MCH(Shm, Proc);
SET_CHIPSET(IC_EAGLELAKE_G);
break;
case DID_INTEL_SLM_PTR:
SLM_PTR(Shm, Proc, Core);
SET_CHIPSET(IC_BAYTRAIL);
break;
case DID_INTEL_X58_HUB_CTRL:
QPI_CLK(Shm, Proc, Core);
break;
case DID_INTEL_X58_HUB_CORE:
X58_VTD(Shm, Proc, Core);
break;
case DID_INTEL_I7_MCR: /* Bloomfield */
case DID_INTEL_NHM_EP_MCR: /* Westmere EP */
NHM_IMC(Shm, Proc);
SET_CHIPSET(IC_TYLERSBURG);
break;
case DID_INTEL_I7_MC_TEST:
case DID_INTEL_LYNNFIELD_MC_TEST:
case DID_INTEL_NHM_EP_MC_TEST:
DMI_CLK(Shm, Proc, Core);
break;
case DID_INTEL_LYNNFIELD_MCR: /* Lynnfield */
case 0x2cd8:
NHM_IMC(Shm, Proc);
SET_CHIPSET(IC_IBEXPEAK);
break;
case DID_INTEL_SNB_IMC_HA0: /* Sandy Bridge-E */
SNB_EP_CAP(Shm, Proc, Core);
SNB_EP_IMC(Shm, Proc);
SET_CHIPSET(IC_PATSBURG);
break;
case DID_INTEL_SNB_IMC_SA: /* SNB Desktop */
SNB_CAP(Shm, Proc, Core);
SNB_IMC(Shm, Proc);
SET_CHIPSET(IC_COUGARPOINT);
break;
case DID_INTEL_SNB_IMC_0104:
SNB_CAP(Shm, Proc, Core);
SNB_IMC(Shm, Proc);
SET_CHIPSET(IC_IBEXPEAK_M);
break;
case DID_INTEL_IVB_EP_HOST_BRIDGE: /* Xeon E5 & E7 v2 */
SNB_EP_CAP(Shm, Proc, Core);
SNB_EP_IMC(Shm, Proc);
SET_CHIPSET(IC_CAVECREEK);
break;
case DID_INTEL_IVB_IMC_SA: /* IVB Desktop */
IVB_CAP(Shm, Proc, Core);
SNB_IMC(Shm, Proc);
SET_CHIPSET(IC_PANTHERPOINT);
break;
case DID_INTEL_IVB_IMC_0154: /* IVB Mobile i5-3337U */
IVB_CAP(Shm, Proc, Core);
SNB_IMC(Shm, Proc);
SET_CHIPSET(IC_PANTHERPOINT_M);
break;
case DID_INTEL_HASWELL_IMC_SA: /* HSW & BDW Desktop */
case DID_INTEL_HASWELL_MH_IMC_HA0: /* HSW Mobile M/H */
case DID_INTEL_HASWELL_UY_IMC_HA0: /* HSW Mobile U/Y */
IVB_CAP(Shm, Proc, Core);
HSW_IMC(Shm, Proc);
SET_CHIPSET(IC_LYNXPOINT_M);
break;
case DID_INTEL_HASWELL_IMC_HA0: /* Haswell */
IVB_CAP(Shm, Proc, Core);
HSW_IMC(Shm, Proc);
SET_CHIPSET(IC_LYNXPOINT);
break;
case DID_INTEL_BROADWELL_IMC_HA0: /* Broadwell/Y/U Core m */
IVB_CAP(Shm, Proc, Core);
HSW_IMC(Shm, Proc);
SET_CHIPSET(IC_WILDCATPOINT_M);
break;
case DID_INTEL_BROADWELL_D_IMC_HA0: /* BDW/Desktop */
case DID_INTEL_BROADWELL_H_IMC_HA0: /* Broadwell/H */
IVB_CAP(Shm, Proc, Core);
HSW_IMC(Shm, Proc);
SET_CHIPSET(IC_WELLSBURG);
break;
case DID_INTEL_SKYLAKE_U_IMC_HA: /* Skylake/U Processor */
SKL_CAP(Shm, Proc, Core);
SKL_IMC(Shm, Proc);
SET_CHIPSET(IC_SUNRISEPOINT);
break;
case DID_INTEL_SKYLAKE_Y_IMC_HA: /* Skylake/Y Processor */
SKL_CAP(Shm, Proc, Core);
SKL_IMC(Shm, Proc);
SET_CHIPSET(IC_SUNRISEPOINT);
break;
case DID_INTEL_SKYLAKE_S_IMC_HAD: /* Skylake/S Dual Core */
SKL_CAP(Shm, Proc, Core);
SKL_IMC(Shm, Proc);
SET_CHIPSET(IC_SUNRISEPOINT);
break;
case DID_INTEL_SKYLAKE_S_IMC_HAQ: /* Skylake/S Quad Core */
SKL_CAP(Shm, Proc, Core);
SKL_IMC(Shm, Proc);
SET_CHIPSET(IC_SUNRISEPOINT);
break;
case DID_INTEL_SKYLAKE_H_IMC_HAD: /* Skylake/H Dual Core */
SKL_CAP(Shm, Proc, Core);
SKL_IMC(Shm, Proc);
SET_CHIPSET(IC_SUNRISEPOINT);
break;
case DID_INTEL_SKYLAKE_H_IMC_HAQ: /* Skylake/H Quad Core */
SKL_CAP(Shm, Proc, Core);
SKL_IMC(Shm, Proc);
SET_CHIPSET(IC_SUNRISEPOINT);
break;
case DID_INTEL_SKYLAKE_DT_IMC_HA: /* Skylake/DT Server */
SKL_CAP(Shm, Proc, Core);
SKL_IMC(Shm, Proc);
SET_CHIPSET(IC_SUNRISEPOINT);
break;
case DID_INTEL_KABYLAKE_U_IMC_HA: /* BGA 1356 */
SKL_CAP(Shm, Proc, Core);
SKL_IMC(Shm, Proc);
SET_CHIPSET(IC_UNIONPOINT);
break;
case DID_INTEL_KABYLAKE_Y_IMC_HA: /* BGA 1515 */
case DID_INTEL_KABYLAKE_Y_IMC_HQ:
SKL_CAP(Shm, Proc, Core);
SKL_IMC(Shm, Proc);
SET_CHIPSET(IC_UNIONPOINT);
break;
case DID_INTEL_KABYLAKE_H_IMC_HAD: /* Kaby Lake/H Dual Core */
SKL_CAP(Shm, Proc, Core);
SKL_IMC(Shm, Proc);
SET_CHIPSET(IC_UNIONPOINT);
break;
case DID_INTEL_KABYLAKE_S_IMC_HAD: /* Kaby Lake/S Dual Core */
SKL_CAP(Shm, Proc, Core);
SKL_IMC(Shm, Proc);
SET_CHIPSET(IC_UNIONPOINT);
break;
case DID_INTEL_KABYLAKE_H_IMC_HAQ: /* Kaby Lake/H Quad Core */
SKL_CAP(Shm, Proc, Core);
SKL_IMC(Shm, Proc);
SET_CHIPSET(IC_UNIONPOINT);
break;
case DID_INTEL_KABYLAKE_DT_IMC_HA: /* Kaby Lake/DT Server */
SKL_CAP(Shm, Proc, Core);
SKL_IMC(Shm, Proc);
SET_CHIPSET(IC_UNIONPOINT);
break;
case DID_INTEL_KABYLAKE_U_IMC_HAQ: /* U-Quad Core BGA 1356 */
SKL_CAP(Shm, Proc, Core);
SKL_IMC(Shm, Proc);
SET_CHIPSET(IC_UNIONPOINT);
break;
case DID_INTEL_KABYLAKE_S_IMC_HAQ: /* Kaby Lake/S Quad Core */
SKL_CAP(Shm, Proc, Core);
SKL_IMC(Shm, Proc);
SET_CHIPSET(IC_UNIONPOINT);
break;
case DID_INTEL_KABYLAKE_X_IMC_HAQ:
SKL_CAP(Shm, Proc, Core);
SKL_IMC(Shm, Proc);
SET_CHIPSET(IC_UNIONPOINT);
break;
case DID_INTEL_COFFEELAKE_S_IMC_HAQ: /* Coffee Lake Quad Core */
SKL_CAP(Shm, Proc, Core);
SKL_IMC(Shm, Proc);
SET_CHIPSET(IC_CANNONPOINT);
break;
case DID_INTEL_COFFEELAKE_S_IMC_HAS: /* Coffee Lake Hexa Core */
SKL_CAP(Shm, Proc, Core);
SKL_IMC(Shm, Proc);
SET_CHIPSET(IC_CANNONPOINT);
break;
case DID_INTEL_COFFEELAKE_R_S_IMC_HAD:
SKL_CAP(Shm, Proc, Core);
SKL_IMC(Shm, Proc);
SET_CHIPSET(IC_CANNONPOINT);
break;
case DID_INTEL_COFFEELAKE_R_U_IMC_HAD:
SKL_CAP(Shm, Proc, Core);
SKL_IMC(Shm, Proc);
SET_CHIPSET(IC_CANNONPOINT);
break;
case DID_INTEL_COFFEELAKE_R_U_IMC_HAQ:
SKL_CAP(Shm, Proc, Core);
SKL_IMC(Shm, Proc);
SET_CHIPSET(IC_CANNONPOINT);
break;
case DID_INTEL_COFFEELAKE_R_H_IMC_HAQ:
SKL_CAP(Shm, Proc, Core);
SKL_IMC(Shm, Proc);
SET_CHIPSET(IC_CANNONPOINT);
break;
case DID_INTEL_COFFEELAKE_R_H_IMC_HAS:
SKL_CAP(Shm, Proc, Core);
SKL_IMC(Shm, Proc);
SET_CHIPSET(IC_CANNONPOINT);
break;
case DID_INTEL_COFFEELAKE_R_H_IMC_HAO:
SKL_CAP(Shm, Proc, Core);
SKL_IMC(Shm, Proc);
SET_CHIPSET(IC_CANNONPOINT);
break;
case DID_INTEL_COFFEELAKE_R_W_IMC_HAQ:
SKL_CAP(Shm, Proc, Core);
SKL_IMC(Shm, Proc);
SET_CHIPSET(IC_CANNONPOINT);
break;
case DID_INTEL_COFFEELAKE_R_W_IMC_HAS:
SKL_CAP(Shm, Proc, Core);
SKL_IMC(Shm, Proc);
SET_CHIPSET(IC_CANNONPOINT);
break;
case DID_INTEL_COFFEELAKE_R_W_IMC_HAO:
SKL_CAP(Shm, Proc, Core);
SKL_IMC(Shm, Proc);
SET_CHIPSET(IC_CANNONPOINT);
break;
case DID_INTEL_COFFEELAKE_R_S_IMC_HAQ:
SKL_CAP(Shm, Proc, Core);
SKL_IMC(Shm, Proc);
SET_CHIPSET(IC_CANNONPOINT);
break;
case DID_INTEL_COFFEELAKE_R_S_IMC_HAS:
SKL_CAP(Shm, Proc, Core);
SKL_IMC(Shm, Proc);
SET_CHIPSET(IC_CANNONPOINT);
break;
case DID_INTEL_COFFEELAKE_R_S_IMC_HAO:
SKL_CAP(Shm, Proc, Core);
SKL_IMC(Shm, Proc);
SET_CHIPSET(IC_CANNONPOINT);
break;
case DID_INTEL_WHISKEYLAKE_U_IMC_HAD: /* WHL Dual Core */
SKL_CAP(Shm, Proc, Core);
SKL_IMC(Shm, Proc);
SET_CHIPSET(IC_CANNONPOINT);
break;
case DID_INTEL_WHISKEYLAKE_U_IMC_HAQ: /* WHL Quad Core */
SKL_CAP(Shm, Proc, Core);
SKL_IMC(Shm, Proc);
SET_CHIPSET(IC_CANNONPOINT);
break;
case DID_INTEL_COMETLAKE_S_IMC_6C:
case DID_INTEL_COMETLAKE_S_IMC_10C:
case DID_INTEL_COMETLAKE_H_IMC_10C:
case DID_INTEL_COMETLAKE_W_IMC_10C:
case DID_INTEL_COMETLAKE_M_IMC_6C:
case DID_INTEL_COMETLAKE_S1_IMC:
case DID_INTEL_COMETLAKE_S2_IMC:
case DID_INTEL_COMETLAKE_S5_IMC:
SKL_CAP(Shm, Proc, Core);
SKL_IMC(Shm, Proc);
break;
case DID_INTEL_COMETLAKE_U_IMC_HB:
case DID_INTEL_COMETLAKE_U1_IMC:
case DID_INTEL_COMETLAKE_U3_IMC:
RKL_CAP(Shm, Proc, Core);
RKL_IMC(Shm, Proc);
break;
case DID_INTEL_COMETLAKE_PREM_U_PCH:
SET_CHIPSET(IC_400_SERIES_P);
break;
case DID_INTEL_COMETLAKE_BASE_U_PCH:
SET_CHIPSET(IC_400_SERIES_M);
break;
case DID_INTEL_COMETLAKE_U_ES_PCH:
case DID_INTEL_COMETLAKE_Y_ES_PCH:
case DID_INTEL_COMETLAKE_Y_PCH:
case DID_INTEL_ICELAKE_U_PCH:
SET_CHIPSET(IC_495);
break;
case DID_INTEL_COMETLAKE_H470_PCH:
SET_CHIPSET(IC_H470);
break;
case DID_INTEL_COMETLAKE_Z490_PCH:
SET_CHIPSET(IC_Z490);
break;
case DID_INTEL_COMETLAKE_Q470_PCH:
SET_CHIPSET(IC_Q470);
break;
case DID_INTEL_COMETLAKE_HM470_PCH:
SET_CHIPSET(IC_HM470);
break;
case DID_INTEL_COMETLAKE_QM480_PCH:
SET_CHIPSET(IC_QM480);
break;
case DID_INTEL_COMETLAKE_WM490_PCH:
SET_CHIPSET(IC_WM490);
break;
case DID_INTEL_COMETLAKE_W480_PCH:
SET_CHIPSET(IC_W480);
break;
case DID_INTEL_ICELAKE_U_IMC:
case DID_INTEL_ICELAKE_U_4C:
SKL_CAP(Shm, Proc, Core);
SKL_IMC(Shm, Proc);
break;
case DID_INTEL_TIGERLAKE_U1_IMC:
case DID_INTEL_TIGERLAKE_U2_IMC:
case DID_INTEL_TIGERLAKE_U3_IMC:
case DID_INTEL_TIGERLAKE_U4_IMC:
case DID_INTEL_TIGERLAKE_H_IMC:
TGL_CAP(Shm, Proc, Core);
TGL_IMC(Shm, Proc);
break;
case DID_INTEL_ROCKETLAKE_S_8C_IMC_HB:
case DID_INTEL_ROCKETLAKE_S_6C_IMC_HB:
RKL_CAP(Shm, Proc, Core);
RKL_IMC(Shm, Proc);
break;
case DID_INTEL_ROCKETLAKE_H510_PCH:
SET_CHIPSET(IC_H510);
break;
case DID_INTEL_ROCKETLAKE_B560_PCH:
SET_CHIPSET(IC_B560);
break;
case DID_INTEL_ROCKETLAKE_H570_PCH:
SET_CHIPSET(IC_H570);
break;
case DID_INTEL_ROCKETLAKE_Q570_PCH:
SET_CHIPSET(IC_Q570);
break;
case DID_INTEL_ROCKETLAKE_Z590_PCH:
SET_CHIPSET(IC_Z590);
break;
case DID_INTEL_ROCKETLAKE_W580_PCH:
SET_CHIPSET(IC_W580);
break;
case DID_INTEL_ALDERLAKE_1_IMC:
case DID_INTEL_ALDERLAKE_2_IMC:
RKL_CAP(Shm, Proc, Core);
RKL_IMC(Shm, Proc);
break;
}
}
void PCI_AMD(SHM_STRUCT *Shm, PROC_RO *Proc, CORE_RO *Core, unsigned short DID)
{
switch (DID) {
case DID_AMD_K8_NB_MEMCTL:
AMD_0Fh_HTT(Shm, Proc);
AMD_0Fh_MCH(Shm, Proc);
SET_CHIPSET(IC_K8);
break;
case DID_AMD_17H_ZEN_PLUS_NB_IOMMU:
case DID_AMD_17H_ZEPPELIN_NB_IOMMU:
case DID_AMD_17H_RAVEN_NB_IOMMU:
case DID_AMD_17H_ZEN2_MTS_NB_IOMMU:
case DID_AMD_17H_STARSHIP_NB_IOMMU:
case DID_AMD_17H_RENOIR_NB_IOMMU:
case DID_AMD_17H_ZEN_APU_NB_IOMMU:
case DID_AMD_17H_ZEN2_APU_NB_IOMMU:
AMD_17h_IOMMU(Shm, Proc);
break;
case DID_AMD_17H_ZEPPELIN_DF_F3:
case DID_AMD_17H_RAVEN_DF_F3:
case DID_AMD_17H_MATISSE_DF_F3:
case DID_AMD_17H_STARSHIP_DF_F3:
case DID_AMD_17H_RENOIR_DF_F3:
case DID_AMD_17H_ARIEL_DF_F3:
case DID_AMD_17H_FIREFLIGHT_DF_F3:
case DID_AMD_17H_ARDEN_DF_F3:
AMD_17h_CAP(Shm, Proc, Core);
AMD_17h_UMC(Shm, Proc);
SET_CHIPSET(IC_ZEN);
break;
}
}
#undef SET_CHIPSET
void Uncore_Update(SHM_STRUCT *Shm, PROC_RO *Proc, CORE_RO *Core)
{
unsigned int idx;
/* Copy the # of controllers. */
Shm->Uncore.CtrlCount = Proc->Uncore.CtrlCount;
/* Decode the Memory Controller for each found vendor:device */
Chipset[IC_CHIPSET] = Proc->Features.Info.Vendor.ID;
Shm->Uncore.ChipID = 0x0;
Shm->Uncore.Chipset.ArchID = IC_CHIPSET;
for (idx = 0; idx < CHIP_MAX_PCI; idx++)
{
switch (Proc->Uncore.Chip[idx].VID) {
case PCI_VENDOR_ID_INTEL:
PCI_Intel(Shm, Proc, Core, Proc->Uncore.Chip[idx].DID);
break;
case PCI_VENDOR_ID_AMD:
PCI_AMD(Shm, Proc, Core, Proc->Uncore.Chip[idx].DID);
break;
}
}
/* Copy the chipset codename. */
StrCopy(Shm->Uncore.Chipset.CodeName,
Chipset[Shm->Uncore.Chipset.ArchID],
CODENAME_LEN);
/* Copy the Uncore clock ratios. */
memcpy( Shm->Uncore.Boost,
Proc->Uncore.Boost,
(UNCORE_BOOST(SIZE)) * sizeof(unsigned int) );
}
void CPUID_Dump(SHM_STRUCT *Shm, CORE_RO **Core, unsigned int cpu)
{ /* Copy the Vendor CPUID dump per Core. */
Shm->Cpu[cpu].Query.StdFunc = Core[cpu]->Query.StdFunc;
Shm->Cpu[cpu].Query.ExtFunc = Core[cpu]->Query.ExtFunc;
enum CPUID_ENUM i;
for (i = 0; i < CPUID_MAX_FUNC; i++) {
Shm->Cpu[cpu].CpuID[i].func = Core[cpu]->CpuID[i].func;
Shm->Cpu[cpu].CpuID[i].sub = Core[cpu]->CpuID[i].sub;
Shm->Cpu[cpu].CpuID[i].reg[0] = Core[cpu]->CpuID[i].reg[0];
Shm->Cpu[cpu].CpuID[i].reg[1] = Core[cpu]->CpuID[i].reg[1];
Shm->Cpu[cpu].CpuID[i].reg[2] = Core[cpu]->CpuID[i].reg[2];
Shm->Cpu[cpu].CpuID[i].reg[3] = Core[cpu]->CpuID[i].reg[3];
}
}
unsigned int AMD_L2_L3_Way_Associativity(CORE_RO **Core,
unsigned int cpu,
unsigned int level)
{
switch (Core[cpu]->T.Cache[level].Way) {
case 0x9:
return ((Core[cpu]->CpuID[
CPUID_8000001D_00000000_CACHE_L1D_PROPERTIES + level
].reg[1] >> 22) + 1);
case 0x6:
return (8);
case 0x8:
return (16);
case 0xa:
return (32);
case 0xb:
return (48);
case 0xc:
return (64);
case 0xd:
return (96);
case 0xe:
return (128);
default:
return (Core[cpu]->T.Cache[level].Way);
}
}
void Topology(SHM_STRUCT *Shm, PROC_RO *Proc, CORE_RO **Core, unsigned int cpu)
{
unsigned int loop;
/* Copy each Core topology. */
Shm->Cpu[cpu].Topology.MP.BSP = (Core[cpu]->T.Base.BSP) ? 1 : 0;
Shm->Cpu[cpu].Topology.ApicID = Core[cpu]->T.ApicID;
Shm->Cpu[cpu].Topology.CoreID = Core[cpu]->T.CoreID;
Shm->Cpu[cpu].Topology.ThreadID = Core[cpu]->T.ThreadID;
Shm->Cpu[cpu].Topology.PackageID = Core[cpu]->T.PackageID;
Shm->Cpu[cpu].Topology.Cluster.ID = Core[cpu]->T.Cluster.ID;
/* x2APIC capability. */
Shm->Cpu[cpu].Topology.MP.x2APIC = Proc->Features.Std.ECX.x2APIC;
if ((Shm->Proc.Features.Info.Vendor.CRC == CRC_AMD)
|| (Shm->Proc.Features.Info.Vendor.CRC == CRC_HYGON))
{
Shm->Cpu[cpu].Topology.MP.x2APIC |=Proc->Features.ExtInfo.ECX.ExtApicId;
}
/* Is local APIC enabled in xAPIC mode ? */
Shm->Cpu[cpu].Topology.MP.x2APIC &= Core[cpu]->T.Base.APIC_EN;
/* Is xAPIC enabled in x2APIC mode ? */
Shm->Cpu[cpu].Topology.MP.x2APIC = Shm->Cpu[cpu].Topology.MP.x2APIC
<< Core[cpu]->T.Base.x2APIC_EN;
/* Aggregate the Caches topology. */
for (loop = 0; loop < CACHE_MAX_LEVEL; loop++)
{
if (Core[cpu]->T.Cache[loop].Type > 0)
{
unsigned int level = Core[cpu]->T.Cache[loop].Level;
if (Core[cpu]->T.Cache[loop].Type == 2) {/* Instruction */
level = 0;
}
if (Shm->Proc.Features.Info.Vendor.CRC == CRC_INTEL)
{
Shm->Cpu[cpu].Topology.Cache[level].Set = \
Core[cpu]->T.Cache[loop].Set + 1;
Shm->Cpu[cpu].Topology.Cache[level].LineSz = \
Core[cpu]->T.Cache[loop].LineSz + 1;
Shm->Cpu[cpu].Topology.Cache[level].Part = \
Core[cpu]->T.Cache[loop].Part + 1;
Shm->Cpu[cpu].Topology.Cache[level].Way = \
Core[cpu]->T.Cache[loop].Way + 1;
Shm->Cpu[cpu].Topology.Cache[level].Size = \
Shm->Cpu[cpu].Topology.Cache[level].Set
* Shm->Cpu[cpu].Topology.Cache[level].LineSz
* Shm->Cpu[cpu].Topology.Cache[level].Part
* Shm->Cpu[cpu].Topology.Cache[level].Way;
} else {
if ((Shm->Proc.Features.Info.Vendor.CRC == CRC_AMD)
|| (Shm->Proc.Features.Info.Vendor.CRC == CRC_HYGON))
{
Shm->Cpu[cpu].Topology.Cache[level].Way = \
(loop == 2) || (loop == 3) ?
AMD_L2_L3_Way_Associativity(Core, cpu, loop)
: Core[cpu]->T.Cache[loop].Way;
Shm->Cpu[cpu].Topology.Cache[level].Size = \
Core[cpu]->T.Cache[loop].Size;
}
}
Shm->Cpu[cpu].Topology.Cache[level].Feature.WriteBack = \
Core[cpu]->T.Cache[loop].WrBack;
Shm->Cpu[cpu].Topology.Cache[level].Feature.Inclusive = \
Core[cpu]->T.Cache[loop].Inclus;
}
}
/* Apply various architecture size unit. */
switch (Proc->ArchID) {
case AMD_Family_15h:
/*TODO: do models 60h & 70h need a 512 KB size unit adjustment ? */
if ((Shm->Proc.Features.Std.EAX.ExtModel == 0x6)
|| (Shm->Proc.Features.Std.EAX.ExtModel == 0x7)) {
break;
}
/* Fallthrough */
case AMD_Zen:
case AMD_Zen_APU:
case AMD_ZenPlus:
case AMD_ZenPlus_APU:
case AMD_Zen_APU_Dali:
case AMD_EPYC_Rome:
case AMD_Zen2_CPK:
case AMD_Zen2_APU:
case AMD_Zen2_MTS:
case AMD_Zen2_Xbox:
case AMD_Zen3_VMR:
case AMD_Zen3_CZN:
case AMD_EPYC_Milan:
case AMD_Family_17h:
case AMD_Family_18h:
case AMD_Family_19h:
VIRTUALIZED_L3:
/* CPUID_Fn80000006_EDX: Value in [3FFFh - 0001h] = (<Value> *0.5) MB */
Shm->Cpu[cpu].Topology.Cache[3].Size *= 512;
break;
default:
if ( Shm->Proc.Features.Std.ECX.Hyperv ) { /* Virtualized ? */
goto VIRTUALIZED_L3;
}
break;
}
}
void CStates(SHM_STRUCT *Shm, CORE_RO **Core, unsigned int cpu)
{ /* Copy the C-State Configuration Control */
Shm->Cpu[cpu].Query.CfgLock = Core[cpu]->Query.CfgLock;
Shm->Cpu[cpu].Query.CStateLimit = Core[cpu]->Query.CStateLimit;
/* Copy Intel Max C-State Inclusion */
Shm->Cpu[cpu].Query.IORedir = Core[cpu]->Query.IORedir;
Shm->Cpu[cpu].Query.CStateInclude = Core[cpu]->Query.CStateInclude;
/* Copy any architectural C-States I/O Base Address */
Shm->Cpu[cpu].Query.CStateBaseAddr= Core[cpu]->Query.CStateBaseAddr;
}
void PowerThermal(SHM_STRUCT *Shm,PROC_RO *Proc,CORE_RO **Core,unsigned int cpu)
{
Shm->Cpu[cpu].PowerThermal.DutyCycle.Extended =
Core[cpu]->PowerThermal.ClockModulation.ECMD;
Shm->Cpu[cpu].PowerThermal.DutyCycle.ClockMod =
Core[cpu]->PowerThermal.ClockModulation.DutyCycle
>> !Shm->Cpu[cpu].PowerThermal.DutyCycle.Extended;
Shm->Cpu[cpu].PowerThermal.PowerPolicy =
Core[cpu]->PowerThermal.PerfEnergyBias.PowerPolicy;
Shm->Cpu[cpu].PowerThermal.TM1 = Proc->Features.Std.EDX.TM1; /* 000v */
Shm->Cpu[cpu].PowerThermal.TM1 |=
(Core[cpu]->PowerThermal.TCC_Enable << 1); /* 00v0 */
Shm->Cpu[cpu].PowerThermal.TM2 = Proc->Features.Std.ECX.TM2; /* 000v */
Shm->Cpu[cpu].PowerThermal.TM2 |=
(Core[cpu]->PowerThermal.TM2_Enable << 1); /* 00v0 */
Shm->Cpu[cpu].PowerThermal.HWP.Capabilities.Highest =
Core[cpu]->PowerThermal.HWP_Capabilities.Highest;
Shm->Cpu[cpu].PowerThermal.HWP.Capabilities.Guaranteed =
Core[cpu]->PowerThermal.HWP_Capabilities.Guaranteed;
Shm->Cpu[cpu].PowerThermal.HWP.Capabilities.Most_Efficient =
Core[cpu]->PowerThermal.HWP_Capabilities.Most_Efficient;
Shm->Cpu[cpu].PowerThermal.HWP.Capabilities.Lowest =
Core[cpu]->PowerThermal.HWP_Capabilities.Lowest;
Shm->Cpu[cpu].PowerThermal.HWP.Request.Minimum_Perf =
Core[cpu]->PowerThermal.HWP_Request.Minimum_Perf;
Shm->Cpu[cpu].PowerThermal.HWP.Request.Maximum_Perf =
Core[cpu]->PowerThermal.HWP_Request.Maximum_Perf;
Shm->Cpu[cpu].PowerThermal.HWP.Request.Desired_Perf =
Core[cpu]->PowerThermal.HWP_Request.Desired_Perf;
Shm->Cpu[cpu].PowerThermal.HWP.Request.Energy_Pref =
Core[cpu]->PowerThermal.HWP_Request.Energy_Pref;
}
void SystemRegisters(SHM_STRUCT *Shm, CORE_RO **Core, unsigned int cpu)
{
Shm->Cpu[cpu].SystemRegister.RFLAGS = Core[cpu]->SystemRegister.RFLAGS;
Shm->Cpu[cpu].SystemRegister.CR0 = Core[cpu]->SystemRegister.CR0;
Shm->Cpu[cpu].SystemRegister.CR3 = Core[cpu]->SystemRegister.CR3;
Shm->Cpu[cpu].SystemRegister.CR4 = Core[cpu]->SystemRegister.CR4;
Shm->Cpu[cpu].SystemRegister.CR8 = Core[cpu]->SystemRegister.CR8;
Shm->Cpu[cpu].SystemRegister.EFER = Core[cpu]->SystemRegister.EFER;
Shm->Cpu[cpu].SystemRegister.EFCR = Core[cpu]->SystemRegister.EFCR;
}
void SysGate_OS_Driver(REF *Ref)
{
SHM_STRUCT *Shm = Ref->Shm;
PROC_RO *Proc = Ref->Proc_RO;
memset(&Shm->SysGate.OS, 0, sizeof(OS_DRIVER));
if (strlen(Proc->OS.IdleDriver.Name) > 0) {
int idx;
StrCopy(Shm->SysGate.OS.IdleDriver.Name,
Proc->OS.IdleDriver.Name,
CPUIDLE_NAME_LEN);
Shm->SysGate.OS.IdleDriver.stateCount = Proc->OS.IdleDriver.stateCount;
Shm->SysGate.OS.IdleDriver.stateLimit = Proc->OS.IdleDriver.stateLimit;
for (idx = 0; idx < Shm->SysGate.OS.IdleDriver.stateCount; idx++)
{
StrCopy(Shm->SysGate.OS.IdleDriver.State[idx].Name,
Proc->OS.IdleDriver.State[idx].Name,
CPUIDLE_NAME_LEN);
StrCopy(Shm->SysGate.OS.IdleDriver.State[idx].Desc,
Proc->OS.IdleDriver.State[idx].Desc,
CPUIDLE_NAME_LEN);
Shm->SysGate.OS.IdleDriver.State[idx].exitLatency =
Proc->OS.IdleDriver.State[idx].exitLatency;
Shm->SysGate.OS.IdleDriver.State[idx].powerUsage =
Proc->OS.IdleDriver.State[idx].powerUsage;
Shm->SysGate.OS.IdleDriver.State[idx].targetResidency =
Proc->OS.IdleDriver.State[idx].targetResidency;
}
}
if (strlen(Proc->OS.FreqDriver.Name) > 0) {
StrCopy(Shm->SysGate.OS.FreqDriver.Name,
Proc->OS.FreqDriver.Name,
CPUFREQ_NAME_LEN);
}
if (strlen(Proc->OS.FreqDriver.Governor) > 0) {
StrCopy(Shm->SysGate.OS.FreqDriver.Governor,
Proc->OS.FreqDriver.Governor,
CPUFREQ_NAME_LEN);
}
}
void SysGate_Kernel(REF *Ref)
{
SHM_STRUCT *Shm = Ref->Shm;
SYSGATE_RO *SysGate = Ref->SysGate;
Shm->SysGate.kernel.version = SysGate->kernelVersionNumber >> 16;
Shm->SysGate.kernel.major = (SysGate->kernelVersionNumber >> 8) & 0xff;
Shm->SysGate.kernel.minor = SysGate->kernelVersionNumber & 0xff;
memcpy(Shm->SysGate.sysname, SysGate->sysname, MAX_UTS_LEN);
memcpy(Shm->SysGate.release, SysGate->release, MAX_UTS_LEN);
memcpy(Shm->SysGate.version, SysGate->version, MAX_UTS_LEN);
memcpy(Shm->SysGate.machine, SysGate->machine, MAX_UTS_LEN);
}
static const int reverseSign[2] = {+1, -1};
static int SortByRuntime(const void *p1, const void *p2, void *arg)
{
TASK_MCB *task1 = (TASK_MCB*) p1, *task2 = (TASK_MCB*) p2;
SHM_STRUCT *Shm = (SHM_STRUCT *) arg;
int sort = task1->runtime < task2->runtime ? +1 : -1;
sort *= reverseSign[Shm->SysGate.reverseOrder];
return (sort);
}
static int SortByUsertime(const void *p1, const void *p2, void *arg)
{
TASK_MCB *task1 = (TASK_MCB*) p1, *task2 = (TASK_MCB*) p2;
SHM_STRUCT *Shm = (SHM_STRUCT *) arg;
int sort = task1->usertime < task2->usertime ? +1 : -1;
sort *= reverseSign[Shm->SysGate.reverseOrder];
return (sort);
}
static int SortBySystime(const void *p1, const void *p2, void *arg)
{
TASK_MCB *task1 = (TASK_MCB*) p1, *task2 = (TASK_MCB*) p2;
SHM_STRUCT *Shm = (SHM_STRUCT *) arg;
int sort = task1->systime < task2->systime ? +1 : -1;
sort *= reverseSign[Shm->SysGate.reverseOrder];
return (sort);
}
static int SortByState(const void *p1, const void *p2, void *arg)
{
TASK_MCB *task1 = (TASK_MCB*) p1, *task2 = (TASK_MCB*) p2;
SHM_STRUCT *Shm = (SHM_STRUCT *) arg;
int sort = task1->state < task2->state ? -1 : +1;
sort *= reverseSign[Shm->SysGate.reverseOrder];
return (sort);
}
static int SortByPID(const void *p1, const void *p2, void *arg)
{
TASK_MCB *task1 = (TASK_MCB*) p1, *task2 = (TASK_MCB*) p2;
SHM_STRUCT *Shm = (SHM_STRUCT *) arg;
int sort = task1->pid < task2->pid ? -1 : +1;
sort *= reverseSign[Shm->SysGate.reverseOrder];
return (sort);
}
static int SortByCommand(const void *p1, const void *p2, void *arg)
{
TASK_MCB *task1 = (TASK_MCB*) p1, *task2 = (TASK_MCB*) p2;
SHM_STRUCT *Shm = (SHM_STRUCT *) arg;
int sort = strncmp(task1->comm, task2->comm, TASK_COMM_LEN);
sort *= reverseSign[Shm->SysGate.reverseOrder];
return (sort);
}
typedef int (*SORTBYFUNC)(const void *, const void *, void *);
static SORTBYFUNC SortByFunc[SORTBYCOUNT] = {
SortByState,
SortByRuntime,
SortByUsertime,
SortBySystime,
SortByPID,
SortByCommand
};
static int SortByTracker(const void *p1, const void *p2, void *arg)
{
TASK_MCB *task1 = (TASK_MCB*) p1, *task2 = (TASK_MCB*) p2;
SHM_STRUCT *Shm = (SHM_STRUCT *) arg;
int sort = (task1->pid == Shm->SysGate.trackTask) ?
-1 : (task2->pid == Shm->SysGate.trackTask) ?
+1 : SortByFunc[Shm->SysGate.sortByField](p1, p2, Shm);
return (sort);
}
void SysGate_Update(REF *Ref)
{
SHM_STRUCT *Shm = Ref->Shm;
SYSGATE_RO *SysGate = Ref->SysGate;
PROC_RO *Proc = Ref->Proc_RO;
Shm->SysGate.taskCount = SysGate->taskCount;
memcpy( Shm->SysGate.taskList, SysGate->taskList,
Shm->SysGate.taskCount * sizeof(TASK_MCB));
qsort_r(Shm->SysGate.taskList, Shm->SysGate.taskCount, sizeof(TASK_MCB),
Shm->SysGate.trackTask ?
SortByTracker
: SortByFunc[Shm->SysGate.sortByField], Shm);
Shm->SysGate.memInfo.totalram = SysGate->memInfo.totalram;
Shm->SysGate.memInfo.sharedram = SysGate->memInfo.sharedram;
Shm->SysGate.memInfo.freeram = SysGate->memInfo.freeram;
Shm->SysGate.memInfo.bufferram = SysGate->memInfo.bufferram;
Shm->SysGate.memInfo.totalhigh = SysGate->memInfo.totalhigh;
Shm->SysGate.memInfo.freehigh = SysGate->memInfo.freehigh;
Shm->SysGate.OS.IdleDriver.stateLimit = Proc->OS.IdleDriver.stateLimit;
}
void PerCore_Update( SHM_STRUCT *Shm, PROC_RO *Proc, CORE_RO **Core,
unsigned int cpu )
{
if (BITVAL(Core[cpu]->OffLine, HW)) {
BITSET(LOCKLESS, Shm->Cpu[cpu].OffLine, HW);
} else {
BITCLR(LOCKLESS, Shm->Cpu[cpu].OffLine, HW);
}
/* Initialize all clock ratios. */
memcpy( Shm->Cpu[cpu].Boost, Core[cpu]->Boost,
(BOOST(SIZE)) * sizeof(unsigned int) );
Shm->Cpu[cpu].Query.Microcode = Core[cpu]->Query.Microcode;
Topology(Shm, Proc, Core, cpu);
CStates(Shm, Core, cpu);
PowerThermal(Shm, Proc, Core, cpu);
SystemRegisters(Shm, Core, cpu);
CPUID_Dump(Shm, Core, cpu);
}
int SysGate_OnDemand(REF *Ref, int operation)
{
int rc = -1;
const size_t allocPages = PAGE_SIZE << Ref->Proc_RO->Gate.ReqMem.Order;
if (operation == 0) {
if (Ref->SysGate != NULL) {
if ((rc = munmap(Ref->SysGate, allocPages)) == 0) {
Ref->SysGate = NULL;
}
} else {
rc = -1;
}
} else {
if (Ref->SysGate == NULL) {
const off_t vm_pgoff = ID_RO_VMA_GATE * PAGE_SIZE;
SYSGATE_RO *MapGate = mmap(NULL, allocPages,
PROT_READ,
MAP_SHARED,
Ref->fd->Drv, vm_pgoff);
if (MapGate != MAP_FAILED) {
Ref->SysGate = MapGate;
rc = 0;
}
} else {
rc = 0;
}
}
return (rc);
}
void SysGate_Toggle(REF *Ref, unsigned int state)
{
if (state == 0) {
if (BITWISEAND(LOCKLESS, Ref->Shm->SysGate.Operation, 0x1)) {
/* Stop SysGate */
BITCLR(LOCKLESS, Ref->Shm->SysGate.Operation, 0);
/* Notify */
BITWISESET(LOCKLESS, PendingSync, BIT_MASK_NTFY);
}
} else {
if (!BITWISEAND(LOCKLESS, Ref->Shm->SysGate.Operation, 0x1)) {
if (SysGate_OnDemand(Ref, 1) == 0) {
if (ioctl(Ref->fd->Drv, COREFREQ_IOCTL_SYSONCE) != -EPERM) {
/* Aggregate the OS idle driver data. */
SysGate_OS_Driver(Ref);
/* Copy system information. */
SysGate_Kernel(Ref);
/* Start SysGate */
BITSET(LOCKLESS, Ref->Shm->SysGate.Operation, 0);
/* Notify */
BITWISESET(LOCKLESS, PendingSync,BIT_MASK_NTFY);
}
}
}
}
}
void Master_Ring_Handler(REF *Ref, unsigned int rid)
{
if (!RING_NULL(Ref->Shm->Ring[rid]))
{
RING_CTRL ctrl __attribute__ ((aligned(16)));
RING_READ(Ref->Shm->Ring[rid], ctrl);
int rc = -EPERM, drc = -EPERM;
if ( (ctrl.cmd >= COREFREQ_IOCTL_SYSUPDT)
&& (ctrl.cmd <= COREFREQ_IOCTL_CLEAR_EVENTS) )
{
rc = ioctl(Ref->fd->Drv, ctrl.cmd, ctrl.arg);
drc = errno;
}
if (Quiet & 0x100) {
printf("\tRING[%u](%x,%x)(%lx)>(%d,%d)\n",
rid, ctrl.cmd, ctrl.sub, ctrl.arg, rc, drc);
}
switch (rc) {
case -EPERM:
{
RING_CTRL error __attribute__ ((aligned(16))) = {
.arg = ctrl.arg,
.cmd = ctrl.cmd,
.drc = drc,
.tds = ELAPSED(Ref->Shm->StartedAt)
};
RING_WRITE_1xPARAM( error.sub,
Ref->Shm->Error,
error.cmd,
error.arg );
}
break;
case RC_OK_SYSGATE:
SysGate_OS_Driver(Ref);
/* Fallthrough */
case RC_SUCCESS: /* Platform changed -> pending notification. */
BITWISESET(LOCKLESS, PendingSync, BIT_MASK_NTFY);
break;
case RC_OK_COMPUTE: /* Compute claimed -> pending notification. */
BITWISESET(LOCKLESS, PendingSync, BIT_MASK_COMP);
break;
}
}
}
void Child_Ring_Handler(REF *Ref, unsigned int rid)
{
if (!RING_NULL(Ref->Shm->Ring[rid]))
{
RING_CTRL ctrl __attribute__ ((aligned(16)));
RING_READ(Ref->Shm->Ring[rid], ctrl);
switch (ctrl.cmd) {
case COREFREQ_TOGGLE_SYSGATE:
switch (ctrl.arg) {
case COREFREQ_TOGGLE_OFF:
case COREFREQ_TOGGLE_ON:
SysGate_Toggle(Ref, ctrl.arg);
BITWISESET(LOCKLESS, Ref->Shm->Proc.Sync, BIT_MASK_NTFY);
break;
}
break;
case COREFREQ_ORDER_MACHINE:
switch (ctrl.arg) {
case COREFREQ_TOGGLE_OFF:
SCHEDULER_STOP:
if (BITVAL(Ref->Shm->Proc.Sync, BURN))
{
BITCLR(BUS_LOCK, Ref->Shm->Proc.Sync, BURN);
while (BITWISEAND_CC(BUS_LOCK, roomCore, roomSeed))
{
if (BITVAL(Shutdown, SYNC)) { /* SpinLock */
break;
}
}
BITSTOR_CC(BUS_LOCK, Ref->Shm->roomSched, roomClear);
Ref->Slice.Func = Slice_NOP;
Ref->Slice.arg = 0;
Ref->Slice.pattern = RESET_CSP;
/* Notify the Slice module has stopped */
BITWISESET(LOCKLESS, Ref->Shm->Proc.Sync, BIT_MASK_NTFY);
}
break;
}
break;
default:
{
RING_SLICE *porder = order_list;
while (porder->func != NULL)
{
if ((porder->ctrl.cmd == ctrl.cmd) && (porder->ctrl.sub == ctrl.sub))
{
if ( !BITVAL(Ref->Shm->Proc.Sync, BURN)
|| ((Ref->Slice.Func == Slice_Turbo) && (Ref->Slice.pattern == USR_CPU)
&& (ctrl.cmd == COREFREQ_ORDER_TURBO) && (ctrl.sub == USR_CPU)))
{
if (ctrl.sub == USR_CPU) {
if (BITVAL_CC(Ref->Shm->roomSched, ctrl.dl.lo))
{
BITCLR_CC(LOCKLESS, Ref->Shm->roomSched, ctrl.dl.lo);
if (!BITWISEAND_CC(BUS_LOCK, Ref->Shm->roomSched, roomSeed))
{
goto SCHEDULER_STOP;
}
} else {
BITSET_CC(LOCKLESS, Ref->Shm->roomSched, ctrl.dl.lo);
goto SCHEDULER_START;
}
} else {
SliceScheduling(Ref->Shm, ctrl.dl.lo, porder->pattern);
SCHEDULER_START:
Ref->Slice.Func = porder->func;
Ref->Slice.arg = porder->ctrl.dl.lo;
Ref->Slice.pattern = porder->pattern;
BITSET(BUS_LOCK, Ref->Shm->Proc.Sync, BURN);
}
/* Notify the Slice module is starting up */
BITWISESET(LOCKLESS, Ref->Shm->Proc.Sync, BIT_MASK_NTFY);
}
break;
}
porder++;
}
}
break;
}
if (Quiet & 0x100) {
printf("\tRING[%u](%x,%x)(%hx:%hx,%hx:%hx)\n",
rid, ctrl.cmd, ctrl.sub,
ctrl.dh.hi, ctrl.dh.lo, ctrl.dl.hi, ctrl.dl.lo);
}
}
}
int ServerFollowService(SERVICE_PROC *pSlave,
SERVICE_PROC *pMaster,
pthread_t tid)
{
if (pSlave->Proc != pMaster->Proc) {
pSlave->Proc = pMaster->Proc;
cpu_set_t cpuset;
CPU_ZERO(&cpuset);
CPU_SET(pSlave->Core, &cpuset);
if (pSlave->Thread != -1) {
CPU_SET(pSlave->Thread, &cpuset);
}
return(pthread_setaffinity_np(tid, sizeof(cpu_set_t), &cpuset));
}
return (-1);
}
static void *Emergency_Handler(void *pRef)
{
REF *Ref = (REF *) pRef;
unsigned int rid = (Ref->CPID == 0);
SERVICE_PROC localService = {.Proc = -1};
int caught = 0, leave = 0;
char handlerName[TASK_COMM_LEN] = {
'c','o','r','e','f','r','e','q','d','-','r','i','n','g','0',0
};
handlerName[14] += rid;
pthread_t tid = pthread_self();
if(ServerFollowService(&localService, &Ref->Shm->Proc.Service, tid) == 0) {
pthread_setname_np(tid, handlerName);
}
while (!leave) {
caught = sigtimedwait(&Ref->Signal, NULL, &Ref->Shm->Sleep.ringWaiting);
if (caught != -1) {
switch (caught) {
case SIGUSR2:
if (Ref->CPID) { /* Stop SysGate */
SysGate_Toggle(Ref, 0);
}
break;
case SIGUSR1:
if (Ref->CPID) { /* Start SysGate */
SysGate_Toggle(Ref, 1);
}
break;
case SIGCHLD: /* Exit Ring Thread */
leave = 0x1;
/* Fallthrough */
case SIGSTKFLT:
case SIGXFSZ:
case SIGXCPU:
case SIGSEGV:
case SIGTERM:
case SIGQUIT:
case SIGALRM:
case SIGABRT:
case SIGPIPE:
case SIGTRAP:
case SIGSYS:
case SIGFPE:
case SIGBUS:
case SIGILL:
case SIGINT: /* [CTRL] + [C] */
BITSET(LOCKLESS, Shutdown, SYNC);
break;
case SIGVTALRM:
case SIGWINCH:
case SIGTTOU:
case SIGTTIN:
case SIGTSTP:
case SIGPROF:
case SIGHUP:
case SIGPWR:
case SIGIO:
default: /* RTMIN ... RTMAX */
break;
}
} else if (errno == EAGAIN) {
if (Ref->CPID) {
Master_Ring_Handler(Ref, rid);
} else {
Child_Ring_Handler(Ref, rid);
}
}
ServerFollowService(&localService, &Ref->Shm->Proc.Service, tid);
}
return (NULL);
}
void Emergency_Command(REF *Ref, unsigned int cmd)
{
switch (cmd) {
case 0:
if (Ref->Started) {
if (!pthread_kill(Ref->KID, SIGCHLD)) {
if (!pthread_join(Ref->KID, NULL)) {
Ref->Started = 0;
}
}
}
break;
case 1: {
const int ignored[] = {
SIGIO, SIGPROF, SIGPWR, SIGHUP, SIGTSTP,
SIGTTIN, SIGTTOU, SIGVTALRM, SIGWINCH
}, handled[] = {
SIGUSR1, SIGUSR2, SIGCHLD, SIGINT, SIGILL, SIGBUS,
SIGFPE, SIGSYS, SIGTRAP, SIGPIPE, SIGABRT, SIGALRM,
SIGQUIT, SIGTERM, SIGSEGV, SIGXCPU, SIGXFSZ, SIGSTKFLT
};
/* SIGKILL,SIGCONT,SIGSTOP,SIGURG: Reserved */
const ssize_t ignoredCount = sizeof(ignored) / sizeof(int),
handledCount = sizeof(handled) / sizeof(int);
int signo;
sigemptyset(&Ref->Signal);
for (signo = SIGRTMIN; signo <= SIGRTMAX; signo++) {
sigaddset(&Ref->Signal, signo);
}
for (signo = 0; signo < ignoredCount; signo++) {
sigaddset(&Ref->Signal, ignored[signo]);
}
for (signo = 0; signo < handledCount; signo++) {
sigaddset(&Ref->Signal, handled[signo]);
}
if (!pthread_sigmask(SIG_BLOCK, &Ref->Signal, NULL))
{
if(!pthread_create(&Ref->KID, NULL, Emergency_Handler, Ref))
{
Ref->Started = 1;
}
}
}
break;
}
}
static inline void Pkg_ComputeThermal_None( struct PKG_FLIP_FLOP *PFlip,
struct FLIP_FLOP *SProc )
{
UNUSED(PFlip);
UNUSED(SProc);
}
static inline void Pkg_ComputeThermal_Intel( struct PKG_FLIP_FLOP *PFlip,
struct FLIP_FLOP *SProc )
{
COMPUTE_THERMAL(INTEL,
PFlip->Thermal.Temp,
SProc->Thermal.Param,
PFlip->Thermal.Sensor);
}
static inline void Pkg_ComputeThermal_AMD( struct PKG_FLIP_FLOP *PFlip,
struct FLIP_FLOP *SProc )
{
COMPUTE_THERMAL(AMD,
PFlip->Thermal.Temp,
SProc->Thermal.Param,
PFlip->Thermal.Sensor);
}
static inline void Pkg_ComputeThermal_AMD_0Fh( struct PKG_FLIP_FLOP *PFlip,
struct FLIP_FLOP *SProc )
{
COMPUTE_THERMAL(AMD_0Fh,
PFlip->Thermal.Temp,
SProc->Thermal.Param,
PFlip->Thermal.Sensor);
}
static inline void Pkg_ComputeThermal_AMD_15h( struct PKG_FLIP_FLOP *PFlip,
struct FLIP_FLOP *SProc )
{
COMPUTE_THERMAL(AMD_15h,
PFlip->Thermal.Temp,
SProc->Thermal.Param,
PFlip->Thermal.Sensor);
}
static inline void Pkg_ComputeThermal_AMD_17h( struct PKG_FLIP_FLOP *PFlip,
struct FLIP_FLOP *SProc )
{
COMPUTE_THERMAL(AMD_17h,
PFlip->Thermal.Temp,
SProc->Thermal.Param,
PFlip->Thermal.Sensor);
}
static inline void Pkg_ComputeVoltage_None(struct PKG_FLIP_FLOP *PFlip)
{
UNUSED(PFlip);
}
#define Pkg_ComputeVoltage_Intel Pkg_ComputeVoltage_None
#define Pkg_ComputeVoltage_Intel_Core2 Pkg_ComputeVoltage_None
static inline void Pkg_ComputeVoltage_Intel_SoC(struct PKG_FLIP_FLOP *PFlip)
{
COMPUTE_VOLTAGE(INTEL_SOC,
PFlip->Voltage.CPU,
PFlip->Voltage.VID.CPU);
}
static inline void Pkg_ComputeVoltage_Intel_SNB(struct PKG_FLIP_FLOP *PFlip)
{ /* Intel 2nd Generation Datasheet Vol-1 §7.4 Table 7-1 */
COMPUTE_VOLTAGE(INTEL_SNB,
PFlip->Voltage.CPU,
PFlip->Voltage.VID.CPU);
}
#define Pkg_ComputeVoltage_Intel_SKL_X Pkg_ComputeVoltage_None
#define Pkg_ComputeVoltage_AMD Pkg_ComputeVoltage_None
#define Pkg_ComputeVoltage_AMD_0Fh Pkg_ComputeVoltage_None
#define Pkg_ComputeVoltage_AMD_15h Pkg_ComputeVoltage_None
static inline void Pkg_ComputeVoltage_AMD_17h(struct PKG_FLIP_FLOP *PFlip)
{
COMPUTE_VOLTAGE(AMD_17h,
PFlip->Voltage.CPU,
PFlip->Voltage.VID.CPU);
COMPUTE_VOLTAGE(AMD_17h,
PFlip->Voltage.SOC,
PFlip->Voltage.VID.SOC);
}
static inline void Pkg_ComputeVoltage_Winbond_IO(struct PKG_FLIP_FLOP *PFlip)
{ /* Winbond W83627EHF/EF, W83627EHG,EG */
COMPUTE_VOLTAGE(WINBOND_IO,
PFlip->Voltage.CPU,
PFlip->Voltage.VID.CPU);
}
static inline void Pkg_ComputeVoltage_ITE_Tech_IO(struct PKG_FLIP_FLOP *PFlip)
{
COMPUTE_VOLTAGE(ITETECH_IO,
PFlip->Voltage.CPU,
PFlip->Voltage.VID.CPU);
}
static inline void Pkg_ComputePower_None(PROC_RW *Proc, struct FLIP_FLOP *CFlop)
{
UNUSED(Proc);
UNUSED(CFlop);
}
#define Pkg_ComputePower_Intel Pkg_ComputePower_None
#define Pkg_ComputePower_Intel_Atom Pkg_ComputePower_None
#define Pkg_ComputePower_AMD Pkg_ComputePower_None
static inline void Pkg_ComputePower_AMD_17h( PROC_RW *Proc,
struct FLIP_FLOP *CFlop )
{
Proc->Delta.Power.ACCU[PWR_DOMAIN(CORES)] += CFlop->Delta.Power.ACCU;
}
static inline void Pkg_ResetPower_None(PROC_RW *Proc)
{
UNUSED(Proc);
}
#define Pkg_ResetPower_Intel Pkg_ResetPower_None
#define Pkg_ResetPower_Intel_Atom Pkg_ResetPower_None
#define Pkg_ResetPower_AMD Pkg_ResetPower_None
static inline void Pkg_ResetPower_AMD_17h(PROC_RW *Proc)
{
Proc->Delta.Power.ACCU[PWR_DOMAIN(CORES)] = 0;
}
void Pkg_ResetSensorLimits(PROC_STRUCT *Pkg)
{
enum PWR_DOMAIN pw;
for (pw = PWR_DOMAIN(PKG); pw < PWR_DOMAIN(SIZE); pw++)
{
RESET_SENSOR_LIMIT(ENERGY, LOWEST , Pkg->State.Energy[pw].Limit);
RESET_SENSOR_LIMIT(ENERGY, HIGHEST, Pkg->State.Energy[pw].Limit );
RESET_SENSOR_LIMIT(POWER , LOWEST , Pkg->State.Power[pw].Limit );
RESET_SENSOR_LIMIT(POWER , HIGHEST, Pkg->State.Power[pw].Limit );
}
RESET_SENSOR_LIMIT(VOLTAGE, LOWEST, Pkg->State.Voltage.Limit );
RESET_SENSOR_LIMIT(VOLTAGE, HIGHEST,Pkg->State.Voltage.Limit );
}
REASON_CODE Core_Manager(REF *Ref)
{
SHM_STRUCT *Shm = Ref->Shm;
PROC_RO *Proc = Ref->Proc_RO;
PROC_RW *Proc_RW = Ref->Proc_RW;
CORE_RO **Core = Ref->Core_RO;
struct PKG_FLIP_FLOP *PFlip;
struct FLIP_FLOP *SProc;
SERVICE_PROC localService = {.Proc = -1};
struct {
double RelFreq,
AbsFreq;
} prevTop;
REASON_INIT (reason);
unsigned int cpu = 0;
pthread_t tid = pthread_self();
Shm->App.Svr = tid;
if (ServerFollowService(&localService, &Shm->Proc.Service, tid) == 0) {
pthread_setname_np(tid, "corefreqd-pmgr");
}
ARG *Arg = calloc(Shm->Proc.CPU.Count, sizeof(ARG));
if (Arg != NULL)
{
void (*Pkg_ComputeThermalFormula)( struct PKG_FLIP_FLOP*,
struct FLIP_FLOP* );
void (*Pkg_ComputeVoltageFormula)( struct PKG_FLIP_FLOP* );
void (*Pkg_ComputePowerFormula)( PROC_RW*, struct FLIP_FLOP* );
void (*Pkg_ResetPowerFormula)(PROC_RW*);
switch (KIND_OF_FORMULA(Shm->Proc.thermalFormula)) {
case THERMAL_KIND_INTEL:
Pkg_ComputeThermalFormula = Pkg_ComputeThermal_Intel;
break;
case THERMAL_KIND_AMD:
Pkg_ComputeThermalFormula = Pkg_ComputeThermal_AMD;
break;
case THERMAL_KIND_AMD_0Fh:
Pkg_ComputeThermalFormula = Pkg_ComputeThermal_AMD_0Fh;
break;
case THERMAL_KIND_AMD_15h:
Pkg_ComputeThermalFormula = Pkg_ComputeThermal_AMD_15h;
break;
case THERMAL_KIND_AMD_17h:
Pkg_ComputeThermalFormula = Pkg_ComputeThermal_AMD_17h;
break;
case THERMAL_KIND_NONE:
default:
Pkg_ComputeThermalFormula = Pkg_ComputeThermal_None;
}
switch (KIND_OF_FORMULA(Shm->Proc.voltageFormula)) {
case VOLTAGE_KIND_INTEL:
Pkg_ComputeVoltageFormula = Pkg_ComputeVoltage_Intel;
break;
case VOLTAGE_KIND_INTEL_CORE2:
Pkg_ComputeVoltageFormula = Pkg_ComputeVoltage_Intel_Core2;
break;
case VOLTAGE_KIND_INTEL_SOC:
Pkg_ComputeVoltageFormula = Pkg_ComputeVoltage_Intel_SoC;
break;
case VOLTAGE_KIND_INTEL_SNB:
Pkg_ComputeVoltageFormula = Pkg_ComputeVoltage_Intel_SNB;
break;
case VOLTAGE_KIND_INTEL_SKL_X:
Pkg_ComputeVoltageFormula = Pkg_ComputeVoltage_Intel_SKL_X;
break;
case VOLTAGE_KIND_AMD:
Pkg_ComputeVoltageFormula = Pkg_ComputeVoltage_AMD;
break;
case VOLTAGE_KIND_AMD_0Fh:
Pkg_ComputeVoltageFormula = Pkg_ComputeVoltage_AMD_0Fh;
break;
case VOLTAGE_KIND_AMD_15h:
Pkg_ComputeVoltageFormula = Pkg_ComputeVoltage_AMD_15h;
break;
case VOLTAGE_KIND_AMD_17h:
Pkg_ComputeVoltageFormula = Pkg_ComputeVoltage_AMD_17h;
break;
case VOLTAGE_KIND_WINBOND_IO:
Pkg_ComputeVoltageFormula = Pkg_ComputeVoltage_Winbond_IO;
break;
case VOLTAGE_KIND_ITETECH_IO:
Pkg_ComputeVoltageFormula = Pkg_ComputeVoltage_ITE_Tech_IO;
break;
case VOLTAGE_KIND_NONE:
default:
Pkg_ComputeVoltageFormula = Pkg_ComputeVoltage_None;
break;
}
switch (KIND_OF_FORMULA(Shm->Proc.powerFormula)) {
case POWER_KIND_INTEL:
Pkg_ComputePowerFormula = Pkg_ComputePower_Intel;
Pkg_ResetPowerFormula = Pkg_ResetPower_Intel;
break;
case POWER_KIND_INTEL_ATOM:
Pkg_ComputePowerFormula = Pkg_ComputePower_Intel_Atom;
Pkg_ResetPowerFormula = Pkg_ResetPower_Intel_Atom;
break;
case POWER_KIND_AMD:
Pkg_ComputePowerFormula = Pkg_ComputePower_AMD;
Pkg_ResetPowerFormula = Pkg_ResetPower_AMD;
break;
case POWER_KIND_AMD_17h:
Pkg_ComputePowerFormula = Pkg_ComputePower_AMD_17h;
Pkg_ResetPowerFormula = Pkg_ResetPower_AMD_17h;
break;
case POWER_KIND_NONE:
default:
Pkg_ComputePowerFormula = Pkg_ComputePower_None;
Pkg_ResetPowerFormula = Pkg_ResetPower_None;
break;
}
#define CONDITION_RDTSCP() \
( (Proc->Features.AdvPower.EDX.Inv_TSC == 1) \
|| (Proc->Features.ExtInfo.EDX.RDTSCP == 1) )
#define CONDITION_RDPMC() \
( (Proc->Features.Info.Vendor.CRC == CRC_INTEL) \
&& (Proc->Features.PerfMon.EAX.Version >= 1) \
&& (BITVAL(Core[Proc->Service.Core]->SystemRegister.CR4, \
CR4_PCE) == 1) )
UBENCH_SETUP(CONDITION_RDTSCP(), CONDITION_RDPMC());
Print_uBenchmark((Quiet & 0x100));
while (!BITVAL(Shutdown, SYNC))
{ /* Loop while all the cpu room bits are not cleared. */
while ( !BITVAL(Shutdown, SYNC) &&
#if defined(LEGACY) && LEGACY > 0
!BITZERO(BUS_LOCK, roomCore[CORE_WORD_TOP(CORE_COUNT)])
#else
!BITCMP_CC(BUS_LOCK, roomCore, roomClear)
#endif
)
{
nanosleep(&Shm->Sleep.pollingWait, NULL);
}
UBENCH_RDCOUNTER(1);
Shm->Proc.Toggle = !Shm->Proc.Toggle;
PFlip = &Shm->Proc.FlipFlop[Shm->Proc.Toggle];
SProc = &Shm->Cpu[Shm->Proc.Service.Core].FlipFlop[ \
!Shm->Cpu[Shm->Proc.Service.Core].Toggle
];
PFlip->Thermal.Temp = 0;
/* Reset the averages & the max frequency */
Shm->Proc.Avg.Turbo = 0;
Shm->Proc.Avg.C0 = 0;
Shm->Proc.Avg.C3 = 0;
Shm->Proc.Avg.C6 = 0;
Shm->Proc.Avg.C7 = 0;
Shm->Proc.Avg.C1 = 0;
prevTop.RelFreq = 0.0;
prevTop.AbsFreq = 0.0;
Pkg_ResetPowerFormula(Proc_RW);
for (cpu=0; !BITVAL(Shutdown, SYNC)&&(cpu < Shm->Proc.CPU.Count);cpu++)
{
if (BITVAL(Core[cpu]->OffLine, OS) == 1)
{
if (Arg[cpu].TID)
{ /* Remove this cpu. */
pthread_join(Arg[cpu].TID, NULL);
Arg[cpu].TID = 0;
PerCore_Update(Shm, Proc, Core, cpu);
if (ServerFollowService( &localService,
&Shm->Proc.Service,
tid ) == 0)
{
SProc = &Shm->Cpu[Shm->Proc.Service.Core].FlipFlop[ \
!Shm->Cpu[Shm->Proc.Service.Core].Toggle ];
}
/* Raise these bits up to notify a platform change. */
BITWISESET(LOCKLESS, PendingSync, BIT_MASK_NTFY);
}
BITSET(LOCKLESS, Shm->Cpu[cpu].OffLine, OS);
} else {
struct FLIP_FLOP *CFlop = \
&Shm->Cpu[cpu].FlipFlop[!Shm->Cpu[cpu].Toggle];
if (!Arg[cpu].TID)
{ /* Add this cpu. */
PerCore_Update(Shm, Proc, Core, cpu);
Arg[cpu].Ref = Ref;
Arg[cpu].Bind = cpu;
pthread_create( &Arg[cpu].TID,
NULL,
Core_Cycle,
&Arg[cpu]);
if (ServerFollowService(&localService,
&Shm->Proc.Service,
tid) == 0)
{
SProc = &Shm->Cpu[Shm->Proc.Service.Core].FlipFlop[ \
!Shm->Cpu[Shm->Proc.Service.Core].Toggle ];
}
if (Quiet & 0x100) {
printf( " CPU #%03u @ %.2f MHz\n", cpu,
ABS_FREQ_MHz(double , Shm->Cpu[cpu].Boost[BOOST(MAX)],
Core[cpu]->Clock) );
}
/* Notify a CPU has been brought up */
BITWISESET(LOCKLESS, PendingSync, BIT_MASK_NTFY);
}
BITCLR(LOCKLESS, Shm->Cpu[cpu].OffLine, OS);
/* Index CPU with the highest Rel. and Abs frequencies. */
if (CFlop->Relative.Freq > prevTop.RelFreq) {
prevTop.RelFreq = CFlop->Relative.Freq;
Shm->Proc.Top.Rel = cpu;
}
if (CFlop->Absolute.Freq > prevTop.AbsFreq) {
prevTop.AbsFreq = CFlop->Absolute.Freq;
Shm->Proc.Top.Abs = cpu;
}
/* Workaround to Package Thermal Management: the hottest Core */
if (!Shm->Proc.Features.Power.EAX.PTM) {
if (CFlop->Thermal.Temp > PFlip->Thermal.Temp)
PFlip->Thermal.Temp = CFlop->Thermal.Temp;
}
/* Workaround to RAPL Package counter: sum of all Cores */
Pkg_ComputePowerFormula(Proc_RW, CFlop);
/* Sum counters. */
Shm->Proc.Avg.Turbo += CFlop->State.Turbo;
Shm->Proc.Avg.C0 += CFlop->State.C0;
Shm->Proc.Avg.C3 += CFlop->State.C3;
Shm->Proc.Avg.C6 += CFlop->State.C6;
Shm->Proc.Avg.C7 += CFlop->State.C7;
Shm->Proc.Avg.C1 += CFlop->State.C1;
}
}
if (!BITVAL(Shutdown, SYNC))
{
double dPTSC;
unsigned char fRESET = 0;
/* Compute the counters averages. */
Shm->Proc.Avg.Turbo /= Shm->Proc.CPU.OnLine;
Shm->Proc.Avg.C0 /= Shm->Proc.CPU.OnLine;
Shm->Proc.Avg.C3 /= Shm->Proc.CPU.OnLine;
Shm->Proc.Avg.C6 /= Shm->Proc.CPU.OnLine;
Shm->Proc.Avg.C7 /= Shm->Proc.CPU.OnLine;
Shm->Proc.Avg.C1 /= Shm->Proc.CPU.OnLine;
/* Package scope counters */
PFlip->Delta.PTSC = Proc->Delta.PTSC;
PFlip->Delta.PC02 = Proc->Delta.PC02;
PFlip->Delta.PC03 = Proc->Delta.PC03;
PFlip->Delta.PC04 = Proc->Delta.PC04;
PFlip->Delta.PC06 = Proc->Delta.PC06;
PFlip->Delta.PC07 = Proc->Delta.PC07;
PFlip->Delta.PC08 = Proc->Delta.PC08;
PFlip->Delta.PC09 = Proc->Delta.PC09;
PFlip->Delta.PC10 = Proc->Delta.PC10;
PFlip->Delta.MC6 = Proc->Delta.MC6;
/* Package C-state Residency counters */
dPTSC = (double) PFlip->Delta.PTSC;
Shm->Proc.State.PC02 = (double) PFlip->Delta.PC02 / dPTSC;
Shm->Proc.State.PC03 = (double) PFlip->Delta.PC03 / dPTSC;
Shm->Proc.State.PC04 = (double) PFlip->Delta.PC04 / dPTSC;
Shm->Proc.State.PC06 = (double) PFlip->Delta.PC06 / dPTSC;
Shm->Proc.State.PC07 = (double) PFlip->Delta.PC07 / dPTSC;
Shm->Proc.State.PC08 = (double) PFlip->Delta.PC08 / dPTSC;
Shm->Proc.State.PC09 = (double) PFlip->Delta.PC09 / dPTSC;
Shm->Proc.State.PC10 = (double) PFlip->Delta.PC10 / dPTSC;
Shm->Proc.State.MC6 = (double) PFlip->Delta.MC6 / dPTSC;
/* Uncore scope counters */
PFlip->Uncore.FC0 = Proc->Delta.Uncore.FC0;
/* Power & Energy counters */
enum PWR_DOMAIN pw;
for (pw = PWR_DOMAIN(PKG); pw < PWR_DOMAIN(SIZE); pw++)
{
PFlip->Delta.ACCU[pw] = Proc_RW->Delta.Power.ACCU[pw];
Shm->Proc.State.Energy[pw].Current = \
(double) PFlip->Delta.ACCU[pw]
* Shm->Proc.Power.Unit.Joules;
Shm->Proc.State.Power[pw].Current = \
(1000.0 * Shm->Proc.State.Energy[pw].Current)
/ (double) Shm->Sleep.Interval;
/* Processor scope: computes Min and Max energy consumed. */
TEST_AND_SET_SENSOR( ENERGY, LOWEST,
Shm->Proc.State.Energy[pw].Current,
Shm->Proc.State.Energy[pw].Limit );
TEST_AND_SET_SENSOR( ENERGY, HIGHEST,
Shm->Proc.State.Energy[pw].Current,
Shm->Proc.State.Energy[pw].Limit );
/* Processor scope: computes Min and Max power consumed. */
TEST_AND_SET_SENSOR( POWER, LOWEST,
Shm->Proc.State.Power[pw].Current,
Shm->Proc.State.Power[pw].Limit );
TEST_AND_SET_SENSOR( POWER, HIGHEST,
Shm->Proc.State.Power[pw].Current,
Shm->Proc.State.Power[pw].Limit );
}
/* Package thermal formulas */
PFlip->Thermal.Events = Proc->PowerThermal.Events;
if (Shm->Proc.Features.Power.EAX.PTM)
{
PFlip->Thermal.Sensor = Proc->PowerThermal.Sensor;
Pkg_ComputeThermalFormula(PFlip, SProc);
}
/* Package Voltage formulas */
PFlip->Voltage.VID.CPU = Proc->PowerThermal.VID.CPU;
PFlip->Voltage.VID.SOC = Proc->PowerThermal.VID.SOC;
Pkg_ComputeVoltageFormula(PFlip);
/* Computes the Min Processor voltage. */
TEST_AND_SET_SENSOR( VOLTAGE, LOWEST, PFlip->Voltage.CPU,
Shm->Proc.State.Voltage.Limit );
/* Computes the Max Processor voltage. */
TEST_AND_SET_SENSOR( VOLTAGE, HIGHEST, PFlip->Voltage.CPU,
Shm->Proc.State.Voltage.Limit );
/*
The Driver tick is bound to the Service Core:
1- Tasks collection; Tasks count; and Memory usage.
2- Processor has resumed from Suspend To RAM.
*/
Shm->SysGate.tickStep = Proc->tickStep;
if (Shm->SysGate.tickStep == Shm->SysGate.tickReset)
{
if (BITWISEAND(LOCKLESS, Shm->SysGate.Operation, 0x1))
{
if (SysGate_OnDemand(Ref, 1) == 0) {
SysGate_Update(Ref);
}
}
/* OS notifications: such as Resumed from Suspend. */
if ( (fRESET = BITCLR(BUS_LOCK, Proc_RW->OS.Signal, NTFY)) == 1)
{
BITWISESET(LOCKLESS, PendingSync, BIT_MASK_COMP|BIT_MASK_NTFY);
}
}
if (BITWISEAND(LOCKLESS, PendingSync, BIT_MASK_COMP|BIT_MASK_NTFY))
{
Package_Update(Shm, Proc, Proc_RW);
Uncore_Update(Shm, Proc, Core[Proc->Service.Core]);
for (cpu = 0; cpu < Ref->Shm->Proc.CPU.Count; cpu++)
{
if (fRESET == 1)
{
Core_ResetSensorLimits(&Shm->Cpu[cpu]);
}
if (BITVAL(Ref->Core_RO[cpu]->OffLine, OS) == 0)
{
PerCore_Update(Ref->Shm,Ref->Proc_RO,Ref->Core_RO, cpu);
}
}
if (fRESET == 1)
{
Pkg_ResetSensorLimits(&Shm->Proc);
}
Technology_Update(Shm, Proc, Proc_RW);
if (ServerFollowService(&localService,
&Shm->Proc.Service,
tid) == 0)
{
SProc = &Shm->Cpu[Shm->Proc.Service.Core].FlipFlop[ \
!Shm->Cpu[Shm->Proc.Service.Core].Toggle ];
}
if (Quiet & 0x100) {
printf("\t%s || %s\n",
BITVAL(PendingSync, NTFY0)?"NTFY":"....",
BITVAL(PendingSync, COMP0)?"COMP":"....");
}
}
/* All aggregations done: Notify Clients. */
BITWISESET(LOCKLESS, PendingSync, BIT_MASK_SYNC);
BITWISESET(LOCKLESS, Shm->Proc.Sync, PendingSync);
BITWISECLR(LOCKLESS, PendingSync);
}
/* Reset the Room mask */
BITSTOR_CC(BUS_LOCK, roomCore, roomSeed);
UBENCH_RDCOUNTER(2);
UBENCH_COMPUTE();
Print_uBenchmark((Quiet & 0x100));
}
for (cpu = 0; cpu < Shm->Proc.CPU.Count; cpu++) {
if (Arg[cpu].TID) {
pthread_join(Arg[cpu].TID, NULL);
}
}
free(Arg);
} else {
REASON_SET(reason, RC_MEM_ERR, (errno == 0 ? ENOMEM : errno));
}
return (reason);
}
REASON_CODE Child_Manager(REF *Ref)
{
SHM_STRUCT *Shm = Ref->Shm;
SERVICE_PROC localService = {.Proc = -1};
REASON_INIT(reason);
unsigned int cpu = 0;
pthread_t tid = pthread_self();
if (ServerFollowService(&localService, &Shm->Proc.Service, tid) == 0) {
pthread_setname_np(tid, "corefreqd-cmgr");
}
ARG *Arg = calloc(Shm->Proc.CPU.Count, sizeof(ARG));
if (Arg != NULL)
{
do {
for (cpu=0; !BITVAL(Shutdown, SYNC)&&(cpu < Shm->Proc.CPU.Count);cpu++)
{
if (BITVAL(Shm->Cpu[cpu].OffLine, OS) == 1) {
if (Arg[cpu].TID) {
/* Remove this child thread. */
pthread_join(Arg[cpu].TID, NULL);
Arg[cpu].TID = 0;
}
} else {
if (!Arg[cpu].TID) {
/* Add this child thread. */
Arg[cpu].Ref = Ref;
Arg[cpu].Bind = cpu;
pthread_create( &Arg[cpu].TID,
NULL,
Child_Thread,
&Arg[cpu]);
}
}
}
ServerFollowService(&localService, &Shm->Proc.Service, tid);
nanosleep(&Shm->Sleep.childWaiting, NULL);
}
while (!BITVAL(Shutdown, SYNC)) ;
for (cpu = 0; cpu < Shm->Proc.CPU.Count; cpu++) {
if (Arg[cpu].TID) {
pthread_join(Arg[cpu].TID, NULL);
}
}
free(Arg);
} else {
REASON_SET(reason, RC_MEM_ERR, (errno == 0 ? ENOMEM : errno));
}
return (reason);
}
REASON_CODE Shm_Manager(FD *fd, PROC_RO *Proc_RO, PROC_RW *Proc_RW,
uid_t uid, uid_t gid, mode_t cmask)
{
unsigned int cpu = 0;
CORE_RO **Core_RO;
CORE_RW **Core_RW;
SHM_STRUCT *Shm = NULL;
const size_t Core_RO_Size = ROUND_TO_PAGES(sizeof(CORE_RO)),
Core_RW_Size = ROUND_TO_PAGES(sizeof(CORE_RW));
REASON_INIT(reason);
if ((Core_RO = calloc(Proc_RO->CPU.Count, sizeof(Core_RO))) == NULL) {
REASON_SET(reason, RC_MEM_ERR, (errno == 0 ? ENOMEM : errno));
}
if ((Core_RW = calloc(Proc_RO->CPU.Count, sizeof(Core_RW))) == NULL) {
REASON_SET(reason, RC_MEM_ERR, (errno == 0 ? ENOMEM : errno));
}
for(cpu = 0; (reason.rc == RC_SUCCESS) && (cpu < Proc_RO->CPU.Count); cpu++)
{
const off_t vm_ro_pgoff = (ID_RO_VMA_CORE + cpu) * PAGE_SIZE,
vm_rw_pgoff = (ID_RW_VMA_CORE + cpu) * PAGE_SIZE;
if ((Core_RO[cpu] = mmap(NULL, Core_RO_Size,
PROT_READ,
MAP_SHARED,
fd->Drv, vm_ro_pgoff)) == MAP_FAILED)
{
REASON_SET(reason, RC_SHM_MMAP);
}
if ((Core_RW[cpu] = mmap(NULL, Core_RW_Size,
PROT_READ|PROT_WRITE,
MAP_SHARED,
fd->Drv, vm_rw_pgoff)) == MAP_FAILED)
{
REASON_SET(reason, RC_SHM_MMAP);
}
}
if (reason.rc == RC_SUCCESS) {
if (gid != 0) {
if (setregid(-1, gid) != 0) {
REASON_SET(reason, RC_SYS_CALL);
}
}
}
if (reason.rc == RC_SUCCESS) {
if (uid != 0) {
if (setreuid(-1, uid) != 0) {
REASON_SET(reason, RC_SYS_CALL);
}
}
}
if (reason.rc == RC_SUCCESS) {
umask(cmask);
}
if (reason.rc == RC_SUCCESS)
{ /* Initialize shared memory. */
const size_t ShmCpuSize = sizeof(CPU_STRUCT) * Proc_RO->CPU.Count,
ShmSize = ROUND_TO_PAGES((sizeof(SHM_STRUCT)
+ ShmCpuSize));
if ((fd->Svr = shm_open(SHM_FILENAME, O_CREAT|O_TRUNC|O_RDWR,
S_IRUSR|S_IWUSR
|S_IRGRP|S_IWGRP
|S_IROTH|S_IWOTH)) != -1)
{
pid_t CPID = -1;
if (ftruncate(fd->Svr, ShmSize) != -1)
{
if ((Shm = mmap(NULL, ShmSize,
PROT_READ|PROT_WRITE, MAP_SHARED,
fd->Svr, 0)) != MAP_FAILED)
{
__typeof__ (errno) fork_err = 0;
/* Clear SHM */
memset(Shm, 0, ShmSize);
/* Store version footprint into SHM */
SET_FOOTPRINT(Shm->FootPrint, MAX_FREQ_HZ,
CORE_COUNT,
TASK_ORDER,
COREFREQ_MAJOR,
COREFREQ_MINOR,
COREFREQ_REV );
/* Reference time the Server is starting at. */
time(&Shm->StartedAt);
/* Store the daemon gate name. */
StrCopy(Shm->ShmName, SHM_FILENAME, TASK_COMM_LEN);
/* Initialize the busy wait times. */
Shm->Sleep.ringWaiting = TIMESPEC(SIG_RING_MS);
Shm->Sleep.childWaiting = TIMESPEC(CHILD_PS_MS);
Shm->Sleep.sliceWaiting = TIMESPEC(CHILD_TH_MS);
REF Ref = {
.CPID = -1,
.KID = 0,
.Started = 0,
.Slice.Func = NULL,
.Slice.arg = 0,
.fd = fd,
.Shm = Shm,
.Proc_RO = Proc_RO,
.Proc_RW = Proc_RW,
.Core_RO = Core_RO,
.Core_RW = Core_RW,
.SysGate = NULL
};
sigemptyset(&Ref.Signal);
Package_Update(Shm, Proc_RO, Proc_RW);
Uncore_Update(Shm, Proc_RO, Core_RO[Proc_RO->Service.Core]);
memcpy(&Shm->SMB, &Proc_RO->SMB, sizeof(SMBIOS_ST));
/* Initialize notifications. */
BITCLR(LOCKLESS, Shm->Proc.Sync, SYNC0);
BITCLR(LOCKLESS, Shm->Proc.Sync, SYNC1);
SysGate_Toggle(&Ref, SysGateStartUp);
/* Welcomes with brand and per CPU base clock. */
if (Quiet & 0x001) {
printf( "CoreFreq Daemon %s" \
" Copyright (C) 2015-2021 CYRIL INGENIERIE\n",
COREFREQ_VERSION );
}
if (Quiet & 0x010) {
printf( "\n" \
" Processor [%s]\n" \
" Architecture [%s] %u/%u CPU Online.\n",
Shm->Proc.Brand,
Shm->Proc.Architecture,
Shm->Proc.CPU.OnLine,
Shm->Proc.CPU.Count );
}
if (Quiet & 0x100) {
printf( " SleepInterval(%u), SysGate(%u), %ld tasks\n\n",
Shm->Sleep.Interval,
!BITVAL(Shm->SysGate.Operation, 0) ?
0:Shm->Sleep.Interval * Shm->SysGate.tickReset,
TASK_LIMIT );
}
if (Quiet) {
fflush(stdout);
}
CPID = Ref.CPID = fork();
/*-----[ Resources inherited ]----------------------------------*/
fork_err = errno;
Emergency_Command(&Ref, 1);
switch (Ref.CPID) {
case 0:
reason = Child_Manager(&Ref);
break;
case -1:
REASON_SET(reason, RC_EXEC_ERR, fork_err);
break;
default:
reason = Core_Manager(&Ref);
if (gid != 0) {
if (setregid(-1, 0) != 0) {
REASON_SET(reason, RC_SYS_CALL);
}
}
if (uid != 0) {
if (setreuid(-1, 0) != 0) {
REASON_SET(reason, RC_SYS_CALL);
}
}
if (Shm->App.Cli) {
if (kill(Shm->App.Cli, SIGTERM) == -1) {
REASON_SET(reason, RC_EXEC_ERR);
}
}
if (Shm->App.GUI) {
if (kill(Shm->App.GUI, SIGTERM) == -1) {
REASON_SET(reason, RC_EXEC_ERR);
}
}
SysGate_OnDemand(&Ref, 0);
if (kill(Ref.CPID, SIGQUIT) == 0) {
if (waitpid(Ref.CPID, NULL, 0) == -1) {
REASON_SET(reason, RC_EXEC_ERR);
}
} else {
REASON_SET(reason, RC_EXEC_ERR);
}
break;
}
Emergency_Command(&Ref, 0);
if (munmap(Shm, ShmSize) == -1) {
REASON_SET(reason, RC_SHM_MMAP);
}
} else {
REASON_SET(reason, RC_SHM_MMAP);
}
} else {
REASON_SET(reason, RC_SHM_FILE);
}
if (close(fd->Svr) == -1) {
REASON_SET(reason, RC_SHM_FILE);
}
if (CPID != 0) {
if (shm_unlink(SHM_FILENAME) == -1) {
REASON_SET(reason, RC_SHM_FILE);
}
}
} else {
REASON_SET(reason, RC_SHM_FILE);
}
}
for (cpu = 0; cpu < Proc_RO->CPU.Count; cpu++)
{
if (Core_RO[cpu] != NULL) {
if (munmap(Core_RO[cpu], Core_RO_Size) == -1) {
REASON_SET(reason, RC_SHM_MMAP);
}
}
if (Core_RW[cpu] != NULL) {
if (munmap(Core_RW[cpu], Core_RW_Size) == -1) {
REASON_SET(reason, RC_SHM_MMAP);
}
}
}
if (Core_RO != NULL) {
free(Core_RO);
}
if (Core_RW != NULL) {
free(Core_RW);
}
return (reason);
}
REASON_CODE Help(REASON_CODE reason, ...)
{
va_list ap;
va_start(ap, reason);
switch (reason.rc) {
case RC_SUCCESS:
case RC_OK_SYSGATE:
case RC_OK_COMPUTE:
case RC_DRIVER_BASE ... RC_DRIVER_LAST:
break;
case RC_CMD_SYNTAX: {
char *appName = va_arg(ap, char *);
printf( "Usage:\t%s [-option <arguments>]\n" \
"\t-q\t\tQuiet\n" \
"\t-i\t\tInfo\n" \
"\t-d\t\tDebug\n" \
"\t-gon\t\tEnable SysGate\n" \
"\t-goff\t\tDisable SysGate\n" \
"\t-U <decimal>\tSet the effective user ID\n" \
"\t-G <decimal>\tSet the effective group ID\n" \
"\t-M <octal>\tSet the mode creation mask\n" \
"\t-h\t\tPrint out this message\n" \
"\t-v\t\tPrint the version number\n" \
"\nExit status:\n" \
"\t%u\tSUCCESS\t\tSuccessful execution\n" \
"\t%u\tCMD_SYNTAX\tCommand syntax error\n" \
"\t%u\tSHM_FILE\tShared memory file error\n" \
"\t%u\tSHM_MMAP\tShared memory mapping error\n" \
"\t%u\tPERM_ERR\tExecution not permitted\n" \
"\t%u\tMEM_ERR\t\tMemory operation error\n" \
"\t%u\tEXEC_ERR\tGeneral execution error\n" \
"\t%u\tSYS_CALL\tSystem call error\n" \
"\nReport bugs to labs[at]cyring.fr\n", appName,
RC_SUCCESS,
RC_CMD_SYNTAX,
RC_SHM_FILE,
RC_SHM_MMAP,
RC_PERM_ERR,
RC_MEM_ERR,
RC_EXEC_ERR,
RC_SYS_CALL);
}
break;
case RC_PERM_ERR:
case RC_MEM_ERR:
case RC_EXEC_ERR: {
char *appName = va_arg(ap, char *);
char *sysMsg = strerror(reason.no);
fprintf(stderr, "%s execution error code %d\n%s @ line %d\n",
appName, reason.no, sysMsg, reason.ln);
}
break;
case RC_SHM_FILE:
case RC_SHM_MMAP: {
char *shmFileName = va_arg(ap, char *);
char *sysMsg = strerror(reason.no);
fprintf(stderr , "Driver connection error code %d\n" \
"%s: '%s' @ line %d\n",
reason.no, shmFileName, sysMsg, reason.ln);
}
break;
case RC_SYS_CALL: {
char *sysMsg = strerror(reason.no);
fprintf(stderr, "System error code %d\n%s @ line %d\n",
reason.no, sysMsg, reason.ln);
}
break;
}
va_end(ap);
return (reason);
}
int main(int argc, char *argv[])
{
FD fd = {0, 0};
PROC_RO *Proc = NULL; /* Kernel module anchor points. */
PROC_RW *Proc_RW = NULL;
uid_t uid = 0, gid = 0;
mode_t cmask = !S_IRUSR|!S_IWUSR|!S_IRGRP|!S_IWGRP|!S_IROTH|!S_IWOTH;
char *program = strdup(argv[0]),
*appName = program != NULL ? basename(program) : argv[0];
REASON_INIT(reason);
int i;
for (i = 1; i < argc; i++)
{
if (strlen(argv[i]) > 1) {
if (argv[i][0] == '-')
{
char option = argv[i][1];
switch (option) {
case 'q':
Quiet = 0x000;
break;
case 'i':
Quiet = 0x011;
break;
case 'd':
Quiet = 0x111;
break;
case 'g':
if (argv[i][2]=='o'
&& argv[i][3]=='f'
&& argv[i][4]=='f') {
SysGateStartUp = 0;
} else if ( argv[i][2]=='o'
&& argv[i][3]=='n') {
SysGateStartUp = 1;
} else {
REASON_SET(reason, RC_CMD_SYNTAX, 0);
reason = Help(reason, appName);
}
break;
case 'v':
printf("%s\n", COREFREQ_VERSION);
reason.rc = RC_CMD_SYNTAX;
break;
case 'U': {
char trailing = '\0';
if (argv[++i] == NULL) {
REASON_SET(reason, RC_CMD_SYNTAX, 0);
reason = Help(reason, appName);
} else if (sscanf(argv[i], "%d%c",
&uid,
&trailing) != 1) {
REASON_SET(reason, RC_CMD_SYNTAX);
reason = Help(reason, appName);
}
}
break;
case 'G': {
char trailing = '\0';
if (argv[++i] == NULL) {
REASON_SET(reason, RC_CMD_SYNTAX, 0);
reason = Help(reason, appName);
} else if (sscanf(argv[i], "%d%c",
&gid,
&trailing) != 1) {
REASON_SET(reason, RC_CMD_SYNTAX);
reason = Help(reason, appName);
}
}
break;
case 'M': {
char trailing = '\0';
if (argv[++i] == NULL) {
REASON_SET(reason, RC_CMD_SYNTAX, 0);
reason = Help(reason, appName);
} else if (sscanf(argv[i] , "%o%c",
&cmask,
&trailing) != 1) {
REASON_SET(reason, RC_CMD_SYNTAX);
reason = Help(reason, appName);
}
}
break;
case 'h':
default: {
REASON_SET(reason, RC_CMD_SYNTAX, 0);
reason = Help(reason, appName);
}
break;
}
} else {
REASON_SET(reason, RC_CMD_SYNTAX, 0);
reason = Help(reason, appName);
}
} else {
REASON_SET(reason, RC_CMD_SYNTAX, 0);
reason = Help(reason, appName);
}
}
if (reason.rc == RC_SUCCESS)
{
if (geteuid() == 0)
{
if ((fd.Drv = open(DRV_FILENAME, O_RDWR|O_SYNC)) != -1)
{
const size_t packageSize[] = {
ROUND_TO_PAGES(sizeof(PROC_RO)),
ROUND_TO_PAGES(sizeof(PROC_RW))
};
const off_t vm_pgoff[] = {
ID_RO_VMA_PROC * PAGE_SIZE,
ID_RW_VMA_PROC * PAGE_SIZE
};
if ((Proc = mmap(NULL, packageSize[0],
PROT_READ, MAP_SHARED,
fd.Drv, vm_pgoff[0])) != MAP_FAILED)
{
if ((Proc_RW = mmap(NULL, packageSize[1],
PROT_READ|PROT_WRITE, MAP_SHARED,
fd.Drv, vm_pgoff[1])) != MAP_FAILED)
{
if (CHK_FOOTPRINT(Proc->FootPrint, MAX_FREQ_HZ,
CORE_COUNT,
TASK_ORDER,
COREFREQ_MAJOR,
COREFREQ_MINOR,
COREFREQ_REV) )
{
reason=Shm_Manager(&fd, Proc, Proc_RW, uid, gid, cmask);
switch (reason.rc) {
case RC_SUCCESS:
case RC_OK_SYSGATE:
case RC_OK_COMPUTE:
case RC_DRIVER_BASE ... RC_DRIVER_LAST:
break;
case RC_CMD_SYNTAX:
case RC_PERM_ERR:
break;
case RC_SHM_FILE:
case RC_SHM_MMAP:
reason = Help(reason, SHM_FILENAME);
break;
case RC_MEM_ERR:
case RC_EXEC_ERR:
reason = Help(reason, appName);
break;
case RC_SYS_CALL:
reason = Help(reason);
break;
}
} else {
char *wrongVersion = malloc(10+5+5+5+1);
REASON_SET(reason, RC_SHM_MMAP, EACCES);
if (wrongVersion != NULL) {
snprintf(wrongVersion, 10+5+5+5+1,
"Version %hu.%hu.%hu",
Proc->FootPrint.major,
Proc->FootPrint.minor,
Proc->FootPrint.rev);
reason = Help(reason, wrongVersion);
free(wrongVersion);
}
}
if (munmap(Proc_RW, packageSize[1]) == -1) {
REASON_SET(reason, RC_SHM_MMAP);
reason = Help(reason, DRV_FILENAME);
}
}
if (munmap(Proc, packageSize[0]) == -1) {
REASON_SET(reason, RC_SHM_MMAP);
reason = Help(reason, DRV_FILENAME);
}
} else {
REASON_SET(reason, RC_SHM_MMAP);
reason = Help(reason, DRV_FILENAME);
}
if (close(fd.Drv) == -1) {
REASON_SET(reason, RC_SHM_FILE);
reason = Help(reason, DRV_FILENAME);
}
} else {
REASON_SET(reason, RC_SHM_FILE);
reason = Help(reason, DRV_FILENAME);
}
} else {
REASON_SET(reason, RC_PERM_ERR, EACCES);
reason = Help(reason, appName);
}
}
if (program != NULL) {
free(program);
}
return (reason.rc);
}
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