Skip to content

Instantly share code, notes, and snippets.

@svmlegacy

svmlegacy/02.EC5509-20210627-s

Last active June 27, 2021 14:53
Show Gist options

  • Select an option

    Learn more about clone URLs
  • Save svmlegacy/4e6dce1579e820e967284b1288875df7 to your computer and use it in GitHub Desktop.

Select an option

Learn more about clone URLs
Save svmlegacy/4e6dce1579e820e967284b1288875df7 to your computer and use it in GitHub Desktop.
Download ZIP
2x EC5509 Corefreq Test 20210627
Raw
02.EC5509-20210627-s
Processor [Intel(R) Xeon(R) CPU C5509 @ 2.00GHz]
|- Architecture [Nehalem/Lynnfield]
|- Vendor ID [GenuineIntel]
|- Microcode [0xffff0002]
|- Signature [ 06_1E]
|- Stepping [ 4]
|- Online CPU [ 8/ 8]
|- Base Clock [133.000]
|- Frequency (MHz) Ratio
Min 798.00 < 6 >
Max 1995.00 < 15 >
|- Factory [133.333]
2000 [ 15 ]
|- Performance
|- P-State
TGT 1197.00 < 9 >
|- Turbo Boost [ LOCK]
1C 1995.00 < 15 >
2C 1995.00 < 15 >
3C 1995.00 < 15 >
4C 1995.00 < 15 >
|- Uncore [ LOCK]
Min 1596.00 [ 12 ]
Max 1596.00 [ 12 ]
|- TDP Level [ 0:0 ]
|- Programmable [ LOCK]
|- Configuration [ LOCK]
|- Turbo Activation [ LOCK]
Turbo AUTO [ 0 ]
Instruction Set Extensions
|- 3DNow!/Ext [N/N] ADX [N] AES [N] AVX/AVX2 [N/N]
|- AVX512-F [N] AVX512-DQ [N] AVX512-IFMA [N] AVX512-PF [N]
|- AVX512-ER [N] AVX512-CD [N] AVX512-BW [N] AVX512-VL [N]
|- AVX512-VBMI [N] AVX512-VBMI2 [N] AVX512-VNMI [N] AVX512-ALG [N]
|- AVX512-VPOP [N] AVX512-VNNIW [N] AVX512-FMAPS [N] AVX512-VP2I [N]
|- AVX512-BF16 [N] BMI1/BMI2 [N/N] CLWB [N] CLFLUSH/O [Y/N]
|- CLAC-STAC [N] CMOV [Y] CMPXCHG8B [Y] CMPXCHG16B [Y]
|- F16C [N] FPU [Y] FXSR [Y] LAHF-SAHF [Y]
|- MMX/Ext [Y/N] MON/MWAITX [Y/N] MOVBE [N] PCLMULQDQ [N]
|- POPCNT [Y] RDRAND [N] RDSEED [N] RDTSCP [Y]
|- SEP [Y] SHA [N] SSE [Y] SSE2 [Y]
|- SSE3 [Y] SSSE3 [Y] SSE4.1/4A [Y/N] SSE4.2 [Y]
|- SERIALIZE [N] SYSCALL [Y] SGX [N] RDPID [N]
Features
|- 1 GB Pages Support 1GB-PAGES [Missing]
|- Advanced Configuration & Power Interface ACPI [Capable]
|- Advanced Programmable Interrupt Controller APIC [Capable]
|- Core Multi-Processing CMP Legacy [Missing]
|- L1 Data Cache Context ID CNXT-ID [Missing]
|- Direct Cache Access DCA [Capable]
|- Debugging Extension DE [Capable]
|- Debug Store & Precise Event Based Sampling DS, PEBS [Capable]
|- CPL Qualified Debug Store DS-CPL [Capable]
|- 64-Bit Debug Store DTES64 [Capable]
|- Fast-String Operation Fast-Strings [Missing]
|- Fused Multiply Add FMA | FMA4 [Missing]
|- Hardware Lock Elision HLE [Missing]
|- Instruction Based Sampling IBS [Missing]
|- Long Mode 64 bits IA64 | LM [Capable]
|- LightWeight Profiling LWP [Missing]
|- Machine-Check Architecture MCA [Capable]
|- Memory Protection Extensions MPX [Missing]
|- Model Specific Registers MSR [Capable]
|- Memory Type Range Registers MTRR [Capable]
|- OS-Enabled Ext. State Management OSXSAVE [Missing]
|- Physical Address Extension PAE [Capable]
|- Page Attribute Table PAT [Capable]
|- Pending Break Enable PBE [Capable]
|- Process Context Identifiers PCID [Missing]
|- Perfmon and Debug Capability PDCM [Capable]
|- Page Global Enable PGE [Capable]
|- Page Size Extension PSE [Capable]
|- 36-bit Page Size Extension PSE36 [Capable]
|- Processor Serial Number PSN [Missing]
|- Resource Director Technology/PQE RDT-A [Missing]
|- Resource Director Technology/PQM RDT-M [Missing]
|- Restricted Transactional Memory RTM [Missing]
|- Safer Mode Extensions SMX [Missing]
|- Self-Snoop SS [Capable]
|- Supervisor-Mode Access Prevention SMAP [Missing]
|- Supervisor-Mode Execution Prevention SMEP [Missing]
|- Time Stamp Counter TSC [Invariant]
|- Time Stamp Counter Deadline TSC-DEADLINE [Missing]
|- TSX Force Abort MSR Register TSX-ABORT [Missing]
|- TSX Suspend Load Address Tracking TSX-LDTRK [Missing]
|- User-Mode Instruction Prevention UMIP [Missing]
|- Virtual Mode Extension VME [Capable]
|- Virtual Machine Extensions VMX [Capable]
|- Extended xAPIC Support x2APIC [Missing]
|- Execution Disable Bit Support XD-Bit [Capable]
|- XSAVE/XSTOR States XSAVE [Missing]
|- xTPR Update Control xTPR [Capable]
Mitigation mechanisms
|- Indirect Branch Restricted Speculation IBRS [Missing]
|- Indirect Branch Prediction Barrier IBPB [Missing]
|- Single Thread Indirect Branch Predictor STIBP [Missing]
|- Speculative Store Bypass Disable SSBD [Missing]
|- Writeback & invalidate the L1 data cache L1D-FLUSH [Missing]
|- Hypervisor - No flush L1D on VM entry L1DFL_VMENTRY_NO [Missing]
|- Architectural - Buffer Overwriting MD-CLEAR [Missing]
|- Architectural - Rogue Data Cache Load RDCL_NO [Missing]
|- Architectural - Enhanced IBRS IBRS_ALL [Missing]
|- Architectural - Return Stack Buffer Alternate RSBA [Missing]
|- Architectural - Speculative Store Bypass SSB_NO [Missing]
|- Architectural - Microarchitectural Data Sampling MDS_NO [Missing]
|- Architectural - TSX Asynchronous Abort TAA_NO [Missing]
|- Architectural - Page Size Change MCE PSCHANGE_MC_NO [Missing]
|- Architectural - Split Locked Access Exception SPLA [Missing]
Technologies
|- Data Cache Unit
|- L1 Prefetcher L1 HW < ON>
|- L1 IP Prefetcher L1 HW IP < ON>
|- L2 Prefetcher L2 HW < ON>
|- L2 Line Prefetcher L2 HW CL < ON>
|- System Management Mode SMM-Dual [ ON]
|- Hyper-Threading HTT [OFF]
|- SpeedStep EIST < ON>
|- Dynamic Acceleration IDA [OFF]
|- Turbo Boost TURBO <OFF>
|- Energy Efficiency Optimization EEO <OFF>
|- Race To Halt Optimization R2H <OFF>
|- Watchdog Timer TCO < ON>
|- Virtualization VMX [ ON]
|- I/O MMU VT-d [ ON]
|- Version [ 1.0]
|- Hypervisor [OFF]
|- Vendor ID [ N/A]
Performance Monitoring
|- Version PM [ 3]
|- Counters: General Fixed
| 4 x 48 bits 3 x 48 bits
|- Enhanced Halt State C1E <OFF>
|- C1 Auto Demotion C1A <OFF>
|- C3 Auto Demotion C3A <OFF>
|- C1 UnDemotion C1U <OFF>
|- C3 UnDemotion C3U <OFF>
|- C6 Core Demotion CC6 <OFF>
|- C6 Module Demotion MC6 <OFF>
|- Legacy Frequency ID control FID [OFF]
|- Legacy Voltage ID control VID [OFF]
|- P-State Hardware Coordination Feedback MPERF/APERF [ ON]
|- Hardware-Controlled Performance States HWP [OFF]
|- Hardware Duty Cycling HDC [OFF]
|- Package C-States
|- Configuration Control CONFIG [ LOCK]
|- Lowest C-State LIMIT < UNS>
|- I/O MWAIT Redirection IOMWAIT < Enable>
|- Max C-State Inclusion RANGE < C6>
|- Core C-States
|- C-States Base Address BAR [ 0x414 ]
|- MONITOR/MWAIT
|- State index: #0 #1 #2 #3 #4 #5 #6 #7
|- Sub C-State: 0 2 1 1 0 0 0 0
|- Core Cycles [Capable]
|- Instructions Retired [Capable]
|- Reference Cycles [Missing]
|- Last Level Cache References [Capable]
|- Last Level Cache Misses [Capable]
|- Branch Instructions Retired [Capable]
|- Branch Mispredicts Retired [Missing]
Power, Current & Thermal
|- Clock Modulation ODCM <Disable>
|- DutyCycle [ 0.00%]
|- Power Management PWR MGMT [ LOCK]
|- Energy Policy Bias Hint [ 0]
|- Energy Policy HWP EPP [ 0]
|- Junction Temperature TjMax [ 0: 91C]
|- Digital Thermal Sensor DTS [Capable]
|- Power Limit Notification PLN [Missing]
|- Package Thermal Management PTM [Missing]
|- Thermal Monitor 1 TM1 [ Enable]
|- Thermal Monitor 2 TM2 [Capable]
|- Thermal Design Power TDP [Missing]
|- Minimum Power Min [Missing]
|- Maximum Power Max [Missing]
|- Thermal Design Power Package [Disable]
|- Power Limit ( 0 sec) PL1 [ 85 W]
|- Power Limit PL2 [Missing]
|- Thermal Design Power Core [Disable]
|- Power Limit PL1 [Missing]
|- Thermal Design Power Uncore [Disable]
|- Power Limit PL1 [Missing]
|- Thermal Design Power DRAM [Disable]
|- Power Limit PL1 [Missing]
|- Thermal Design Power Platform [Disable]
|- Power Limit PL1 [Missing]
|- Power Limit PL2 [Missing]
|- Electrical Design Current EDC [Missing]
|- Thermal Design Current TDC [ 85 A]
|- Units
|- Power watt [ 0.125000000]
|- Energy joule [ Missing]
|- Window second [ 0.000976562]
Raw
03.EC5509-20210627-M
P55/Ibex Peak [2CD8]
Controller #0
Bus Rate 2500 MT/s Bus Speed 2493 MT/s DRAM Speed 1063 MHz
Cha CL RCD RP RAS RRD RFC WR RTPr WTPr FAW B2B CWL CMD REFI
ddWR drWR srWR ddRW drRW srRW ddRR drRR srRR ddWW drWW srWW CKE ECC
Controller #1 Triple Channel
Bus Rate 2500 MT/s Bus Speed 2493 MT/s DRAM Speed 1063 MHz
Cha CL RCD RP RAS RRD RFC WR RTPr WTPr FAW B2B CWL CMD REFI
#0 7 7 7 20 4 59 8 6 19 20 0 6 1T 509
#1 7 7 7 20 4 59 8 6 19 20 0 6 1T 509
#2 7 7 7 20 4 59 8 6 19 20 0 6 1T 509
ddWR drWR srWR ddRW drRW srRW ddRR drRR srRR ddWW drWW srWW CKE ECC
#0 6 6 14 9 9 9 7 6 4 7 7 4 3 1
#1 6 6 14 9 9 9 7 6 4 7 7 4 3 1
#2 6 6 14 9 9 9 7 6 4 7 7 4 3 1
DIMM Geometry for channel #0
Slot Bank Rank Rows Columns Memory Size (MB)
#0 8 1 16384 1024 1024
DIMM Geometry for channel #1
Slot Bank Rank Rows Columns Memory Size (MB)
#0 8 1 16384 1024 1024
DIMM Geometry for channel #2
Slot Bank Rank Rows Columns Memory Size (MB)
#0 8 1 16384 1024 1024
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment