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svmlegacy/L16G7 corefreq-cli -s

Created November 12, 2021 00:08
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L16G7 corefreq-cli -s
Processor [Intel(R) Core(TM) i5-L16G7 CPU @ 1.40GHz]
|- Architecture [Tremont/Lakefield]
|- Vendor ID [GenuineIntel]
|- Microcode [0x00000027]
|- Signature [ 06_8A]
|- Stepping [ 1]
|- Online CPU [ 5/ 5]
|- Base Clock [ 98.734]
|- Frequency (MHz) Ratio
Min 789.75 < 8 >
Max 1382.07 < 14 >
|- Factory [100.000]
1400 [ 14 ]
|- Performance
|- P-State
TGT 789.75 < 8 >
|- HWP
Min 789.75 < 8 >
Max 2764.14 < 28 >
TGT AUTO < 0 >
|- Turbo Boost [ UNLOCK]
1C 2961.58 < 30 >
2C 2369.26 < 24 >
3C 2171.83 < 22 >
4C 1974.39 < 20 >
5C 1776.95 < 18 >
|- Uncore [ UNLOCK]
Min 789.75 < 8 >
Max 1974.39 < 20 >
|- TDP Level [ 0:0 ]
|- Programmable [ UNLOCK]
|- Configuration [ LOCK]
|- Turbo Activation [ UNLOCK]
Nominal 1382.07 [ 14 ]
Turbo AUTO < 0 >
Instruction Set Extensions
|- 3DNow!/Ext [N/N] ADX [N] AES [Y] AVX/AVX2 [N/N]
|- AVX512-F [N] AVX512-DQ [N] AVX512-IFMA [N] AVX512-PF [N]
|- AVX512-ER [N] AVX512-CD [N] AVX512-BW [N] AVX512-VL [N]
|- AVX512-VBMI [N] AVX512-VBMI2 [N] AVX512-VNMI [N] AVX512-ALG [N]
|- AVX512-VPOP [N] AVX512-VNNIW [N] AVX512-FMAPS [N] AVX512-VP2I [N]
|- AVX512-BF16 [N] BMI1/BMI2 [N/N] CLWB [Y] CLFLUSH/O [Y/Y]
|- CLAC-STAC [Y] CMOV [Y] CMPXCHG8B [Y] CMPXCHG16B [Y]
|- F16C [N] FPU [Y] FXSR [Y] LAHF-SAHF [Y]
|- MMX/Ext [Y/N] MON/MWAITX [Y/N] MOVBE [Y] PCLMULQDQ [Y]
|- POPCNT [Y] RDRAND [Y] RDSEED [Y] RDTSCP [Y]
|- SEP [Y] SHA [Y] SSE [Y] SSE2 [Y]
|- SSE3 [Y] SSSE3 [Y] SSE4.1/4A [Y/N] SSE4.2 [Y]
|- SERIALIZE [N] SYSCALL [Y] SGX [N] RDPID [Y]
Features
|- 1 GB Pages Support 1GB-PAGES [Missing]
|- Advanced Configuration & Power Interface ACPI [Capable]
|- Advanced Programmable Interrupt Controller APIC [Capable]
|- Core Multi-Processing CMP Legacy [Missing]
|- L1 Data Cache Context ID CNXT-ID [Missing]
|- Direct Cache Access DCA [Missing]
|- Debugging Extension DE [Capable]
|- Debug Store & Precise Event Based Sampling DS, PEBS [Capable]
|- CPL Qualified Debug Store DS-CPL [Capable]
|- 64-Bit Debug Store DTES64 [Capable]
|- Fast-String Operation Fast-Strings [Capable]
|- Fused Multiply Add FMA | FMA4 [Missing]
|- Hardware Lock Elision HLE [Missing]
|- Instruction Based Sampling IBS [Missing]
|- Long Mode 64 bits IA64 | LM [Capable]
|- LightWeight Profiling LWP [Missing]
|- Machine-Check Architecture MCA [Capable]
|- Memory Protection Extensions MPX [Missing]
|- Model Specific Registers MSR [Capable]
|- Memory Type Range Registers MTRR [Capable]
|- OS-Enabled Ext. State Management OSXSAVE [Capable]
|- Physical Address Extension PAE [Capable]
|- Page Attribute Table PAT [Capable]
|- Pending Break Enable PBE [Capable]
|- Process Context Identifiers PCID [Missing]
|- Perfmon and Debug Capability PDCM [Capable]
|- Page Global Enable PGE [Capable]
|- Page Size Extension PSE [Capable]
|- 36-bit Page Size Extension PSE36 [Capable]
|- Processor Serial Number PSN [Missing]
|- Resource Director Technology/PQE RDT-A [Missing]
|- Resource Director Technology/PQM RDT-M [Missing]
|- Restricted Transactional Memory RTM [Missing]
|- Safer Mode Extensions SMX [Missing]
|- Self-Snoop SS [Capable]
|- Supervisor-Mode Access Prevention SMAP [Capable]
|- Supervisor-Mode Execution Prevention SMEP [Capable]
|- Time Stamp Counter TSC [Invariant]
|- Time Stamp Counter Deadline TSC-DEADLINE [Capable]
|- TSX Force Abort MSR Register TSX-ABORT [Missing]
|- TSX Suspend Load Address Tracking TSX-LDTRK [Missing]
|- User-Mode Instruction Prevention UMIP [Capable]
|- Virtual Mode Extension VME [Capable]
|- Virtual Machine Extensions VMX [Capable]
|- Extended xAPIC Support x2APIC [Missing]
|- Execution Disable Bit Support XD-Bit [Capable]
|- XSAVE/XSTOR States XSAVE [Capable]
|- xTPR Update Control xTPR [Capable]
Mitigation mechanisms
|- Indirect Branch Restricted Speculation IBRS [ Enable]
|- Indirect Branch Prediction Barrier IBPB [Capable]
|- Single Thread Indirect Branch Predictor STIBP [Capable]
|- Speculative Store Bypass Disable SSBD [Capable]
|- Writeback & invalidate the L1 data cache L1D-FLUSH [Capable]
|- Hypervisor - No flush L1D on VM entry L1DFL_VMENTRY_NO [ Enable]
|- Architectural - Buffer Overwriting MD-CLEAR [Capable]
|- Architectural - Rogue Data Cache Load RDCL_NO [ Enable]
|- Architectural - Enhanced IBRS IBRS_ALL [ Enable]
|- Architectural - Return Stack Buffer Alternate RSBA [Capable]
|- Architectural - Speculative Store Bypass SSB_NO [Capable]
|- Architectural - Microarchitectural Data Sampling MDS_NO [ Enable]
|- Architectural - TSX Asynchronous Abort TAA_NO [Capable]
|- Architectural - Page Size Change MCE PSCHANGE_MC_NO [Capable]
|- Architectural - STLB QoS STLB [Missing]
|- Architectural - Functional Safety Island FuSa [Missing]
|- Architectural - RSM in CPL0 only RSM [Missing]
|- Architectural - Split Locked Access Exception SPLA [Missing]
|- Architectural - Snoop Filter QoS Mask SNOOP_FILTER [Missing]
Technologies
|- Data Cache Unit
|- L1 Prefetcher L1 HW < ON>
|- L1 IP Prefetcher L1 HW IP < ON>
|- L2 Prefetcher L2 HW < ON>
|- L2 Line Prefetcher L2 HW CL < ON>
|- System Management Mode SMM-Dual [ ON]
|- Hyper-Threading HTT [OFF]
|- SpeedStep EIST <OFF>
|- Dynamic Acceleration IDA [ ON]
|- Turbo Boost TURBO < ON>
|- Energy Efficiency Optimization EEO < ON>
|- Race To Halt Optimization R2H < ON>
|- Watchdog Timer TCO < ON>
|- Virtualization VMX [ ON]
|- I/O MMU VT-d [OFF]
|- Version [ N/A]
|- Hypervisor [OFF]
|- Vendor ID [ N/A]
Performance Monitoring
|- Version PM [ 5]
|- Counters: General Fixed
| 4 x 48 bits 3 x 48 bits
|- Enhanced Halt State C1E < ON>
|- C1 Auto Demotion C1A < ON>
|- C3 Auto Demotion C3A <OFF>
|- C1 UnDemotion C1U < ON>
|- C3 UnDemotion C3U <OFF>
|- C6 Core Demotion CC6 <OFF>
|- C6 Module Demotion MC6 <OFF>
|- Legacy Frequency ID control FID [OFF]
|- Legacy Voltage ID control VID [OFF]
|- P-State Hardware Coordination Feedback MPERF/APERF [ ON]
|- Hardware-Controlled Performance States HWP < ON>
|- Capabilities (MHz) Ratio
Lowest 98.73 [ 1 ]
Efficient 1184.81 [ 12 ]
Guaranteed 1974.68 [ 20 ]
Highest 4245.57 [ 43 ]
|- Hardware Duty Cycling HDC [OFF]
|- Package C-States
|- Configuration Control CONFIG [ LOCK]
|- Lowest C-State LIMIT < C0>
|- I/O MWAIT Redirection IOMWAIT <Disable>
|- Max C-State Inclusion RANGE < C8>
|- Core C-States
|- C-States Base Address BAR [ 0x1814]
|- MONITOR/MWAIT
|- State index: #0 #1 #2 #3 #4 #5 #6 #7
|- Sub C-State: 0 2 0 2 2 1 1 1
|- Core Cycles [Capable]
|- Instructions Retired [Capable]
|- Reference Cycles [Capable]
|- Last Level Cache References [Capable]
|- Last Level Cache Misses [Capable]
|- Branch Instructions Retired [Capable]
|- Branch Mispredicts Retired [Capable]
|- Top-down slots Counter [Capable]
Power, Current & Thermal
|- Clock Modulation ODCM <Disable>
|- DutyCycle [ 0.00%]
|- Power Management PWR MGMT [ LOCK]
|- Energy Policy Bias Hint [ 0]
|- Energy Policy HWP EPP < 128>
|- Junction Temperature TjMax [10:100C]
|- Digital Thermal Sensor DTS [Capable]
|- Power Limit Notification PLN [Capable]
|- Package Thermal Management PTM [Capable]
|- Thermal Monitor 1 TM1 [ Enable]
|- Thermal Monitor 2 TM2 [Capable]
|- Thermal Design Power TDP [ 7 W]
|- Minimum Power Min [Missing]
|- Maximum Power Max [Missing]
|- Thermal Design Power Package < Enable>
|- Power Limit (28 sec) PL1 < 7 W>
|- Power Limit (1 sec) PL2 < 9 W>
|- Thermal Design Power Core <Disable>
|- Power Limit PL1 [Missing]
|- Thermal Design Power Uncore <Disable>
|- Power Limit PL1 [Missing]
|- Thermal Design Power DRAM <Disable>
|- Power Limit PL1 [Missing]
|- Thermal Design Power Platform <Disable>
|- Power Limit PL1 [Missing]
|- Power Limit PL2 [Missing]
|- Electrical Design Current EDC [Missing]
|- Thermal Design Current TDC [Missing]
|- Units
|- Power watt [ 0.125000000]
|- Energy joule [ 0.000061035]
|- Window second [ 0.000976562]
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