Repro for yosys issue report. Run script simul.sh, adjust path of cells_sim.v inside.

dsp_debug_build.v

`define ICEBREAKER 1
`default_nettype none

module M_main (
out_leds,
out_result,
in_run,
out_done,
reset,
out_clock,
clock
);
output  [4:0] out_leds;
output  [7:0] out_result;
input in_run;
output out_done;
input reset;
output out_clock;
input clock;
assign out_clock = clock;
wire signed [15:0] _c_table[1:0];
assign _c_table[0] = 114;
assign _c_table[1] = 0;

reg  [7:0] _d_u;
reg  [7:0] _q_u;

reg  [15:0] _d_pos_u;
reg  [15:0] _q_pos_u;
reg  [9:0] _d_pix_x;
reg  [9:0] _q_pix_x;
reg  [15:0] _t_cur_inv_y;

reg  [7:0] _d_iter;
reg  [7:0] _q_iter;
reg  [4:0] _d_leds,_q_leds;
reg  [1:0] _d_index,_q_index;

assign out_leds = _q_leds;
assign out_result = _q_u;
assign out_done = (_q_index == 3);

always @(posedge clock) begin
  if (reset || !in_run) begin
_q_u <= 0;
_q_pos_u <= 1024;
_q_pix_x <= 0;
_q_iter <= 0;
  if (reset) begin
_q_index <= 0;
end else begin
_q_index <= 0;
end
  end else begin
_q_u <= _d_u;
_q_pos_u <= _d_pos_u;
_q_pix_x <= _d_pix_x;
_q_iter <= _d_iter;
_q_leds <= _d_leds;
_q_index <= _d_index;
  end
end




always @* begin
_d_u = _q_u;
_d_pos_u = _q_pos_u;
_d_pix_x = _q_pix_x;
_d_iter = _q_iter;
_d_leds = _q_leds;
_d_index = _q_index;
_t_cur_inv_y = 0;
// _always_pre
(* full_case *)
case (_q_index)
0: begin
// _top
// var inits
_d_u = 0;
_d_pos_u = 1024;
_t_cur_inv_y = 0;
_d_pix_x = 0;
_d_iter = 0;
// --
_d_index = 1;
end
1: begin
// __while__block_1
if (_q_iter==0) begin
// __block_2
// __block_4
_t_cur_inv_y = _c_table[_q_iter+0];
_d_u = _q_pos_u+((_q_pix_x-320)*_t_cur_inv_y)>>8;
_d_iter = _q_iter+1;
_d_pos_u = _q_pos_u+1024;
_d_pix_x = _q_pix_x+1;
// __block_5
_d_index = 1;
end else begin
_d_index = 2;
end
end
2: begin
// __block_3
$display("iter:%d u:%d",_q_iter,_q_u);
if (_q_u==117) begin
// __block_6
// __block_8
$display("OK");
_d_leds = 30;
// __block_9
end else begin
// __block_7
// __block_10
$display("FAILED");
_d_leds = 1;
// __block_11
end
// __block_12
_d_index = 3;
end
3: begin // end of main
end
default: begin 
_d_index = 3;
 end
endcase
// _always_post
end
endmodule

dsp_debug_tb.v

`define ICARUS 1

`timescale 1ns / 1ps

module top;

reg clk;
reg rst_n;

wire [7:0] __main_leds;
wire [7:0] __main_result;

initial begin
  clk = 1'b0;
  rst_n = 1'b0;
  $display("icarus framework started");
  $dumpfile("icarus.vcd");
  $dumpvars(0,top); // dump all (for full debugging)
  // generate a 25 MHz clock
  repeat(4) #20 clk = ~clk; 
  rst_n = 1'b1;
  forever #20 clk = ~clk;
end

reg ready = 0;
reg [3:0] RST_d;
reg [3:0] RST_q;

always @* begin
  RST_d = RST_q >> 1;
end

always @(posedge clk) begin
  if (ready) begin
    RST_q <= RST_d;
  end else begin
    ready <= 1;
    RST_q <= 4'b1111;
  end
end

wire run_main;
assign run_main = 1'b1;
wire done_main;

M_main __main(
  .clock(clk),
  .reset(RST_d[0]),
  .out_leds(__main_leds),
  .out_result(__main_result),
  .in_run(run_main),
  .out_done(done_main)
);

always @* begin
  if (done_main && !RST_d[0]) begin
    $display("result = %d (should be 117)",__main_result);
    $finish;
  end
end

endmodule

simul.sh

#!/bin/bash

rm test_post
rm build.json
rm build_syn.v

yosys -g -p "synth_ice40 -dsp -json build.json" dsp_debug_build.v

yosys -o build_syn.v build.json

iverilog -o test_post dsp_debug_tb.v build_syn.v ../share/ice40/cells_sim.v

vvp test_post