STM32F05x defines for controlling flash memory

stm32f05x-flash-control.diff

diff --git src/stlink-common.c src/stlink-common.c
index 08bd0bb..1e3c480 100644
--- src/stlink-common.c
+++ src/stlink-common.c
@@ -48,6 +48,38 @@
 #define FLASH_CR_STRT 6
 #define FLASH_CR_LOCK 7
 
+/**************************
+ Begin stm32f05x flash controller defines
+ RM0091 reference manual */
+#define STM32F0_FLASH_REGS_ADDR 0x40022000	//FLASH interface (Table 2)
+#define STM32F0_FLASH_REGS_SIZE 0x400		//FLASH interface size in hex (Table 2)
+
+	//These offsets found in Table 8
+#define STM32F0_FLASH_ACR (FLASH_REGS_ADDR + 0x00)
+#define STM32F0_FLASH_KEYR (FLASH_REGS_ADDR + 0x04)
+#define STM32F0_FLASH_SR (FLASH_REGS_ADDR + 0x0c)
+#define STM32F0_FLASH_CR (FLASH_REGS_ADDR + 0x10)
+#define STM32F0_FLASH_AR (FLASH_REGS_ADDR + 0x14)
+#define STM32F0_FLASH_OBR (FLASH_REGS_ADDR + 0x1c)
+#define STM32F0_FLASH_WRPR (FLASH_REGS_ADDR + 0x20)
+
+	//"Unlocking Flash Memory" -- Page 45
+//#define STM32F0_FLASH_RDPTR_KEY 0x00a5 //NOTE: This chip has no RDPTR_KEY
+#define STM32F0_FLASH_KEY1 0x45670123
+#define STM32F0_FLASH_KEY2 0xcdef89ab
+
+	//Section 3.5.4
+#define STM32F0_FLASH_SR_BSY 0
+#define STM32F0_FLASH_SR_EOP 5
+
+	//Section 3.5.5
+#define STM32F0_FLASH_CR_PG 0
+#define STM32F0_FLASH_CR_PER 1
+#define STM32F0_FLASH_CR_MER 2
+#define STM32F0_FLASH_CR_STRT 6
+#define STM32F0_FLASH_CR_LOCK 7
+/* End stm32f05x flash controller defines
+*****************************/
 
 //32L = 32F1 same CoreID as 32F4!
 #define STM32L_FLASH_REGS_ADDR ((uint32_t)0x40023c00)