foo.v

module pipeRegister(clk, reset,
                    stall,
                    regWrEnIn, memWrEnIn, mulSelIn, aluOutIn, PCIn, instrTypeIn, isBranchTakenIn,
                    regWrEnOut, memWrEnOut, mulSelOut, aluOutOut, PCOut, instrTypeOut, isBranchTakenOut
                    );
                    
  parameter BIT_WIDTH = 32;

  input clk, reset;
  input stall;
  
  input regWrEnIn;
  input memWrEnIn;
  input mulSelIn; ****
  input[BIT_WIDTH - 1: 0] aluOutIn;
  input[BIT_WIDTH - 1: 0] PCIn;
  input instrTypeIn; ****
  input isBranchTakenIn;
  
  output regWrEnOut;
  output memWrEnOut;
  output mulSelOut; ****
  output[BIT_WIDTH - 1: 0] aluOutOut;
  output[BIT_WIDTH - 1: 0] PCOut;
  output instrTypeOut; ****
  output isBranchTakenOut;
  
  Register #(.BIT_WIDTH(1), .RESET_VALUE(1'b0) )  regWrEn       (clk, reset, !stall, regWrEnIn, regWrEnOut);
  Register #(.BIT_WIDTH(1), .RESET_VALUE(1'b0) )  memWrEn       (clk, reset, !stall, memWrEnIn, memWrEnOut);
  Register #(.BIT_WIDTH(1), .RESET_VALUE(1'b0) )  mulSel        (clk, reset, !stall, mulSelIn, mulSelOut);
  Register #(.BIT_WIDTH(32), .RESET_VALUE(32'b0))  aluOut        (clk, reset, !stall, aluOutIn, aluOutOut);
  Register #(.BIT_WIDTH(32), .RESET_VALUE(32'b0))  PC            (clk, reset, !stall, PCIn, PCOut);
  Register #(.BIT_WIDTH(1), .RESET_VALUE(1'b0) )  instrType     (clk, reset, !stall, instrTypeIn, instrTypeOut);
  Register #(.BIT_WIDTH(1), .RESET_VALUE(1'b0) )  isBranchTaken (clk, reset, !stall, isBranchTakenIn, isBranchTakenOut);
	
endmodule