project.tcl

set projName l_ug

proc cp { } {                   # creat proj
    global projName
    create_project $projName $projName -part xc7a35ticsg324-1L -force
}

proc op { } {                   # open proj
    global projName
    open_project $projName/$projName.xpr
}

proc lf { } {                   # re-load file
    add_files [ glob ./Sources/hdl/*.v ]
    add_files [ glob ./Sources/constrs/*.xdc ]

    import_files -force -norecurse
}

proc cb { } {                   # creat board
    global projName

    remove_files -quiet [pwd]/$projName/$projName.srcs/sources_1/bd/design_1/design_1.bd

    create_bd_design "design_1"

    source board.tcl

    save_bd_design
    generate_target all [get_files  [pwd]/$projName/$projName.srcs/sources_1/bd/design_1/design_1.bd]

    import_files -force -norecurse

    export_ip_user_files -of_objects [get_files [pwd]/$projName/$projName.srcs/sources_1/bd/design_1/design_1.bd] -no_script -force -quiet
}


proc synth { } {
    set_property top top [current_fileset]

    update_compile_order -fileset sources_1

    launch_runs -quiet synth_1
    wait_on_run synth_1
}

proc sc { } {
    lf

    set_property top top [current_fileset]

    update_compile_order -fileset sources_1

    synth_design -rtl
}



proc impl { } {
    launch_runs -quiet impl_1 -to_step write_bitstream
    wait_on_run impl_1
}

proc g { } {                    # generate bitfile
    synth
    impl
}

proc lb { } {                   # load bitfile
    exec xsdb load.tcl
}

proc clean { } {
    reset_run -quiet synth_1
    reset_run -quiet impl_1
}