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September 10, 2016 08:56
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module top( | |
input clk_12M, | |
output LED1, | |
output LED2, | |
output LED3, | |
output LED4, | |
output LED5, | |
output LED6, | |
output LED7, | |
output LED8, | |
input UART_RX, | |
output UART_TX | |
) | |
; | |
localparam UART_OVERSAMPLING = 26; | |
localparam UART_CLK_DIV = 104; | |
reg uart_clk115200 = 0; | |
reg [6:0] divider = 0; | |
reg [24:0] cur = 0; | |
wire [4:0] pos; | |
initial begin | |
cur = 0; | |
end | |
assign pos = cur[24:21]; | |
assign LED1 = (pos==0); | |
assign LED2 = (pos==1) | (pos==13); | |
assign LED3 = (pos==2) | (pos==12); | |
assign LED4 = (pos==3) | (pos==11); | |
assign LED5 = (pos==4) | (pos==10); | |
assign LED6 = (pos==5) | (pos==9); | |
assign LED7 = (pos==6) | (pos==8); | |
assign LED8 = (pos==7); | |
always @(posedge clk_12M) | |
begin | |
if (pos == 14) begin cur = 0; end | |
else begin cur = cur+1; end | |
end | |
always @(posedge clk_12M) | |
begin | |
if (divider == UART_CLK_DIV-1) begin | |
divider = 0; | |
if (data_counter >= 9) begin | |
data_counter = 0; | |
if (char_counter == 13) begin | |
char_counter = 0; | |
end else begin | |
char_counter = char_counter+1; | |
end | |
end else begin | |
data_counter = data_counter+1; | |
end | |
end else begin | |
divider = divider+1; | |
end | |
end | |
always @(posedge clk_12M) | |
begin | |
if (divider < UART_CLK_DIV/2) begin | |
uart_clk115200 = 1; | |
end else begin | |
uart_clk115200 = 0; | |
end | |
end | |
wire [7:0] out_char; | |
assign out_char = ((char_counter == 0)?8'h48: | |
(char_counter == 1)?8'h65: | |
(char_counter == 2)?8'h6c: | |
(char_counter == 3)?8'h6c: | |
(char_counter == 4)?8'h6f: | |
(char_counter == 5)?8'h20: | |
(char_counter == 6)?8'h57: | |
(char_counter == 7)?8'h6f: | |
(char_counter == 8)?8'h72: | |
(char_counter == 9)?8'h6c: | |
(char_counter == 10)?8'h64: | |
(char_counter == 11)?8'h21: | |
(char_counter == 12)?8'h0d: 8'h0a); | |
reg [3:0] char_counter = 0; | |
reg [3:0] data_counter = 0; | |
wire [9:0] data = 10'b1010000010; | |
assign UART_TX = data_counter == 0?0: | |
data_counter == 9?1: | |
out_char[data_counter-1]; | |
endmodule | |
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