Using SystemVerilog interfaces with pure Verilog modules

Makefile

all: compile gsim

.PHONY: compile gsim

compile:
	if [ -d work]; then vdel -lib work -all; fi
	vlib work
	vmap work work
	vlog -sv mux.sv
	vlog -sv mux_tb.sv

gsim:
	vsim -novopt mux_tb

clean:
	if [ -d work ]; then vdel -lib work -all; fi
	if [ -f transcript ]; then rm transcript; fi
	if [ -f vsim.wlf ]; then rm vsim.wlf; fi
	rm *~

Makefile_muxv

all: compile gsim

.PHONY: compile gsim

compile:
	if [ -d work]; then vdel -lib work -all; fi
	vlib work
	vmap work work
	vlog -sv mux.v
	vlog -sv muxv_tb.sv

gsim:
	vsim -novopt muxv_tb

mux.sv

interface mux_if();
	bit [3:0] in1, in2;
	bit sel;
	bit [3:0] out;
endinterface

module mux(mux_if muxif);

	always_comb begin
		if (muxif.sel == 1) begin
			muxif.out = muxif.in2;
		end else begin
			muxif.out = muxif.in1;
		end
	end

endmodule

mux.v

module mux(out, sel, in1, in2);

	input bit [3:0] in1, in2;
	input bit sel;
	output bit [3:0] out;

	always_comb begin
		if (sel == 1) begin
			out = in2;
		end else begin
			out = in1;
		end
	end

endmodule

mux_tb.sv

module mux_tb();

	mux_if muxif();

	mux i_mux(muxif);

	initial begin
		muxif.in1 = 4'b1010;
		muxif.in2 = 4'b0101;
		muxif.sel = 0;
		#10
		muxif.sel = 1;
		#10
		muxif.in1 = 4'b1111;
		muxif.in2 = 4'b0000;
		#10
		muxif.sel = 0;
		#10
		muxif.in1 = 4'b1100;
		#10 $finish;
	end	

endmodule

muxv_tb.sv

interface mux_if();
	bit [3:0] in1, in2;
	bit sel;
	bit [3:0] out;
endinterface

module muxv_tb();

	mux_if muxif();

	mux i_mux(.out(muxif.out), .sel(muxif.sel), .in1(muxif.in1), .in2(muxif.in2));

	initial begin
		muxif.in1 = 4'b1010;
		muxif.in2 = 4'b0101;
		muxif.sel = 0;
		#10
		muxif.sel = 1;
		#10
		muxif.in1 = 4'b1111;
		muxif.in2 = 4'b0000;
		#10
		muxif.sel = 0;
		#10
		muxif.in1 = 4'b1100;
		#10 $finish;
	end	

endmodule