VHDL comparison operators

comp_logic_vector.vhd

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity comp is port (
	a_i : in std_ulogic_vector(3 downto 0);
	c_o : out std_ulogic
);
end entity comp;

architecture rtl of comp is

begin
	
	c_o <= '0' when a_i < "0101" else '1';

end architecture;

comp_logic_vector_convert_int.vhd

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity comp is port (
	a_i : in std_ulogic_vector(3 downto 0);
	c_o : out std_ulogic
);
end entity comp;

architecture rtl of comp is

begin
	
	c_o <= '0' when a_i < std_ulogic_vector(to_unsigned(5, 4)) else '1';

end architecture;

comp_logic_vector_wrong_int.vhd

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity comp is port (
	a_i : in std_ulogic_vector(3 downto 0);
	c_o : out std_ulogic
);
end entity comp;

architecture rtl of comp is

begin
	
	c_o <= '0' when a_i < 5 else '1';

end architecture;

comp_scal.vhd

library ieee;
use ieee.std_logic_1164.all;

entity comp_scal is port (
	a_i : in std_ulogic;
	c_o : out std_ulogic
);
end entity comp_scal;

architecture rtl of comp_scal is

begin
	
	c_o <= '0' when a_i = '1' else '1';

end architecture;