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tejainece / LinkedHashMapValueByIndexArray.java
Last active March 9, 2023 21:21
Get element by index in LinkedHashMap
import java.util.LinkedHashMap;
import java.util.Map;
import java.util.Set;
public class LinkedHashMapValueByIndexArray {
public static void main(String []args){
LinkedHashMap<String, Integer> map = new LinkedHashMap<String, Integer>();
map.put("Qatar", 98814);
@tejainece
tejainece / configure_modelsim.sh
Last active June 30, 2024 06:42
This script installs all the 32 bit library dependencies of modelsim and also compiles freetype.
#!/bin/bash
ALTERA_PATH=~/altera/13.1/
sudo dpkg --add-architecture i386
sudo apt-get update
sudo apt-get install gcc-multilib g++-multilib \
lib32z1 lib32stdc++6 lib32gcc1 \
expat:i386 fontconfig:i386 libfreetype6:i386 libexpat1:i386 libc6:i386 libgtk-3-0:i386 \
libcanberra0:i386 libpng12-0:i386 libice6:i386 libsm6:i386 libncurses5:i386 zlib1g:i386 \
@tejainece
tejainece / req_gnt.sv
Created June 18, 2014 12:55
SystemVerilog: Basic assertion, property and sequence
module req_gnt();
logic clk = 0;
always #1 clk = ~clk;
logic req, gnt;
logic reset;
sequence req_gnt_1clock_seq;
@(posedge clk)
@tejainece
tejainece / Makefile
Last active March 15, 2023 15:50
Passing and receiving different SystemVerilog datatypes with C/C++ using DPI
dt: dt_compile dt_csim
.PHONY: dt dt_compile dt_csim clean
dt_compile:
if [ -d work ]; then vdel -lib work -all; fi;
vlib work
vmap work work
vlog -sv -dpiheader dt.h tb_dt_dpi.sv
g++ -shared -Bsymbolic -I/home/$(whoami)/modelsim/modeltech/include/ -fPIC -o dt.so dt.cc
@tejainece
tejainece / Makefile
Created June 21, 2014 10:47
Using SystemVerilog interfaces with pure Verilog modules
all: compile gsim
.PHONY: compile gsim
compile:
if [ -d work]; then vdel -lib work -all; fi
vlib work
vmap work work
vlog -sv mux.sv
vlog -sv mux_tb.sv
@tejainece
tejainece / select_prio.vhd
Last active August 29, 2015 14:02
VHDL conditional concurrent assignment: when vs with ... select
library IEEE;
use IEEE.std_logic_1164.all;
entity select_prio is port (
a : std_ulogic_vector(5 downto 0);
o : out std_ulogic_vector(2 downto 0)
);
end entity select_prio;
architecture behav of select_prio is
@tejainece
tejainece / cpp_no_assignment.cc
Last active August 29, 2015 14:03
Vector of arrays in C++
void main() {
int a0[4] = {0, 1, 2};
int a1[4] = a0;
}
@tejainece
tejainece / swapfile.sh
Created June 29, 2014 08:56
Enable suspend/hibernate in ubuntu or linux with a swap parition
fallocate -l 16GB /swapfile
mkswap /swapfile
swapon /swapfile
@tejainece
tejainece / egk_binarize.py
Last active August 29, 2015 14:03
EGK binarisation in python
from random import randrange
def egkKBinarize(data, riceP):
k = riceP + 1
cMax = 4 << (riceP)
inp = data - cMax
kbits = bin(inp & ((2**k) - 1))[2:]
kbits = ("0" * (k - len(kbits))) + kbits
ps = inp >> k
@tejainece
tejainece / vector_assign.cc
Last active August 29, 2015 14:03
C++ vectors and me
#include <iostream>
#include <vector>
using namespace std;
int main() {
vector<int> ints;
ints.push_back(500);
ints.push_back(510);