Atmel Software Framework PMC implementation - NOP WAT

pmc.c

void pmc_enable_waitmode(void)
{
	uint32_t i;

	/* Flash in Deep Power Down mode */
	i = PMC->PMC_FSMR;
	i &= ~PMC_FSMR_FLPM_Msk;
	i |= ul_flash_in_wait_mode;
	PMC->PMC_FSMR = i;

	/* Clear SLEEPDEEP bit */
	SCB->SCR &= (uint32_t) ~ SCB_SCR_SLEEPDEEP_Msk;

	/* Backup FWS setting and set Flash Wait State at 0 */
#if defined(ID_EFC)
	uint32_t fmr_backup;
	fmr_backup = EFC->EEFC_FMR;
	EFC->EEFC_FMR &= (uint32_t) ~ EEFC_FMR_FWS_Msk;
#endif
#if defined(ID_EFC0)
	uint32_t fmr0_backup;
	fmr0_backup = EFC0->EEFC_FMR;
	EFC0->EEFC_FMR &= (uint32_t) ~ EEFC_FMR_FWS_Msk;
#endif
#if defined(ID_EFC1)
	uint32_t fmr1_backup;
	fmr1_backup = EFC1->EEFC_FMR;
	EFC1->EEFC_FMR &= (uint32_t) ~ EEFC_FMR_FWS_Msk;
#endif

	/* Set the WAITMODE bit = 1 */
	PMC->CKGR_MOR |= CKGR_MOR_KEY(0x37u) | CKGR_MOR_WAITMODE;

	/* Waiting for Master Clock Ready MCKRDY = 1 */
	while (!(PMC->PMC_SR & PMC_SR_MCKRDY));

	/* Waiting for MOSCRCEN bit cleared is strongly recommended
	 * to ensure that the core will not execute undesired instructions
	 */
	for (i = 0; i < 500; i++) {
		__NOP();
	}
	while (!(PMC->CKGR_MOR & CKGR_MOR_MOSCRCEN));

	/* Restore EFC FMR setting */
#if defined(ID_EFC)
	EFC->EEFC_FMR = fmr_backup;
#endif
#if defined(ID_EFC0)
	EFC0->EEFC_FMR = fmr0_backup;
#endif
#if defined(ID_EFC1)
	EFC1->EEFC_FMR = fmr1_backup;
#endif
}

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