boot_z180.asm

; ==============================================================================
; Minimal Z180 Boot & Serial Test Code
; Target: Z8S180 
; ==============================================================================

; Z180 Internal I/O Register Addresses (Default Map: 00h - 3Fh)
DREQ0       equ 04h     ; DMA Request 0
STAT0       equ 08h     ; ASCI Status Register Channel 0
TDR0        equ 09h     ; ASCI Transmit Data Register Channel 0
CNTLA0      equ 00h     ; ASCI Control Register A Channel 0
CNTLB0      equ 01h     ; ASCI Control Register B Channel 0
ASEXT0      equ 12h     ; ASCI Extension Register Channel 0
DCNTL       equ 32h     ; DMA/Wait State Control Register
RCR         equ 36h     ; Refresh Control Register
CCR         equ 1Fh     ; CPU Control Register (Clock Multiplier)

            org 0000h   ; Boot Vector

Reset:
            di          ; Disable interrupts immediately
            ld  sp, 0FFFFh ; Set stack pointer to top of logical memory (64KB)

            ; 1. Disable Dynamic RAM Refresh (Not needed for SRAM)
            xor a
            out0 (RCR), a ; Write 00h to Refresh Control Register to disable [1.3.1]

            ; 2. Configure Wait States (Safe starting defaults)
            ld  a, 11110000b ; Max wait states for I/O & Memory [1.3.1]
            out0 (DCNTL), a

            ; 3. Configure CPU Clock Multiplier (Optional / Hardware Dependent)
            ; If using an 18.432 MHz crystal, we can set PHI = Crystal (1x)
            ld  a, 10000000b ; Bit 7: XTAL/2 dble clock (0 = 1x, 1 = 2x depending on version)
            out0 (CCR), a

            ; 4. Initialize ASCI0 Serial Port (8-N-1, Polled Mode)
            ; CNTLA0: Enable Receiver/Transmitter, no parity, 8-bit data, 1 stop bit
            ld  a, 01100100b ; [TE]=1, [RE]=1, [MPBR/EPE]=0, [P]=0, [M1]=0, [M0]=0
            out0 (CNTLA0), a

            ; CNTLB0: Configure baud rate source (SS2, SS1, SS0)
            ; Assumes System Clock (PHI) / 30 prescaler.
            ld  a, 00000000b ; Clear prescaler / source bits to select basic divider
            out0 (CNTLB0), a

            ; 5. Send Hello Message
MainLoop:
            ld  a, 'O'
            call TxChar
            ld  a, 'K'
            call TxChar
            ld  a, 0Dh     ; Carriage Return
            call TxChar
            ld  a, 0Ah     ; Line Feed
            call TxChar

            ; Simple delay loop before repeating
            ld  bc, 0FFFFh
Delay:      dec bc
            ld  a, b
            or  c
            jr  nz, Delay
            jr  MainLoop

; ==============================================================================
; Subroutine: Transmit Character in Register A via ASCI0
; ==============================================================================
TxChar:
            push af
.WaitTx:
            in0 a, (STAT0) ; Read Serial Status Register [1.3.1]
            bit 1, a       ; Bit 1 is TDRE (Transmit Data Register Empty)
            jr  z, .WaitTx ; Loop until TDRE is 1 (ready)
            
            pop af
            out0 (TDR0), a ; Send character [1.3.1]
            ret