Forward HDMI signal on FPGA in SystemVerilog

hdmi_forward.sv

module hdmi_forward (
    input logic clk,         // System clock
    input logic reset,       // Asynchronous reset

    // HDMI inputs
    input logic [2:0] tmds_i_red,
    input logic [2:0] tmds_i_green,
    input logic [2:0] tmds_i_blue,
    input logic hsync_i,
    input logic vsync_i,
    // Add other HDMI inputs as needed...

    // HDMI outputs
    output logic [2:0] tmds_o_red,
    output logic [2:0] tmds_o_green,
    output logic [2:0] tmds_o_blue,
    output logic hsync_o,
    output logic vsync_o
    // Add other HDMI outputs as needed...
);

always_ff @(posedge clk or posedge reset) begin
    if (reset) begin
        // Reset output signals to a known state
        tmds_o_red <= 3'b0;
        tmds_o_green <= 3'b0;
        tmds_o_blue <= 3'b0;
        hsync_o <= 1'b0;
        vsync_o <= 1'b0;
    end else begin
        // Forward HDMI input signals to output signals
        tmds_o_red <= tmds_i_red;
        tmds_o_green <= tmds_i_green;
        tmds_o_blue <= tmds_i_blue;
        hsync_o <= hsync_i;
        vsync_o <= vsync_i;
    end
end

endmodule