one_hot_mux_styles.v

module wor_mux #(
    parameter WIDTH = 32,
    parameter DEPTH = 8
) (
    input  [DEPTH - 1 : 0]           en,
    input  [(WIDTH * DEPTH) - 1 : 0] mux_in,
    output [WIDTH - 1 : 0]           mux_out
);
    reg [WIDTH - 1 : 0] bus;
    assign mux_out = bus;

    integer i;
    always @* begin
        bus = {WIDTH{1'b0}};
        for (i = 0; i < DEPTH; i = i + 1) begin
            if (en[i]) bus = bus | mux_in[32 * i +: 32];
        end
    end
endmodule

    wor_mux #(
        .WIDTH(32),
        .DEPTH(10)
    ) wor_mux_bus (
        .en ({
            en_imm,
            en_alu_logic,
            en_alu_add,
            en_alu_slt,
            en_alu_shift,
            en_reg,
            en_mem,
            en_addr_rst,
            en_cycle_counter,
            en_instret_counter
        }),
        .mux_in ({
            imm_value[31:0],
            alu_logic_output[31:0],
            alu_add_output[31:0],
            alu_slt_output[31:0],
            shift_output[31:0],
            reg_out[31:0],
            mem_rdata[31:0],
            PROGADDR_RESET[31:0],
            cycle_counter[31:0],
            instret_counter[31:0]
        }),
        .mux_out(bus)
    );

    always @* begin
        bus = 32'h00000000;
        if (en_imm)             bus = bus | imm_value;
        if (en_alu_logic)       bus = bus | alu_logic_output;
        if (en_alu_add)         bus = bus | alu_add_output;
        if (en_alu_slt)         bus = bus | alu_slt_output;
        if (en_alu_shift)       bus = bus | shift_output;
        if (en_reg)             bus = bus | reg_out;
        if (en_mem)             bus = bus | mem_rdata;
        if (en_addr_rst)        bus = bus | PROGADDR_RESET;
        if (en_cycle_counter)   bus = bus | cycle_counter;
        if (en_instret_counter) bus = bus | instret_counter;
    end

    assign bus = 
        (
          (en_imm         ? imm_value         : 32'h00000000) |
          (en_alu_logic   ? alu_logic_output  : 32'h00000000)
        ) | (
          (en_alu_add     ? alu_add_output    : 32'h00000000) |
          (en_alu_slt     ? alu_slt_output    : 32'h00000000) 
        ) | (
          (en_alu_shift   ? shift_output      : 32'h00000000) |
          (en_reg         ? reg_out           : 32'h00000000) 
        ) | (
          (en_mem         ? mem_rdata         : 32'h00000000) |
          (en_addr_rst    ? PROGADDR_RESET    : 32'h00000000)
        );