Created
January 28, 2019 21:38
-
-
Save titouanc/ee3b9406a6649faa82d32e2d59b71a85 to your computer and use it in GitHub Desktop.
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| /dts-v1/; | |
| /memreserve/ 0x00000000081e4000 0x0000000000019000; | |
| / { | |
| serial-number = "526e84fcaa8e34b9"; | |
| compatible = "firefly,roc-rk3399-pc", "rockchip,rk3399"; | |
| interrupt-parent = <0x1>; | |
| #address-cells = <0x2>; | |
| #size-cells = <0x2>; | |
| model = "Firefly roc-rk3399-pc"; | |
| memory { | |
| reg = <0x0 0x200000 0x0 0x8200000 0x0 0xa200000 0x0 0xede00000>; | |
| device_type = "memory"; | |
| }; | |
| ddr_timing { | |
| compatible = "rockchip,ddr-timing"; | |
| ddr3_speed_bin = <0x15>; | |
| pd_idle = <0x0>; | |
| sr_idle = <0x0>; | |
| sr_mc_gate_idle = <0x0>; | |
| srpd_lite_idle = <0x0>; | |
| standby_idle = <0x0>; | |
| auto_lp_dis_freq = <0x29a>; | |
| ddr3_dll_dis_freq = <0x12c>; | |
| phy_dll_dis_freq = <0x104>; | |
| ddr3_odt_dis_freq = <0x29a>; | |
| ddr3_drv = <0x28>; | |
| ddr3_odt = <0x78>; | |
| phy_ddr3_ca_drv = <0x28>; | |
| phy_ddr3_dq_drv = <0x28>; | |
| phy_ddr3_odt = <0xf0>; | |
| lpddr3_odt_dis_freq = <0x29a>; | |
| lpddr3_drv = <0x22>; | |
| lpddr3_odt = <0xf0>; | |
| phy_lpddr3_ca_drv = <0x22>; | |
| phy_lpddr3_dq_drv = <0x22>; | |
| phy_lpddr3_odt = <0xf0>; | |
| lpddr4_odt_dis_freq = <0x320>; | |
| lpddr4_drv = <0xf0>; | |
| lpddr4_dq_odt = <0x28>; | |
| lpddr4_ca_odt = <0x0>; | |
| phy_lpddr4_ca_drv = <0x28>; | |
| phy_lpddr4_ck_cs_drv = <0x28>; | |
| phy_lpddr4_dq_drv = <0x3c>; | |
| phy_lpddr4_odt = <0x28>; | |
| phandle = <0x93>; | |
| }; | |
| aliases { | |
| dsi0 = "/dsi@ff960000"; | |
| dsi1 = "/dsi@ff968000"; | |
| ethernet0 = "/ethernet@fe300000"; | |
| i2c0 = "/i2c@ff3c0000"; | |
| i2c1 = "/i2c@ff110000"; | |
| i2c2 = "/i2c@ff120000"; | |
| i2c3 = "/i2c@ff130000"; | |
| i2c4 = "/i2c@ff3d0000"; | |
| i2c5 = "/i2c@ff140000"; | |
| i2c6 = "/i2c@ff150000"; | |
| i2c7 = "/i2c@ff160000"; | |
| i2c8 = "/i2c@ff3e0000"; | |
| serial0 = "/serial@ff180000"; | |
| serial1 = "/serial@ff190000"; | |
| serial2 = "/serial@ff1a0000"; | |
| serial3 = "/serial@ff1b0000"; | |
| serial4 = "/serial@ff370000"; | |
| }; | |
| cpus { | |
| #address-cells = <0x2>; | |
| #size-cells = <0x0>; | |
| cpu-map { | |
| cluster0 { | |
| core0 { | |
| cpu = <0x2>; | |
| }; | |
| core1 { | |
| cpu = <0x3>; | |
| }; | |
| core2 { | |
| cpu = <0x4>; | |
| }; | |
| core3 { | |
| cpu = <0x5>; | |
| }; | |
| }; | |
| cluster1 { | |
| core0 { | |
| cpu = <0x6>; | |
| }; | |
| core1 { | |
| cpu = <0x7>; | |
| }; | |
| }; | |
| }; | |
| cpu@0 { | |
| device_type = "cpu"; | |
| compatible = "arm,cortex-a53", "arm,armv8"; | |
| reg = <0x0 0x0>; | |
| enable-method = "psci"; | |
| #cooling-cells = <0x2>; | |
| clocks = <0x8 0x8>; | |
| cpu-idle-states = <0x9 0xa>; | |
| dynamic-power-coefficient = <0x64>; | |
| operating-points-v2 = <0xb>; | |
| sched-energy-costs = <0xc 0xd>; | |
| cpu-supply = <0xe>; | |
| phandle = <0x2>; | |
| }; | |
| cpu@1 { | |
| device_type = "cpu"; | |
| compatible = "arm,cortex-a53", "arm,armv8"; | |
| reg = <0x0 0x1>; | |
| enable-method = "psci"; | |
| clocks = <0x8 0x8>; | |
| cpu-idle-states = <0x9 0xa>; | |
| dynamic-power-coefficient = <0x64>; | |
| operating-points-v2 = <0xb>; | |
| sched-energy-costs = <0xc 0xd>; | |
| cpu-supply = <0xe>; | |
| phandle = <0x3>; | |
| }; | |
| cpu@2 { | |
| device_type = "cpu"; | |
| compatible = "arm,cortex-a53", "arm,armv8"; | |
| reg = <0x0 0x2>; | |
| enable-method = "psci"; | |
| clocks = <0x8 0x8>; | |
| cpu-idle-states = <0x9 0xa>; | |
| dynamic-power-coefficient = <0x64>; | |
| operating-points-v2 = <0xb>; | |
| sched-energy-costs = <0xc 0xd>; | |
| cpu-supply = <0xe>; | |
| phandle = <0x4>; | |
| }; | |
| cpu@3 { | |
| device_type = "cpu"; | |
| compatible = "arm,cortex-a53", "arm,armv8"; | |
| reg = <0x0 0x3>; | |
| enable-method = "psci"; | |
| clocks = <0x8 0x8>; | |
| cpu-idle-states = <0x9 0xa>; | |
| dynamic-power-coefficient = <0x64>; | |
| operating-points-v2 = <0xb>; | |
| sched-energy-costs = <0xc 0xd>; | |
| cpu-supply = <0xe>; | |
| phandle = <0x5>; | |
| }; | |
| cpu@100 { | |
| device_type = "cpu"; | |
| compatible = "arm,cortex-a72", "arm,armv8"; | |
| reg = <0x0 0x100>; | |
| enable-method = "psci"; | |
| #cooling-cells = <0x2>; | |
| clocks = <0x8 0x9>; | |
| cpu-idle-states = <0x9 0xa>; | |
| dynamic-power-coefficient = <0x1b4>; | |
| operating-points-v2 = <0xf>; | |
| sched-energy-costs = <0x10 0x11>; | |
| cpu-supply = <0x12>; | |
| phandle = <0x6>; | |
| }; | |
| cpu@101 { | |
| device_type = "cpu"; | |
| compatible = "arm,cortex-a72", "arm,armv8"; | |
| reg = <0x0 0x101>; | |
| enable-method = "psci"; | |
| clocks = <0x8 0x9>; | |
| cpu-idle-states = <0x9 0xa>; | |
| dynamic-power-coefficient = <0x1b4>; | |
| operating-points-v2 = <0xf>; | |
| sched-energy-costs = <0x10 0x11>; | |
| cpu-supply = <0x12>; | |
| phandle = <0x7>; | |
| }; | |
| idle-states { | |
| entry-method = "psci"; | |
| cpu-sleep { | |
| compatible = "arm,idle-state"; | |
| local-timer-stop; | |
| arm,psci-suspend-param = <0x10000>; | |
| entry-latency-us = <0x78>; | |
| exit-latency-us = <0xfa>; | |
| min-residency-us = <0x384>; | |
| phandle = <0x9>; | |
| }; | |
| cluster-sleep { | |
| compatible = "arm,idle-state"; | |
| local-timer-stop; | |
| arm,psci-suspend-param = <0x1010000>; | |
| entry-latency-us = <0x190>; | |
| exit-latency-us = <0x1f4>; | |
| min-residency-us = <0x7d0>; | |
| phandle = <0xa>; | |
| }; | |
| }; | |
| }; | |
| pmu_a53 { | |
| compatible = "arm,cortex-a53-pmu"; | |
| interrupts = <0x1 0x7 0x8 0x13>; | |
| }; | |
| pmu_a72 { | |
| compatible = "arm,cortex-a72-pmu"; | |
| interrupts = <0x1 0x7 0x8 0x14>; | |
| }; | |
| psci { | |
| compatible = "arm,psci-1.0"; | |
| method = "smc"; | |
| }; | |
| cpuinfo { | |
| compatible = "rockchip,cpuinfo"; | |
| nvmem-cells = <0x15>; | |
| nvmem-cell-names = "id"; | |
| }; | |
| timer { | |
| compatible = "arm,armv8-timer"; | |
| interrupts = <0x1 0xd 0x8 0x0 0x1 0xe 0x8 0x0 0x1 0xb 0x8 0x0 0x1 0xa 0x8 0x0>; | |
| arm,no-tick-in-suspend; | |
| }; | |
| xin24m { | |
| compatible = "fixed-clock"; | |
| clock-frequency = <0x16e3600>; | |
| clock-output-names = "xin24m"; | |
| #clock-cells = <0x0>; | |
| phandle = <0xe7>; | |
| }; | |
| dummy_cpll { | |
| compatible = "fixed-clock"; | |
| clock-frequency = <0x0>; | |
| clock-output-names = "dummy_cpll"; | |
| #clock-cells = <0x0>; | |
| phandle = <0xe8>; | |
| }; | |
| dummy_vpll { | |
| compatible = "fixed-clock"; | |
| clock-frequency = <0x0>; | |
| clock-output-names = "dummy_vpll"; | |
| #clock-cells = <0x0>; | |
| phandle = <0xe9>; | |
| }; | |
| amba { | |
| compatible = "simple-bus"; | |
| #address-cells = <0x2>; | |
| #size-cells = <0x2>; | |
| ranges; | |
| dma-controller@ff6d0000 { | |
| compatible = "arm,pl330", "arm,primecell"; | |
| reg = <0x0 0xff6d0000 0x0 0x4000>; | |
| interrupts = <0x0 0x5 0x4 0x0 0x0 0x6 0x4 0x0>; | |
| #dma-cells = <0x1>; | |
| clocks = <0x8 0xd3>; | |
| clock-names = "apb_pclk"; | |
| peripherals-req-type-burst; | |
| phandle = <0x9b>; | |
| }; | |
| dma-controller@ff6e0000 { | |
| compatible = "arm,pl330", "arm,primecell"; | |
| reg = <0x0 0xff6e0000 0x0 0x4000>; | |
| interrupts = <0x0 0x7 0x4 0x0 0x0 0x8 0x4 0x0>; | |
| #dma-cells = <0x1>; | |
| clocks = <0x8 0xd4>; | |
| clock-names = "apb_pclk"; | |
| peripherals-req-type-burst; | |
| phandle = <0xea>; | |
| }; | |
| }; | |
| ethernet@fe300000 { | |
| local-mac-address = [36 72 38 01 8d 30]; | |
| compatible = "rockchip,rk3399-gmac"; | |
| reg = <0x0 0xfe300000 0x0 0x10000>; | |
| interrupts = <0x0 0xc 0x4 0x0>; | |
| interrupt-names = "macirq"; | |
| clocks = <0x8 0x69 0x8 0x67 0x8 0x68 0x8 0x66 0x8 0x6a 0x8 0xd5 0x8 0x166>; | |
| clock-names = "stmmaceth", "mac_clk_rx", "mac_clk_tx", "clk_mac_ref", "clk_mac_refout", "aclk_mac", "pclk_mac"; | |
| power-domains = <0x16 0x16>; | |
| resets = <0x8 0x89>; | |
| reset-names = "stmmaceth"; | |
| rockchip,grf = <0x17>; | |
| status = "okay"; | |
| phy-supply = <0x18>; | |
| phy-mode = "rgmii"; | |
| clock_in_out = "input"; | |
| snps,reset-gpio = <0x19 0xf 0x1>; | |
| snps,reset-active-low; | |
| snps,reset-delays-us = <0x0 0x2710 0xc350>; | |
| assigned-clocks = <0x8 0xa6>; | |
| assigned-clock-parents = <0x1a>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x1b>; | |
| tx_delay = <0x28>; | |
| rx_delay = <0x1b>; | |
| phandle = <0xeb>; | |
| }; | |
| dwmmc@fe310000 { | |
| compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc"; | |
| reg = <0x0 0xfe310000 0x0 0x4000>; | |
| interrupts = <0x0 0x40 0x4 0x0>; | |
| max-frequency = <0x5f5e100>; | |
| clocks = <0x8 0x1ee 0x8 0x4d 0x8 0x9c 0x8 0x9d>; | |
| clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; | |
| fifo-depth = <0x100>; | |
| power-domains = <0x16 0x1c>; | |
| resets = <0x8 0x79>; | |
| reset-names = "reset"; | |
| status = "okay"; | |
| supports-sdio; | |
| bus-width = <0x4>; | |
| disable-wp; | |
| cap-sd-highspeed; | |
| keep-power-in-suspend; | |
| mmc-pwrseq = <0x1c>; | |
| non-removable; | |
| num-slots = <0x1>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x1d 0x1e 0x1f>; | |
| sd-uhs-sdr104; | |
| phandle = <0xec>; | |
| }; | |
| dwmmc@fe320000 { | |
| compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc"; | |
| reg = <0x0 0xfe320000 0x0 0x4000>; | |
| interrupts = <0x0 0x41 0x4 0x0>; | |
| max-frequency = <0x8f0d180>; | |
| assigned-clocks = <0x8 0x1cd>; | |
| assigned-clock-rates = <0xbebc200>; | |
| clocks = <0x8 0x1ce 0x8 0x4c 0x8 0x9a 0x8 0x9b>; | |
| clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; | |
| fifo-depth = <0x100>; | |
| power-domains = <0x16 0x1b>; | |
| resets = <0x8 0x7a>; | |
| reset-names = "reset"; | |
| status = "okay"; | |
| clock-frequency = <0x8f0d180>; | |
| clock-freq-min-max = <0x186a0 0x8f0d180>; | |
| supports-sd; | |
| bus-width = <0x4>; | |
| cap-mmc-highspeed; | |
| cap-sd-highspeed; | |
| disable-wp; | |
| num-slots = <0x1>; | |
| sd-uhs-sdr104; | |
| vmmc-supply = <0x20>; | |
| vqmmc-supply = <0x21>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x22 0x23 0x24 0x25>; | |
| phandle = <0xed>; | |
| }; | |
| sdhci@fe330000 { | |
| compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1"; | |
| reg = <0x0 0xfe330000 0x0 0x10000>; | |
| interrupts = <0x0 0xb 0x4 0x0>; | |
| arasan,soc-ctl-syscon = <0x17>; | |
| assigned-clocks = <0x8 0x4e>; | |
| assigned-clock-rates = <0xbebc200>; | |
| clocks = <0x8 0x4e 0x8 0xf0>; | |
| clock-names = "clk_xin", "clk_ahb"; | |
| clock-output-names = "emmc_cardclock"; | |
| #clock-cells = <0x0>; | |
| phys = <0x26>; | |
| phy-names = "phy_arasan"; | |
| power-domains = <0x16 0x17>; | |
| status = "okay"; | |
| assigned-clock-parents = <0x8 0x5>; | |
| bus-width = <0x8>; | |
| keep-power-in-suspend; | |
| mmc-hs400-1_8v; | |
| mmc-hs400-enhanced-strobe; | |
| non-removable; | |
| supports-emmc; | |
| phandle = <0x9a>; | |
| }; | |
| usb@fe340000 { | |
| compatible = "generic-ehci"; | |
| reg = <0x0 0xfe340000 0x0 0x30000>; | |
| interrupts = <0x0 0x21 0x4 0x0>; | |
| clocks = <0x8 0x1cc 0x8 0x79 0x8 0x154>; | |
| clock-names = "hclk_hsic", "clk_hsicphy", "pclk_hsicphy"; | |
| rockchip-has-usic; | |
| status = "disabled"; | |
| phandle = <0xee>; | |
| }; | |
| usb@fe380000 { | |
| compatible = "generic-ehci"; | |
| reg = <0x0 0xfe380000 0x0 0x20000>; | |
| interrupts = <0x0 0x1a 0x4 0x0>; | |
| clocks = <0x8 0x1c8 0x8 0x1c9 0x8 0xa8>; | |
| clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m"; | |
| phys = <0x27>; | |
| phy-names = "usb"; | |
| power-domains = <0x16 0xe>; | |
| status = "okay"; | |
| phandle = <0xef>; | |
| }; | |
| usb@fe3a0000 { | |
| compatible = "generic-ohci"; | |
| reg = <0x0 0xfe3a0000 0x0 0x20000>; | |
| interrupts = <0x0 0x1c 0x4 0x0>; | |
| clocks = <0x8 0x1c8 0x8 0x1c9 0x8 0xa8>; | |
| clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m"; | |
| phys = <0x27>; | |
| phy-names = "usb"; | |
| power-domains = <0x16 0xe>; | |
| status = "okay"; | |
| phandle = <0xf0>; | |
| }; | |
| usb@fe3c0000 { | |
| compatible = "generic-ehci"; | |
| reg = <0x0 0xfe3c0000 0x0 0x20000>; | |
| interrupts = <0x0 0x1e 0x4 0x0>; | |
| clocks = <0x8 0x1ca 0x8 0x1cb 0x8 0xa9>; | |
| clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m"; | |
| phys = <0x28>; | |
| phy-names = "usb"; | |
| power-domains = <0x16 0xe>; | |
| status = "okay"; | |
| phandle = <0xf1>; | |
| }; | |
| usb@fe3e0000 { | |
| compatible = "generic-ohci"; | |
| reg = <0x0 0xfe3e0000 0x0 0x20000>; | |
| interrupts = <0x0 0x20 0x4 0x0>; | |
| clocks = <0x8 0x1ca 0x8 0x1cb 0x8 0xa9>; | |
| clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m"; | |
| phys = <0x28>; | |
| phy-names = "usb"; | |
| power-domains = <0x16 0xe>; | |
| status = "okay"; | |
| pinctrl-names = "default"; | |
| phandle = <0xf2>; | |
| }; | |
| usb@fe800000 { | |
| compatible = "rockchip,rk3399-dwc3"; | |
| clocks = <0x8 0x81 0x8 0x83 0x8 0xf6 0x8 0xf9>; | |
| clock-names = "ref_clk", "suspend_clk", "bus_clk", "grf_clk"; | |
| power-domains = <0x16 0x18>; | |
| resets = <0x8 0x125>; | |
| reset-names = "usb3-otg"; | |
| #address-cells = <0x2>; | |
| #size-cells = <0x2>; | |
| ranges; | |
| status = "okay"; | |
| extcon = <0x29>; | |
| phandle = <0xf3>; | |
| dwc3@fe800000 { | |
| compatible = "snps,dwc3"; | |
| reg = <0x0 0xfe800000 0x0 0x100000>; | |
| interrupts = <0x0 0x69 0x4 0x0>; | |
| dr_mode = "otg"; | |
| phys = <0x2a 0x2b>; | |
| phy-names = "usb2-phy", "usb3-phy"; | |
| phy_type = "utmi_wide"; | |
| snps,dis_enblslpm_quirk; | |
| snps,dis-u2-freeclk-exists-quirk; | |
| snps,dis_u2_susphy_quirk; | |
| snps,dis-del-phy-power-chg-quirk; | |
| snps,tx-ipgap-linecheck-dis-quirk; | |
| snps,xhci-slow-suspend-quirk; | |
| snps,usb3-warm-reset-on-resume-quirk; | |
| status = "okay"; | |
| phandle = <0xf4>; | |
| }; | |
| }; | |
| usb@fe900000 { | |
| compatible = "rockchip,rk3399-dwc3"; | |
| clocks = <0x8 0x82 0x8 0x84 0x8 0xf7 0x8 0xf9>; | |
| clock-names = "ref_clk", "suspend_clk", "bus_clk", "grf_clk"; | |
| power-domains = <0x16 0x18>; | |
| resets = <0x8 0x126>; | |
| reset-names = "usb3-otg"; | |
| #address-cells = <0x2>; | |
| #size-cells = <0x2>; | |
| ranges; | |
| status = "okay"; | |
| extcon = <0x2c>; | |
| phandle = <0xf5>; | |
| dwc3@fe900000 { | |
| compatible = "snps,dwc3"; | |
| reg = <0x0 0xfe900000 0x0 0x100000>; | |
| interrupts = <0x0 0x6e 0x4 0x0>; | |
| dr_mode = "host"; | |
| phys = <0x2d 0x2e>; | |
| phy-names = "usb2-phy", "usb3-phy"; | |
| phy_type = "utmi_wide"; | |
| snps,dis_enblslpm_quirk; | |
| snps,dis-u2-freeclk-exists-quirk; | |
| snps,dis_u2_susphy_quirk; | |
| snps,dis-del-phy-power-chg-quirk; | |
| snps,tx-ipgap-linecheck-dis-quirk; | |
| snps,xhci-slow-suspend-quirk; | |
| snps,usb3-warm-reset-on-resume-quirk; | |
| status = "okay"; | |
| phandle = <0xf6>; | |
| }; | |
| }; | |
| dp@fec00000 { | |
| compatible = "rockchip,rk3399-cdn-dp"; | |
| reg = <0x0 0xfec00000 0x0 0x100000>; | |
| interrupts = <0x0 0x9 0x4 0x0>; | |
| assigned-clocks = <0x8 0x72 0x8 0xa1>; | |
| assigned-clock-rates = <0x5f5e100 0xbebc200>; | |
| clocks = <0x8 0x72 0x8 0x175 0x8 0xa1 0x8 0x16f>; | |
| clock-names = "core-clk", "pclk", "spdif", "grf"; | |
| power-domains = <0x16 0x15>; | |
| phys = <0x2f 0x30>; | |
| resets = <0x8 0x103 0x8 0x148 0x8 0x14a 0x8 0xfd>; | |
| reset-names = "spdif", "dptx", "apb", "core"; | |
| rockchip,grf = <0x17>; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| #sound-dai-cells = <0x1>; | |
| status = "okay"; | |
| extcon = <0x29 0x2c>; | |
| phandle = <0xd1>; | |
| ports { | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| port { | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| phandle = <0xf7>; | |
| endpoint@0 { | |
| reg = <0x0>; | |
| remote-endpoint = <0x31>; | |
| status = "okay"; | |
| phandle = <0xac>; | |
| }; | |
| endpoint@1 { | |
| reg = <0x1>; | |
| remote-endpoint = <0x32>; | |
| status = "disabled"; | |
| phandle = <0xa5>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| interrupt-controller@fee00000 { | |
| compatible = "arm,gic-v3"; | |
| #interrupt-cells = <0x4>; | |
| #address-cells = <0x2>; | |
| #size-cells = <0x2>; | |
| ranges; | |
| interrupt-controller; | |
| reg = <0x0 0xfee00000 0x0 0x10000 0x0 0xfef00000 0x0 0xc0000 0x0 0xfff00000 0x0 0x10000 0x0 0xfff10000 0x0 0x10000 0x0 0xfff20000 0x0 0x10000>; | |
| interrupts = <0x1 0x9 0x4 0x0>; | |
| phandle = <0x1>; | |
| interrupt-controller@fee20000 { | |
| compatible = "arm,gic-v3-its"; | |
| msi-controller; | |
| reg = <0x0 0xfee20000 0x0 0x20000>; | |
| phandle = <0x89>; | |
| }; | |
| ppi-partitions { | |
| interrupt-partition-0 { | |
| affinity = <0x2 0x3 0x4 0x5>; | |
| phandle = <0x13>; | |
| }; | |
| interrupt-partition-1 { | |
| affinity = <0x6 0x7>; | |
| phandle = <0x14>; | |
| }; | |
| }; | |
| }; | |
| saradc@ff100000 { | |
| compatible = "rockchip,rk3399-saradc"; | |
| reg = <0x0 0xff100000 0x0 0x100>; | |
| interrupts = <0x0 0x3e 0x4 0x0>; | |
| #io-channel-cells = <0x1>; | |
| clocks = <0x8 0x50 0x8 0x165>; | |
| clock-names = "saradc", "apb_pclk"; | |
| resets = <0x8 0xd4>; | |
| reset-names = "saradc-apb"; | |
| status = "okay"; | |
| phandle = <0xe4>; | |
| }; | |
| i2c@ff3c0000 { | |
| compatible = "rockchip,rk3399-i2c"; | |
| reg = <0x0 0xff3c0000 0x0 0x1000>; | |
| clocks = <0x33 0x9 0x33 0x1b>; | |
| clock-names = "i2c", "pclk"; | |
| interrupts = <0x0 0x39 0x4 0x0>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x34>; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| status = "okay"; | |
| i2c-scl-rising-time-ns = <0xa8>; | |
| i2c-scl-falling-time-ns = <0x4>; | |
| clock-frequency = <0x61a80>; | |
| phandle = <0xf8>; | |
| syr827@40 { | |
| compatible = "silergy,syr827"; | |
| reg = <0x40>; | |
| vin-supply = <0x35>; | |
| regulator-compatible = "fan53555-reg"; | |
| regulator-name = "vdd_cpu_b"; | |
| regulator-min-microvolt = <0xadf34>; | |
| regulator-max-microvolt = <0x16e360>; | |
| regulator-ramp-delay = <0x3e8>; | |
| pinctrl-0 = <0x36>; | |
| vsel-gpios = <0x37 0x12 0x0>; | |
| fcs,suspend-voltage-selector = <0x1>; | |
| regulator-always-on; | |
| regulator-boot-on; | |
| regulator-initial-state = <0x3>; | |
| phandle = <0x12>; | |
| regulator-state-mem { | |
| regulator-off-in-suspend; | |
| }; | |
| }; | |
| syr828@41 { | |
| compatible = "silergy,syr828"; | |
| reg = <0x41>; | |
| vin-supply = <0x35>; | |
| pinctrl-0 = <0x38>; | |
| vsel-gpios = <0x37 0xe 0x0>; | |
| regulator-compatible = "fan53555-reg"; | |
| regulator-name = "vdd_gpu"; | |
| regulator-min-microvolt = <0xadf34>; | |
| regulator-max-microvolt = <0x16e360>; | |
| regulator-ramp-delay = <0x3e8>; | |
| fcs,suspend-voltage-selector = <0x1>; | |
| regulator-always-on; | |
| regulator-boot-on; | |
| regulator-initial-state = <0x3>; | |
| phandle = <0xa0>; | |
| regulator-state-mem { | |
| regulator-off-in-suspend; | |
| }; | |
| }; | |
| pmic@1b { | |
| compatible = "rockchip,rk808"; | |
| reg = <0x1b>; | |
| interrupt-parent = <0x37>; | |
| interrupts = <0x15 0x8>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x39 0x3a>; | |
| rockchip,system-power-controller; | |
| wakeup-source; | |
| #clock-cells = <0x1>; | |
| clock-output-names = "xin32k", "rk808-clkout2"; | |
| vcc1-supply = <0x3b>; | |
| vcc2-supply = <0x3b>; | |
| vcc3-supply = <0x3b>; | |
| vcc4-supply = <0x3b>; | |
| vcc6-supply = <0x3b>; | |
| vcc7-supply = <0x3b>; | |
| vcc8-supply = <0x3b>; | |
| vcc9-supply = <0x3b>; | |
| vcc10-supply = <0x3b>; | |
| vcc11-supply = <0x3b>; | |
| vcc12-supply = <0x3b>; | |
| vddio-supply = <0x3c>; | |
| phandle = <0xdd>; | |
| regulators { | |
| DCDC_REG1 { | |
| regulator-always-on; | |
| regulator-boot-on; | |
| regulator-min-microvolt = <0xb71b0>; | |
| regulator-max-microvolt = <0x149970>; | |
| regulator-ramp-delay = <0x1771>; | |
| regulator-name = "vdd_center"; | |
| phandle = <0xf9>; | |
| regulator-state-mem { | |
| regulator-off-in-suspend; | |
| }; | |
| }; | |
| DCDC_REG2 { | |
| regulator-always-on; | |
| regulator-boot-on; | |
| regulator-min-microvolt = <0xb71b0>; | |
| regulator-max-microvolt = <0x149970>; | |
| regulator-ramp-delay = <0x1771>; | |
| regulator-name = "vdd_cpu_l"; | |
| phandle = <0xe>; | |
| regulator-state-mem { | |
| regulator-off-in-suspend; | |
| }; | |
| }; | |
| DCDC_REG3 { | |
| regulator-always-on; | |
| regulator-boot-on; | |
| regulator-name = "vcc_ddr"; | |
| phandle = <0xfa>; | |
| regulator-state-mem { | |
| regulator-on-in-suspend; | |
| }; | |
| }; | |
| DCDC_REG4 { | |
| regulator-always-on; | |
| regulator-boot-on; | |
| regulator-min-microvolt = <0x1b7740>; | |
| regulator-max-microvolt = <0x1b7740>; | |
| regulator-name = "vcc_1v8"; | |
| phandle = <0xfb>; | |
| regulator-state-mem { | |
| regulator-on-in-suspend; | |
| regulator-suspend-microvolt = <0x1b7740>; | |
| }; | |
| }; | |
| LDO_REG1 { | |
| regulator-always-on; | |
| regulator-boot-on; | |
| regulator-min-microvolt = <0x1b7740>; | |
| regulator-max-microvolt = <0x1b7740>; | |
| regulator-name = "vcca1v8_codec"; | |
| phandle = <0x98>; | |
| regulator-state-mem { | |
| regulator-off-in-suspend; | |
| }; | |
| }; | |
| LDO_REG2 { | |
| regulator-always-on; | |
| regulator-boot-on; | |
| regulator-min-microvolt = <0x1b7740>; | |
| regulator-max-microvolt = <0x1b7740>; | |
| regulator-name = "vcc1v8_hdmi"; | |
| phandle = <0xfc>; | |
| regulator-state-mem { | |
| regulator-off-in-suspend; | |
| }; | |
| }; | |
| LDO_REG3 { | |
| regulator-always-on; | |
| regulator-boot-on; | |
| regulator-min-microvolt = <0x1b7740>; | |
| regulator-max-microvolt = <0x1b7740>; | |
| regulator-name = "vcc1v8_pmu"; | |
| phandle = <0x3c>; | |
| regulator-state-mem { | |
| regulator-on-in-suspend; | |
| regulator-suspend-microvolt = <0x1b7740>; | |
| }; | |
| }; | |
| LDO_REG4 { | |
| regulator-always-on; | |
| regulator-boot-on; | |
| regulator-min-microvolt = <0x1b7740>; | |
| regulator-max-microvolt = <0x325aa0>; | |
| regulator-name = "vccio_sd"; | |
| phandle = <0x21>; | |
| regulator-state-mem { | |
| regulator-on-in-suspend; | |
| regulator-suspend-microvolt = <0x325aa0>; | |
| }; | |
| }; | |
| LDO_REG5 { | |
| regulator-always-on; | |
| regulator-boot-on; | |
| regulator-min-microvolt = <0x2dc6c0>; | |
| regulator-max-microvolt = <0x2dc6c0>; | |
| regulator-name = "vcca3v0_codec"; | |
| phandle = <0xfd>; | |
| regulator-state-mem { | |
| regulator-off-in-suspend; | |
| }; | |
| }; | |
| LDO_REG6 { | |
| regulator-always-on; | |
| regulator-boot-on; | |
| regulator-min-microvolt = <0x16e360>; | |
| regulator-max-microvolt = <0x16e360>; | |
| regulator-name = "vcc_1v5"; | |
| phandle = <0xfe>; | |
| regulator-state-mem { | |
| regulator-on-in-suspend; | |
| regulator-suspend-microvolt = <0x16e360>; | |
| }; | |
| }; | |
| LDO_REG7 { | |
| regulator-always-on; | |
| regulator-boot-on; | |
| regulator-min-microvolt = <0xdbba0>; | |
| regulator-max-microvolt = <0xdbba0>; | |
| regulator-name = "vcca0v9_hdmi"; | |
| phandle = <0xff>; | |
| regulator-state-mem { | |
| regulator-off-in-suspend; | |
| }; | |
| }; | |
| LDO_REG8 { | |
| regulator-always-on; | |
| regulator-boot-on; | |
| regulator-min-microvolt = <0x2dc6c0>; | |
| regulator-max-microvolt = <0x2dc6c0>; | |
| regulator-name = "vcc_3v0"; | |
| phandle = <0x7e>; | |
| regulator-state-mem { | |
| regulator-on-in-suspend; | |
| regulator-suspend-microvolt = <0x2dc6c0>; | |
| }; | |
| }; | |
| SWITCH_REG1 { | |
| regulator-always-on; | |
| regulator-boot-on; | |
| regulator-name = "vcc3v3_s3"; | |
| phandle = <0x100>; | |
| regulator-state-mem { | |
| regulator-off-in-suspend; | |
| }; | |
| }; | |
| SWITCH_REG2 { | |
| regulator-always-on; | |
| regulator-boot-on; | |
| regulator-name = "vcc3v3_s0"; | |
| phandle = <0x101>; | |
| regulator-state-mem { | |
| regulator-off-in-suspend; | |
| }; | |
| }; | |
| }; | |
| }; | |
| }; | |
| i2c@ff110000 { | |
| compatible = "rockchip,rk3399-i2c"; | |
| reg = <0x0 0xff110000 0x0 0x1000>; | |
| clocks = <0x8 0x41 0x8 0x155>; | |
| clock-names = "i2c", "pclk"; | |
| interrupts = <0x0 0x3b 0x4 0x0>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x3d>; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| status = "okay"; | |
| i2c-scl-rising-time-ns = <0x12c>; | |
| i2c-scl-falling-time-ns = <0xf>; | |
| clock-frequency = <0x186a0>; | |
| phandle = <0x102>; | |
| }; | |
| i2c@ff120000 { | |
| compatible = "rockchip,rk3399-i2c"; | |
| reg = <0x0 0xff120000 0x0 0x1000>; | |
| clocks = <0x8 0x42 0x8 0x156>; | |
| clock-names = "i2c", "pclk"; | |
| interrupts = <0x0 0x23 0x4 0x0>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x3e>; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| status = "okay"; | |
| phandle = <0x103>; | |
| cw2015@62 { | |
| status = "okay"; | |
| compatible = "cw201x"; | |
| reg = <0x62>; | |
| bat_config_info = <0x15 0x42 0x60 0x59 0x52 0x58 0x4d 0x48 0x48 0x44 0x44 0x46 0x49 0x48 0x32 0x24 0x20 0x17 0x13 0xf 0x19 0x3e 0x51 0x45 0x8 0x76 0xb 0x85 0xe 0x1c 0x2e 0x3e 0x4d 0x52 0x52 0x57 0x3d 0x1b 0x6a 0x2d 0x25 0x43 0x52 0x87 0x8f 0x91 0x94 0x52 0x82 0x8c 0x92 0x96 0xff 0x7b 0xbb 0xcb 0x2f 0x7d 0x72 0xa5 0xb5 0xc1 0x46 0xae>; | |
| monitor_sec = <0x5>; | |
| virtual_power = <0x0>; | |
| }; | |
| }; | |
| i2c@ff130000 { | |
| compatible = "rockchip,rk3399-i2c"; | |
| reg = <0x0 0xff130000 0x0 0x1000>; | |
| clocks = <0x8 0x43 0x8 0x157>; | |
| clock-names = "i2c", "pclk"; | |
| interrupts = <0x0 0x22 0x4 0x0>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x3f>; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| status = "disabled"; | |
| i2c-scl-rising-time-ns = <0x1c2>; | |
| i2c-scl-falling-time-ns = <0xf>; | |
| phandle = <0x104>; | |
| }; | |
| i2c@ff140000 { | |
| compatible = "rockchip,rk3399-i2c"; | |
| reg = <0x0 0xff140000 0x0 0x1000>; | |
| clocks = <0x8 0x44 0x8 0x158>; | |
| clock-names = "i2c", "pclk"; | |
| interrupts = <0x0 0x26 0x4 0x0>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x40>; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| status = "disabled"; | |
| phandle = <0x105>; | |
| }; | |
| i2c@ff150000 { | |
| compatible = "rockchip,rk3399-i2c"; | |
| reg = <0x0 0xff150000 0x0 0x1000>; | |
| clocks = <0x8 0x45 0x8 0x159>; | |
| clock-names = "i2c", "pclk"; | |
| interrupts = <0x0 0x25 0x4 0x0>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x41>; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| status = "disabled"; | |
| phandle = <0x106>; | |
| }; | |
| i2c@ff160000 { | |
| compatible = "rockchip,rk3399-i2c"; | |
| reg = <0x0 0xff160000 0x0 0x1000>; | |
| clocks = <0x8 0x46 0x8 0x15a>; | |
| clock-names = "i2c", "pclk"; | |
| interrupts = <0x0 0x24 0x4 0x0>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x42>; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| status = "okay"; | |
| i2c-scl-rising-time-ns = <0x159>; | |
| i2c-scl-falling-time-ns = <0xb>; | |
| clock-frequency = <0x61a80>; | |
| phandle = <0x107>; | |
| fusb30x@22 { | |
| compatible = "fairchild,fusb302"; | |
| reg = <0x22>; | |
| charge-dev = <0x43>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x44>; | |
| int-n-gpios = <0x37 0x2 0x0>; | |
| status = "okay"; | |
| phandle = <0x29>; | |
| }; | |
| mp8859@66 { | |
| compatible = "mps,mp8859"; | |
| reg = <0x66>; | |
| status = "okay"; | |
| extcon = <0x29>; | |
| mp,max-input-voltage = <0xe4e1c0>; | |
| mp,max-input-current = <0x2dc6c0>; | |
| phandle = <0x43>; | |
| regulators { | |
| mp8859_dcdc1 { | |
| regulator-name = "sys_12v"; | |
| regulator-min-microvolt = <0xb71b00>; | |
| regulator-max-microvolt = <0xb71b00>; | |
| regulator-ramp-delay = <0x1f40>; | |
| regulator-always-on; | |
| regulator-boot-on; | |
| phandle = <0x108>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| serial@ff180000 { | |
| compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; | |
| reg = <0x0 0xff180000 0x0 0x100>; | |
| clocks = <0x8 0x51 0x8 0x160>; | |
| clock-names = "baudclk", "apb_pclk"; | |
| interrupts = <0x0 0x63 0x4 0x0>; | |
| reg-shift = <0x2>; | |
| reg-io-width = <0x4>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x45 0x46>; | |
| status = "okay"; | |
| assigned-clocks = <0x8 0xac>; | |
| assigned-clock-parents = <0x8 0x5>; | |
| phandle = <0x109>; | |
| }; | |
| serial@ff190000 { | |
| compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; | |
| reg = <0x0 0xff190000 0x0 0x100>; | |
| clocks = <0x8 0x52 0x8 0x161>; | |
| clock-names = "baudclk", "apb_pclk"; | |
| interrupts = <0x0 0x62 0x4 0x0>; | |
| reg-shift = <0x2>; | |
| reg-io-width = <0x4>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x47>; | |
| status = "disabled"; | |
| assigned-clocks = <0x8 0xad>; | |
| assigned-clock-parents = <0x8 0x5>; | |
| phandle = <0x10a>; | |
| }; | |
| serial@ff1a0000 { | |
| compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; | |
| reg = <0x0 0xff1a0000 0x0 0x100>; | |
| clocks = <0x8 0x53 0x8 0x162>; | |
| clock-names = "baudclk", "apb_pclk"; | |
| interrupts = <0x0 0x64 0x4 0x0>; | |
| reg-shift = <0x2>; | |
| reg-io-width = <0x4>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x48>; | |
| status = "okay"; | |
| assigned-clocks = <0x8 0xad>; | |
| assigned-clock-parents = <0x8 0x5>; | |
| phandle = <0x10b>; | |
| }; | |
| serial@ff1b0000 { | |
| compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; | |
| reg = <0x0 0xff1b0000 0x0 0x100>; | |
| clocks = <0x8 0x54 0x8 0x163>; | |
| clock-names = "baudclk", "apb_pclk"; | |
| interrupts = <0x0 0x65 0x4 0x0>; | |
| reg-shift = <0x2>; | |
| reg-io-width = <0x4>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x49 0x4a 0x4b>; | |
| status = "disabled"; | |
| assigned-clocks = <0x8 0xad>; | |
| assigned-clock-parents = <0x8 0x5>; | |
| phandle = <0x10c>; | |
| }; | |
| spi@ff1c0000 { | |
| compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; | |
| reg = <0x0 0xff1c0000 0x0 0x1000>; | |
| clocks = <0x8 0x47 0x8 0x15b>; | |
| clock-names = "spiclk", "apb_pclk"; | |
| interrupts = <0x0 0x44 0x4 0x0>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x4c 0x4d 0x4e 0x4f>; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| status = "disabled"; | |
| phandle = <0x10d>; | |
| }; | |
| spi@ff1d0000 { | |
| compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; | |
| reg = <0x0 0xff1d0000 0x0 0x1000>; | |
| clocks = <0x8 0x48 0x8 0x15c>; | |
| clock-names = "spiclk", "apb_pclk"; | |
| interrupts = <0x0 0x35 0x4 0x0>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x50 0x51 0x52 0x53>; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| status = "disabled"; | |
| phandle = <0x10e>; | |
| }; | |
| spi@ff1e0000 { | |
| compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; | |
| reg = <0x0 0xff1e0000 0x0 0x1000>; | |
| clocks = <0x8 0x49 0x8 0x15d>; | |
| clock-names = "spiclk", "apb_pclk"; | |
| interrupts = <0x0 0x34 0x4 0x0>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x54 0x55 0x56 0x57>; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| status = "disabled"; | |
| phandle = <0x10f>; | |
| }; | |
| spi@ff1f0000 { | |
| compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; | |
| reg = <0x0 0xff1f0000 0x0 0x1000>; | |
| clocks = <0x8 0x4a 0x8 0x15e>; | |
| clock-names = "spiclk", "apb_pclk"; | |
| interrupts = <0x0 0x43 0x4 0x0>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x58 0x59 0x5a 0x5b>; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| status = "disabled"; | |
| phandle = <0x110>; | |
| }; | |
| spi@ff200000 { | |
| compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; | |
| reg = <0x0 0xff200000 0x0 0x1000>; | |
| clocks = <0x8 0x4b 0x8 0x15f>; | |
| clock-names = "spiclk", "apb_pclk"; | |
| interrupts = <0x0 0x84 0x4 0x0>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x5c 0x5d 0x5e 0x5f>; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| status = "disabled"; | |
| phandle = <0x111>; | |
| }; | |
| thermal-zones { | |
| phandle = <0x112>; | |
| soc-thermal { | |
| polling-delay-passive = <0x14>; | |
| polling-delay = <0x3e8>; | |
| sustainable-power = <0x3e8>; | |
| thermal-sensors = <0x60 0x0>; | |
| phandle = <0x113>; | |
| trips { | |
| trip-point-0 { | |
| temperature = <0x11170>; | |
| hysteresis = <0x7d0>; | |
| type = "passive"; | |
| phandle = <0x114>; | |
| }; | |
| trip-point-1 { | |
| temperature = <0x14c08>; | |
| hysteresis = <0x7d0>; | |
| type = "passive"; | |
| phandle = <0x61>; | |
| }; | |
| soc-crit { | |
| temperature = <0x1c138>; | |
| hysteresis = <0x7d0>; | |
| type = "critical"; | |
| phandle = <0x115>; | |
| }; | |
| }; | |
| cooling-maps { | |
| map0 { | |
| trip = <0x61>; | |
| cooling-device = <0x2 0xffffffff 0xffffffff>; | |
| contribution = <0x1000>; | |
| }; | |
| map1 { | |
| trip = <0x61>; | |
| cooling-device = <0x6 0xffffffff 0xffffffff>; | |
| contribution = <0x400>; | |
| }; | |
| map2 { | |
| trip = <0x61>; | |
| cooling-device = <0x62 0xffffffff 0xffffffff>; | |
| contribution = <0x1000>; | |
| }; | |
| }; | |
| }; | |
| gpu-thermal { | |
| polling-delay-passive = <0x64>; | |
| polling-delay = <0x3e8>; | |
| thermal-sensors = <0x60 0x1>; | |
| phandle = <0x116>; | |
| }; | |
| }; | |
| tsadc@ff260000 { | |
| compatible = "rockchip,rk3399-tsadc"; | |
| reg = <0x0 0xff260000 0x0 0x100>; | |
| interrupts = <0x0 0x61 0x4 0x0>; | |
| assigned-clocks = <0x8 0x4f>; | |
| assigned-clock-rates = <0xb71b0>; | |
| clocks = <0x8 0x4f 0x8 0x164>; | |
| clock-names = "tsadc", "apb_pclk"; | |
| resets = <0x8 0xe8>; | |
| reset-names = "tsadc-apb"; | |
| rockchip,grf = <0x17>; | |
| rockchip,hw-tshut-temp = <0x1d4c0>; | |
| pinctrl-names = "init", "default", "sleep"; | |
| pinctrl-0 = <0x63>; | |
| pinctrl-1 = <0x64>; | |
| pinctrl-2 = <0x63>; | |
| #thermal-sensor-cells = <0x1>; | |
| status = "okay"; | |
| rockchip,hw-tshut-mode = <0x1>; | |
| rockchip,hw-tshut-polarity = <0x1>; | |
| phandle = <0x60>; | |
| }; | |
| qos@ffa58000 { | |
| compatible = "syscon"; | |
| reg = <0x0 0xffa58000 0x0 0x20>; | |
| phandle = <0x6c>; | |
| }; | |
| qos@ffa5c000 { | |
| compatible = "syscon"; | |
| reg = <0x0 0xffa5c000 0x0 0x20>; | |
| phandle = <0x6d>; | |
| }; | |
| qos@ffa60080 { | |
| compatible = "syscon"; | |
| reg = <0x0 0xffa60080 0x0 0x20>; | |
| phandle = <0x6f>; | |
| }; | |
| qos@ffa60100 { | |
| compatible = "syscon"; | |
| reg = <0x0 0xffa60100 0x0 0x20>; | |
| phandle = <0x70>; | |
| }; | |
| qos@ffa60180 { | |
| compatible = "syscon"; | |
| reg = <0x0 0xffa60180 0x0 0x20>; | |
| phandle = <0x71>; | |
| }; | |
| qos@ffa70000 { | |
| compatible = "syscon"; | |
| reg = <0x0 0xffa70000 0x0 0x20>; | |
| phandle = <0x74>; | |
| }; | |
| qos@ffa70080 { | |
| compatible = "syscon"; | |
| reg = <0x0 0xffa70080 0x0 0x20>; | |
| phandle = <0x75>; | |
| }; | |
| qos@ffa74000 { | |
| compatible = "syscon"; | |
| reg = <0x0 0xffa74000 0x0 0x20>; | |
| phandle = <0x72>; | |
| }; | |
| qos@ffa76000 { | |
| compatible = "syscon"; | |
| reg = <0x0 0xffa76000 0x0 0x20>; | |
| phandle = <0x73>; | |
| }; | |
| qos@ffa90000 { | |
| compatible = "syscon"; | |
| reg = <0x0 0xffa90000 0x0 0x20>; | |
| phandle = <0x76>; | |
| }; | |
| qos@ffa98000 { | |
| compatible = "syscon"; | |
| reg = <0x0 0xffa98000 0x0 0x20>; | |
| phandle = <0x65>; | |
| }; | |
| qos@ffaa0000 { | |
| compatible = "syscon"; | |
| reg = <0x0 0xffaa0000 0x0 0x20>; | |
| phandle = <0x77>; | |
| }; | |
| qos@ffaa0080 { | |
| compatible = "syscon"; | |
| reg = <0x0 0xffaa0080 0x0 0x20>; | |
| phandle = <0x78>; | |
| }; | |
| qos@ffaa8000 { | |
| compatible = "syscon"; | |
| reg = <0x0 0xffaa8000 0x0 0x20>; | |
| phandle = <0x79>; | |
| }; | |
| qos@ffaa8080 { | |
| compatible = "syscon"; | |
| reg = <0x0 0xffaa8080 0x0 0x20>; | |
| phandle = <0x7a>; | |
| }; | |
| qos@ffab0000 { | |
| compatible = "syscon"; | |
| reg = <0x0 0xffab0000 0x0 0x20>; | |
| phandle = <0x66>; | |
| }; | |
| qos@ffab0080 { | |
| compatible = "syscon"; | |
| reg = <0x0 0xffab0080 0x0 0x20>; | |
| phandle = <0x67>; | |
| }; | |
| qos@ffab8000 { | |
| compatible = "syscon"; | |
| reg = <0x0 0xffab8000 0x0 0x20>; | |
| phandle = <0x68>; | |
| }; | |
| qos@ffac0000 { | |
| compatible = "syscon"; | |
| reg = <0x0 0xffac0000 0x0 0x20>; | |
| phandle = <0x69>; | |
| }; | |
| qos@ffac0080 { | |
| compatible = "syscon"; | |
| reg = <0x0 0xffac0080 0x0 0x20>; | |
| phandle = <0x6a>; | |
| }; | |
| qos@ffac8000 { | |
| compatible = "syscon"; | |
| reg = <0x0 0xffac8000 0x0 0x20>; | |
| phandle = <0x7b>; | |
| }; | |
| qos@ffac8080 { | |
| compatible = "syscon"; | |
| reg = <0x0 0xffac8080 0x0 0x20>; | |
| phandle = <0x7c>; | |
| }; | |
| qos@ffad0000 { | |
| compatible = "syscon"; | |
| reg = <0x0 0xffad0000 0x0 0x20>; | |
| phandle = <0x7d>; | |
| }; | |
| qos@ffad8080 { | |
| compatible = "syscon"; | |
| reg = <0x0 0xffad8080 0x0 0x20>; | |
| phandle = <0x6e>; | |
| }; | |
| qos@ffae0000 { | |
| compatible = "syscon"; | |
| reg = <0x0 0xffae0000 0x0 0x20>; | |
| phandle = <0x6b>; | |
| }; | |
| power-management@ff310000 { | |
| compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd"; | |
| reg = <0x0 0xff310000 0x0 0x1000>; | |
| phandle = <0x117>; | |
| power-controller { | |
| compatible = "rockchip,rk3399-power-controller"; | |
| #power-domain-cells = <0x1>; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| phandle = <0x16>; | |
| pd_iep@34 { | |
| reg = <0x22>; | |
| clocks = <0x8 0xe1 0x8 0x1dd>; | |
| pm_qos = <0x65>; | |
| }; | |
| pd_rga@33 { | |
| reg = <0x21>; | |
| clocks = <0x8 0xdc 0x8 0x1e5>; | |
| pm_qos = <0x66 0x67>; | |
| }; | |
| pd_vcodec@31 { | |
| reg = <0x1f>; | |
| clocks = <0x8 0xeb 0x8 0x1ea>; | |
| pm_qos = <0x68>; | |
| }; | |
| pd_vdu@32 { | |
| reg = <0x20>; | |
| clocks = <0x8 0xed 0x8 0x1ec>; | |
| pm_qos = <0x69 0x6a>; | |
| }; | |
| pd_gpu@35 { | |
| reg = <0x23>; | |
| clocks = <0x8 0xd0>; | |
| pm_qos = <0x6b>; | |
| }; | |
| pd_edp@25 { | |
| reg = <0x19>; | |
| clocks = <0x8 0x16c>; | |
| }; | |
| pd_emmc@23 { | |
| reg = <0x17>; | |
| clocks = <0x8 0xf0>; | |
| pm_qos = <0x6c>; | |
| }; | |
| pd_gmac@22 { | |
| reg = <0x16>; | |
| clocks = <0x8 0xd5 0x8 0x166>; | |
| pm_qos = <0x6d>; | |
| }; | |
| pd_perihp@14 { | |
| reg = <0xe>; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| clocks = <0x8 0xc0>; | |
| pm_qos = <0x6e 0x6f 0x70 0x71>; | |
| pd_sd@27 { | |
| reg = <0x1b>; | |
| clocks = <0x8 0x1ce 0x8 0x4c>; | |
| pm_qos = <0x72>; | |
| }; | |
| }; | |
| pd_sdioaudio@28 { | |
| reg = <0x1c>; | |
| clocks = <0x8 0x1ee>; | |
| pm_qos = <0x73>; | |
| }; | |
| pd_usb3@24 { | |
| reg = <0x18>; | |
| clocks = <0x8 0xf4>; | |
| pm_qos = <0x74 0x75>; | |
| }; | |
| pd_vio@15 { | |
| reg = <0xf>; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| pd_hdcp@21 { | |
| reg = <0x15>; | |
| clocks = <0x8 0xde 0x8 0x1e7 0x8 0x172>; | |
| pm_qos = <0x76>; | |
| }; | |
| pd_isp0@19 { | |
| reg = <0x13>; | |
| clocks = <0x8 0xe5 0x8 0x1df>; | |
| pm_qos = <0x77 0x78>; | |
| }; | |
| pd_isp1@20 { | |
| reg = <0x14>; | |
| clocks = <0x8 0xe6 0x8 0x1e0>; | |
| pm_qos = <0x79 0x7a>; | |
| }; | |
| pd_tcpc0@RK3399_PD_TCPC0 { | |
| reg = <0x8>; | |
| clocks = <0x8 0x7e 0x8 0x7d>; | |
| }; | |
| pd_tcpc1@RK3399_PD_TCPC1 { | |
| reg = <0x9>; | |
| clocks = <0x8 0x80 0x8 0x7f>; | |
| }; | |
| pd_vo@16 { | |
| reg = <0x10>; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| pd_vopb@17 { | |
| reg = <0x11>; | |
| clocks = <0x8 0xd9 0x8 0x1d9>; | |
| pm_qos = <0x7b 0x7c>; | |
| }; | |
| pd_vopl@18 { | |
| reg = <0x12>; | |
| clocks = <0x8 0xdb 0x8 0x1db>; | |
| pm_qos = <0x7d>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| }; | |
| syscon@ff320000 { | |
| compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd"; | |
| reg = <0x0 0xff320000 0x0 0x1000>; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x1>; | |
| phandle = <0x91>; | |
| io-domains { | |
| compatible = "rockchip,rk3399-pmu-io-voltage-domain"; | |
| status = "okay"; | |
| pmu1830-supply = <0x7e>; | |
| phandle = <0x118>; | |
| }; | |
| reboot-mode { | |
| compatible = "syscon-reboot-mode"; | |
| offset = <0x300>; | |
| mode-bootloader = <0x5242c301>; | |
| mode-charge = <0x5242c30b>; | |
| mode-fastboot = <0x5242c309>; | |
| mode-loader = <0x5242c301>; | |
| mode-normal = <0x5242c300>; | |
| mode-recovery = <0x5242c303>; | |
| mode-ums = <0x5242c30c>; | |
| }; | |
| pmu-pvtm { | |
| compatible = "rockchip,rk3399-pmu-pvtm"; | |
| clocks = <0x33 0x7>; | |
| clock-names = "pmu"; | |
| resets = <0x8 0x1b>; | |
| reset-names = "pmu"; | |
| status = "disabled"; | |
| phandle = <0x119>; | |
| }; | |
| }; | |
| spi@ff350000 { | |
| compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; | |
| reg = <0x0 0xff350000 0x0 0x1000>; | |
| clocks = <0x33 0x3 0x33 0x1f>; | |
| clock-names = "spiclk", "apb_pclk"; | |
| interrupts = <0x0 0x3c 0x4 0x0>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x7f 0x80 0x81 0x82>; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| status = "disabled"; | |
| phandle = <0x11a>; | |
| }; | |
| serial@ff370000 { | |
| compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; | |
| reg = <0x0 0xff370000 0x0 0x100>; | |
| clocks = <0x33 0x6 0x33 0x22>; | |
| clock-names = "baudclk", "apb_pclk"; | |
| interrupts = <0x0 0x66 0x4 0x0>; | |
| reg-shift = <0x2>; | |
| reg-io-width = <0x4>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x83>; | |
| status = "disabled"; | |
| assigned-clocks = <0x33 0xc>; | |
| assigned-clock-parents = <0x33 0x1>; | |
| phandle = <0x11b>; | |
| }; | |
| i2c@ff3d0000 { | |
| compatible = "rockchip,rk3399-i2c"; | |
| reg = <0x0 0xff3d0000 0x0 0x1000>; | |
| clocks = <0x33 0xa 0x33 0x1c>; | |
| clock-names = "i2c", "pclk"; | |
| interrupts = <0x0 0x38 0x4 0x0>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x84>; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| status = "okay"; | |
| i2c-scl-rising-time-ns = <0x1db>; | |
| i2c-scl-falling-time-ns = <0x1a>; | |
| phandle = <0x11c>; | |
| gsl3680@40 { | |
| status = "disabled"; | |
| compatible = "gslX680"; | |
| reg = <0x40>; | |
| screen_max_x = <0x600>; | |
| screen_max_y = <0x800>; | |
| revert_xy = <0x0>; | |
| revert_x = <0x0>; | |
| revert_y = <0x0>; | |
| touch-gpio = <0x85 0x1c 0x8>; | |
| reset-gpio = <0x85 0x15 0x0>; | |
| phandle = <0x11d>; | |
| }; | |
| fusb30x@22 { | |
| compatible = "fairchild,fusb302"; | |
| reg = <0x22>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x86 0x87>; | |
| int-n-gpios = <0x37 0x1 0x0>; | |
| vbus-5v-gpios = <0x37 0xd 0x0>; | |
| status = "okay"; | |
| phandle = <0x2c>; | |
| }; | |
| }; | |
| i2c@ff3e0000 { | |
| compatible = "rockchip,rk3399-i2c"; | |
| reg = <0x0 0xff3e0000 0x0 0x1000>; | |
| clocks = <0x33 0xb 0x33 0x1d>; | |
| clock-names = "i2c", "pclk"; | |
| interrupts = <0x0 0x3a 0x4 0x0>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x88>; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| status = "disabled"; | |
| phandle = <0x11e>; | |
| }; | |
| pcie-phy { | |
| compatible = "rockchip,rk3399-pcie-phy"; | |
| #phy-cells = <0x0>; | |
| rockchip,grf = <0x17>; | |
| clocks = <0x8 0x8a>; | |
| clock-names = "refclk"; | |
| resets = <0x8 0x87>; | |
| reset-names = "phy"; | |
| status = "okay"; | |
| phandle = <0x8b>; | |
| }; | |
| pcie@f8000000 { | |
| compatible = "rockchip,rk3399-pcie"; | |
| #address-cells = <0x3>; | |
| #size-cells = <0x2>; | |
| aspm-no-l0s; | |
| clocks = <0x8 0xc5 0x8 0xc4 0x8 0x147 0x8 0xa0>; | |
| clock-names = "aclk", "aclk-perf", "hclk", "pm"; | |
| bus-range = <0x0 0x1f>; | |
| max-link-speed = <0x1>; | |
| linux,pci-domain = <0x0>; | |
| msi-map = <0x0 0x89 0x0 0x1000>; | |
| interrupts = <0x0 0x31 0x4 0x0 0x0 0x32 0x4 0x0 0x0 0x33 0x4 0x0>; | |
| interrupt-names = "sys", "legacy", "client"; | |
| #interrupt-cells = <0x1>; | |
| interrupt-map-mask = <0x0 0x0 0x0 0x7>; | |
| interrupt-map = <0x0 0x0 0x0 0x1 0x8a 0x0 0x0 0x0 0x0 0x2 0x8a 0x1 0x0 0x0 0x0 0x3 0x8a 0x2 0x0 0x0 0x0 0x4 0x8a 0x3>; | |
| phys = <0x8b>; | |
| phy-names = "pcie-phy"; | |
| ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000 0x81000000 0x0 0xfbe00000 0x0 0xfbe00000 0x0 0x100000>; | |
| reg = <0x0 0xf8000000 0x0 0x2000000 0x0 0xfd000000 0x0 0x1000000>; | |
| reg-names = "axi-base", "apb-base"; | |
| resets = <0x8 0x82 0x8 0x83 0x8 0x84 0x8 0x85 0x8 0x86 0x8 0x81 0x8 0x80>; | |
| reset-names = "core", "mgmt", "mgmt-sticky", "pipe", "pm", "pclk", "aclk"; | |
| status = "okay"; | |
| ep-gpios = <0x85 0x19 0x0>; | |
| num-lanes = <0x4>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x8c>; | |
| phandle = <0x11f>; | |
| interrupt-controller { | |
| interrupt-controller; | |
| #address-cells = <0x0>; | |
| #interrupt-cells = <0x1>; | |
| phandle = <0x8a>; | |
| }; | |
| }; | |
| pwm@ff420000 { | |
| compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; | |
| reg = <0x0 0xff420000 0x0 0x10>; | |
| #pwm-cells = <0x3>; | |
| pinctrl-names = "active"; | |
| pinctrl-0 = <0x8d>; | |
| clocks = <0x33 0x1e>; | |
| clock-names = "pwm"; | |
| status = "okay"; | |
| phandle = <0x120>; | |
| }; | |
| pwm@ff420010 { | |
| compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; | |
| reg = <0x0 0xff420010 0x0 0x10>; | |
| #pwm-cells = <0x3>; | |
| pinctrl-names = "active"; | |
| pinctrl-0 = <0x8e>; | |
| clocks = <0x33 0x1e>; | |
| clock-names = "pwm"; | |
| status = "okay"; | |
| phandle = <0xcb>; | |
| }; | |
| pwm@ff420020 { | |
| compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; | |
| reg = <0x0 0xff420020 0x0 0x10>; | |
| #pwm-cells = <0x3>; | |
| pinctrl-names = "active"; | |
| pinctrl-0 = <0x8f>; | |
| clocks = <0x33 0x1e>; | |
| clock-names = "pwm"; | |
| status = "okay"; | |
| phandle = <0xdb>; | |
| }; | |
| pwm@ff420030 { | |
| compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; | |
| reg = <0x0 0xff420030 0x0 0x10>; | |
| #pwm-cells = <0x3>; | |
| pinctrl-names = "active"; | |
| pinctrl-0 = <0x90>; | |
| clocks = <0x33 0x1e>; | |
| clock-names = "pwm"; | |
| status = "disabled"; | |
| phandle = <0x121>; | |
| }; | |
| dfi@ff630000 { | |
| reg = <0x0 0xff630000 0x0 0x4000>; | |
| compatible = "rockchip,rk3399-dfi"; | |
| rockchip,pmu = <0x91>; | |
| clocks = <0x8 0x179>; | |
| clock-names = "pclk_ddr_mon"; | |
| status = "disabled"; | |
| phandle = <0x92>; | |
| }; | |
| dmc { | |
| compatible = "rockchip,rk3399-dmc"; | |
| devfreq-events = <0x92>; | |
| interrupts = <0x0 0x1 0x4 0x0>; | |
| clocks = <0x8 0xaa>; | |
| clock-names = "dmc_clk"; | |
| ddr_timing = <0x93>; | |
| upthreshold = <0x28>; | |
| downdifferential = <0x14>; | |
| system-status-freq = <0x1 0xc3500 0x8 0x80e80 0x2 0x30d40 0x20 0x493e0 0x10 0x927c0 0x10000 0xc3500 0x2000 0xc3500 0x1000 0x61a80 0xc00 0x927c0 0x4000 0x927c0>; | |
| auto-min-freq = <0x61a80>; | |
| auto-freq-en = <0x1>; | |
| status = "disabled"; | |
| operating-points-v2 = <0x94>; | |
| phandle = <0xaf>; | |
| }; | |
| vpu_service@ff650000 { | |
| compatible = "rockchip,vpu_service"; | |
| rockchip,grf = <0x17>; | |
| iommus = <0x95>; | |
| iommu_enabled = <0x1>; | |
| reg = <0x0 0xff650000 0x0 0x800>; | |
| interrupts = <0x0 0x71 0x4 0x0 0x0 0x72 0x4 0x0>; | |
| interrupt-names = "irq_dec", "irq_enc"; | |
| clocks = <0x8 0xeb 0x8 0x1ea>; | |
| clock-names = "aclk_vcodec", "hclk_vcodec"; | |
| resets = <0x8 0x53 0x8 0x51>; | |
| reset-names = "video_h", "video_a"; | |
| power-domains = <0x16 0x1f>; | |
| dev_mode = <0x0>; | |
| allocator = <0x1>; | |
| status = "okay"; | |
| phandle = <0x122>; | |
| }; | |
| iommu@ff650800 { | |
| compatible = "rockchip,iommu"; | |
| reg = <0x0 0xff650800 0x0 0x40>; | |
| interrupts = <0x0 0x73 0x4 0x0>; | |
| interrupt-names = "vpu_mmu"; | |
| clocks = <0x8 0xeb 0x8 0x1ea>; | |
| clock-names = "aclk", "hclk"; | |
| power-domains = <0x16 0x1f>; | |
| #iommu-cells = <0x0>; | |
| phandle = <0x95>; | |
| }; | |
| rkvdec@ff660000 { | |
| compatible = "rockchip,rkvdec"; | |
| rockchip,grf = <0x17>; | |
| iommus = <0x96>; | |
| iommu_enabled = <0x1>; | |
| reg = <0x0 0xff660000 0x0 0x400>; | |
| interrupts = <0x0 0x74 0x4 0x0>; | |
| interrupt-names = "irq_dec"; | |
| clocks = <0x8 0xed 0x8 0x1ec 0x8 0x9f 0x8 0x9e>; | |
| clock-names = "aclk_vcodec", "hclk_vcodec", "clk_cabac", "clk_core"; | |
| resets = <0x8 0x5b 0x8 0x59 0x8 0x5c 0x8 0x5d 0x8 0x58 0x8 0x5a>; | |
| reset-names = "video_h", "video_a", "video_core", "video_cabac", "niu_a", "niu_h"; | |
| power-domains = <0x16 0x20>; | |
| dev_mode = <0x2>; | |
| allocator = <0x1>; | |
| status = "okay"; | |
| phandle = <0x123>; | |
| }; | |
| iommu@ff660480 { | |
| compatible = "rockchip,iommu"; | |
| reg = <0x0 0xff660480 0x0 0x40 0x0 0xff6604c0 0x0 0x40>; | |
| interrupts = <0x0 0x75 0x4 0x0>; | |
| interrupt-names = "vdec_mmu"; | |
| clocks = <0x8 0xed 0x8 0x1ec>; | |
| clock-names = "aclk", "hclk"; | |
| power-domains = <0x16 0x20>; | |
| #iommu-cells = <0x0>; | |
| phandle = <0x96>; | |
| }; | |
| iep@ff670000 { | |
| compatible = "rockchip,iep"; | |
| iommu_enabled = <0x1>; | |
| iommus = <0x97>; | |
| reg = <0x0 0xff670000 0x0 0x800>; | |
| interrupts = <0x0 0x2a 0x4 0x0>; | |
| clocks = <0x8 0xe1 0x8 0x1dd>; | |
| clock-names = "aclk_iep", "hclk_iep"; | |
| power-domains = <0x16 0x22>; | |
| allocator = <0x1>; | |
| version = <0x2>; | |
| status = "disabled"; | |
| phandle = <0x124>; | |
| }; | |
| iommu@ff670800 { | |
| compatible = "rockchip,iommu"; | |
| reg = <0x0 0xff670800 0x0 0x40>; | |
| interrupts = <0x0 0x2a 0x4 0x0>; | |
| interrupt-names = "iep_mmu"; | |
| #iommu-cells = <0x0>; | |
| status = "disabled"; | |
| phandle = <0x97>; | |
| }; | |
| rga@ff680000 { | |
| compatible = "rockchip,rk3399-rga"; | |
| reg = <0x0 0xff680000 0x0 0x10000>; | |
| interrupts = <0x0 0x37 0x4 0x0>; | |
| clocks = <0x8 0xdc 0x8 0x1e5 0x8 0x6d>; | |
| clock-names = "aclk", "hclk", "sclk"; | |
| resets = <0x8 0x6a 0x8 0x67 0x8 0x69>; | |
| reset-names = "core", "axi", "ahb"; | |
| power-domains = <0x16 0x21>; | |
| status = "disabled"; | |
| phandle = <0x125>; | |
| }; | |
| efuse@ff690000 { | |
| compatible = "rockchip,rk3399-efuse"; | |
| reg = <0x0 0xff690000 0x0 0x80>; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x1>; | |
| clocks = <0x8 0x17d>; | |
| clock-names = "pclk_efuse"; | |
| phandle = <0x126>; | |
| cpu-id@7 { | |
| reg = <0x7 0x10>; | |
| phandle = <0x15>; | |
| }; | |
| cpu-leakage@17 { | |
| reg = <0x17 0x1>; | |
| phandle = <0xc9>; | |
| }; | |
| gpu-leakage@18 { | |
| reg = <0x18 0x1>; | |
| phandle = <0xca>; | |
| }; | |
| center-leakage@19 { | |
| reg = <0x19 0x1>; | |
| phandle = <0x127>; | |
| }; | |
| cpu-leakage@1a { | |
| reg = <0x1a 0x1>; | |
| phandle = <0xc8>; | |
| }; | |
| logic-leakage@1b { | |
| reg = <0x1b 0x1>; | |
| phandle = <0x128>; | |
| }; | |
| wafer-info@1c { | |
| reg = <0x1c 0x1>; | |
| phandle = <0x129>; | |
| }; | |
| }; | |
| pmu-clock-controller@ff750000 { | |
| compatible = "rockchip,rk3399-pmucru"; | |
| reg = <0x0 0xff750000 0x0 0x1000>; | |
| #clock-cells = <0x1>; | |
| #reset-cells = <0x1>; | |
| assigned-clocks = <0x33 0x1 0x33 0x2c>; | |
| assigned-clock-rates = <0x284af100 0x5c81a40>; | |
| phandle = <0x33>; | |
| }; | |
| clock-controller@ff760000 { | |
| compatible = "rockchip,rk3399-cru"; | |
| reg = <0x0 0xff760000 0x0 0x1000>; | |
| #clock-cells = <0x1>; | |
| #reset-cells = <0x1>; | |
| assigned-clocks = <0x8 0xc0 0x8 0xc2 0x8 0x1c2 0x8 0x4c 0x8 0xf0 0x8 0xcd 0x8 0x1cd 0x8 0x9f 0x8 0x9e 0x8 0xf4 0x8 0xbe 0x8 0xc9 0x8 0x186 0x8 0xd5 0x8 0x88 0x8 0x87 0x8 0x8 0x8 0x9 0x8 0x6 0x8 0xd0 0x8 0x5 0x8 0xc0 0x8 0x1c0 0x8 0x140 0x8 0xc2 0x8 0x1c1 0x8 0x142 0x8 0x1c2 0x8 0x143 0x8 0x41 0x8 0x42 0x8 0x43 0x8 0x44 0x8 0x45 0x8 0x46 0x8 0x47 0x8 0x48 0x8 0x49 0x8 0x4a 0x8 0x4b 0x8 0xfa 0x8 0xe5 0x8 0xe6 0x8 0x6b 0x8 0x6c 0x8 0x16a 0x8 0xde 0x8 0xe3 0x8 0x1cd 0x8 0x85 0x8 0x86 0x8 0x4e 0x8 0xf0 0x8 0xcd 0x8 0xe1 0x8 0xdc 0x8 0x6d 0x8 0xed 0x8 0xeb 0x8 0x178 0x8 0xd5 0x8 0x9f 0x8 0x9e 0x8 0xf4 0x8 0xbe 0x8 0xc9 0x8 0x186 0x8 0x88 0x8 0x87 0x8 0xd9 0x8 0x1d9 0x8 0xdb 0x8 0x1db>; | |
| assigned-clock-rates = <0x47868c0 0x2faf080 0x2faf080 0x2faf080 0x2faf080 0x5f5e100 0x2faf080 0x8f0d180 0x8f0d180 0x8f0d180 0x2faf080 0x8f0d180 0x2faf080 0x5f5e100 0x47868c0 0x47868c0 0x30a32c00 0x30a32c00 0x23c34600 0xbebc200 0x2faf0800 0x8f0d180 0x47868c0 0x23c3460 0x11e1a300 0x5f5e100 0x2faf080 0x5f5e100 0x2faf080 0x5f5e100 0x5f5e100 0x5f5e100 0x5f5e100 0x5f5e100 0x5f5e100 0x2faf080 0x2faf080 0x2faf080 0x2faf080 0x2faf080 0xbebc200 0x17d78400 0x17d78400 0x5f5e100 0x5f5e100 0x5f5e100 0x17d78400 0x17d78400 0xbebc200 0x5f5e100 0xbebc200 0xbebc200 0x5f5e100 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x11e1a300 0x17d78400 0xbebc200 0x17d78400 0x11e1a300 0x11e1a300 0x11e1a300 0x11e1a300 0x11e1a300 0x5f5e100 0x8f0d180 0x8f0d180 0x17d78400 0x5f5e100 0x17d78400 0x5f5e100>; | |
| phandle = <0x8>; | |
| }; | |
| syscon@ff770000 { | |
| compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd"; | |
| reg = <0x0 0xff770000 0x0 0x10000>; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x1>; | |
| phandle = <0x17>; | |
| io-domains { | |
| compatible = "rockchip,rk3399-io-voltage-domain"; | |
| status = "okay"; | |
| bt656-supply = <0x7e>; | |
| audio-supply = <0x98>; | |
| sdmmc-supply = <0x21>; | |
| gpio1830-supply = <0x7e>; | |
| phandle = <0x12a>; | |
| }; | |
| usb2-phy@e450 { | |
| compatible = "rockchip,rk3399-usb2phy"; | |
| reg = <0xe450 0x10>; | |
| clocks = <0x8 0x7b>; | |
| clock-names = "phyclk"; | |
| #clock-cells = <0x0>; | |
| clock-output-names = "clk_usbphy0_480m"; | |
| status = "okay"; | |
| extcon = <0x29>; | |
| phandle = <0x12b>; | |
| host-port { | |
| #phy-cells = <0x0>; | |
| interrupts = <0x0 0x1b 0x4 0x0>; | |
| interrupt-names = "linestate"; | |
| status = "okay"; | |
| phy-supply = <0x99>; | |
| phandle = <0x27>; | |
| }; | |
| otg-port { | |
| #phy-cells = <0x0>; | |
| interrupts = <0x0 0x67 0x4 0x0 0x0 0x68 0x4 0x0 0x0 0x6a 0x4 0x0>; | |
| interrupt-names = "otg-bvalid", "otg-id", "linestate"; | |
| status = "okay"; | |
| phandle = <0x2a>; | |
| }; | |
| }; | |
| usb2-phy@e460 { | |
| compatible = "rockchip,rk3399-usb2phy"; | |
| reg = <0xe460 0x10>; | |
| clocks = <0x8 0x7c>; | |
| clock-names = "phyclk"; | |
| #clock-cells = <0x0>; | |
| clock-output-names = "clk_usbphy1_480m"; | |
| status = "okay"; | |
| extcon = <0x2c>; | |
| phandle = <0x12c>; | |
| host-port { | |
| #phy-cells = <0x0>; | |
| interrupts = <0x0 0x1f 0x4 0x0>; | |
| interrupt-names = "linestate"; | |
| status = "okay"; | |
| phy-supply = <0x99>; | |
| phandle = <0x28>; | |
| }; | |
| otg-port { | |
| #phy-cells = <0x0>; | |
| interrupts = <0x0 0x6c 0x4 0x0 0x0 0x6d 0x4 0x0 0x0 0x6f 0x4 0x0>; | |
| interrupt-names = "otg-bvalid", "otg-id", "linestate"; | |
| status = "okay"; | |
| phandle = <0x2d>; | |
| }; | |
| }; | |
| phy@f780 { | |
| compatible = "rockchip,rk3399-emmc-phy"; | |
| reg = <0xf780 0x24>; | |
| clocks = <0x9a>; | |
| clock-names = "emmcclk"; | |
| #phy-cells = <0x0>; | |
| status = "okay"; | |
| phandle = <0x26>; | |
| }; | |
| mipi-dphy-rx0 { | |
| compatible = "rockchip,rk3399-mipi-dphy"; | |
| clocks = <0x8 0x77 0x8 0xa5 0x8 0x16f>; | |
| clock-names = "dphy-ref", "dphy-cfg", "grf"; | |
| power-domains = <0x16 0xf>; | |
| status = "disabled"; | |
| phandle = <0x12d>; | |
| }; | |
| pvtm { | |
| compatible = "rockchip,rk3399-pvtm"; | |
| clocks = <0x8 0x73 0x8 0x74 0x8 0x75 0x8 0x76>; | |
| clock-names = "core_l", "core_b", "gpu", "ddr"; | |
| resets = <0x8 0x1f 0x8 0x2f 0x8 0x123 0x8 0x4f>; | |
| reset-names = "core_l", "core_b", "gpu", "ddr"; | |
| status = "disabled"; | |
| phandle = <0x12e>; | |
| }; | |
| }; | |
| phy@ff7c0000 { | |
| compatible = "rockchip,rk3399-typec-phy"; | |
| reg = <0x0 0xff7c0000 0x0 0x40000>; | |
| #phy-cells = <0x1>; | |
| clocks = <0x8 0x7e 0x8 0x7d>; | |
| clock-names = "tcpdcore", "tcpdphy-ref"; | |
| assigned-clocks = <0x8 0x7e>; | |
| assigned-clock-rates = <0x2faf080>; | |
| power-domains = <0x16 0x8>; | |
| resets = <0x8 0x95 0x8 0x94 0x8 0x14c>; | |
| reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; | |
| rockchip,grf = <0x17>; | |
| rockchip,typec-conn-dir = <0xe580 0x0 0x10>; | |
| rockchip,usb3tousb2-en = <0xe580 0x3 0x13>; | |
| rockchip,usb3-host-disable = <0x2434 0x0 0x10>; | |
| rockchip,usb3-host-port = <0x2434 0xc 0x1c>; | |
| rockchip,external-psm = <0xe588 0xe 0x1e>; | |
| rockchip,pipe-status = <0xe5c0 0x0 0x0>; | |
| rockchip,uphy-dp-sel = <0x6268 0x13 0x13>; | |
| status = "okay"; | |
| extcon = <0x29>; | |
| phandle = <0x12f>; | |
| dp-port { | |
| #phy-cells = <0x0>; | |
| phandle = <0x2f>; | |
| }; | |
| usb3-port { | |
| #phy-cells = <0x0>; | |
| phandle = <0x2b>; | |
| }; | |
| }; | |
| phy@ff800000 { | |
| compatible = "rockchip,rk3399-typec-phy"; | |
| reg = <0x0 0xff800000 0x0 0x40000>; | |
| #phy-cells = <0x1>; | |
| clocks = <0x8 0x80 0x8 0x7f>; | |
| clock-names = "tcpdcore", "tcpdphy-ref"; | |
| assigned-clocks = <0x8 0x80>; | |
| assigned-clock-rates = <0x2faf080>; | |
| power-domains = <0x16 0x9>; | |
| resets = <0x8 0x9d 0x8 0x9c 0x8 0x14d>; | |
| reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; | |
| rockchip,grf = <0x17>; | |
| rockchip,typec-conn-dir = <0xe58c 0x0 0x10>; | |
| rockchip,usb3tousb2-en = <0xe58c 0x3 0x13>; | |
| rockchip,usb3-host-disable = <0x2444 0x0 0x10>; | |
| rockchip,usb3-host-port = <0x2444 0xc 0x1c>; | |
| rockchip,external-psm = <0xe594 0xe 0x1e>; | |
| rockchip,pipe-status = <0xe5c0 0x10 0x10>; | |
| rockchip,uphy-dp-sel = <0x6268 0x3 0x13>; | |
| status = "okay"; | |
| extcon = <0x2c>; | |
| rockchip,phy-config = <0x2a 0x0 0x1f 0x15 0x14 0x22 0x2 0x2b 0x21 0x0 0x12 0x15 0x2 0x22 0x0 0x0 0x15 0x4 0x0 0x20 0x0 0x0 0x0 0x0>; | |
| phandle = <0x130>; | |
| dp-port { | |
| #phy-cells = <0x0>; | |
| phandle = <0x30>; | |
| }; | |
| usb3-port { | |
| #phy-cells = <0x0>; | |
| phandle = <0x2e>; | |
| }; | |
| }; | |
| watchdog@ff848000 { | |
| compatible = "snps,dw-wdt"; | |
| reg = <0x0 0xff848000 0x0 0x100>; | |
| clocks = <0x8 0x17c>; | |
| interrupts = <0x0 0x78 0x4 0x0>; | |
| phandle = <0x131>; | |
| }; | |
| rktimer@ff850000 { | |
| compatible = "rockchip,rk3399-timer"; | |
| reg = <0x0 0xff850000 0x0 0x1000>; | |
| interrupts = <0x0 0x51 0x4 0x0>; | |
| clocks = <0x8 0x168 0x8 0x5a>; | |
| clock-names = "pclk", "timer"; | |
| phandle = <0x132>; | |
| }; | |
| spdif@ff870000 { | |
| compatible = "rockchip,rk3399-spdif"; | |
| reg = <0x0 0xff870000 0x0 0x1000>; | |
| interrupts = <0x0 0x42 0x4 0x0>; | |
| dmas = <0x9b 0x7>; | |
| dma-names = "tx"; | |
| clock-names = "mclk", "hclk"; | |
| clocks = <0x8 0x55 0x8 0x1d7>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x9c>; | |
| power-domains = <0x16 0x1c>; | |
| status = "okay"; | |
| assigned-clocks = <0x8 0xb1>; | |
| assigned-clock-parents = <0x8 0x5>; | |
| i2c-scl-rising-time-ns = <0x1c2>; | |
| i2c-scl-falling-time-ns = <0xf>; | |
| #sound-dai-cells = <0x0>; | |
| phandle = <0x133>; | |
| }; | |
| i2s@ff880000 { | |
| compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; | |
| reg = <0x0 0xff880000 0x0 0x1000>; | |
| rockchip,grf = <0x17>; | |
| interrupts = <0x0 0x27 0x4 0x0>; | |
| dmas = <0x9b 0x0 0x9b 0x1>; | |
| dma-names = "tx", "rx"; | |
| clock-names = "i2s_clk", "i2s_hclk"; | |
| clocks = <0x8 0x56 0x8 0x1d4>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x9d>; | |
| power-domains = <0x16 0x1c>; | |
| status = "disabled"; | |
| assigned-clocks = <0x8 0xae>; | |
| assigned-clock-parents = <0x8 0x5>; | |
| rockchip,i2s-broken-burst-len; | |
| rockchip,playback-channels = <0x8>; | |
| rockchip,capture-channels = <0x8>; | |
| #sound-dai-cells = <0x0>; | |
| phandle = <0x134>; | |
| }; | |
| i2s@ff890000 { | |
| compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; | |
| reg = <0x0 0xff890000 0x0 0x1000>; | |
| interrupts = <0x0 0x28 0x4 0x0>; | |
| dmas = <0x9b 0x2 0x9b 0x3>; | |
| dma-names = "tx", "rx"; | |
| clock-names = "i2s_clk", "i2s_hclk"; | |
| clocks = <0x8 0x57 0x8 0x1d5>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x9e>; | |
| power-domains = <0x16 0x1c>; | |
| status = "okay"; | |
| assigned-clocks = <0x8 0xaf 0x8 0xbb>; | |
| assigned-clock-parents = <0x8 0x5 0x8 0x57>; | |
| rockchip,i2s-broken-burst-len; | |
| rockchip,playback-channels = <0x2>; | |
| rockchip,capture-channels = <0x2>; | |
| #sound-dai-cells = <0x0>; | |
| phandle = <0x135>; | |
| }; | |
| i2s@ff8a0000 { | |
| compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; | |
| reg = <0x0 0xff8a0000 0x0 0x1000>; | |
| interrupts = <0x0 0x29 0x4 0x0>; | |
| dmas = <0x9b 0x4>; | |
| dma-names = "tx"; | |
| clock-names = "i2s_clk", "i2s_hclk"; | |
| clocks = <0x8 0x58 0x8 0x1d6>; | |
| power-domains = <0x16 0x1c>; | |
| status = "okay"; | |
| assigned-clocks = <0x8 0xb0 0x8 0xbb>; | |
| assigned-clock-parents = <0x8 0x5 0x8 0x58>; | |
| #sound-dai-cells = <0x0>; | |
| phandle = <0xce>; | |
| }; | |
| gpu@ff9a0000 { | |
| compatible = "arm,malit860", "arm,malit86x", "arm,malit8xx", "arm,mali-midgard"; | |
| reg = <0x0 0xff9a0000 0x0 0x10000>; | |
| interrupts = <0x0 0x13 0x4 0x0 0x0 0x14 0x4 0x0 0x0 0x15 0x4 0x0>; | |
| interrupt-names = "GPU", "JOB", "MMU"; | |
| clocks = <0x8 0xd0>; | |
| clock-names = "clk_mali"; | |
| #cooling-cells = <0x2>; | |
| power-domains = <0x16 0x23>; | |
| power-off-delay-ms = <0xc8>; | |
| status = "okay"; | |
| operating-points-v2 = <0x9f>; | |
| mali-supply = <0xa0>; | |
| phandle = <0x62>; | |
| power_model { | |
| compatible = "arm,mali-simple-power-model"; | |
| static-coefficient = <0x64578>; | |
| dynamic-coefficient = <0x2dd>; | |
| ts = <0x7d00 0x125c 0xffffffb0 0x2>; | |
| thermal-zone = "gpu-thermal"; | |
| phandle = <0x136>; | |
| }; | |
| }; | |
| vop@ff8f0000 { | |
| compatible = "rockchip,rk3399-vop-lit"; | |
| reg = <0x0 0xff8f0000 0x0 0x600 0x0 0xff8f1c00 0x0 0x200 0x0 0xff8f2000 0x0 0x400>; | |
| reg-names = "regs", "cabc_lut", "gamma_lut"; | |
| interrupts = <0x0 0x77 0x4 0x0>; | |
| clocks = <0x8 0xdb 0x8 0xb5 0x8 0x1db 0x8 0xb7>; | |
| clock-names = "aclk_vop", "dclk_vop", "hclk_vop", "dclk_source"; | |
| iommus = <0xa1>; | |
| power-domains = <0x16 0x12>; | |
| resets = <0x8 0x113 0x8 0x117 0x8 0x119>; | |
| reset-names = "axi", "ahb", "dclk"; | |
| status = "okay"; | |
| assigned-clocks = <0x8 0xb7>; | |
| assigned-clock-parents = <0x8 0x4>; | |
| phandle = <0x137>; | |
| port { | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| phandle = <0xc1>; | |
| endpoint@0 { | |
| reg = <0x0>; | |
| remote-endpoint = <0xa2>; | |
| phandle = <0xb6>; | |
| }; | |
| endpoint@1 { | |
| reg = <0x1>; | |
| remote-endpoint = <0xa3>; | |
| phandle = <0xbe>; | |
| }; | |
| endpoint@2 { | |
| reg = <0x2>; | |
| remote-endpoint = <0xa4>; | |
| phandle = <0xb4>; | |
| }; | |
| endpoint@3 { | |
| reg = <0x3>; | |
| remote-endpoint = <0xa5>; | |
| phandle = <0x32>; | |
| }; | |
| endpoint@4 { | |
| reg = <0x4>; | |
| remote-endpoint = <0xa6>; | |
| phandle = <0xbb>; | |
| }; | |
| }; | |
| }; | |
| voppwm@ff8f01a0 { | |
| compatible = "rockchip,vop-pwm"; | |
| reg = <0x0 0xff8f01a0 0x0 0x10>; | |
| #pwm-cells = <0x3>; | |
| pinctrl-names = "active"; | |
| pinctrl-0 = <0xa7>; | |
| clocks = <0x8 0x6c>; | |
| clock-names = "pwm"; | |
| status = "disabled"; | |
| phandle = <0x138>; | |
| }; | |
| iommu@ff8f3f00 { | |
| compatible = "rockchip,iommu"; | |
| reg = <0x0 0xff8f3f00 0x0 0x100>; | |
| interrupts = <0x0 0x77 0x4 0x0>; | |
| interrupt-names = "vopl_mmu"; | |
| clocks = <0x8 0xdb 0x8 0x1db>; | |
| clock-names = "aclk", "hclk"; | |
| power-domains = <0x16 0x12>; | |
| #iommu-cells = <0x0>; | |
| status = "okay"; | |
| phandle = <0xa1>; | |
| }; | |
| vop@ff900000 { | |
| compatible = "rockchip,rk3399-vop-big"; | |
| reg = <0x0 0xff900000 0x0 0x600 0x0 0xff901c00 0x0 0x200 0x0 0xff902000 0x0 0x1000>; | |
| reg-names = "regs", "cabc_lut", "gamma_lut"; | |
| interrupts = <0x0 0x76 0x4 0x0>; | |
| clocks = <0x8 0xd9 0x8 0xb4 0x8 0x1d9 0x8 0xb6>; | |
| clock-names = "aclk_vop", "dclk_vop", "hclk_vop", "dclk_source"; | |
| resets = <0x8 0x112 0x8 0x116 0x8 0x118>; | |
| reset-names = "axi", "ahb", "dclk"; | |
| power-domains = <0x16 0x11>; | |
| iommus = <0xa8>; | |
| status = "okay"; | |
| assigned-clocks = <0x8 0xb6>; | |
| assigned-clock-parents = <0x8 0x7>; | |
| phandle = <0x139>; | |
| port { | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| phandle = <0xc0>; | |
| endpoint@0 { | |
| reg = <0x0>; | |
| remote-endpoint = <0xa9>; | |
| phandle = <0xbd>; | |
| }; | |
| endpoint@1 { | |
| reg = <0x1>; | |
| remote-endpoint = <0xaa>; | |
| phandle = <0xb5>; | |
| }; | |
| endpoint@2 { | |
| reg = <0x2>; | |
| remote-endpoint = <0xab>; | |
| phandle = <0xb3>; | |
| }; | |
| endpoint@3 { | |
| reg = <0x3>; | |
| remote-endpoint = <0xac>; | |
| phandle = <0x31>; | |
| }; | |
| endpoint@4 { | |
| reg = <0x4>; | |
| remote-endpoint = <0xad>; | |
| phandle = <0xba>; | |
| }; | |
| }; | |
| }; | |
| voppwm@ff9001a0 { | |
| compatible = "rockchip,vop-pwm"; | |
| reg = <0x0 0xff9001a0 0x0 0x10>; | |
| #pwm-cells = <0x3>; | |
| pinctrl-names = "active"; | |
| pinctrl-0 = <0xae>; | |
| clocks = <0x8 0x6b>; | |
| clock-names = "pwm"; | |
| status = "disabled"; | |
| phandle = <0x13a>; | |
| }; | |
| iommu@ff903f00 { | |
| compatible = "rockchip,iommu"; | |
| reg = <0x0 0xff903f00 0x0 0x100>; | |
| interrupts = <0x0 0x76 0x4 0x0>; | |
| interrupt-names = "vopb_mmu"; | |
| clocks = <0x8 0xd9 0x8 0x1d9>; | |
| clock-names = "aclk", "hclk"; | |
| power-domains = <0x16 0x11>; | |
| #iommu-cells = <0x0>; | |
| status = "okay"; | |
| phandle = <0xa8>; | |
| }; | |
| rkisp1@ff910000 { | |
| compatible = "rockchip,rk3399-rkisp1"; | |
| reg = <0x0 0xff910000 0x0 0x4000>; | |
| interrupts = <0x0 0x2b 0x4 0x0>; | |
| clocks = <0x8 0x6e 0x8 0xe5 0x8 0x1df 0x8 0xe9 0x8 0x1e3>; | |
| clock-names = "clk_isp", "aclk_isp", "hclk_isp", "aclk_isp_wrap", "hclk_isp_wrap"; | |
| devfreq = <0xaf>; | |
| power-domains = <0x16 0x13>; | |
| iommus = <0xb0>; | |
| status = "disabled"; | |
| phandle = <0x13b>; | |
| }; | |
| iommu@ff914000 { | |
| compatible = "rockchip,iommu"; | |
| reg = <0x0 0xff914000 0x0 0x100 0x0 0xff915000 0x0 0x100>; | |
| interrupts = <0x0 0x2b 0x4 0x0>; | |
| interrupt-names = "isp0_mmu"; | |
| #iommu-cells = <0x0>; | |
| clocks = <0x8 0xe9 0x8 0x1e3>; | |
| clock-names = "aclk", "hclk"; | |
| power-domains = <0x16 0x13>; | |
| rk_iommu,disable_reset_quirk; | |
| status = "disabled"; | |
| phandle = <0xb0>; | |
| }; | |
| rkisp1@ff920000 { | |
| compatible = "rockchip,rk3399-rkisp1"; | |
| reg = <0x0 0xff920000 0x0 0x4000>; | |
| interrupts = <0x0 0x2c 0x4 0x0>; | |
| clocks = <0x8 0x6f 0x8 0xe6 0x8 0x1e0 0x8 0xea 0x8 0x1e4 0x8 0x17b>; | |
| clock-names = "clk_isp", "aclk_isp", "hclk_isp", "aclk_isp_wrap", "hclk_isp_wrap", "pclk_isp_wrap"; | |
| devfreq = <0xaf>; | |
| power-domains = <0x16 0x14>; | |
| iommus = <0xb1>; | |
| status = "disabled"; | |
| phandle = <0x13c>; | |
| }; | |
| iommu@ff924000 { | |
| compatible = "rockchip,iommu"; | |
| reg = <0x0 0xff924000 0x0 0x100 0x0 0xff925000 0x0 0x100>; | |
| interrupts = <0x0 0x2c 0x4 0x0>; | |
| interrupt-names = "isp1_mmu"; | |
| #iommu-cells = <0x0>; | |
| clocks = <0x8 0xea 0x8 0x1e4>; | |
| clock-names = "aclk", "hclk"; | |
| power-domains = <0x16 0x14>; | |
| rk_iommu,disable_reset_quirk; | |
| status = "disabled"; | |
| phandle = <0xb1>; | |
| }; | |
| hdmi@ff940000 { | |
| compatible = "rockchip,rk3399-dw-hdmi"; | |
| reg = <0x0 0xff940000 0x0 0x20000>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0xb2>; | |
| interrupts = <0x0 0x17 0x4 0x0>; | |
| clocks = <0x8 0x174 0x8 0x71 0x8 0x7 0x8 0x16f 0x8 0x70>; | |
| clock-names = "iahb", "isfr", "vpll", "grf", "cec"; | |
| power-domains = <0x16 0x15>; | |
| reg-io-width = <0x4>; | |
| rockchip,grf = <0x17>; | |
| status = "okay"; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| #sound-dai-cells = <0x0>; | |
| phandle = <0xd0>; | |
| ports { | |
| port { | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| phandle = <0x13d>; | |
| endpoint@0 { | |
| reg = <0x0>; | |
| remote-endpoint = <0xb3>; | |
| phandle = <0xab>; | |
| }; | |
| endpoint@1 { | |
| reg = <0x1>; | |
| remote-endpoint = <0xb4>; | |
| status = "disabled"; | |
| phandle = <0xa4>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| dsi@ff960000 { | |
| compatible = "rockchip,rk3399-mipi-dsi"; | |
| reg = <0x0 0xff960000 0x0 0x8000>; | |
| interrupts = <0x0 0x2d 0x4 0x0>; | |
| clocks = <0x8 0xa2 0x8 0x170 0x8 0xa3>; | |
| clock-names = "ref", "pclk", "phy_cfg"; | |
| power-domains = <0x16 0xf>; | |
| resets = <0x8 0xfb>; | |
| reset-names = "apb"; | |
| rockchip,grf = <0x17>; | |
| status = "disabled"; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| phandle = <0x13e>; | |
| ports { | |
| port { | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| endpoint@0 { | |
| reg = <0x0>; | |
| remote-endpoint = <0xb5>; | |
| phandle = <0xaa>; | |
| }; | |
| endpoint@1 { | |
| reg = <0x1>; | |
| remote-endpoint = <0xb6>; | |
| phandle = <0xa2>; | |
| }; | |
| }; | |
| }; | |
| panel { | |
| compatible = "simple-panel-dsi"; | |
| reg = <0x0>; | |
| power-supply = <0xb7>; | |
| reset-gpios = <0x37 0x4 0x1>; | |
| enable-gpios = <0x85 0x1d 0x1>; | |
| backlight = <0xb8>; | |
| dsi,flags = <0x3>; | |
| dsi,format = <0x0>; | |
| dsi,lanes = <0x4>; | |
| dsi,channel = <0x0>; | |
| enable-delay-ms = <0x23>; | |
| prepare-delay-ms = <0x6>; | |
| unprepare-delay-ms = <0x0>; | |
| disable-delay-ms = <0x14>; | |
| size,width = <0x78>; | |
| size,height = <0xaa>; | |
| status = "okay"; | |
| panel-init-sequence = <0x5200129 0x5960111>; | |
| panel-exit-sequence = <0x5050128 0x5780110>; | |
| phandle = <0x13f>; | |
| display-timings { | |
| native-mode = <0xb9>; | |
| phandle = <0x140>; | |
| timing0 { | |
| clock-frequency = <0x4c4b400>; | |
| hactive = <0x300>; | |
| vactive = <0x400>; | |
| hsync-len = <0x14>; | |
| hback-porch = <0x82>; | |
| hfront-porch = <0x96>; | |
| vsync-len = <0x28>; | |
| vback-porch = <0x82>; | |
| vfront-porch = <0x88>; | |
| hsync-active = <0x0>; | |
| vsync-active = <0x0>; | |
| de-active = <0x0>; | |
| pixelclk-active = <0x0>; | |
| phandle = <0xb9>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| dsi@ff968000 { | |
| compatible = "rockchip,rk3399-mipi-dsi"; | |
| reg = <0x0 0xff968000 0x0 0x8000>; | |
| interrupts = <0x0 0x2e 0x4 0x0>; | |
| clocks = <0x8 0xa2 0x8 0x171 0x8 0xa4>; | |
| clock-names = "ref", "pclk", "phy_cfg"; | |
| power-domains = <0x16 0xf>; | |
| resets = <0x8 0xfc>; | |
| reset-names = "apb"; | |
| rockchip,grf = <0x17>; | |
| status = "disabled"; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| phandle = <0x141>; | |
| ports { | |
| port { | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| endpoint@0 { | |
| reg = <0x0>; | |
| remote-endpoint = <0xba>; | |
| phandle = <0xad>; | |
| }; | |
| endpoint@1 { | |
| reg = <0x1>; | |
| remote-endpoint = <0xbb>; | |
| phandle = <0xa6>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| mipi-dphy-tx1rx1@0xff968000 { | |
| compatible = "rockchip,rk3399-mipi-dphy"; | |
| reg = <0x0 0xff968000 0x0 0x8000>; | |
| clocks = <0x8 0x77 0x8 0xa4 0x8 0x16f 0x8 0x171>; | |
| clock-names = "dphy-ref", "dphy-cfg", "grf", "pclk_mipi_dsi"; | |
| rockchip,grf = <0x17>; | |
| power-domains = <0x16 0xf>; | |
| status = "disabled"; | |
| phandle = <0x142>; | |
| }; | |
| edp@ff970000 { | |
| compatible = "rockchip,rk3399-edp"; | |
| reg = <0x0 0xff970000 0x0 0x8000>; | |
| interrupts = <0x0 0xa 0x4 0x0>; | |
| clocks = <0x8 0x16a 0x8 0x16c>; | |
| clock-names = "dp", "pclk"; | |
| power-domains = <0x16 0x19>; | |
| resets = <0x8 0x11d>; | |
| reset-names = "dp"; | |
| rockchip,grf = <0x17>; | |
| status = "disabled"; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0xbc>; | |
| phandle = <0x143>; | |
| ports { | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| port@0 { | |
| reg = <0x0>; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| phandle = <0x144>; | |
| endpoint@0 { | |
| reg = <0x0>; | |
| remote-endpoint = <0xbd>; | |
| phandle = <0xa9>; | |
| }; | |
| endpoint@1 { | |
| reg = <0x1>; | |
| remote-endpoint = <0xbe>; | |
| phandle = <0xa3>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x1>; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| phandle = <0x145>; | |
| endpoint@0 { | |
| reg = <0x0>; | |
| remote-endpoint = <0xbf>; | |
| phandle = <0xcd>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| hdmi-hdcp2@ff988000 { | |
| compatible = "rockchip,rk3399-hdmi-hdcp2"; | |
| reg = <0x0 0xff988000 0x0 0x2000>; | |
| interrupts = <0x0 0x16 0x4 0x0>; | |
| clocks = <0x8 0xe0 0x8 0x176 0x8 0x1e9>; | |
| clock-names = "aclk_hdcp2", "pclk_hdcp2", "hdcp2_clk_hdmi"; | |
| status = "disabled"; | |
| phandle = <0x146>; | |
| }; | |
| display-subsystem { | |
| compatible = "rockchip,display-subsystem"; | |
| ports = <0xc0 0xc1>; | |
| clocks = <0x8 0x7 0x8 0x4>; | |
| clock-names = "hdmi-tmds-pll", "default-vop-pll"; | |
| devfreq = <0xaf>; | |
| status = "okay"; | |
| logo-memory-region = <0xc2>; | |
| phandle = <0x147>; | |
| route { | |
| route-hdmi { | |
| status = "disabled"; | |
| logo,uboot = "logo.bmp"; | |
| logo,kernel = "logo_kernel.bmp"; | |
| logo,mode = "center"; | |
| charge_logo,mode = "center"; | |
| connect = <0xb4>; | |
| video,hdisplay = <0x400>; | |
| video,vdisplay = <0x300>; | |
| video,vrefresh = <0x3c>; | |
| video,flags = <0xa>; | |
| video,crtc_hsync_end = <0x4a0>; | |
| video,crtc_vsync_end = <0x309>; | |
| phandle = <0x148>; | |
| }; | |
| route-dsi { | |
| status = "disabled"; | |
| logo,uboot = "logo.bmp"; | |
| logo,kernel = "logo_kernel.bmp"; | |
| logo,mode = "center"; | |
| charge_logo,mode = "center"; | |
| connect = <0xb5>; | |
| phandle = <0x149>; | |
| }; | |
| route-edp { | |
| status = "disabled"; | |
| logo,uboot = "logo.bmp"; | |
| logo,kernel = "logo_kernel.bmp"; | |
| logo,mode = "center"; | |
| charge_logo,mode = "center"; | |
| connect = <0xbd>; | |
| phandle = <0x14a>; | |
| }; | |
| }; | |
| }; | |
| nocp-cci-msch0@ffa86000 { | |
| compatible = "rockchip,rk3399-nocp"; | |
| reg = <0x0 0xffa86000 0x0 0x400>; | |
| phandle = <0x14b>; | |
| }; | |
| nocp-gpu-msch0@ffa86400 { | |
| compatible = "rockchip,rk3399-nocp"; | |
| reg = <0x0 0xffa86400 0x0 0x400>; | |
| phandle = <0x14c>; | |
| }; | |
| nocp-hp-msch0@ffa86800 { | |
| compatible = "rockchip,rk3399-nocp"; | |
| reg = <0x0 0xffa86800 0x0 0x400>; | |
| phandle = <0x14d>; | |
| }; | |
| nocp-lp-msch0@ffa86c00 { | |
| compatible = "rockchip,rk3399-nocp"; | |
| reg = <0x0 0xffa86c00 0x0 0x400>; | |
| phandle = <0x14e>; | |
| }; | |
| nocp-video-msch0@ffa87000 { | |
| compatible = "rockchip,rk3399-nocp"; | |
| reg = <0x0 0xffa87000 0x0 0x400>; | |
| phandle = <0x14f>; | |
| }; | |
| nocp-vio0-msch0@ffa87400 { | |
| compatible = "rockchip,rk3399-nocp"; | |
| reg = <0x0 0xffa87400 0x0 0x400>; | |
| phandle = <0x150>; | |
| }; | |
| nocp-vio1-msch0@ffa87800 { | |
| compatible = "rockchip,rk3399-nocp"; | |
| reg = <0x0 0xffa87800 0x0 0x400>; | |
| phandle = <0x151>; | |
| }; | |
| nocp-cci-msch1@ffa8e000 { | |
| compatible = "rockchip,rk3399-nocp"; | |
| reg = <0x0 0xffa8e000 0x0 0x400>; | |
| phandle = <0x152>; | |
| }; | |
| nocp-gpu-msch1@ffa8e400 { | |
| compatible = "rockchip,rk3399-nocp"; | |
| reg = <0x0 0xffa8e400 0x0 0x400>; | |
| phandle = <0x153>; | |
| }; | |
| nocp-hp-msch1@ffa8e800 { | |
| compatible = "rockchip,rk3399-nocp"; | |
| reg = <0x0 0xffa8e800 0x0 0x400>; | |
| phandle = <0x154>; | |
| }; | |
| nocp-lp-msch1@ffa8ec00 { | |
| compatible = "rockchip,rk3399-nocp"; | |
| reg = <0x0 0xffa8ec00 0x0 0x400>; | |
| phandle = <0x155>; | |
| }; | |
| nocp-video-msch1@ffa8f000 { | |
| compatible = "rockchip,rk3399-nocp"; | |
| reg = <0x0 0xffa8f000 0x0 0x400>; | |
| phandle = <0x156>; | |
| }; | |
| nocp-vio0-msch1@ffa8f400 { | |
| compatible = "rockchip,rk3399-nocp"; | |
| reg = <0x0 0xffa8f400 0x0 0x400>; | |
| phandle = <0x157>; | |
| }; | |
| nocp-vio1-msch1@ffa8f800 { | |
| compatible = "rockchip,rk3399-nocp"; | |
| reg = <0x0 0xffa8f800 0x0 0x400>; | |
| phandle = <0x158>; | |
| }; | |
| pinctrl { | |
| compatible = "rockchip,rk3399-pinctrl"; | |
| rockchip,grf = <0x17>; | |
| rockchip,pmu = <0x91>; | |
| #address-cells = <0x2>; | |
| #size-cells = <0x2>; | |
| ranges; | |
| phandle = <0x159>; | |
| gpio0@ff720000 { | |
| compatible = "rockchip,gpio-bank"; | |
| reg = <0x0 0xff720000 0x0 0x100>; | |
| clocks = <0x33 0x17>; | |
| interrupts = <0x0 0xe 0x4 0x0>; | |
| gpio-controller; | |
| #gpio-cells = <0x2>; | |
| interrupt-controller; | |
| #interrupt-cells = <0x2>; | |
| phandle = <0xdf>; | |
| }; | |
| gpio1@ff730000 { | |
| compatible = "rockchip,gpio-bank"; | |
| reg = <0x0 0xff730000 0x0 0x100>; | |
| clocks = <0x33 0x18>; | |
| interrupts = <0x0 0xf 0x4 0x0>; | |
| gpio-controller; | |
| #gpio-cells = <0x2>; | |
| interrupt-controller; | |
| #interrupt-cells = <0x2>; | |
| phandle = <0x37>; | |
| }; | |
| gpio2@ff780000 { | |
| compatible = "rockchip,gpio-bank"; | |
| reg = <0x0 0xff780000 0x0 0x100>; | |
| clocks = <0x8 0x150>; | |
| interrupts = <0x0 0x10 0x4 0x0>; | |
| gpio-controller; | |
| #gpio-cells = <0x2>; | |
| interrupt-controller; | |
| #interrupt-cells = <0x2>; | |
| phandle = <0xd4>; | |
| }; | |
| gpio3@ff788000 { | |
| compatible = "rockchip,gpio-bank"; | |
| reg = <0x0 0xff788000 0x0 0x100>; | |
| clocks = <0x8 0x151>; | |
| interrupts = <0x0 0x11 0x4 0x0>; | |
| gpio-controller; | |
| #gpio-cells = <0x2>; | |
| interrupt-controller; | |
| #interrupt-cells = <0x2>; | |
| phandle = <0x19>; | |
| }; | |
| gpio4@ff790000 { | |
| compatible = "rockchip,gpio-bank"; | |
| reg = <0x0 0xff790000 0x0 0x100>; | |
| clocks = <0x8 0x152>; | |
| interrupts = <0x0 0x12 0x4 0x0>; | |
| gpio-controller; | |
| #gpio-cells = <0x2>; | |
| interrupt-controller; | |
| #interrupt-cells = <0x2>; | |
| phandle = <0x85>; | |
| }; | |
| pcfg-pull-up { | |
| bias-pull-up; | |
| phandle = <0xc3>; | |
| }; | |
| pcfg-pull-down { | |
| bias-pull-down; | |
| phandle = <0xc7>; | |
| }; | |
| pcfg-pull-none { | |
| bias-disable; | |
| phandle = <0xc5>; | |
| }; | |
| pcfg-pull-up-20ma { | |
| bias-pull-up; | |
| drive-strength = <0x14>; | |
| phandle = <0x15a>; | |
| }; | |
| pcfg-pull-none-20ma { | |
| bias-disable; | |
| drive-strength = <0x14>; | |
| phandle = <0x15b>; | |
| }; | |
| pcfg-pull-none-18ma { | |
| bias-disable; | |
| drive-strength = <0x12>; | |
| phandle = <0x15c>; | |
| }; | |
| pcfg-pull-none-12ma { | |
| bias-disable; | |
| drive-strength = <0xc>; | |
| phandle = <0xc6>; | |
| }; | |
| pcfg-pull-up-8ma { | |
| bias-pull-up; | |
| drive-strength = <0x8>; | |
| phandle = <0x15d>; | |
| }; | |
| pcfg-pull-down-4ma { | |
| bias-pull-down; | |
| drive-strength = <0x4>; | |
| phandle = <0x15e>; | |
| }; | |
| pcfg-pull-up-2ma { | |
| bias-pull-up; | |
| drive-strength = <0x2>; | |
| phandle = <0x15f>; | |
| }; | |
| pcfg-pull-down-12ma { | |
| bias-pull-down; | |
| drive-strength = <0xc>; | |
| phandle = <0x160>; | |
| }; | |
| pcfg-pull-none-13ma { | |
| bias-disable; | |
| drive-strength = <0xd>; | |
| phandle = <0xc4>; | |
| }; | |
| pcfg-output-high { | |
| output-high; | |
| phandle = <0x161>; | |
| }; | |
| pcfg-output-low { | |
| output-low; | |
| phandle = <0x162>; | |
| }; | |
| pcfg-input { | |
| input-enable; | |
| phandle = <0x163>; | |
| }; | |
| emmc { | |
| emmc-pwr { | |
| rockchip,pins = <0x0 0x5 0x1 0xc3>; | |
| phandle = <0x164>; | |
| }; | |
| }; | |
| gmac { | |
| rgmii-pins { | |
| rockchip,pins = <0x3 0x11 0x1 0xc4 0x3 0xe 0x1 0xc5 0x3 0xd 0x1 0xc5 0x3 0xc 0x1 0xc4 0x3 0xb 0x1 0xc5 0x3 0x9 0x1 0xc5 0x3 0x8 0x1 0xc5 0x3 0x7 0x1 0xc5 0x3 0x6 0x1 0xc5 0x3 0x5 0x1 0xc4 0x3 0x4 0x1 0xc4 0x3 0x3 0x1 0xc5 0x3 0x2 0x1 0xc5 0x3 0x1 0x1 0xc4 0x3 0x0 0x1 0xc4>; | |
| phandle = <0x1b>; | |
| }; | |
| rmii-pins { | |
| rockchip,pins = <0x3 0xd 0x1 0xc5 0x3 0xc 0x1 0xc4 0x3 0xb 0x1 0xc5 0x3 0xa 0x1 0xc5 0x3 0x9 0x1 0xc5 0x3 0x8 0x1 0xc5 0x3 0x7 0x1 0xc5 0x3 0x6 0x1 0xc5 0x3 0x5 0x1 0xc4 0x3 0x4 0x1 0xc4>; | |
| phandle = <0x165>; | |
| }; | |
| }; | |
| i2c0 { | |
| i2c0-xfer { | |
| rockchip,pins = <0x1 0xf 0x2 0xc5 0x1 0x10 0x2 0xc5>; | |
| phandle = <0x34>; | |
| }; | |
| }; | |
| i2c1 { | |
| i2c1-xfer { | |
| rockchip,pins = <0x4 0x2 0x1 0xc5 0x4 0x1 0x1 0xc5>; | |
| phandle = <0x3d>; | |
| }; | |
| }; | |
| i2c2 { | |
| i2c2-xfer { | |
| rockchip,pins = <0x2 0x1 0x2 0xc6 0x2 0x0 0x2 0xc6>; | |
| phandle = <0x3e>; | |
| }; | |
| }; | |
| i2c3 { | |
| i2c3-xfer { | |
| rockchip,pins = <0x4 0x11 0x1 0xc5 0x4 0x10 0x1 0xc5>; | |
| phandle = <0x3f>; | |
| }; | |
| i2c3_gpio { | |
| rockchip,pins = <0x4 0x11 0x0 0xc5 0x4 0x10 0x0 0xc5>; | |
| phandle = <0x166>; | |
| }; | |
| }; | |
| i2c4 { | |
| i2c4-xfer { | |
| rockchip,pins = <0x1 0xc 0x1 0xc5 0x1 0xb 0x1 0xc5>; | |
| phandle = <0x84>; | |
| }; | |
| }; | |
| i2c5 { | |
| i2c5-xfer { | |
| rockchip,pins = <0x3 0xb 0x2 0xc5 0x3 0xa 0x2 0xc5>; | |
| phandle = <0x40>; | |
| }; | |
| }; | |
| i2c6 { | |
| i2c6-xfer { | |
| rockchip,pins = <0x2 0xa 0x2 0xc5 0x2 0x9 0x2 0xc5>; | |
| phandle = <0x41>; | |
| }; | |
| }; | |
| i2c7 { | |
| i2c7-xfer { | |
| rockchip,pins = <0x2 0x8 0x2 0xc5 0x2 0x7 0x2 0xc5>; | |
| phandle = <0x42>; | |
| }; | |
| }; | |
| i2c8 { | |
| i2c8-xfer { | |
| rockchip,pins = <0x1 0x15 0x1 0xc5 0x1 0x14 0x1 0xc5>; | |
| phandle = <0x88>; | |
| }; | |
| }; | |
| i2s0 { | |
| i2s0-8ch-bus { | |
| rockchip,pins = <0x3 0x18 0x1 0xc5 0x3 0x19 0x1 0xc5 0x3 0x1a 0x1 0xc5 0x3 0x1b 0x1 0xc5 0x3 0x1c 0x1 0xc5 0x3 0x1d 0x1 0xc5 0x3 0x1e 0x1 0xc5 0x3 0x1f 0x1 0xc5>; | |
| phandle = <0x9d>; | |
| }; | |
| i2s-8ch-mclk { | |
| rockchip,pins = <0x4 0x0 0x1 0xc5>; | |
| phandle = <0x167>; | |
| }; | |
| }; | |
| i2s1 { | |
| i2s1-2ch-bus { | |
| rockchip,pins = <0x4 0x3 0x1 0xc5 0x4 0x4 0x1 0xc5 0x4 0x5 0x1 0xc5 0x4 0x6 0x1 0xc5 0x4 0x7 0x1 0xc5>; | |
| phandle = <0x9e>; | |
| }; | |
| }; | |
| sdio0 { | |
| sdio0-bus1 { | |
| rockchip,pins = <0x2 0x14 0x1 0xc3>; | |
| phandle = <0x168>; | |
| }; | |
| sdio0-bus4 { | |
| rockchip,pins = <0x2 0x14 0x1 0xc3 0x2 0x15 0x1 0xc3 0x2 0x16 0x1 0xc3 0x2 0x17 0x1 0xc3>; | |
| phandle = <0x1d>; | |
| }; | |
| sdio0-cmd { | |
| rockchip,pins = <0x2 0x18 0x1 0xc3>; | |
| phandle = <0x1e>; | |
| }; | |
| sdio0-clk { | |
| rockchip,pins = <0x2 0x19 0x1 0xc5>; | |
| phandle = <0x1f>; | |
| }; | |
| sdio0-cd { | |
| rockchip,pins = <0x2 0x1a 0x1 0xc3>; | |
| phandle = <0x169>; | |
| }; | |
| sdio0-pwr { | |
| rockchip,pins = <0x2 0x1b 0x1 0xc3>; | |
| phandle = <0x16a>; | |
| }; | |
| sdio0-bkpwr { | |
| rockchip,pins = <0x2 0x1c 0x1 0xc3>; | |
| phandle = <0x16b>; | |
| }; | |
| sdio0-wp { | |
| rockchip,pins = <0x0 0x3 0x1 0xc3>; | |
| phandle = <0x16c>; | |
| }; | |
| sdio0-int { | |
| rockchip,pins = <0x0 0x4 0x1 0xc3>; | |
| phandle = <0x16d>; | |
| }; | |
| }; | |
| sdmmc { | |
| sdmmc-bus1 { | |
| rockchip,pins = <0x4 0x8 0x1 0xc3>; | |
| phandle = <0x16e>; | |
| }; | |
| sdmmc-bus4 { | |
| rockchip,pins = <0x4 0x8 0x1 0xc3 0x4 0x9 0x1 0xc3 0x4 0xa 0x1 0xc3 0x4 0xb 0x1 0xc3>; | |
| phandle = <0x25>; | |
| }; | |
| sdmmc-clk { | |
| rockchip,pins = <0x4 0xc 0x1 0xc5>; | |
| phandle = <0x22>; | |
| }; | |
| sdmmc-cmd { | |
| rockchip,pins = <0x4 0xd 0x1 0xc3>; | |
| phandle = <0x23>; | |
| }; | |
| sdmcc-cd { | |
| rockchip,pins = <0x0 0x7 0x1 0xc3>; | |
| phandle = <0x24>; | |
| }; | |
| sdmmc-wp { | |
| rockchip,pins = <0x0 0x8 0x1 0xc3>; | |
| phandle = <0x16f>; | |
| }; | |
| }; | |
| spdif { | |
| spdif-bus { | |
| rockchip,pins = <0x4 0x15 0x1 0xc5>; | |
| phandle = <0x170>; | |
| }; | |
| spdif-bus-1 { | |
| rockchip,pins = <0x3 0x10 0x3 0xc5>; | |
| phandle = <0x9c>; | |
| }; | |
| }; | |
| spi0 { | |
| spi0-clk { | |
| rockchip,pins = <0x3 0x6 0x2 0xc3>; | |
| phandle = <0x4c>; | |
| }; | |
| spi0-cs0 { | |
| rockchip,pins = <0x3 0x7 0x2 0xc3>; | |
| phandle = <0x4f>; | |
| }; | |
| spi0-cs1 { | |
| rockchip,pins = <0x3 0x8 0x2 0xc3>; | |
| phandle = <0x171>; | |
| }; | |
| spi0-tx { | |
| rockchip,pins = <0x3 0x5 0x2 0xc3>; | |
| phandle = <0x4d>; | |
| }; | |
| spi0-rx { | |
| rockchip,pins = <0x3 0x4 0x2 0xc3>; | |
| phandle = <0x4e>; | |
| }; | |
| }; | |
| spi1 { | |
| spi1-clk { | |
| rockchip,pins = <0x1 0x9 0x2 0xc3>; | |
| phandle = <0x50>; | |
| }; | |
| spi1-cs0 { | |
| rockchip,pins = <0x1 0xa 0x2 0xc3>; | |
| phandle = <0x53>; | |
| }; | |
| spi1-rx { | |
| rockchip,pins = <0x1 0x7 0x2 0xc3>; | |
| phandle = <0x52>; | |
| }; | |
| spi1-tx { | |
| rockchip,pins = <0x1 0x8 0x2 0xc3>; | |
| phandle = <0x51>; | |
| }; | |
| }; | |
| spi2 { | |
| spi2-clk { | |
| rockchip,pins = <0x2 0xb 0x1 0xc3>; | |
| phandle = <0x54>; | |
| }; | |
| spi2-cs0 { | |
| rockchip,pins = <0x2 0xc 0x1 0xc3>; | |
| phandle = <0x57>; | |
| }; | |
| spi2-rx { | |
| rockchip,pins = <0x2 0x9 0x1 0xc3>; | |
| phandle = <0x56>; | |
| }; | |
| spi2-tx { | |
| rockchip,pins = <0x2 0xa 0x1 0xc3>; | |
| phandle = <0x55>; | |
| }; | |
| }; | |
| spi3 { | |
| spi3-clk { | |
| rockchip,pins = <0x1 0x11 0x1 0xc3>; | |
| phandle = <0x7f>; | |
| }; | |
| spi3-cs0 { | |
| rockchip,pins = <0x1 0x12 0x1 0xc3>; | |
| phandle = <0x82>; | |
| }; | |
| spi3-rx { | |
| rockchip,pins = <0x1 0xf 0x1 0xc3>; | |
| phandle = <0x81>; | |
| }; | |
| spi3-tx { | |
| rockchip,pins = <0x1 0x10 0x1 0xc3>; | |
| phandle = <0x80>; | |
| }; | |
| }; | |
| spi4 { | |
| spi4-clk { | |
| rockchip,pins = <0x3 0x2 0x2 0xc3>; | |
| phandle = <0x58>; | |
| }; | |
| spi4-cs0 { | |
| rockchip,pins = <0x3 0x3 0x2 0xc3>; | |
| phandle = <0x5b>; | |
| }; | |
| spi4-rx { | |
| rockchip,pins = <0x3 0x0 0x2 0xc3>; | |
| phandle = <0x5a>; | |
| }; | |
| spi4-tx { | |
| rockchip,pins = <0x3 0x1 0x2 0xc3>; | |
| phandle = <0x59>; | |
| }; | |
| }; | |
| spi5 { | |
| spi5-clk { | |
| rockchip,pins = <0x2 0x16 0x2 0xc3>; | |
| phandle = <0x5c>; | |
| }; | |
| spi5-cs0 { | |
| rockchip,pins = <0x2 0x17 0x2 0xc3>; | |
| phandle = <0x5f>; | |
| }; | |
| spi5-rx { | |
| rockchip,pins = <0x2 0x14 0x2 0xc3>; | |
| phandle = <0x5e>; | |
| }; | |
| spi5-tx { | |
| rockchip,pins = <0x2 0x15 0x2 0xc3>; | |
| phandle = <0x5d>; | |
| }; | |
| }; | |
| tsadc { | |
| otp-gpio { | |
| rockchip,pins = <0x1 0x6 0x0 0xc5>; | |
| phandle = <0x63>; | |
| }; | |
| otp-out { | |
| rockchip,pins = <0x1 0x6 0x1 0xc5>; | |
| phandle = <0x64>; | |
| }; | |
| }; | |
| uart0 { | |
| uart0-xfer { | |
| rockchip,pins = <0x2 0x10 0x1 0xc3 0x2 0x11 0x1 0xc5>; | |
| phandle = <0x45>; | |
| }; | |
| uart0-cts { | |
| rockchip,pins = <0x2 0x12 0x1 0xc5>; | |
| phandle = <0x46>; | |
| }; | |
| uart0-rts { | |
| rockchip,pins = <0x2 0x13 0x1 0xc5>; | |
| phandle = <0xe0>; | |
| }; | |
| }; | |
| uart1 { | |
| uart1-xfer { | |
| rockchip,pins = <0x3 0xc 0x2 0xc3 0x3 0xd 0x2 0xc5>; | |
| phandle = <0x47>; | |
| }; | |
| }; | |
| uart2a { | |
| uart2a-xfer { | |
| rockchip,pins = <0x4 0x8 0x2 0xc3 0x4 0x9 0x2 0xc5>; | |
| phandle = <0x172>; | |
| }; | |
| }; | |
| uart2b { | |
| uart2b-xfer { | |
| rockchip,pins = <0x4 0x10 0x2 0xc3 0x4 0x11 0x2 0xc5>; | |
| phandle = <0x173>; | |
| }; | |
| }; | |
| uart2c { | |
| uart2c-xfer { | |
| rockchip,pins = <0x4 0x13 0x1 0xc3 0x4 0x14 0x1 0xc5>; | |
| phandle = <0x48>; | |
| }; | |
| }; | |
| uart3 { | |
| uart3-xfer { | |
| rockchip,pins = <0x3 0xe 0x2 0xc3 0x3 0xf 0x2 0xc5>; | |
| phandle = <0x49>; | |
| }; | |
| uart3-cts { | |
| rockchip,pins = <0x3 0x12 0x2 0xc5>; | |
| phandle = <0x4a>; | |
| }; | |
| uart3-rts { | |
| rockchip,pins = <0x3 0x13 0x2 0xc5>; | |
| phandle = <0x4b>; | |
| }; | |
| }; | |
| uart4 { | |
| uart4-xfer { | |
| rockchip,pins = <0x1 0x7 0x1 0xc3 0x1 0x8 0x1 0xc5>; | |
| phandle = <0x83>; | |
| }; | |
| }; | |
| uarthdcp { | |
| uarthdcp-xfer { | |
| rockchip,pins = <0x4 0x15 0x2 0xc3 0x4 0x16 0x2 0xc5>; | |
| phandle = <0x174>; | |
| }; | |
| }; | |
| pwm0 { | |
| pwm0-pin { | |
| rockchip,pins = <0x4 0x12 0x1 0xc5>; | |
| phandle = <0x8d>; | |
| }; | |
| pwm0-pin-pull-down { | |
| rockchip,pins = <0x4 0x12 0x1 0xc7>; | |
| phandle = <0x175>; | |
| }; | |
| vop0-pwm-pin { | |
| rockchip,pins = <0x4 0x12 0x2 0xc5>; | |
| phandle = <0xae>; | |
| }; | |
| vop1-pwm-pin { | |
| rockchip,pins = <0x4 0x12 0x3 0xc5>; | |
| phandle = <0xa7>; | |
| }; | |
| }; | |
| pwm1 { | |
| pwm1-pin { | |
| rockchip,pins = <0x4 0x16 0x1 0xc5>; | |
| phandle = <0x8e>; | |
| }; | |
| pwm1-pin-pull-down { | |
| rockchip,pins = <0x4 0x16 0x1 0xc7>; | |
| phandle = <0x176>; | |
| }; | |
| }; | |
| pwm2 { | |
| pwm2-pin { | |
| rockchip,pins = <0x1 0x13 0x1 0xc5>; | |
| phandle = <0x177>; | |
| }; | |
| pwm2-pin-pull-down { | |
| rockchip,pins = <0x1 0x13 0x1 0xc7>; | |
| phandle = <0x8f>; | |
| }; | |
| }; | |
| pwm3a { | |
| pwm3a-pin { | |
| rockchip,pins = <0x0 0x6 0x1 0xc5>; | |
| phandle = <0x90>; | |
| }; | |
| pwm3a-pin-pull-down { | |
| rockchip,pins = <0x0 0x6 0x1 0xc7>; | |
| phandle = <0x178>; | |
| }; | |
| }; | |
| pwm3b { | |
| pwm3b-pin { | |
| rockchip,pins = <0x1 0xe 0x1 0xc5>; | |
| phandle = <0x179>; | |
| }; | |
| pwm3b-pin-pull-down { | |
| rockchip,pins = <0x1 0xe 0x1 0xc7>; | |
| phandle = <0x17a>; | |
| }; | |
| }; | |
| edp { | |
| edp-hpd { | |
| rockchip,pins = <0x4 0x17 0x2 0xc5>; | |
| phandle = <0xbc>; | |
| }; | |
| }; | |
| hdmi { | |
| hdmi-i2c-xfer { | |
| rockchip,pins = <0x4 0x11 0x3 0xc5 0x4 0x10 0x3 0xc5>; | |
| phandle = <0xb2>; | |
| }; | |
| hdmi-cec { | |
| rockchip,pins = <0x4 0x17 0x1 0xc5>; | |
| phandle = <0x17b>; | |
| }; | |
| }; | |
| pcie { | |
| pci-clkreqn { | |
| rockchip,pins = <0x2 0x1a 0x2 0xc5>; | |
| phandle = <0x17c>; | |
| }; | |
| pci-clkreqnb { | |
| rockchip,pins = <0x4 0x18 0x1 0xc5>; | |
| phandle = <0x17d>; | |
| }; | |
| pci-clkreqn-cpm { | |
| rockchip,pins = <0x2 0x1a 0x0 0xc5>; | |
| phandle = <0x8c>; | |
| }; | |
| pci-clkreqnb-cpm { | |
| rockchip,pins = <0x4 0x18 0x0 0xc5>; | |
| phandle = <0x17e>; | |
| }; | |
| pcie-drv { | |
| rockchip,pins = <0x1 0x11 0x0 0xc5>; | |
| phandle = <0xd2>; | |
| }; | |
| vcc-pcie-h { | |
| rockchip,pins = <0x1 0x11 0x0 0xc5>; | |
| phandle = <0xd8>; | |
| }; | |
| }; | |
| isp { | |
| cif-clkout { | |
| rockchip,pins = <0x2 0xb 0x3 0xc5>; | |
| phandle = <0x17f>; | |
| }; | |
| isp-dvp-d0d7 { | |
| rockchip,pins = <0x4 0x1b 0x0 0xc5 0x2 0xb 0x3 0xc5 0x2 0x0 0x3 0xc5 0x2 0x1 0x3 0xc5 0x2 0x2 0x3 0xc5 0x2 0x3 0x3 0xc5 0x2 0x4 0x3 0xc5 0x2 0x5 0x3 0xc5 0x2 0x6 0x3 0xc5 0x2 0x7 0x3 0xc5 0x2 0x8 0x3 0xc5 0x2 0x9 0x3 0xc5 0x2 0xa 0x3 0xc5>; | |
| phandle = <0x180>; | |
| }; | |
| isp-shutter { | |
| rockchip,pins = <0x1 0x1 0x1 0xc5 0x1 0x0 0x1 0xc5>; | |
| phandle = <0x181>; | |
| }; | |
| isp-flash-trigger { | |
| rockchip,pins = <0x1 0x3 0x1 0xc5>; | |
| phandle = <0x182>; | |
| }; | |
| isp-flash-trigger-as-gpio { | |
| rockchip,pins = <0x0 0x11 0x0 0xc5>; | |
| phandle = <0x183>; | |
| }; | |
| }; | |
| cam_pins { | |
| cam0-default-pins { | |
| rockchip,pins = <0x4 0x1b 0x0 0xc5 0x2 0xb 0x3 0xc5>; | |
| phandle = <0x184>; | |
| }; | |
| cam0-sleep-pins { | |
| rockchip,pins = <0x4 0x1b 0x3 0xc5 0x2 0xb 0x0 0xc5>; | |
| phandle = <0x185>; | |
| }; | |
| }; | |
| lcd-panel { | |
| lcd-panel-reset { | |
| rockchip,pins = <0x4 0x1d 0x0 0xc3>; | |
| phandle = <0xcc>; | |
| }; | |
| lcd-en { | |
| rockchip,pins = <0x1 0x18 0x0 0xc3>; | |
| phandle = <0xdc>; | |
| }; | |
| }; | |
| pmic { | |
| vsel1-gpio { | |
| rockchip,pins = <0x1 0x12 0x0 0xc7>; | |
| phandle = <0x36>; | |
| }; | |
| vsel2-gpio { | |
| rockchip,pins = <0x1 0xe 0x0 0xc7>; | |
| phandle = <0x38>; | |
| }; | |
| pmic-int-l { | |
| rockchip,pins = <0x1 0x15 0x0 0xc3>; | |
| phandle = <0x39>; | |
| }; | |
| pmic-dvs2 { | |
| rockchip,pins = <0x1 0x12 0x0 0xc7>; | |
| phandle = <0x3a>; | |
| }; | |
| }; | |
| leds { | |
| led-power { | |
| rockchip,pins = <0x2 0x1b 0x0 0xc5>; | |
| phandle = <0xe2>; | |
| }; | |
| led-user { | |
| rockchip,pins = <0x0 0x2 0x0 0xc5>; | |
| phandle = <0xe3>; | |
| }; | |
| }; | |
| sdio-pwrseq { | |
| wifi-enable-h { | |
| rockchip,pins = <0x0 0xa 0x0 0xc5>; | |
| phandle = <0xde>; | |
| }; | |
| }; | |
| wireless-bluetooth { | |
| uart0-gpios { | |
| rockchip,pins = <0x2 0x13 0x0 0xc5>; | |
| phandle = <0xe1>; | |
| }; | |
| }; | |
| usb2 { | |
| host-vbus-drv { | |
| rockchip,pins = <0x1 0x0 0x0 0xc5>; | |
| phandle = <0xd3>; | |
| }; | |
| hub-rst-en { | |
| rockchip,pins = <0x2 0x4 0x0 0xc5>; | |
| phandle = <0xd5>; | |
| }; | |
| }; | |
| fusb30x { | |
| fusb1-int { | |
| rockchip,pins = <0x1 0x1 0x0 0xc3>; | |
| phandle = <0x86>; | |
| }; | |
| fusb0-int { | |
| rockchip,pins = <0x1 0x2 0x0 0xc3>; | |
| phandle = <0x44>; | |
| }; | |
| typec1-vbus-drv { | |
| rockchip,pins = <0x1 0xd 0x0 0xc3>; | |
| phandle = <0x87>; | |
| }; | |
| }; | |
| vcc_sd { | |
| vcc-sd-h { | |
| rockchip,pins = <0x4 0x1e 0x0 0xc5>; | |
| phandle = <0xda>; | |
| }; | |
| }; | |
| wifi { | |
| vcc-wifi-h { | |
| rockchip,pins = <0x4 0x1b 0x0 0xc5>; | |
| phandle = <0xd7>; | |
| }; | |
| }; | |
| chargen { | |
| vcc-chargen-h { | |
| rockchip,pins = <0x0 0x1 0x0 0xc5>; | |
| phandle = <0xd9>; | |
| }; | |
| bat-int-h { | |
| rockchip,pins = <0x2 0x1c 0x0 0xc5>; | |
| phandle = <0xe5>; | |
| }; | |
| cur-ctl-h { | |
| rockchip,pins = <0x3 0x1a 0x0 0xc5>; | |
| phandle = <0xe6>; | |
| }; | |
| }; | |
| vcc_dis { | |
| vcc-dis-en0 { | |
| rockchip,pins = <0x2 0x6 0x0 0xc5>; | |
| phandle = <0xd6>; | |
| }; | |
| }; | |
| }; | |
| rockchip-suspend { | |
| compatible = "rockchip,pm-rk3399"; | |
| status = "disabled"; | |
| rockchip,sleep-debug-en = <0x0>; | |
| rockchip,virtual-poweroff = <0x0>; | |
| rockchip,sleep-mode-config = <0xfe>; | |
| rockchip,wakeup-config = <0x4>; | |
| rockchip,power-ctrl = <0x37 0x12 0x1 0x37 0xe 0x0>; | |
| phandle = <0x186>; | |
| }; | |
| energy-costs { | |
| rk3399-core-cost0 { | |
| busy-cost-data = <0x6c 0x2e 0x9f 0x43 0xd8 0x5a 0x10b 0x78 0x13e 0x99 0x177 0xc6 0x191 0xde>; | |
| idle-cost-data = <0x6 0x6 0x0 0x0>; | |
| phandle = <0xc>; | |
| }; | |
| rk3399-core-cost1 { | |
| busy-cost-data = <0xd2 0x81 0x134 0xb8 0x1a3 0xf6 0x206 0x14f 0x269 0x1ac 0x2d8 0x23d 0x33b 0x2d4 0x39d 0x384 0x400 0x454>; | |
| idle-cost-data = <0xf 0xf 0x0 0x0>; | |
| phandle = <0x10>; | |
| }; | |
| rk3399-cluster-cost0 { | |
| busy-cost-data = <0x6c 0x2e 0x9f 0x43 0xd8 0x5a 0x10b 0x78 0x13e 0x99 0x177 0xc6 0x191 0xde>; | |
| idle-cost-data = <0x38 0x38 0x38 0x38>; | |
| phandle = <0xd>; | |
| }; | |
| rk3399-cluster-cost1 { | |
| busy-cost-data = <0xd2 0x81 0x134 0xb8 0x1a3 0xf6 0x206 0x14f 0x269 0x1ac 0x2d8 0x23d 0x33b 0x2d4 0x39d 0x384 0x400 0x454>; | |
| idle-cost-data = <0x41 0x41 0x41 0x41>; | |
| phandle = <0x11>; | |
| }; | |
| }; | |
| opp-table0 { | |
| compatible = "operating-points-v2"; | |
| opp-shared; | |
| rockchip,temp-hysteresis = <0x1388>; | |
| rockchip,low-temp = <0x0>; | |
| rockchip,low-temp-min-volt = <0xdbba0>; | |
| nvmem-cells = <0xc8>; | |
| nvmem-cell-names = "cpu_leakage"; | |
| rockchip,pvtm-voltage-sel = <0x0 0x2308c 0x0 0x2308d 0x24414 0x1 0x24415 0x251c0 0x2 0x251c1 0xf423f 0x3>; | |
| rockchip,pvtm-freq = <0x639c0>; | |
| rockchip,pvtm-volt = <0xf4240>; | |
| rockchip,pvtm-ch = <0x0 0x0>; | |
| rockchip,pvtm-sample-time = <0x3e8>; | |
| rockchip,pvtm-number = <0xa>; | |
| rockchip,pvtm-error = <0x3e8>; | |
| rockchip,pvtm-ref-temp = <0x29>; | |
| rockchip,pvtm-temp-prop = <0x73 0x42>; | |
| rockchip,thermal-zone = "soc-thermal"; | |
| phandle = <0xb>; | |
| opp-408000000 { | |
| opp-hz = <0x0 0x18519600>; | |
| opp-microvolt = <0xc3500 0xc3500 0x124f80>; | |
| opp-microvolt-L0 = <0xc3500 0xc3500 0x124f80>; | |
| opp-microvolt-L1 = <0xc3500 0xc3500 0x124f80>; | |
| opp-microvolt-L2 = <0xc3500 0xc3500 0x124f80>; | |
| opp-microvolt-L3 = <0xc3500 0xc3500 0x124f80>; | |
| clock-latency-ns = <0x9c40>; | |
| }; | |
| opp-600000000 { | |
| opp-hz = <0x0 0x23c34600>; | |
| opp-microvolt = <0xc3500 0xc3500 0x124f80>; | |
| opp-microvolt-L0 = <0xc3500 0xc3500 0x124f80>; | |
| opp-microvolt-L1 = <0xc3500 0xc3500 0x124f80>; | |
| opp-microvolt-L2 = <0xc3500 0xc3500 0x124f80>; | |
| opp-microvolt-L3 = <0xc3500 0xc3500 0x124f80>; | |
| clock-latency-ns = <0x9c40>; | |
| }; | |
| opp-816000000 { | |
| opp-hz = <0x0 0x30a32c00>; | |
| opp-microvolt = <0xcf850 0xcf850 0x124f80>; | |
| opp-microvolt-L0 = <0xcf850 0xcf850 0x124f80>; | |
| opp-microvolt-L1 = <0xc96a8 0xc96a8 0x124f80>; | |
| opp-microvolt-L2 = <0xc3500 0xc3500 0x124f80>; | |
| opp-microvolt-L3 = <0xc3500 0xc3500 0x124f80>; | |
| clock-latency-ns = <0x9c40>; | |
| opp-suspend; | |
| }; | |
| opp-1008000000 { | |
| opp-hz = <0x0 0x3c14dc00>; | |
| opp-microvolt = <0xe1d48 0xe1d48 0x124f80>; | |
| opp-microvolt-L0 = <0xe1d48 0xe1d48 0x124f80>; | |
| opp-microvolt-L1 = <0xdbba0 0xdbba0 0x124f80>; | |
| opp-microvolt-L2 = <0xd59f8 0xd59f8 0x124f80>; | |
| opp-microvolt-L3 = <0xcf850 0xcf850 0x124f80>; | |
| clock-latency-ns = <0x9c40>; | |
| }; | |
| opp-1200000000 { | |
| opp-hz = <0x0 0x47868c00>; | |
| opp-microvolt = <0xf4240 0xf4240 0x124f80>; | |
| opp-microvolt-L0 = <0xf4240 0xf4240 0x124f80>; | |
| opp-microvolt-L1 = <0xee098 0xee098 0x124f80>; | |
| opp-microvolt-L2 = <0xe7ef0 0xe7ef0 0x124f80>; | |
| opp-microvolt-L3 = <0xe1d48 0xe1d48 0x124f80>; | |
| clock-latency-ns = <0x9c40>; | |
| }; | |
| opp-1416000000 { | |
| opp-hz = <0x0 0x54667200>; | |
| opp-microvolt = <0x112a88 0x112a88 0x124f80>; | |
| opp-microvolt-L0 = <0x112a88 0x112a88 0x124f80>; | |
| opp-microvolt-L1 = <0x10c8e0 0x10c8e0 0x124f80>; | |
| opp-microvolt-L2 = <0x106738 0x106738 0x124f80>; | |
| opp-microvolt-L3 = <0x100590 0x100590 0x124f80>; | |
| clock-latency-ns = <0x9c40>; | |
| }; | |
| }; | |
| opp-table1 { | |
| compatible = "operating-points-v2"; | |
| opp-shared; | |
| rockchip,temp-hysteresis = <0x1388>; | |
| rockchip,low-temp = <0x0>; | |
| rockchip,low-temp-min-volt = <0xdbba0>; | |
| nvmem-cells = <0xc9>; | |
| nvmem-cell-names = "cpu_leakage"; | |
| rockchip,pvtm-voltage-sel = <0x0 0x24608 0x0 0x24609 0x25d78 0x1 0x25d79 0x27100 0x2 0x27101 0xf423f 0x3>; | |
| rockchip,pvtm-freq = <0x639c0>; | |
| rockchip,pvtm-volt = <0xf4240>; | |
| rockchip,pvtm-ch = <0x1 0x0>; | |
| rockchip,pvtm-sample-time = <0x3e8>; | |
| rockchip,pvtm-number = <0xa>; | |
| rockchip,pvtm-error = <0x3e8>; | |
| rockchip,pvtm-ref-temp = <0x29>; | |
| rockchip,pvtm-temp-prop = <0x47 0x23>; | |
| rockchip,thermal-zone = "soc-thermal"; | |
| phandle = <0xf>; | |
| opp-408000000 { | |
| opp-hz = <0x0 0x18519600>; | |
| opp-microvolt = <0xc3500 0xc3500 0x124f80>; | |
| opp-microvolt-L0 = <0xc3500 0xc3500 0x124f80>; | |
| opp-microvolt-L1 = <0xc3500 0xc3500 0x124f80>; | |
| opp-microvolt-L2 = <0xc3500 0xc3500 0x124f80>; | |
| opp-microvolt-L3 = <0xc3500 0xc3500 0x124f80>; | |
| clock-latency-ns = <0x9c40>; | |
| }; | |
| opp-600000000 { | |
| opp-hz = <0x0 0x23c34600>; | |
| opp-microvolt = <0xc3500 0xc3500 0x124f80>; | |
| opp-microvolt-L0 = <0xc3500 0xc3500 0x124f80>; | |
| opp-microvolt-L1 = <0xc3500 0xc3500 0x124f80>; | |
| opp-microvolt-L2 = <0xc3500 0xc3500 0x124f80>; | |
| opp-microvolt-L3 = <0xc3500 0xc3500 0x124f80>; | |
| clock-latency-ns = <0x9c40>; | |
| }; | |
| opp-816000000 { | |
| opp-hz = <0x0 0x30a32c00>; | |
| opp-microvolt = <0xc96a8 0xc96a8 0x124f80>; | |
| opp-microvolt-L0 = <0xc96a8 0xc96a8 0x124f80>; | |
| opp-microvolt-L1 = <0xc96a8 0xc96a8 0x124f80>; | |
| opp-microvolt-L2 = <0xc3500 0xc3500 0x124f80>; | |
| opp-microvolt-L3 = <0xc3500 0xc3500 0x124f80>; | |
| clock-latency-ns = <0x9c40>; | |
| opp-suspend; | |
| }; | |
| opp-1008000000 { | |
| opp-hz = <0x0 0x3c14dc00>; | |
| opp-microvolt = <0xd59f8 0xd59f8 0x124f80>; | |
| opp-microvolt-L0 = <0xd59f8 0xd59f8 0x124f80>; | |
| opp-microvolt-L1 = <0xcf850 0xcf850 0x124f80>; | |
| opp-microvolt-L2 = <0xcf850 0xcf850 0x124f80>; | |
| opp-microvolt-L3 = <0xcf850 0xcf850 0x124f80>; | |
| clock-latency-ns = <0x9c40>; | |
| }; | |
| opp-1200000000 { | |
| opp-hz = <0x0 0x47868c00>; | |
| opp-microvolt = <0xe7ef0 0xe7ef0 0x124f80>; | |
| opp-microvolt-L0 = <0xe7ef0 0xe7ef0 0x124f80>; | |
| opp-microvolt-L1 = <0xe1d48 0xe1d48 0x124f80>; | |
| opp-microvolt-L2 = <0xdbba0 0xdbba0 0x124f80>; | |
| opp-microvolt-L3 = <0xd59f8 0xd59f8 0x124f80>; | |
| clock-latency-ns = <0x9c40>; | |
| }; | |
| opp-1416000000 { | |
| opp-hz = <0x0 0x54667200>; | |
| opp-microvolt = <0xfa3e8 0xfa3e8 0x124f80>; | |
| opp-microvolt-L0 = <0xfa3e8 0xfa3e8 0x124f80>; | |
| opp-microvolt-L1 = <0xf4240 0xf4240 0x124f80>; | |
| opp-microvolt-L2 = <0xf4240 0xf4240 0x124f80>; | |
| opp-microvolt-L3 = <0xee098 0xee098 0x124f80>; | |
| clock-latency-ns = <0x9c40>; | |
| }; | |
| opp-1608000000 { | |
| opp-hz = <0x0 0x5fd82200>; | |
| opp-microvolt = <0x10c8e0 0x10c8e0 0x124f80>; | |
| opp-microvolt-L0 = <0x10c8e0 0x10c8e0 0x124f80>; | |
| opp-microvolt-L1 = <0x106738 0x106738 0x124f80>; | |
| opp-microvolt-L2 = <0x100590 0x100590 0x124f80>; | |
| opp-microvolt-L3 = <0xfa3e8 0xfa3e8 0x124f80>; | |
| clock-latency-ns = <0x9c40>; | |
| }; | |
| opp-1800000000 { | |
| opp-hz = <0x0 0x6b49d200>; | |
| opp-microvolt = <0x124f80 0x124f80 0x124f80>; | |
| opp-microvolt-L0 = <0x124f80 0x124f80 0x124f80>; | |
| opp-microvolt-L1 = <0x11edd8 0x11edd8 0x124f80>; | |
| opp-microvolt-L2 = <0x118c30 0x118c30 0x124f80>; | |
| opp-microvolt-L3 = <0x112a88 0x112a88 0x124f80>; | |
| clock-latency-ns = <0x9c40>; | |
| }; | |
| }; | |
| opp-table2 { | |
| compatible = "operating-points-v2"; | |
| rockchip,thermal-zone = "soc-thermal"; | |
| rockchip,temp-hysteresis = <0x1388>; | |
| rockchip,low-temp = <0x0>; | |
| rockchip,low-temp-min-volt = <0xdbba0>; | |
| nvmem-cells = <0xca>; | |
| nvmem-cell-names = "gpu_leakage"; | |
| rockchip,pvtm-voltage-sel = <0x0 0x1d8a8 0x0 0x1d8a9 0x1ea3c 0x1 0x1ea3d 0x1f5f4 0x2 0x1f5f5 0xf423f 0x3>; | |
| rockchip,pvtm-freq = <0x30d40>; | |
| rockchip,pvtm-volt = <0xdbba0>; | |
| rockchip,pvtm-ch = <0x3 0x0>; | |
| rockchip,pvtm-sample-time = <0x3e8>; | |
| rockchip,pvtm-number = <0xa>; | |
| rockchip,pvtm-error = <0x3e8>; | |
| rockchip,pvtm-ref-temp = <0x29>; | |
| rockchip,pvtm-temp-prop = <0x2e 0xc>; | |
| rockchip,pvtm-thermal-zone = "gpu-thermal"; | |
| phandle = <0x9f>; | |
| opp-200000000 { | |
| opp-hz = <0x0 0xbebc200>; | |
| opp-microvolt = <0xc3500>; | |
| opp-microvolt-L0 = <0xc3500>; | |
| opp-microvolt-L1 = <0xc3500>; | |
| opp-microvolt-L2 = <0xc3500>; | |
| opp-microvolt-L3 = <0xc3500>; | |
| }; | |
| opp-300000000 { | |
| opp-hz = <0x0 0x11e1a300>; | |
| opp-microvolt = <0xc3500>; | |
| opp-microvolt-L0 = <0xc3500>; | |
| opp-microvolt-L1 = <0xc3500>; | |
| opp-microvolt-L2 = <0xc3500>; | |
| opp-microvolt-L3 = <0xc3500>; | |
| }; | |
| opp-400000000 { | |
| opp-hz = <0x0 0x17d78400>; | |
| opp-microvolt = <0xc96a8>; | |
| opp-microvolt-L0 = <0xc96a8>; | |
| opp-microvolt-L1 = <0xc96a8>; | |
| opp-microvolt-L2 = <0xc3500>; | |
| opp-microvolt-L3 = <0xc3500>; | |
| }; | |
| opp-600000000 { | |
| opp-hz = <0x0 0x23c34600>; | |
| opp-microvolt = <0xe1d48>; | |
| opp-microvolt-L0 = <0xe1d48>; | |
| opp-microvolt-L1 = <0xe1d48>; | |
| opp-microvolt-L2 = <0xdbba0>; | |
| opp-microvolt-L3 = <0xdbba0>; | |
| }; | |
| opp-800000000 { | |
| opp-hz = <0x0 0x2faf0800>; | |
| opp-microvolt = <0x10c8e0>; | |
| opp-microvolt-L0 = <0x10c8e0>; | |
| opp-microvolt-L1 = <0x106738>; | |
| opp-microvolt-L2 = <0x100590>; | |
| opp-microvolt-L3 = <0xfa3e8>; | |
| }; | |
| }; | |
| opp-table3 { | |
| compatible = "operating-points-v2"; | |
| phandle = <0x94>; | |
| opp-200000000 { | |
| opp-hz = <0x0 0xbebc200>; | |
| opp-microvolt = <0xdbba0>; | |
| }; | |
| opp-300000000 { | |
| opp-hz = <0x0 0x11e1a300>; | |
| opp-microvolt = <0xdbba0>; | |
| }; | |
| opp-400000000 { | |
| opp-hz = <0x0 0x17d78400>; | |
| opp-microvolt = <0xdbba0>; | |
| }; | |
| opp-528000000 { | |
| opp-hz = <0x0 0x1f78a400>; | |
| opp-microvolt = <0xdbba0>; | |
| }; | |
| opp-600000000 { | |
| opp-hz = <0x0 0x23c34600>; | |
| opp-microvolt = <0xdbba0>; | |
| }; | |
| opp-800000000 { | |
| opp-hz = <0x0 0x2faf0800>; | |
| opp-microvolt = <0xdbba0>; | |
| }; | |
| }; | |
| chosen { | |
| bootargs = "sdfwupdate storagemedia=sd androidboot.mode=sd androidboot.slot_suffix= androidboot.serialno=526e84fcaa8e34b9 rw rootwait earlycon=uart8250,mmio32,0xff1a0000 swiotlb=1 console=ttyFIQ0 root=PARTUUID=614e0000-0000 rootfstype=ext4"; | |
| }; | |
| reserved-memory { | |
| #address-cells = <0x2>; | |
| #size-cells = <0x2>; | |
| ranges; | |
| drm-logo@00000000 { | |
| compatible = "rockchip,drm-logo"; | |
| reg = <0x0 0x0 0x0 0x0>; | |
| phandle = <0xc2>; | |
| }; | |
| }; | |
| fiq-debugger { | |
| compatible = "rockchip,fiq-debugger"; | |
| rockchip,serial-id = <0x2>; | |
| rockchip,signal-irq = <0xb6>; | |
| rockchip,wake-irq = <0x0>; | |
| rockchip,irq-mode-enable = <0x1>; | |
| rockchip,baudrate = <0x16e360>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x48>; | |
| phandle = <0x187>; | |
| }; | |
| cif_isp@ff910000 { | |
| compatible = "rockchip,rk3399-cif-isp"; | |
| rockchip,grf = <0x17>; | |
| reg = <0x0 0xff910000 0x0 0x4000 0x0 0xff968000 0x0 0x8000>; | |
| reg-names = "register", "dsihost-register"; | |
| clocks = <0x8 0xe7 0x8 0xe9 0x8 0x1e1 0x8 0x1e3 0x8 0x6e 0x8 0xa5 0x8 0x89 0x8 0x89 0x8 0x77>; | |
| clock-names = "aclk_isp0_noc", "aclk_isp0_wrapper", "hclk_isp0_noc", "hclk_isp0_wrapper", "clk_isp0", "pclk_dphyrx", "clk_cif_out", "clk_cif_pll", "pclk_dphy_ref"; | |
| interrupts = <0x0 0x2b 0x4 0x0>; | |
| interrupt-names = "cif_isp10_irq"; | |
| power-domains = <0x16 0x13>; | |
| rockchip,isp,iommu-enable = <0x1>; | |
| iommus = <0xb0>; | |
| status = "disabled"; | |
| phandle = <0x188>; | |
| }; | |
| cif_isp@ff920000 { | |
| compatible = "rockchip,rk3399-cif-isp"; | |
| rockchip,grf = <0x17>; | |
| reg = <0x0 0xff920000 0x0 0x4000 0x0 0xff968000 0x0 0x8000>; | |
| reg-names = "register", "dsihost-register"; | |
| clocks = <0x8 0xe8 0x8 0xea 0x8 0x1e2 0x8 0x1e4 0x8 0x6f 0x8 0x17b 0x8 0xa4 0x8 0x171 0x8 0x78 0x8 0x89 0x8 0x89 0x8 0x77>; | |
| clock-names = "aclk_isp1_noc", "aclk_isp1_wrapper", "hclk_isp1_noc", "hclk_isp1_wrapper", "clk_isp1", "pclkin_isp1", "pclk_dphytxrx", "pclk_mipi_dsi", "mipi_dphy_cfg", "clk_cif_out", "clk_cif_pll", "pclk_dphy_ref"; | |
| interrupts = <0x0 0x2c 0x4 0x0>; | |
| interrupt-names = "cif_isp10_irq"; | |
| power-domains = <0x16 0x14>; | |
| rockchip,isp,iommu-enable = <0x1>; | |
| iommus = <0xb1>; | |
| status = "disabled"; | |
| phandle = <0x189>; | |
| }; | |
| backlight { | |
| status = "okay"; | |
| compatible = "pwm-backlight"; | |
| pwms = <0xcb 0x0 0x61a8 0x0>; | |
| brightness-levels = <0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2a 0x2b 0x2c 0x2d 0x2e 0x2f 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3a 0x3b 0x3c 0x3d 0x3e 0x3f 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4a 0x4b 0x4c 0x4d 0x4e 0x4f 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5a 0x5b 0x5c 0x5d 0x5e 0x5f 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6a 0x6b 0x6c 0x6d 0x6e 0x6f 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7a 0x7b 0x7c 0x7d 0x7e 0x7f 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8f 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9a 0x9b 0x9c 0x9d 0x9e 0x9f 0xa0 0xa1 0xa2 0xa3 0xa4 0xa5 0xa6 0xa7 0xa8 0xa9 0xaa 0xab 0xac 0xad 0xae 0xaf 0xb0 0xb1 0xb2 0xb3 0xb4 0xb5 0xb6 0xb7 0xb8 0xb9 0xba 0xbb 0xbc 0xbd 0xbe 0xbf 0xc0 0xc1 0xc2 0xc3 0xc4 0xc5 0xc6 0xc7 0xc8 0xc9 0xca 0xcb 0xcc 0xcd 0xce 0xcf 0xd0 0xd1 0xd2 0xd3 0xd4 0xd5 0xd6 0xd7 0xd8 0xd9 0xda 0xdb 0xdc 0xdd 0xde 0xdf 0xe0 0xe1 0xe2 0xe3 0xe4 0xe5 0xe6 0xe7 0xe8 0xe9 0xea 0xeb 0xec 0xed 0xee 0xef 0xf0 0xf1 0xf2 0xf3 0xf4 0xf5 0xf6 0xf7 0xf8 0xf9 0xfa 0xfb 0xfc 0xfd 0xfe 0xff>; | |
| default-brightness-level = <0xc8>; | |
| phandle = <0xb8>; | |
| }; | |
| sram@ff8d0000 { | |
| compatible = "mmio-sram"; | |
| reg = <0x0 0xff8d0000 0x0 0x20000>; | |
| phandle = <0x18a>; | |
| }; | |
| external-gmac-clock { | |
| compatible = "fixed-clock"; | |
| clock-frequency = <0x7735940>; | |
| clock-output-names = "clkin_gmac"; | |
| #clock-cells = <0x0>; | |
| phandle = <0x1a>; | |
| }; | |
| dw-hdmi-audio { | |
| status = "disabled"; | |
| compatible = "rockchip,dw-hdmi-audio"; | |
| #sound-dai-cells = <0x0>; | |
| phandle = <0xcf>; | |
| }; | |
| edp-panel { | |
| status = "disabled"; | |
| compatible = "sharp,lcd-f402", "panel-simple"; | |
| backlight = <0xb8>; | |
| power-supply = <0xb7>; | |
| enable-gpios = <0x85 0x1d 0x0>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0xcc>; | |
| phandle = <0x18b>; | |
| ports { | |
| endpoint { | |
| remote-endpoint = <0xcd>; | |
| phandle = <0xbf>; | |
| }; | |
| }; | |
| }; | |
| hdmi-sound { | |
| status = "disabled"; | |
| compatible = "simple-audio-card"; | |
| simple-audio-card,format = "i2s"; | |
| simple-audio-card,mclk-fs = <0x100>; | |
| simple-audio-card,name = "rockchip,hdmi"; | |
| phandle = <0x18c>; | |
| simple-audio-card,cpu { | |
| sound-dai = <0xce>; | |
| }; | |
| simple-audio-card,codec { | |
| sound-dai = <0xcf>; | |
| }; | |
| }; | |
| hdmi-codec { | |
| status = "disabled"; | |
| compatible = "simple-audio-card"; | |
| simple-audio-card,format = "i2s"; | |
| simple-audio-card,mclk-fs = <0x100>; | |
| simple-audio-card,name = "HDMI-CODEC"; | |
| phandle = <0x18d>; | |
| simple-audio-card,cpu { | |
| sound-dai = <0xce>; | |
| }; | |
| simple-audio-card,codec { | |
| sound-dai = <0xd0>; | |
| }; | |
| }; | |
| hdmi-dp-sound { | |
| status = "okay"; | |
| compatible = "rockchip,rk3399-hdmi-dp"; | |
| rockchip,cpu = <0xce>; | |
| rockchip,codec = <0xd0 0xd1>; | |
| phandle = <0x18e>; | |
| }; | |
| vcc3v3-sys { | |
| compatible = "regulator-fixed"; | |
| regulator-name = "vcc3v3_sys"; | |
| regulator-always-on; | |
| regulator-boot-on; | |
| regulator-min-microvolt = <0x325aa0>; | |
| regulator-max-microvolt = <0x325aa0>; | |
| phandle = <0x3b>; | |
| }; | |
| vcc3v3-pcie-regulator { | |
| compatible = "regulator-fixed"; | |
| enable-active-high; | |
| regulator-boot-on; | |
| regulator-always-on; | |
| gpio = <0x37 0x11 0x0>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0xd2>; | |
| regulator-name = "vcc3v3_pcie"; | |
| phandle = <0x18f>; | |
| }; | |
| vcc5v0-host-regulator { | |
| compatible = "regulator-fixed"; | |
| enable-active-high; | |
| gpio = <0x37 0x0 0x0>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0xd3>; | |
| regulator-name = "vcc5v0_host"; | |
| regulator-always-on; | |
| phandle = <0x99>; | |
| }; | |
| vcc_hub_en-regulator { | |
| compatible = "regulator-fixed"; | |
| enable-active-high; | |
| gpio = <0xd4 0x4 0x0>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0xd5>; | |
| regulator-name = "vcc_hub_en"; | |
| regulator-always-on; | |
| phandle = <0x190>; | |
| }; | |
| vcc-dis-en { | |
| compatible = "regulator-fixed"; | |
| enable-active-high; | |
| gpio = <0xd4 0x6 0x0>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0xd6>; | |
| regulator-name = "vcc_dis_en"; | |
| regulator-always-on; | |
| phandle = <0x191>; | |
| }; | |
| vcc-wifi { | |
| status = "okay"; | |
| compatible = "regulator-fixed"; | |
| regulator-name = "vcc_wifi"; | |
| enable-active-high; | |
| gpio = <0x85 0x1b 0x0>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0xd7>; | |
| regulator-always-on; | |
| regulator-boot-on; | |
| regulator-min-microvolt = <0x4c4b40>; | |
| regulator-max-microvolt = <0x4c4b40>; | |
| phandle = <0x192>; | |
| }; | |
| vcc-pcie { | |
| status = "okay"; | |
| compatible = "regulator-fixed"; | |
| regulator-name = "vcc_pcie"; | |
| enable-active-high; | |
| gpio = <0x37 0x11 0x0>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0xd8>; | |
| regulator-always-on; | |
| regulator-boot-on; | |
| regulator-min-microvolt = <0x4c4b40>; | |
| regulator-max-microvolt = <0x4c4b40>; | |
| phandle = <0x193>; | |
| }; | |
| vcc-chargen { | |
| status = "disabled"; | |
| compatible = "regulator-fixed"; | |
| regulator-name = "vcc_chargen"; | |
| enable-active-high; | |
| gpio = <0xd4 0x1c 0x0>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0xd9>; | |
| regulator-always-on; | |
| regulator-boot-on; | |
| regulator-min-microvolt = <0x4c4b40>; | |
| regulator-max-microvolt = <0x4c4b40>; | |
| phandle = <0x194>; | |
| }; | |
| vcc-sd { | |
| compatible = "regulator-fixed"; | |
| enable-active-high; | |
| gpio = <0x85 0x1e 0x0>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0xda>; | |
| regulator-name = "vcc_sd"; | |
| regulator-min-microvolt = <0x325aa0>; | |
| regulator-max-microvolt = <0x325aa0>; | |
| phandle = <0x20>; | |
| }; | |
| vcc5v0-sys { | |
| compatible = "regulator-fixed"; | |
| regulator-name = "vcc5v0_sys"; | |
| regulator-always-on; | |
| regulator-boot-on; | |
| regulator-min-microvolt = <0x4c4b40>; | |
| regulator-max-microvolt = <0x4c4b40>; | |
| phandle = <0x35>; | |
| }; | |
| vcc-phy-regulator { | |
| compatible = "regulator-fixed"; | |
| regulator-name = "vcc_phy"; | |
| regulator-always-on; | |
| regulator-boot-on; | |
| phandle = <0x18>; | |
| }; | |
| vdd-log { | |
| compatible = "pwm-regulator"; | |
| pwms = <0xdb 0x0 0x61a8 0x1>; | |
| regulator-name = "vdd_log"; | |
| regulator-min-microvolt = <0xc3500>; | |
| regulator-max-microvolt = <0x10c8e0>; | |
| regulator-always-on; | |
| regulator-boot-on; | |
| rockchip,pwm_id = <0x2>; | |
| rockchip,pwm_voltage = <0xf4240>; | |
| phandle = <0x195>; | |
| }; | |
| vcc-lcd-regulator { | |
| compatible = "regulator-fixed"; | |
| regulator-always-on; | |
| regulator-boot-on; | |
| enable-active-high; | |
| gpio = <0x37 0x18 0x0>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0xdc>; | |
| regulator-name = "vcc_lcd"; | |
| phandle = <0xb7>; | |
| }; | |
| sdio-pwrseq { | |
| compatible = "mmc-pwrseq-simple"; | |
| clocks = <0xdd 0x1>; | |
| clock-names = "ext_clock"; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0xde>; | |
| reset-gpios = <0xdf 0xa 0x1>; | |
| phandle = <0x1c>; | |
| }; | |
| wireless-wlan { | |
| compatible = "wlan-platdata"; | |
| rockchip,grf = <0x17>; | |
| wifi_chip_type = "ap6354"; | |
| sdio_vref = <0x708>; | |
| WIFI,host_wake_irq = <0xdf 0x3 0x0>; | |
| status = "okay"; | |
| }; | |
| wireless-bluetooth { | |
| compatible = "bluetooth-platdata"; | |
| clocks = <0xdd 0x1>; | |
| clock-name = "ext_clock"; | |
| uart_rts_gpios = <0xd4 0x13 0x1>; | |
| pinctrl-names = "default", "rts_gpio"; | |
| pinctrl-0 = <0xe0>; | |
| pinctrl-1 = <0xe1>; | |
| BT,reset_gpio = <0xdf 0x9 0x0>; | |
| BT,wake_gpio = <0xd4 0x1a 0x0>; | |
| BT,wake_host_irq = <0xdf 0x4 0x0>; | |
| status = "okay"; | |
| }; | |
| leds { | |
| compatible = "gpio-leds"; | |
| power { | |
| label = "firefly:blue:power"; | |
| linux,default-trigger = "ir-power-click"; | |
| default-state = "on"; | |
| gpios = <0xd4 0x1b 0x0>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0xe2>; | |
| }; | |
| user { | |
| label = "firefly:yellow:user"; | |
| linux,default-trigger = "ir-user-click"; | |
| default-state = "off"; | |
| gpios = <0xdf 0x2 0x0>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0xe3>; | |
| }; | |
| }; | |
| usb-charge { | |
| compatible = "usb-ext-charge"; | |
| status = "okay"; | |
| io-channels = <0xe4 0x0>; | |
| extcon = <0x29>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0xd9 0xe5 0xe6>; | |
| bat-int = <0xd4 0x1c 0x1>; | |
| charge-en-gpios = <0xdf 0x1 0x0>; | |
| cur-ctl-gpios = <0x19 0x1a 0x0>; | |
| poe-state-gpios = <0xdf 0xc 0x0>; | |
| }; | |
| __symbols__ { | |
| ddr_timing = "/ddr_timing"; | |
| cpu_l0 = "/cpus/cpu@0"; | |
| cpu_l1 = "/cpus/cpu@1"; | |
| cpu_l2 = "/cpus/cpu@2"; | |
| cpu_l3 = "/cpus/cpu@3"; | |
| cpu_b0 = "/cpus/cpu@100"; | |
| cpu_b1 = "/cpus/cpu@101"; | |
| CPU_SLEEP = "/cpus/idle-states/cpu-sleep"; | |
| CLUSTER_SLEEP = "/cpus/idle-states/cluster-sleep"; | |
| xin24m = "/xin24m"; | |
| dummy_cpll = "/dummy_cpll"; | |
| dummy_vpll = "/dummy_vpll"; | |
| dmac_bus = "/amba/dma-controller@ff6d0000"; | |
| dmac_peri = "/amba/dma-controller@ff6e0000"; | |
| gmac = "/ethernet@fe300000"; | |
| sdio0 = "/dwmmc@fe310000"; | |
| sdmmc = "/dwmmc@fe320000"; | |
| sdhci = "/sdhci@fe330000"; | |
| usic = "/usb@fe340000"; | |
| usb_host0_ehci = "/usb@fe380000"; | |
| usb_host0_ohci = "/usb@fe3a0000"; | |
| usb_host1_ehci = "/usb@fe3c0000"; | |
| usb_host1_ohci = "/usb@fe3e0000"; | |
| usbdrd3_0 = "/usb@fe800000"; | |
| usbdrd_dwc3_0 = "/usb@fe800000/dwc3@fe800000"; | |
| usbdrd3_1 = "/usb@fe900000"; | |
| usbdrd_dwc3_1 = "/usb@fe900000/dwc3@fe900000"; | |
| cdn_dp = "/dp@fec00000"; | |
| dp_in = "/dp@fec00000/ports/port"; | |
| dp_in_vopb = "/dp@fec00000/ports/port/endpoint@0"; | |
| dp_in_vopl = "/dp@fec00000/ports/port/endpoint@1"; | |
| gic = "/interrupt-controller@fee00000"; | |
| its = "/interrupt-controller@fee00000/interrupt-controller@fee20000"; | |
| ppi_cluster0 = "/interrupt-controller@fee00000/ppi-partitions/interrupt-partition-0"; | |
| ppi_cluster1 = "/interrupt-controller@fee00000/ppi-partitions/interrupt-partition-1"; | |
| saradc = "/saradc@ff100000"; | |
| i2c0 = "/i2c@ff3c0000"; | |
| vdd_cpu_b = "/i2c@ff3c0000/syr827@40"; | |
| vdd_gpu = "/i2c@ff3c0000/syr828@41"; | |
| rk808 = "/i2c@ff3c0000/pmic@1b"; | |
| vdd_center = "/i2c@ff3c0000/pmic@1b/regulators/DCDC_REG1"; | |
| vdd_cpu_l = "/i2c@ff3c0000/pmic@1b/regulators/DCDC_REG2"; | |
| vcc_ddr = "/i2c@ff3c0000/pmic@1b/regulators/DCDC_REG3"; | |
| vcc_1v8 = "/i2c@ff3c0000/pmic@1b/regulators/DCDC_REG4"; | |
| vcca1v8_codec = "/i2c@ff3c0000/pmic@1b/regulators/LDO_REG1"; | |
| vcc1v8_hdmi = "/i2c@ff3c0000/pmic@1b/regulators/LDO_REG2"; | |
| vcc1v8_pmu = "/i2c@ff3c0000/pmic@1b/regulators/LDO_REG3"; | |
| vccio_sd = "/i2c@ff3c0000/pmic@1b/regulators/LDO_REG4"; | |
| vcca3v0_codec = "/i2c@ff3c0000/pmic@1b/regulators/LDO_REG5"; | |
| vcc_1v5 = "/i2c@ff3c0000/pmic@1b/regulators/LDO_REG6"; | |
| vcca0v9_hdmi = "/i2c@ff3c0000/pmic@1b/regulators/LDO_REG7"; | |
| vcc_3v0 = "/i2c@ff3c0000/pmic@1b/regulators/LDO_REG8"; | |
| vcc3v3_s3 = "/i2c@ff3c0000/pmic@1b/regulators/SWITCH_REG1"; | |
| vcc3v3_s0 = "/i2c@ff3c0000/pmic@1b/regulators/SWITCH_REG2"; | |
| i2c1 = "/i2c@ff110000"; | |
| i2c2 = "/i2c@ff120000"; | |
| i2c3 = "/i2c@ff130000"; | |
| i2c5 = "/i2c@ff140000"; | |
| i2c6 = "/i2c@ff150000"; | |
| i2c7 = "/i2c@ff160000"; | |
| fusb0 = "/i2c@ff160000/fusb30x@22"; | |
| mp8859 = "/i2c@ff160000/mp8859@66"; | |
| sys_12v = "/i2c@ff160000/mp8859@66/regulators/mp8859_dcdc1"; | |
| uart0 = "/serial@ff180000"; | |
| uart1 = "/serial@ff190000"; | |
| uart2 = "/serial@ff1a0000"; | |
| uart3 = "/serial@ff1b0000"; | |
| spi0 = "/spi@ff1c0000"; | |
| spi1 = "/spi@ff1d0000"; | |
| spi2 = "/spi@ff1e0000"; | |
| spi4 = "/spi@ff1f0000"; | |
| spi5 = "/spi@ff200000"; | |
| thermal_zones = "/thermal-zones"; | |
| soc_thermal = "/thermal-zones/soc-thermal"; | |
| threshold = "/thermal-zones/soc-thermal/trips/trip-point-0"; | |
| target = "/thermal-zones/soc-thermal/trips/trip-point-1"; | |
| soc_crit = "/thermal-zones/soc-thermal/trips/soc-crit"; | |
| gpu_thermal = "/thermal-zones/gpu-thermal"; | |
| tsadc = "/tsadc@ff260000"; | |
| qos_emmc = "/qos@ffa58000"; | |
| qos_gmac = "/qos@ffa5c000"; | |
| qos_pcie = "/qos@ffa60080"; | |
| qos_usb_host0 = "/qos@ffa60100"; | |
| qos_usb_host1 = "/qos@ffa60180"; | |
| qos_usb_otg0 = "/qos@ffa70000"; | |
| qos_usb_otg1 = "/qos@ffa70080"; | |
| qos_sd = "/qos@ffa74000"; | |
| qos_sdioaudio = "/qos@ffa76000"; | |
| qos_hdcp = "/qos@ffa90000"; | |
| qos_iep = "/qos@ffa98000"; | |
| qos_isp0_m0 = "/qos@ffaa0000"; | |
| qos_isp0_m1 = "/qos@ffaa0080"; | |
| qos_isp1_m0 = "/qos@ffaa8000"; | |
| qos_isp1_m1 = "/qos@ffaa8080"; | |
| qos_rga_r = "/qos@ffab0000"; | |
| qos_rga_w = "/qos@ffab0080"; | |
| qos_video_m0 = "/qos@ffab8000"; | |
| qos_video_m1_r = "/qos@ffac0000"; | |
| qos_video_m1_w = "/qos@ffac0080"; | |
| qos_vop_big_r = "/qos@ffac8000"; | |
| qos_vop_big_w = "/qos@ffac8080"; | |
| qos_vop_little = "/qos@ffad0000"; | |
| qos_perihp = "/qos@ffad8080"; | |
| qos_gpu = "/qos@ffae0000"; | |
| pmu = "/power-management@ff310000"; | |
| power = "/power-management@ff310000/power-controller"; | |
| pmugrf = "/syscon@ff320000"; | |
| pmu_io_domains = "/syscon@ff320000/io-domains"; | |
| pmu_pvtm = "/syscon@ff320000/pmu-pvtm"; | |
| spi3 = "/spi@ff350000"; | |
| uart4 = "/serial@ff370000"; | |
| i2c4 = "/i2c@ff3d0000"; | |
| gsl3680 = "/i2c@ff3d0000/gsl3680@40"; | |
| fusb1 = "/i2c@ff3d0000/fusb30x@22"; | |
| i2c8 = "/i2c@ff3e0000"; | |
| pcie_phy = "/pcie-phy"; | |
| pcie0 = "/pcie@f8000000"; | |
| pcie0_intc = "/pcie@f8000000/interrupt-controller"; | |
| pwm0 = "/pwm@ff420000"; | |
| pwm1 = "/pwm@ff420010"; | |
| pwm2 = "/pwm@ff420020"; | |
| pwm3 = "/pwm@ff420030"; | |
| dfi = "/dfi@ff630000"; | |
| dmc = "/dmc"; | |
| vpu = "/vpu_service@ff650000"; | |
| vpu_mmu = "/iommu@ff650800"; | |
| rkvdec = "/rkvdec@ff660000"; | |
| vdec_mmu = "/iommu@ff660480"; | |
| iep = "/iep@ff670000"; | |
| iep_mmu = "/iommu@ff670800"; | |
| rga = "/rga@ff680000"; | |
| efuse0 = "/efuse@ff690000"; | |
| cpu_id = "/efuse@ff690000/cpu-id@7"; | |
| cpub_leakage = "/efuse@ff690000/cpu-leakage@17"; | |
| gpu_leakage = "/efuse@ff690000/gpu-leakage@18"; | |
| center_leakage = "/efuse@ff690000/center-leakage@19"; | |
| cpul_leakage = "/efuse@ff690000/cpu-leakage@1a"; | |
| logic_leakage = "/efuse@ff690000/logic-leakage@1b"; | |
| wafer_info = "/efuse@ff690000/wafer-info@1c"; | |
| pmucru = "/pmu-clock-controller@ff750000"; | |
| cru = "/clock-controller@ff760000"; | |
| grf = "/syscon@ff770000"; | |
| io_domains = "/syscon@ff770000/io-domains"; | |
| u2phy0 = "/syscon@ff770000/usb2-phy@e450"; | |
| u2phy0_host = "/syscon@ff770000/usb2-phy@e450/host-port"; | |
| u2phy0_otg = "/syscon@ff770000/usb2-phy@e450/otg-port"; | |
| u2phy1 = "/syscon@ff770000/usb2-phy@e460"; | |
| u2phy1_host = "/syscon@ff770000/usb2-phy@e460/host-port"; | |
| u2phy1_otg = "/syscon@ff770000/usb2-phy@e460/otg-port"; | |
| emmc_phy = "/syscon@ff770000/phy@f780"; | |
| mipi_dphy_rx0 = "/syscon@ff770000/mipi-dphy-rx0"; | |
| pvtm = "/syscon@ff770000/pvtm"; | |
| tcphy0 = "/phy@ff7c0000"; | |
| tcphy0_dp = "/phy@ff7c0000/dp-port"; | |
| tcphy0_usb3 = "/phy@ff7c0000/usb3-port"; | |
| tcphy1 = "/phy@ff800000"; | |
| tcphy1_dp = "/phy@ff800000/dp-port"; | |
| tcphy1_usb3 = "/phy@ff800000/usb3-port"; | |
| wdt = "/watchdog@ff848000"; | |
| rktimer = "/rktimer@ff850000"; | |
| spdif = "/spdif@ff870000"; | |
| i2s0 = "/i2s@ff880000"; | |
| i2s1 = "/i2s@ff890000"; | |
| i2s2 = "/i2s@ff8a0000"; | |
| gpu = "/gpu@ff9a0000"; | |
| gpu_power_model = "/gpu@ff9a0000/power_model"; | |
| vopl = "/vop@ff8f0000"; | |
| vopl_out = "/vop@ff8f0000/port"; | |
| vopl_out_dsi = "/vop@ff8f0000/port/endpoint@0"; | |
| vopl_out_edp = "/vop@ff8f0000/port/endpoint@1"; | |
| vopl_out_hdmi = "/vop@ff8f0000/port/endpoint@2"; | |
| vopl_out_dp = "/vop@ff8f0000/port/endpoint@3"; | |
| vopl_out_dsi1 = "/vop@ff8f0000/port/endpoint@4"; | |
| vop1_pwm = "/voppwm@ff8f01a0"; | |
| vopl_mmu = "/iommu@ff8f3f00"; | |
| vopb = "/vop@ff900000"; | |
| vopb_out = "/vop@ff900000/port"; | |
| vopb_out_edp = "/vop@ff900000/port/endpoint@0"; | |
| vopb_out_dsi = "/vop@ff900000/port/endpoint@1"; | |
| vopb_out_hdmi = "/vop@ff900000/port/endpoint@2"; | |
| vopb_out_dp = "/vop@ff900000/port/endpoint@3"; | |
| vopb_out_dsi1 = "/vop@ff900000/port/endpoint@4"; | |
| vop0_pwm = "/voppwm@ff9001a0"; | |
| vopb_mmu = "/iommu@ff903f00"; | |
| rkisp1_0 = "/rkisp1@ff910000"; | |
| isp0_mmu = "/iommu@ff914000"; | |
| rkisp1_1 = "/rkisp1@ff920000"; | |
| isp1_mmu = "/iommu@ff924000"; | |
| hdmi = "/hdmi@ff940000"; | |
| hdmi_in = "/hdmi@ff940000/ports/port"; | |
| hdmi_in_vopb = "/hdmi@ff940000/ports/port/endpoint@0"; | |
| hdmi_in_vopl = "/hdmi@ff940000/ports/port/endpoint@1"; | |
| dsi = "/dsi@ff960000"; | |
| dsi_in_vopb = "/dsi@ff960000/ports/port/endpoint@0"; | |
| dsi_in_vopl = "/dsi@ff960000/ports/port/endpoint@1"; | |
| dsi_panel = "/dsi@ff960000/panel"; | |
| disp_timings = "/dsi@ff960000/panel/display-timings"; | |
| timing0 = "/dsi@ff960000/panel/display-timings/timing0"; | |
| dsi1 = "/dsi@ff968000"; | |
| dsi1_in_vopb = "/dsi@ff968000/ports/port/endpoint@0"; | |
| dsi1_in_vopl = "/dsi@ff968000/ports/port/endpoint@1"; | |
| mipi_dphy_tx1rx1 = "/mipi-dphy-tx1rx1@0xff968000"; | |
| edp = "/edp@ff970000"; | |
| edp_in = "/edp@ff970000/ports/port@0"; | |
| edp_in_vopb = "/edp@ff970000/ports/port@0/endpoint@0"; | |
| edp_in_vopl = "/edp@ff970000/ports/port@0/endpoint@1"; | |
| edp_out = "/edp@ff970000/ports/port@1"; | |
| edp_out_panel = "/edp@ff970000/ports/port@1/endpoint@0"; | |
| hdmi_hdcp2 = "/hdmi-hdcp2@ff988000"; | |
| display_subsystem = "/display-subsystem"; | |
| route_hdmi = "/display-subsystem/route/route-hdmi"; | |
| route_dsi = "/display-subsystem/route/route-dsi"; | |
| route_edp = "/display-subsystem/route/route-edp"; | |
| nocp_cci_msch0 = "/nocp-cci-msch0@ffa86000"; | |
| nocp_gpu_msch0 = "/nocp-gpu-msch0@ffa86400"; | |
| nocp_hp_msch0 = "/nocp-hp-msch0@ffa86800"; | |
| nocp_lp_msch0 = "/nocp-lp-msch0@ffa86c00"; | |
| nocp_video_msch0 = "/nocp-video-msch0@ffa87000"; | |
| nocp_vio0_msch0 = "/nocp-vio0-msch0@ffa87400"; | |
| nocp_vio1_msch0 = "/nocp-vio1-msch0@ffa87800"; | |
| nocp_cci_msch1 = "/nocp-cci-msch1@ffa8e000"; | |
| nocp_gpu_msch1 = "/nocp-gpu-msch1@ffa8e400"; | |
| nocp_hp_msch1 = "/nocp-hp-msch1@ffa8e800"; | |
| nocp_lp_msch1 = "/nocp-lp-msch1@ffa8ec00"; | |
| nocp_video_msch1 = "/nocp-video-msch1@ffa8f000"; | |
| nocp_vio0_msch1 = "/nocp-vio0-msch1@ffa8f400"; | |
| nocp_vio1_msch1 = "/nocp-vio1-msch1@ffa8f800"; | |
| pinctrl = "/pinctrl"; | |
| gpio0 = "/pinctrl/gpio0@ff720000"; | |
| gpio1 = "/pinctrl/gpio1@ff730000"; | |
| gpio2 = "/pinctrl/gpio2@ff780000"; | |
| gpio3 = "/pinctrl/gpio3@ff788000"; | |
| gpio4 = "/pinctrl/gpio4@ff790000"; | |
| pcfg_pull_up = "/pinctrl/pcfg-pull-up"; | |
| pcfg_pull_down = "/pinctrl/pcfg-pull-down"; | |
| pcfg_pull_none = "/pinctrl/pcfg-pull-none"; | |
| pcfg_pull_up_20ma = "/pinctrl/pcfg-pull-up-20ma"; | |
| pcfg_pull_none_20ma = "/pinctrl/pcfg-pull-none-20ma"; | |
| pcfg_pull_none_18ma = "/pinctrl/pcfg-pull-none-18ma"; | |
| pcfg_pull_none_12ma = "/pinctrl/pcfg-pull-none-12ma"; | |
| pcfg_pull_up_8ma = "/pinctrl/pcfg-pull-up-8ma"; | |
| pcfg_pull_down_4ma = "/pinctrl/pcfg-pull-down-4ma"; | |
| pcfg_pull_up_2ma = "/pinctrl/pcfg-pull-up-2ma"; | |
| pcfg_pull_down_12ma = "/pinctrl/pcfg-pull-down-12ma"; | |
| pcfg_pull_none_13ma = "/pinctrl/pcfg-pull-none-13ma"; | |
| pcfg_output_high = "/pinctrl/pcfg-output-high"; | |
| pcfg_output_low = "/pinctrl/pcfg-output-low"; | |
| pcfg_input = "/pinctrl/pcfg-input"; | |
| emmc_pwr = "/pinctrl/emmc/emmc-pwr"; | |
| rgmii_pins = "/pinctrl/gmac/rgmii-pins"; | |
| rmii_pins = "/pinctrl/gmac/rmii-pins"; | |
| i2c0_xfer = "/pinctrl/i2c0/i2c0-xfer"; | |
| i2c1_xfer = "/pinctrl/i2c1/i2c1-xfer"; | |
| i2c2_xfer = "/pinctrl/i2c2/i2c2-xfer"; | |
| i2c3_xfer = "/pinctrl/i2c3/i2c3-xfer"; | |
| i2c3_gpio = "/pinctrl/i2c3/i2c3_gpio"; | |
| i2c4_xfer = "/pinctrl/i2c4/i2c4-xfer"; | |
| i2c5_xfer = "/pinctrl/i2c5/i2c5-xfer"; | |
| i2c6_xfer = "/pinctrl/i2c6/i2c6-xfer"; | |
| i2c7_xfer = "/pinctrl/i2c7/i2c7-xfer"; | |
| i2c8_xfer = "/pinctrl/i2c8/i2c8-xfer"; | |
| i2s0_8ch_bus = "/pinctrl/i2s0/i2s0-8ch-bus"; | |
| i2s_8ch_mclk = "/pinctrl/i2s0/i2s-8ch-mclk"; | |
| i2s1_2ch_bus = "/pinctrl/i2s1/i2s1-2ch-bus"; | |
| sdio0_bus1 = "/pinctrl/sdio0/sdio0-bus1"; | |
| sdio0_bus4 = "/pinctrl/sdio0/sdio0-bus4"; | |
| sdio0_cmd = "/pinctrl/sdio0/sdio0-cmd"; | |
| sdio0_clk = "/pinctrl/sdio0/sdio0-clk"; | |
| sdio0_cd = "/pinctrl/sdio0/sdio0-cd"; | |
| sdio0_pwr = "/pinctrl/sdio0/sdio0-pwr"; | |
| sdio0_bkpwr = "/pinctrl/sdio0/sdio0-bkpwr"; | |
| sdio0_wp = "/pinctrl/sdio0/sdio0-wp"; | |
| sdio0_int = "/pinctrl/sdio0/sdio0-int"; | |
| sdmmc_bus1 = "/pinctrl/sdmmc/sdmmc-bus1"; | |
| sdmmc_bus4 = "/pinctrl/sdmmc/sdmmc-bus4"; | |
| sdmmc_clk = "/pinctrl/sdmmc/sdmmc-clk"; | |
| sdmmc_cmd = "/pinctrl/sdmmc/sdmmc-cmd"; | |
| sdmmc_cd = "/pinctrl/sdmmc/sdmcc-cd"; | |
| sdmmc_wp = "/pinctrl/sdmmc/sdmmc-wp"; | |
| spdif_bus = "/pinctrl/spdif/spdif-bus"; | |
| spdif_bus_1 = "/pinctrl/spdif/spdif-bus-1"; | |
| spi0_clk = "/pinctrl/spi0/spi0-clk"; | |
| spi0_cs0 = "/pinctrl/spi0/spi0-cs0"; | |
| spi0_cs1 = "/pinctrl/spi0/spi0-cs1"; | |
| spi0_tx = "/pinctrl/spi0/spi0-tx"; | |
| spi0_rx = "/pinctrl/spi0/spi0-rx"; | |
| spi1_clk = "/pinctrl/spi1/spi1-clk"; | |
| spi1_cs0 = "/pinctrl/spi1/spi1-cs0"; | |
| spi1_rx = "/pinctrl/spi1/spi1-rx"; | |
| spi1_tx = "/pinctrl/spi1/spi1-tx"; | |
| spi2_clk = "/pinctrl/spi2/spi2-clk"; | |
| spi2_cs0 = "/pinctrl/spi2/spi2-cs0"; | |
| spi2_rx = "/pinctrl/spi2/spi2-rx"; | |
| spi2_tx = "/pinctrl/spi2/spi2-tx"; | |
| spi3_clk = "/pinctrl/spi3/spi3-clk"; | |
| spi3_cs0 = "/pinctrl/spi3/spi3-cs0"; | |
| spi3_rx = "/pinctrl/spi3/spi3-rx"; | |
| spi3_tx = "/pinctrl/spi3/spi3-tx"; | |
| spi4_clk = "/pinctrl/spi4/spi4-clk"; | |
| spi4_cs0 = "/pinctrl/spi4/spi4-cs0"; | |
| spi4_rx = "/pinctrl/spi4/spi4-rx"; | |
| spi4_tx = "/pinctrl/spi4/spi4-tx"; | |
| spi5_clk = "/pinctrl/spi5/spi5-clk"; | |
| spi5_cs0 = "/pinctrl/spi5/spi5-cs0"; | |
| spi5_rx = "/pinctrl/spi5/spi5-rx"; | |
| spi5_tx = "/pinctrl/spi5/spi5-tx"; | |
| otp_gpio = "/pinctrl/tsadc/otp-gpio"; | |
| otp_out = "/pinctrl/tsadc/otp-out"; | |
| uart0_xfer = "/pinctrl/uart0/uart0-xfer"; | |
| uart0_cts = "/pinctrl/uart0/uart0-cts"; | |
| uart0_rts = "/pinctrl/uart0/uart0-rts"; | |
| uart1_xfer = "/pinctrl/uart1/uart1-xfer"; | |
| uart2a_xfer = "/pinctrl/uart2a/uart2a-xfer"; | |
| uart2b_xfer = "/pinctrl/uart2b/uart2b-xfer"; | |
| uart2c_xfer = "/pinctrl/uart2c/uart2c-xfer"; | |
| uart3_xfer = "/pinctrl/uart3/uart3-xfer"; | |
| uart3_cts = "/pinctrl/uart3/uart3-cts"; | |
| uart3_rts = "/pinctrl/uart3/uart3-rts"; | |
| uart4_xfer = "/pinctrl/uart4/uart4-xfer"; | |
| uarthdcp_xfer = "/pinctrl/uarthdcp/uarthdcp-xfer"; | |
| pwm0_pin = "/pinctrl/pwm0/pwm0-pin"; | |
| pwm0_pin_pull_down = "/pinctrl/pwm0/pwm0-pin-pull-down"; | |
| vop0_pwm_pin = "/pinctrl/pwm0/vop0-pwm-pin"; | |
| vop1_pwm_pin = "/pinctrl/pwm0/vop1-pwm-pin"; | |
| pwm1_pin = "/pinctrl/pwm1/pwm1-pin"; | |
| pwm1_pin_pull_down = "/pinctrl/pwm1/pwm1-pin-pull-down"; | |
| pwm2_pin = "/pinctrl/pwm2/pwm2-pin"; | |
| pwm2_pin_pull_down = "/pinctrl/pwm2/pwm2-pin-pull-down"; | |
| pwm3a_pin = "/pinctrl/pwm3a/pwm3a-pin"; | |
| pwm3a_pin_pull_down = "/pinctrl/pwm3a/pwm3a-pin-pull-down"; | |
| pwm3b_pin = "/pinctrl/pwm3b/pwm3b-pin"; | |
| pwm3b_pin_pull_down = "/pinctrl/pwm3b/pwm3b-pin-pull-down"; | |
| edp_hpd = "/pinctrl/edp/edp-hpd"; | |
| hdmi_i2c_xfer = "/pinctrl/hdmi/hdmi-i2c-xfer"; | |
| hdmi_cec = "/pinctrl/hdmi/hdmi-cec"; | |
| pcie_clkreqn = "/pinctrl/pcie/pci-clkreqn"; | |
| pcie_clkreqnb = "/pinctrl/pcie/pci-clkreqnb"; | |
| pcie_clkreqn_cpm = "/pinctrl/pcie/pci-clkreqn-cpm"; | |
| pcie_clkreqnb_cpm = "/pinctrl/pcie/pci-clkreqnb-cpm"; | |
| pcie_drv = "/pinctrl/pcie/pcie-drv"; | |
| vcc_pcie_h = "/pinctrl/pcie/vcc-pcie-h"; | |
| cif_clkout = "/pinctrl/isp/cif-clkout"; | |
| isp_dvp_d0d7 = "/pinctrl/isp/isp-dvp-d0d7"; | |
| isp_shutter = "/pinctrl/isp/isp-shutter"; | |
| isp_flash_trigger = "/pinctrl/isp/isp-flash-trigger"; | |
| isp_flash_trigger_as_gpio = "/pinctrl/isp/isp-flash-trigger-as-gpio"; | |
| cam0_default_pins = "/pinctrl/cam_pins/cam0-default-pins"; | |
| cam0_sleep_pins = "/pinctrl/cam_pins/cam0-sleep-pins"; | |
| lcd_panel_reset = "/pinctrl/lcd-panel/lcd-panel-reset"; | |
| lcd_en = "/pinctrl/lcd-panel/lcd-en"; | |
| vsel1_gpio = "/pinctrl/pmic/vsel1-gpio"; | |
| vsel2_gpio = "/pinctrl/pmic/vsel2-gpio"; | |
| pmic_int_l = "/pinctrl/pmic/pmic-int-l"; | |
| pmic_dvs2 = "/pinctrl/pmic/pmic-dvs2"; | |
| led_power = "/pinctrl/leds/led-power"; | |
| led_user = "/pinctrl/leds/led-user"; | |
| wifi_enable_h = "/pinctrl/sdio-pwrseq/wifi-enable-h"; | |
| uart0_gpios = "/pinctrl/wireless-bluetooth/uart0-gpios"; | |
| host_vbus_drv = "/pinctrl/usb2/host-vbus-drv"; | |
| hub_rst_en = "/pinctrl/usb2/hub-rst-en"; | |
| fusb1_int = "/pinctrl/fusb30x/fusb1-int"; | |
| fusb0_int = "/pinctrl/fusb30x/fusb0-int"; | |
| typec1_vbus_drv = "/pinctrl/fusb30x/typec1-vbus-drv"; | |
| vcc_sd_h = "/pinctrl/vcc_sd/vcc-sd-h"; | |
| vcc_wifi_h = "/pinctrl/wifi/vcc-wifi-h"; | |
| vcc_chargen_h = "/pinctrl/chargen/vcc-chargen-h"; | |
| bat_int_h = "/pinctrl/chargen/bat-int-h"; | |
| cur_ctl_h = "/pinctrl/chargen/cur-ctl-h"; | |
| vcc_dis_en0 = "/pinctrl/vcc_dis/vcc-dis-en0"; | |
| rockchip_suspend = "/rockchip-suspend"; | |
| RK3399_CPU_COST_0 = "/energy-costs/rk3399-core-cost0"; | |
| RK3399_CPU_COST_1 = "/energy-costs/rk3399-core-cost1"; | |
| RK3399_CLUSTER_COST_0 = "/energy-costs/rk3399-cluster-cost0"; | |
| RK3399_CLUSTER_COST_1 = "/energy-costs/rk3399-cluster-cost1"; | |
| cluster0_opp = "/opp-table0"; | |
| cluster1_opp = "/opp-table1"; | |
| gpu_opp_table = "/opp-table2"; | |
| dmc_opp_table = "/opp-table3"; | |
| drm_logo = "/reserved-memory/drm-logo@00000000"; | |
| fiq_debugger = "/fiq-debugger"; | |
| cif_isp0 = "/cif_isp@ff910000"; | |
| cif_isp1 = "/cif_isp@ff920000"; | |
| backlight = "/backlight"; | |
| iram = "/sram@ff8d0000"; | |
| clkin_gmac = "/external-gmac-clock"; | |
| dw_hdmi_audio = "/dw-hdmi-audio"; | |
| edp_panel = "/edp-panel"; | |
| panel_in_edp = "/edp-panel/ports/endpoint"; | |
| hdmi_sound = "/hdmi-sound"; | |
| hdmi_codec = "/hdmi-codec"; | |
| hdmi_dp_sound = "/hdmi-dp-sound"; | |
| vcc3v3_sys = "/vcc3v3-sys"; | |
| vcc3v3_pcie = "/vcc3v3-pcie-regulator"; | |
| vcc5v0_host = "/vcc5v0-host-regulator"; | |
| vcc_hub_en = "/vcc_hub_en-regulator"; | |
| vcc_dis_en = "/vcc-dis-en"; | |
| vcc_wifi = "/vcc-wifi"; | |
| vcc_pcie = "/vcc-pcie"; | |
| vcc_chargen = "/vcc-chargen"; | |
| vcc_sd = "/vcc-sd"; | |
| vcc5v0_sys = "/vcc5v0-sys"; | |
| vcc_phy = "/vcc-phy-regulator"; | |
| vdd_log = "/vdd-log"; | |
| vcc_lcd = "/vcc-lcd-regulator"; | |
| sdio_pwrseq = "/sdio-pwrseq"; | |
| }; | |
| }; |
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment