Created
April 7, 2019 19:24
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Pocket Beagle 2018-10-07 device tree source(from /sys/firmware/fdt)
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| /dts-v1/; | |
| /memreserve/ 0x0000000088000000 0x000000000007f000; | |
| /memreserve/ 0x000000008fb2b000 0x000000000001f000; | |
| /memreserve/ 0x000000008fbad000 0x0000000000452040; | |
| / { | |
| serial-number = "1750EPB00345"; | |
| compatible = "ti,am335x-pocketbeagle", "ti,am335x-bone", "ti,am33xx"; | |
| interrupt-parent = <0x1>; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x1>; | |
| model = "TI AM335x PocketBeagle"; | |
| chosen { | |
| linux,initrd-end = <0x8ffff040>; | |
| linux,initrd-start = <0x8fbad000>; | |
| bootargs = "console=ttyO0,115200n8 root=/dev/mmcblk0p1 ro rootfstype=ext4 rootwait coherent_pool=1M net.ifnames=0 quiet"; | |
| stdout-path = "/ocp/serial@44e09000"; | |
| }; | |
| aliases { | |
| i2c0 = "/ocp/i2c@44e0b000"; | |
| i2c1 = "/ocp/i2c@4802a000"; | |
| i2c2 = "/ocp/i2c@4819c000"; | |
| serial0 = "/ocp/serial@44e09000"; | |
| serial1 = "/ocp/serial@48022000"; | |
| serial2 = "/ocp/serial@48024000"; | |
| serial3 = "/ocp/serial@481a6000"; | |
| serial4 = "/ocp/serial@481a8000"; | |
| serial5 = "/ocp/serial@481aa000"; | |
| d_can0 = "/ocp/can@481cc000"; | |
| d_can1 = "/ocp/can@481d0000"; | |
| usb0 = "/ocp/usb@47400000/usb@47401000"; | |
| usb1 = "/ocp/usb@47400000/usb@47401800"; | |
| phy0 = "/ocp/usb@47400000/usb-phy@47401300"; | |
| phy1 = "/ocp/usb@47400000/usb-phy@47401b00"; | |
| ethernet0 = "/ocp/ethernet@4a100000/slave@4a100200"; | |
| ethernet1 = "/ocp/ethernet@4a100000/slave@4a100300"; | |
| spi1 = "/ocp/spi@48030000"; | |
| spi2 = "/ocp/spi@481a0000"; | |
| phandle = <0x199>; | |
| }; | |
| cpus { | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| cpu@0 { | |
| compatible = "arm,cortex-a8"; | |
| enable-method = "ti,am3352"; | |
| device_type = "cpu"; | |
| reg = <0x0>; | |
| operating-points-v2 = <0x2>; | |
| clocks = <0x3>; | |
| clock-names = "cpu"; | |
| clock-latency = <0x493e0>; | |
| cpu-idle-states = <0x4>; | |
| cpu0-supply = <0x5>; | |
| }; | |
| idle-states { | |
| mpu_gate { | |
| compatible = "arm,idle-state"; | |
| entry-latency-us = <0x28>; | |
| exit-latency-us = <0x5a>; | |
| min-residency-us = <0x12c>; | |
| ti,idle-wkup-m3; | |
| phandle = <0x4>; | |
| }; | |
| }; | |
| }; | |
| opp-table { | |
| compatible = "operating-points-v2-ti-cpu"; | |
| syscon = <0x6>; | |
| phandle = <0x2>; | |
| opp50-300000000 { | |
| opp-hz = <0x0 0x11e1a300>; | |
| opp-microvolt = <0xe7ef0 0xe34b8 0xec928>; | |
| opp-supported-hw = <0x6 0x10>; | |
| opp-suspend; | |
| }; | |
| opp100-275000000 { | |
| opp-hz = <0x0 0x10642ac0>; | |
| opp-microvolt = <0x10c8e0 0x1072f0 0x111ed0>; | |
| opp-supported-hw = <0x1 0xff>; | |
| opp-suspend; | |
| }; | |
| opp100-300000000 { | |
| opp-hz = <0x0 0x11e1a300>; | |
| opp-microvolt = <0x10c8e0 0x1072f0 0x111ed0>; | |
| opp-supported-hw = <0x6 0x20>; | |
| opp-suspend; | |
| }; | |
| opp100-500000000 { | |
| opp-hz = <0x0 0x1dcd6500>; | |
| opp-microvolt = <0x10c8e0 0x1072f0 0x111ed0>; | |
| opp-supported-hw = <0x1 0xffff>; | |
| }; | |
| opp100-600000000 { | |
| opp-hz = <0x0 0x23c34600>; | |
| opp-microvolt = <0x10c8e0 0x1072f0 0x111ed0>; | |
| opp-supported-hw = <0x6 0x40>; | |
| }; | |
| opp120-600000000 { | |
| opp-hz = <0x0 0x23c34600>; | |
| opp-microvolt = <0x124f80 0x11f1c0 0x12ad40>; | |
| opp-supported-hw = <0x1 0xffff>; | |
| }; | |
| opp120-720000000 { | |
| opp-hz = <0x0 0x2aea5400>; | |
| opp-microvolt = <0x124f80 0x11f1c0 0x12ad40>; | |
| opp-supported-hw = <0x6 0x80>; | |
| }; | |
| oppturbo-720000000 { | |
| opp-hz = <0x0 0x2aea5400>; | |
| opp-microvolt = <0x1339e0 0x12d770 0x139c50>; | |
| opp-supported-hw = <0x1 0xffff>; | |
| }; | |
| oppturbo-800000000 { | |
| opp-hz = <0x0 0x2faf0800>; | |
| opp-microvolt = <0x1339e0 0x12d770 0x139c50>; | |
| opp-supported-hw = <0x6 0x100>; | |
| }; | |
| oppnitro-1000000000 { | |
| opp-hz = <0x0 0x3b9aca00>; | |
| opp-microvolt = <0x1437c8 0x13d044 0x149f4c>; | |
| opp-supported-hw = <0x6 0x100>; | |
| }; | |
| }; | |
| pmu { | |
| compatible = "arm,cortex-a8-pmu"; | |
| interrupts = <0x3>; | |
| }; | |
| soc { | |
| compatible = "ti,omap-infra"; | |
| mpu { | |
| compatible = "ti,omap3-mpu"; | |
| ti,hwmods = "mpu"; | |
| pm-sram = <0x7 0x8>; | |
| }; | |
| }; | |
| ocp { | |
| compatible = "simple-bus"; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x1>; | |
| ranges; | |
| ti,hwmods = "l3_main"; | |
| phandle = <0x19a>; | |
| l4_wkup@44c00000 { | |
| compatible = "ti,am3-l4-wkup", "simple-bus"; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x1>; | |
| ranges = <0x0 0x44c00000 0x280000>; | |
| phandle = <0x19b>; | |
| wkup_m3@100000 { | |
| compatible = "ti,am3352-wkup-m3"; | |
| reg = <0x100000 0x4000 0x180000 0x2000>; | |
| reg-names = "umem", "dmem"; | |
| ti,hwmods = "wkup_m3"; | |
| ti,pm-firmware = "am335x-pm-firmware.elf"; | |
| phandle = <0x2a>; | |
| }; | |
| prcm@200000 { | |
| compatible = "ti,am3-prcm"; | |
| reg = <0x200000 0x4000>; | |
| phandle = <0x19c>; | |
| clocks { | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| phandle = <0x19d>; | |
| clk_32768_ck { | |
| #clock-cells = <0x0>; | |
| compatible = "fixed-clock"; | |
| clock-frequency = <0x8000>; | |
| phandle = <0x19>; | |
| }; | |
| clk_rc32k_ck { | |
| #clock-cells = <0x0>; | |
| compatible = "fixed-clock"; | |
| clock-frequency = <0x7d00>; | |
| phandle = <0x18>; | |
| }; | |
| virt_19200000_ck { | |
| #clock-cells = <0x0>; | |
| compatible = "fixed-clock"; | |
| clock-frequency = <0x124f800>; | |
| phandle = <0x25>; | |
| }; | |
| virt_24000000_ck { | |
| #clock-cells = <0x0>; | |
| compatible = "fixed-clock"; | |
| clock-frequency = <0x16e3600>; | |
| phandle = <0x26>; | |
| }; | |
| virt_25000000_ck { | |
| #clock-cells = <0x0>; | |
| compatible = "fixed-clock"; | |
| clock-frequency = <0x17d7840>; | |
| phandle = <0x27>; | |
| }; | |
| virt_26000000_ck { | |
| #clock-cells = <0x0>; | |
| compatible = "fixed-clock"; | |
| clock-frequency = <0x18cba80>; | |
| phandle = <0x28>; | |
| }; | |
| tclkin_ck { | |
| #clock-cells = <0x0>; | |
| compatible = "fixed-clock"; | |
| clock-frequency = <0xb71b00>; | |
| phandle = <0x17>; | |
| }; | |
| dpll_core_ck@490 { | |
| #clock-cells = <0x0>; | |
| compatible = "ti,am3-dpll-core-clock"; | |
| clocks = <0x9 0x9>; | |
| reg = <0x490 0x45c 0x468>; | |
| phandle = <0xa>; | |
| }; | |
| dpll_core_x2_ck { | |
| #clock-cells = <0x0>; | |
| compatible = "ti,am3-dpll-x2-clock"; | |
| clocks = <0xa>; | |
| phandle = <0xb>; | |
| }; | |
| dpll_core_m4_ck@480 { | |
| #clock-cells = <0x0>; | |
| compatible = "ti,divider-clock"; | |
| clocks = <0xb>; | |
| ti,max-div = <0x1f>; | |
| reg = <0x480>; | |
| ti,index-starts-at-one; | |
| phandle = <0x13>; | |
| }; | |
| dpll_core_m5_ck@484 { | |
| #clock-cells = <0x0>; | |
| compatible = "ti,divider-clock"; | |
| clocks = <0xb>; | |
| ti,max-div = <0x1f>; | |
| reg = <0x484>; | |
| ti,index-starts-at-one; | |
| phandle = <0x1b>; | |
| }; | |
| dpll_core_m6_ck@4d8 { | |
| #clock-cells = <0x0>; | |
| compatible = "ti,divider-clock"; | |
| clocks = <0xb>; | |
| ti,max-div = <0x1f>; | |
| reg = <0x4d8>; | |
| ti,index-starts-at-one; | |
| phandle = <0x19e>; | |
| }; | |
| dpll_mpu_ck@488 { | |
| #clock-cells = <0x0>; | |
| compatible = "ti,am3-dpll-clock"; | |
| clocks = <0x9 0x9>; | |
| reg = <0x488 0x420 0x42c>; | |
| phandle = <0x3>; | |
| }; | |
| dpll_mpu_m2_ck@4a8 { | |
| #clock-cells = <0x0>; | |
| compatible = "ti,divider-clock"; | |
| clocks = <0x3>; | |
| ti,max-div = <0x1f>; | |
| reg = <0x4a8>; | |
| ti,index-starts-at-one; | |
| phandle = <0x19f>; | |
| }; | |
| dpll_ddr_ck@494 { | |
| #clock-cells = <0x0>; | |
| compatible = "ti,am3-dpll-no-gate-clock"; | |
| clocks = <0x9 0x9>; | |
| reg = <0x494 0x434 0x440>; | |
| phandle = <0xc>; | |
| }; | |
| dpll_ddr_m2_ck@4a0 { | |
| #clock-cells = <0x0>; | |
| compatible = "ti,divider-clock"; | |
| clocks = <0xc>; | |
| ti,max-div = <0x1f>; | |
| reg = <0x4a0>; | |
| ti,index-starts-at-one; | |
| phandle = <0xd>; | |
| }; | |
| dpll_ddr_m2_div2_ck { | |
| #clock-cells = <0x0>; | |
| compatible = "fixed-factor-clock"; | |
| clocks = <0xd>; | |
| clock-mult = <0x1>; | |
| clock-div = <0x2>; | |
| phandle = <0x1a0>; | |
| }; | |
| dpll_disp_ck@498 { | |
| #clock-cells = <0x0>; | |
| compatible = "ti,am3-dpll-no-gate-clock"; | |
| clocks = <0x9 0x9>; | |
| reg = <0x498 0x448 0x454>; | |
| phandle = <0xe>; | |
| }; | |
| dpll_disp_m2_ck@4a4 { | |
| #clock-cells = <0x0>; | |
| compatible = "ti,divider-clock"; | |
| clocks = <0xe>; | |
| ti,max-div = <0x1f>; | |
| reg = <0x4a4>; | |
| ti,index-starts-at-one; | |
| ti,set-rate-parent; | |
| phandle = <0x15>; | |
| }; | |
| dpll_per_ck@48c { | |
| #clock-cells = <0x0>; | |
| compatible = "ti,am3-dpll-no-gate-j-type-clock"; | |
| clocks = <0x9 0x9>; | |
| reg = <0x48c 0x470 0x49c>; | |
| phandle = <0xf>; | |
| }; | |
| dpll_per_m2_ck@4ac { | |
| #clock-cells = <0x0>; | |
| compatible = "ti,divider-clock"; | |
| clocks = <0xf>; | |
| ti,max-div = <0x1f>; | |
| reg = <0x4ac>; | |
| ti,index-starts-at-one; | |
| phandle = <0x10>; | |
| }; | |
| dpll_per_m2_div4_wkupdm_ck { | |
| #clock-cells = <0x0>; | |
| compatible = "fixed-factor-clock"; | |
| clocks = <0x10>; | |
| clock-mult = <0x1>; | |
| clock-div = <0x4>; | |
| phandle = <0x1a1>; | |
| }; | |
| dpll_per_m2_div4_ck { | |
| #clock-cells = <0x0>; | |
| compatible = "fixed-factor-clock"; | |
| clocks = <0x10>; | |
| clock-mult = <0x1>; | |
| clock-div = <0x4>; | |
| phandle = <0x1a2>; | |
| }; | |
| cefuse_fck@a20 { | |
| #clock-cells = <0x0>; | |
| compatible = "ti,gate-clock"; | |
| clocks = <0x9>; | |
| ti,bit-shift = <0x1>; | |
| reg = <0xa20>; | |
| phandle = <0x1a3>; | |
| }; | |
| clk_24mhz { | |
| #clock-cells = <0x0>; | |
| compatible = "fixed-factor-clock"; | |
| clocks = <0x10>; | |
| clock-mult = <0x1>; | |
| clock-div = <0x8>; | |
| phandle = <0x11>; | |
| }; | |
| clkdiv32k_ck { | |
| #clock-cells = <0x0>; | |
| compatible = "fixed-factor-clock"; | |
| clocks = <0x11>; | |
| clock-mult = <0x1>; | |
| clock-div = <0x2dc>; | |
| phandle = <0x12>; | |
| }; | |
| clkdiv32k_ick@14c { | |
| #clock-cells = <0x0>; | |
| compatible = "ti,gate-clock"; | |
| clocks = <0x12>; | |
| ti,bit-shift = <0x1>; | |
| reg = <0x14c>; | |
| phandle = <0x16>; | |
| }; | |
| l3_gclk { | |
| #clock-cells = <0x0>; | |
| compatible = "fixed-factor-clock"; | |
| clocks = <0x13>; | |
| clock-mult = <0x1>; | |
| clock-div = <0x1>; | |
| phandle = <0x14>; | |
| }; | |
| pruss_ocp_gclk@530 { | |
| #clock-cells = <0x0>; | |
| compatible = "ti,mux-clock"; | |
| clocks = <0x14 0x15>; | |
| reg = <0x530>; | |
| phandle = <0x1a4>; | |
| }; | |
| mmu_fck@914 { | |
| #clock-cells = <0x0>; | |
| compatible = "ti,gate-clock"; | |
| clocks = <0x13>; | |
| ti,bit-shift = <0x1>; | |
| reg = <0x914>; | |
| phandle = <0x1a5>; | |
| }; | |
| timer1_fck@528 { | |
| #clock-cells = <0x0>; | |
| compatible = "ti,mux-clock"; | |
| clocks = <0x9 0x16 0x17 0x18 0x19>; | |
| reg = <0x528>; | |
| phandle = <0x1a6>; | |
| }; | |
| timer2_fck@508 { | |
| #clock-cells = <0x0>; | |
| compatible = "ti,mux-clock"; | |
| clocks = <0x17 0x9 0x16>; | |
| reg = <0x508>; | |
| phandle = <0x1a7>; | |
| }; | |
| timer3_fck@50c { | |
| #clock-cells = <0x0>; | |
| compatible = "ti,mux-clock"; | |
| clocks = <0x17 0x9 0x16>; | |
| reg = <0x50c>; | |
| phandle = <0x1a8>; | |
| }; | |
| timer4_fck@510 { | |
| #clock-cells = <0x0>; | |
| compatible = "ti,mux-clock"; | |
| clocks = <0x17 0x9 0x16>; | |
| reg = <0x510>; | |
| phandle = <0x1a9>; | |
| }; | |
| timer5_fck@518 { | |
| #clock-cells = <0x0>; | |
| compatible = "ti,mux-clock"; | |
| clocks = <0x17 0x9 0x16>; | |
| reg = <0x518>; | |
| phandle = <0x1aa>; | |
| }; | |
| timer6_fck@51c { | |
| #clock-cells = <0x0>; | |
| compatible = "ti,mux-clock"; | |
| clocks = <0x17 0x9 0x16>; | |
| reg = <0x51c>; | |
| phandle = <0x1ab>; | |
| }; | |
| timer7_fck@504 { | |
| #clock-cells = <0x0>; | |
| compatible = "ti,mux-clock"; | |
| clocks = <0x17 0x9 0x16>; | |
| reg = <0x504>; | |
| phandle = <0x1ac>; | |
| }; | |
| usbotg_fck@47c { | |
| #clock-cells = <0x0>; | |
| compatible = "ti,gate-clock"; | |
| clocks = <0xf>; | |
| ti,bit-shift = <0x8>; | |
| reg = <0x47c>; | |
| phandle = <0x1ad>; | |
| }; | |
| dpll_core_m4_div2_ck { | |
| #clock-cells = <0x0>; | |
| compatible = "fixed-factor-clock"; | |
| clocks = <0x13>; | |
| clock-mult = <0x1>; | |
| clock-div = <0x2>; | |
| phandle = <0x1a>; | |
| }; | |
| ieee5000_fck@e4 { | |
| #clock-cells = <0x0>; | |
| compatible = "ti,gate-clock"; | |
| clocks = <0x1a>; | |
| ti,bit-shift = <0x1>; | |
| reg = <0xe4>; | |
| phandle = <0x1ae>; | |
| }; | |
| wdt1_fck@538 { | |
| #clock-cells = <0x0>; | |
| compatible = "ti,mux-clock"; | |
| clocks = <0x18 0x16>; | |
| reg = <0x538>; | |
| phandle = <0x1af>; | |
| }; | |
| l4_rtc_gclk { | |
| #clock-cells = <0x0>; | |
| compatible = "fixed-factor-clock"; | |
| clocks = <0x13>; | |
| clock-mult = <0x1>; | |
| clock-div = <0x2>; | |
| phandle = <0x1b0>; | |
| }; | |
| l4hs_gclk { | |
| #clock-cells = <0x0>; | |
| compatible = "fixed-factor-clock"; | |
| clocks = <0x13>; | |
| clock-mult = <0x1>; | |
| clock-div = <0x1>; | |
| phandle = <0x1b1>; | |
| }; | |
| l3s_gclk { | |
| #clock-cells = <0x0>; | |
| compatible = "fixed-factor-clock"; | |
| clocks = <0x1a>; | |
| clock-mult = <0x1>; | |
| clock-div = <0x1>; | |
| phandle = <0x1b2>; | |
| }; | |
| l4fw_gclk { | |
| #clock-cells = <0x0>; | |
| compatible = "fixed-factor-clock"; | |
| clocks = <0x1a>; | |
| clock-mult = <0x1>; | |
| clock-div = <0x1>; | |
| phandle = <0x1b3>; | |
| }; | |
| l4ls_gclk { | |
| #clock-cells = <0x0>; | |
| compatible = "fixed-factor-clock"; | |
| clocks = <0x1a>; | |
| clock-mult = <0x1>; | |
| clock-div = <0x1>; | |
| phandle = <0x29>; | |
| }; | |
| sysclk_div_ck { | |
| #clock-cells = <0x0>; | |
| compatible = "fixed-factor-clock"; | |
| clocks = <0x13>; | |
| clock-mult = <0x1>; | |
| clock-div = <0x1>; | |
| phandle = <0x1b4>; | |
| }; | |
| cpsw_125mhz_gclk { | |
| #clock-cells = <0x0>; | |
| compatible = "fixed-factor-clock"; | |
| clocks = <0x1b>; | |
| clock-mult = <0x1>; | |
| clock-div = <0x2>; | |
| phandle = <0x3f>; | |
| }; | |
| cpsw_cpts_rft_clk@520 { | |
| #clock-cells = <0x0>; | |
| compatible = "ti,mux-clock"; | |
| clocks = <0x1b 0x13>; | |
| reg = <0x520>; | |
| phandle = <0x40>; | |
| }; | |
| gpio0_dbclk_mux_ck@53c { | |
| #clock-cells = <0x0>; | |
| compatible = "ti,mux-clock"; | |
| clocks = <0x18 0x19 0x16>; | |
| reg = <0x53c>; | |
| phandle = <0x1c>; | |
| }; | |
| gpio0_dbclk@408 { | |
| #clock-cells = <0x0>; | |
| compatible = "ti,gate-clock"; | |
| clocks = <0x1c>; | |
| ti,bit-shift = <0x12>; | |
| reg = <0x408>; | |
| phandle = <0x1b5>; | |
| }; | |
| gpio1_dbclk@ac { | |
| #clock-cells = <0x0>; | |
| compatible = "ti,gate-clock"; | |
| clocks = <0x16>; | |
| ti,bit-shift = <0x12>; | |
| reg = <0xac>; | |
| phandle = <0x1b6>; | |
| }; | |
| gpio2_dbclk@b0 { | |
| #clock-cells = <0x0>; | |
| compatible = "ti,gate-clock"; | |
| clocks = <0x16>; | |
| ti,bit-shift = <0x12>; | |
| reg = <0xb0>; | |
| phandle = <0x1b7>; | |
| }; | |
| gpio3_dbclk@b4 { | |
| #clock-cells = <0x0>; | |
| compatible = "ti,gate-clock"; | |
| clocks = <0x16>; | |
| ti,bit-shift = <0x12>; | |
| reg = <0xb4>; | |
| phandle = <0x1b8>; | |
| }; | |
| lcd_gclk@534 { | |
| #clock-cells = <0x0>; | |
| compatible = "ti,mux-clock"; | |
| clocks = <0x15 0x1b 0x10>; | |
| reg = <0x534>; | |
| ti,set-rate-parent; | |
| phandle = <0x1e>; | |
| }; | |
| mmc_clk { | |
| #clock-cells = <0x0>; | |
| compatible = "fixed-factor-clock"; | |
| clocks = <0x10>; | |
| clock-mult = <0x1>; | |
| clock-div = <0x2>; | |
| phandle = <0x1b9>; | |
| }; | |
| gfx_fclk_clksel_ck@52c { | |
| #clock-cells = <0x0>; | |
| compatible = "ti,mux-clock"; | |
| clocks = <0x13 0x10>; | |
| ti,bit-shift = <0x1>; | |
| reg = <0x52c>; | |
| phandle = <0x1d>; | |
| }; | |
| gfx_fck_div_ck@52c { | |
| #clock-cells = <0x0>; | |
| compatible = "ti,divider-clock"; | |
| clocks = <0x1d>; | |
| reg = <0x52c>; | |
| ti,max-div = <0x2>; | |
| phandle = <0x42>; | |
| }; | |
| sysclkout_pre_ck@700 { | |
| #clock-cells = <0x0>; | |
| compatible = "ti,mux-clock"; | |
| clocks = <0x19 0x14 0xd 0x10 0x1e>; | |
| reg = <0x700>; | |
| phandle = <0x1f>; | |
| }; | |
| clkout2_div_ck@700 { | |
| #clock-cells = <0x0>; | |
| compatible = "ti,divider-clock"; | |
| clocks = <0x1f>; | |
| ti,bit-shift = <0x3>; | |
| ti,max-div = <0x8>; | |
| reg = <0x700>; | |
| phandle = <0x24>; | |
| }; | |
| dbg_sysclk_ck@414 { | |
| #clock-cells = <0x0>; | |
| compatible = "ti,gate-clock"; | |
| clocks = <0x9>; | |
| ti,bit-shift = <0x13>; | |
| reg = <0x414>; | |
| phandle = <0x20>; | |
| }; | |
| dbg_clka_ck@414 { | |
| #clock-cells = <0x0>; | |
| compatible = "ti,gate-clock"; | |
| clocks = <0x13>; | |
| ti,bit-shift = <0x1e>; | |
| reg = <0x414>; | |
| phandle = <0x21>; | |
| }; | |
| stm_pmd_clock_mux_ck@414 { | |
| #clock-cells = <0x0>; | |
| compatible = "ti,mux-clock"; | |
| clocks = <0x20 0x21>; | |
| ti,bit-shift = <0x16>; | |
| reg = <0x414>; | |
| phandle = <0x22>; | |
| }; | |
| trace_pmd_clk_mux_ck@414 { | |
| #clock-cells = <0x0>; | |
| compatible = "ti,mux-clock"; | |
| clocks = <0x20 0x21>; | |
| ti,bit-shift = <0x14>; | |
| reg = <0x414>; | |
| phandle = <0x23>; | |
| }; | |
| stm_clk_div_ck@414 { | |
| #clock-cells = <0x0>; | |
| compatible = "ti,divider-clock"; | |
| clocks = <0x22>; | |
| ti,bit-shift = <0x1b>; | |
| ti,max-div = <0x40>; | |
| reg = <0x414>; | |
| ti,index-power-of-two; | |
| phandle = <0x1ba>; | |
| }; | |
| trace_clk_div_ck@414 { | |
| #clock-cells = <0x0>; | |
| compatible = "ti,divider-clock"; | |
| clocks = <0x23>; | |
| ti,bit-shift = <0x18>; | |
| ti,max-div = <0x40>; | |
| reg = <0x414>; | |
| ti,index-power-of-two; | |
| phandle = <0x1bb>; | |
| }; | |
| clkout2_ck@700 { | |
| #clock-cells = <0x0>; | |
| compatible = "ti,gate-clock"; | |
| clocks = <0x24>; | |
| ti,bit-shift = <0x7>; | |
| reg = <0x700>; | |
| phandle = <0x1bc>; | |
| }; | |
| }; | |
| clockdomains { | |
| phandle = <0x1bd>; | |
| clk_24mhz_clkdm { | |
| compatible = "ti,clockdomain"; | |
| clocks = <0x16>; | |
| phandle = <0x1be>; | |
| }; | |
| }; | |
| }; | |
| scm@210000 { | |
| compatible = "ti,am3-scm", "simple-bus"; | |
| reg = <0x210000 0x2000>; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x1>; | |
| #pinctrl-cells = <0x1>; | |
| ranges = <0x0 0x210000 0x2000>; | |
| phandle = <0x1bf>; | |
| pinmux@800 { | |
| compatible = "pinctrl-single"; | |
| reg = <0x800 0x238>; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| #pinctrl-cells = <0x1>; | |
| pinctrl-single,register-width = <0x20>; | |
| pinctrl-single,function-mask = <0x7f>; | |
| phandle = <0x1c0>; | |
| user_leds_default { | |
| pinctrl-single,pins = <0x54 0x7 0x58 0x17 0x5c 0x7 0x60 0x17>; | |
| phandle = <0x197>; | |
| }; | |
| user_leds_sleep { | |
| pinctrl-single,pins = <0x54 0x27 0x58 0x27 0x5c 0x27 0x60 0x27>; | |
| phandle = <0x198>; | |
| }; | |
| pinmux_i2c0_pins { | |
| pinctrl-single,pins = <0x188 0x30 0x18c 0x30>; | |
| phandle = <0x31>; | |
| }; | |
| pinmux_mmc0_pins { | |
| pinctrl-single,pins = <0x160 0x2f>; | |
| phandle = <0x34>; | |
| }; | |
| pinmux_P1_02_default_pin { | |
| pinctrl-single,pins = <0xe4 0x2f>; | |
| phandle = <0x43>; | |
| }; | |
| pinmux_P1_02_gpio_pin { | |
| pinctrl-single,pins = <0xe4 0x2f>; | |
| phandle = <0x44>; | |
| }; | |
| pinmux_P1_02_gpio_pu_pin { | |
| pinctrl-single,pins = <0xe4 0x37>; | |
| phandle = <0x45>; | |
| }; | |
| pinmux_P1_02_gpio_pd_pin { | |
| pinctrl-single,pins = <0xe4 0x27>; | |
| phandle = <0x46>; | |
| }; | |
| pinmux_P1_02_gpio_input_pin { | |
| pinctrl-single,pins = <0xe4 0x2f>; | |
| phandle = <0x47>; | |
| }; | |
| pinmux_P1_02_pruout_pin { | |
| pinctrl-single,pins = <0xe4 0x25>; | |
| phandle = <0x48>; | |
| }; | |
| pinmux_P1_02_pruin_pin { | |
| pinctrl-single,pins = <0xe4 0x2e>; | |
| phandle = <0x49>; | |
| }; | |
| pinmux_P1_04_default_pin { | |
| pinctrl-single,pins = <0xec 0x27>; | |
| phandle = <0x4a>; | |
| }; | |
| pinmux_P1_04_gpio_pin { | |
| pinctrl-single,pins = <0xec 0x2f>; | |
| phandle = <0x4b>; | |
| }; | |
| pinmux_P1_04_gpio_pu_pin { | |
| pinctrl-single,pins = <0xec 0x37>; | |
| phandle = <0x4c>; | |
| }; | |
| pinmux_P1_04_gpio_pd_pin { | |
| pinctrl-single,pins = <0xec 0x27>; | |
| phandle = <0x4d>; | |
| }; | |
| pinmux_P1_04_gpio_input_pin { | |
| pinctrl-single,pins = <0xec 0x2f>; | |
| phandle = <0x4e>; | |
| }; | |
| pinmux_P1_04_pruout_pin { | |
| pinctrl-single,pins = <0xec 0x25>; | |
| phandle = <0x4f>; | |
| }; | |
| pinmux_P1_04_pruin_pin { | |
| pinctrl-single,pins = <0xec 0x2e>; | |
| phandle = <0x50>; | |
| }; | |
| pinmux_P1_06_default_pin { | |
| pinctrl-single,pins = <0x15c 0x30>; | |
| phandle = <0x51>; | |
| }; | |
| pinmux_P1_06_gpio_pin { | |
| pinctrl-single,pins = <0x15c 0x2f>; | |
| phandle = <0x52>; | |
| }; | |
| pinmux_P1_06_gpio_pu_pin { | |
| pinctrl-single,pins = <0x15c 0x37>; | |
| phandle = <0x53>; | |
| }; | |
| pinmux_P1_06_gpio_pd_pin { | |
| pinctrl-single,pins = <0x15c 0x27>; | |
| phandle = <0x54>; | |
| }; | |
| pinmux_P1_06_gpio_input_pin { | |
| pinctrl-single,pins = <0x15c 0x2f>; | |
| phandle = <0x55>; | |
| }; | |
| pinmux_P1_06_spi_cs_pin { | |
| pinctrl-single,pins = <0x15c 0x30>; | |
| phandle = <0x56>; | |
| }; | |
| pinmux_P1_06_i2c_pin { | |
| pinctrl-single,pins = <0x15c 0x32>; | |
| phandle = <0x57>; | |
| }; | |
| pinmux_P1_06_pwm_pin { | |
| pinctrl-single,pins = <0x15c 0x23>; | |
| phandle = <0x58>; | |
| }; | |
| pinmux_P1_06_pru_uart_pin { | |
| pinctrl-single,pins = <0x15c 0x34>; | |
| phandle = <0x59>; | |
| }; | |
| pinmux_P1_08_default_pin { | |
| pinctrl-single,pins = <0x150 0x30>; | |
| phandle = <0x5a>; | |
| }; | |
| pinmux_P1_08_gpio_pin { | |
| pinctrl-single,pins = <0x150 0x2f>; | |
| phandle = <0x5b>; | |
| }; | |
| pinmux_P1_08_gpio_pu_pin { | |
| pinctrl-single,pins = <0x150 0x37>; | |
| phandle = <0x5c>; | |
| }; | |
| pinmux_P1_08_gpio_pd_pin { | |
| pinctrl-single,pins = <0x150 0x27>; | |
| phandle = <0x5d>; | |
| }; | |
| pinmux_P1_08_gpio_input_pin { | |
| pinctrl-single,pins = <0x150 0x2f>; | |
| phandle = <0x5e>; | |
| }; | |
| pinmux_P1_08_spi_sclk_pin { | |
| pinctrl-single,pins = <0x150 0x30>; | |
| phandle = <0x5f>; | |
| }; | |
| pinmux_P1_08_uart_pin { | |
| pinctrl-single,pins = <0x150 0x31>; | |
| phandle = <0x60>; | |
| }; | |
| pinmux_P1_08_i2c_pin { | |
| pinctrl-single,pins = <0x150 0x32>; | |
| phandle = <0x61>; | |
| }; | |
| pinmux_P1_08_pwm_pin { | |
| pinctrl-single,pins = <0x150 0x23>; | |
| phandle = <0x62>; | |
| }; | |
| pinmux_P1_08_pru_uart_pin { | |
| pinctrl-single,pins = <0x150 0x34>; | |
| phandle = <0x63>; | |
| }; | |
| pinmux_P1_10_default_pin { | |
| pinctrl-single,pins = <0x154 0x30>; | |
| phandle = <0x64>; | |
| }; | |
| pinmux_P1_10_gpio_pin { | |
| pinctrl-single,pins = <0x154 0x2f>; | |
| phandle = <0x65>; | |
| }; | |
| pinmux_P1_10_gpio_pu_pin { | |
| pinctrl-single,pins = <0x154 0x37>; | |
| phandle = <0x66>; | |
| }; | |
| pinmux_P1_10_gpio_pd_pin { | |
| pinctrl-single,pins = <0x154 0x27>; | |
| phandle = <0x67>; | |
| }; | |
| pinmux_P1_10_gpio_input_pin { | |
| pinctrl-single,pins = <0x154 0x2f>; | |
| phandle = <0x68>; | |
| }; | |
| pinmux_P1_10_spi_pin { | |
| pinctrl-single,pins = <0x154 0x30>; | |
| phandle = <0x69>; | |
| }; | |
| pinmux_P1_10_uart_pin { | |
| pinctrl-single,pins = <0x154 0x31>; | |
| phandle = <0x6a>; | |
| }; | |
| pinmux_P1_10_i2c_pin { | |
| pinctrl-single,pins = <0x154 0x32>; | |
| phandle = <0x6b>; | |
| }; | |
| pinmux_P1_10_pwm_pin { | |
| pinctrl-single,pins = <0x154 0x23>; | |
| phandle = <0x6c>; | |
| }; | |
| pinmux_P1_10_pru_uart_pin { | |
| pinctrl-single,pins = <0x154 0x34>; | |
| phandle = <0x6d>; | |
| }; | |
| pinmux_P1_12_default_pin { | |
| pinctrl-single,pins = <0x158 0x30>; | |
| phandle = <0x6e>; | |
| }; | |
| pinmux_P1_12_gpio_pin { | |
| pinctrl-single,pins = <0x158 0x2f>; | |
| phandle = <0x6f>; | |
| }; | |
| pinmux_P1_12_gpio_pu_pin { | |
| pinctrl-single,pins = <0x158 0x37>; | |
| phandle = <0x70>; | |
| }; | |
| pinmux_P1_12_gpio_pd_pin { | |
| pinctrl-single,pins = <0x158 0x27>; | |
| phandle = <0x71>; | |
| }; | |
| pinmux_P1_12_gpio_input_pin { | |
| pinctrl-single,pins = <0x158 0x2f>; | |
| phandle = <0x72>; | |
| }; | |
| pinmux_P1_12_spi_pin { | |
| pinctrl-single,pins = <0x158 0x30>; | |
| phandle = <0x73>; | |
| }; | |
| pinmux_P1_12_i2c_pin { | |
| pinctrl-single,pins = <0x158 0x32>; | |
| phandle = <0x74>; | |
| }; | |
| pinmux_P1_12_pwm_pin { | |
| pinctrl-single,pins = <0x158 0x23>; | |
| phandle = <0x75>; | |
| }; | |
| pinmux_P1_12_pru_uart_pin { | |
| pinctrl-single,pins = <0x158 0x34>; | |
| phandle = <0x76>; | |
| }; | |
| pinmux_P1_20_default_pin { | |
| pinctrl-single,pins = <0x1b4 0x27>; | |
| phandle = <0x77>; | |
| }; | |
| pinmux_P1_20_gpio_pin { | |
| pinctrl-single,pins = <0x1b4 0x2f>; | |
| phandle = <0x78>; | |
| }; | |
| pinmux_P1_20_gpio_pu_pin { | |
| pinctrl-single,pins = <0x1b4 0x37>; | |
| phandle = <0x79>; | |
| }; | |
| pinmux_P1_20_gpio_pd_pin { | |
| pinctrl-single,pins = <0x1b4 0x27>; | |
| phandle = <0x7a>; | |
| }; | |
| pinmux_P1_20_gpio_input_pin { | |
| pinctrl-single,pins = <0x1b4 0x2f>; | |
| phandle = <0x7b>; | |
| }; | |
| pinmux_P1_20_pruin_pin { | |
| pinctrl-single,pins = <0x1b4 0x2d>; | |
| phandle = <0x7c>; | |
| }; | |
| pinmux_P1_26_default_pin { | |
| pinctrl-single,pins = <0x178 0x33>; | |
| phandle = <0x7d>; | |
| }; | |
| pinmux_P1_26_gpio_pin { | |
| pinctrl-single,pins = <0x178 0x2f>; | |
| phandle = <0x7e>; | |
| }; | |
| pinmux_P1_26_gpio_pu_pin { | |
| pinctrl-single,pins = <0x178 0x37>; | |
| phandle = <0x7f>; | |
| }; | |
| pinmux_P1_26_gpio_pd_pin { | |
| pinctrl-single,pins = <0x178 0x27>; | |
| phandle = <0x80>; | |
| }; | |
| pinmux_P1_26_gpio_input_pin { | |
| pinctrl-single,pins = <0x178 0x2f>; | |
| phandle = <0x81>; | |
| }; | |
| pinmux_P1_26_can_pin { | |
| pinctrl-single,pins = <0x178 0x12>; | |
| phandle = <0x83>; | |
| }; | |
| pinmux_P1_26_i2c_pin { | |
| pinctrl-single,pins = <0x178 0x33>; | |
| phandle = <0x84>; | |
| }; | |
| pinmux_P1_26_spi_cs_pin { | |
| pinctrl-single,pins = <0x178 0x34>; | |
| phandle = <0x82>; | |
| }; | |
| pinmux_P1_26_pru_uart_pin { | |
| pinctrl-single,pins = <0x178 0x35>; | |
| phandle = <0x85>; | |
| }; | |
| pinmux_P1_28_default_pin { | |
| pinctrl-single,pins = <0x17c 0x33>; | |
| phandle = <0x86>; | |
| }; | |
| pinmux_P1_28_gpio_pin { | |
| pinctrl-single,pins = <0x17c 0x2f>; | |
| phandle = <0x87>; | |
| }; | |
| pinmux_P1_28_gpio_pu_pin { | |
| pinctrl-single,pins = <0x17c 0x37>; | |
| phandle = <0x88>; | |
| }; | |
| pinmux_P1_28_gpio_pd_pin { | |
| pinctrl-single,pins = <0x17c 0x27>; | |
| phandle = <0x89>; | |
| }; | |
| pinmux_P1_28_gpio_input_pin { | |
| pinctrl-single,pins = <0x17c 0x2f>; | |
| phandle = <0x8a>; | |
| }; | |
| pinmux_P1_28_can_pin { | |
| pinctrl-single,pins = <0x17c 0x32>; | |
| phandle = <0x8c>; | |
| }; | |
| pinmux_P1_28_i2c_pin { | |
| pinctrl-single,pins = <0x17c 0x33>; | |
| phandle = <0x8d>; | |
| }; | |
| pinmux_P1_28_spi_cs_pin { | |
| pinctrl-single,pins = <0x17c 0x34>; | |
| phandle = <0x8b>; | |
| }; | |
| pinmux_P1_28_pru_uart_pin { | |
| pinctrl-single,pins = <0x17c 0x35>; | |
| phandle = <0x8e>; | |
| }; | |
| pinmux_P1_29_default_pin { | |
| pinctrl-single,pins = <0x1ac 0x2e>; | |
| phandle = <0x8f>; | |
| }; | |
| pinmux_P1_29_gpio_pin { | |
| pinctrl-single,pins = <0x1ac 0x2f>; | |
| phandle = <0x90>; | |
| }; | |
| pinmux_P1_29_gpio_pu_pin { | |
| pinctrl-single,pins = <0x1ac 0x37>; | |
| phandle = <0x91>; | |
| }; | |
| pinmux_P1_29_gpio_pd_pin { | |
| pinctrl-single,pins = <0x1ac 0x27>; | |
| phandle = <0x92>; | |
| }; | |
| pinmux_P1_29_gpio_input_pin { | |
| pinctrl-single,pins = <0x1ac 0x2f>; | |
| phandle = <0x93>; | |
| }; | |
| pinmux_P1_29_qep_pin { | |
| pinctrl-single,pins = <0x1ac 0x31>; | |
| phandle = <0x94>; | |
| }; | |
| pinmux_P1_29_pruout_pin { | |
| pinctrl-single,pins = <0x1ac 0x25>; | |
| phandle = <0x95>; | |
| }; | |
| pinmux_P1_29_pruin_pin { | |
| pinctrl-single,pins = <0x1ac 0x2e>; | |
| phandle = <0x96>; | |
| }; | |
| pinmux_P1_30_default_pin { | |
| pinctrl-single,pins = <0x174 0x30>; | |
| phandle = <0x97>; | |
| }; | |
| pinmux_P1_30_gpio_pin { | |
| pinctrl-single,pins = <0x174 0x2f>; | |
| phandle = <0x98>; | |
| }; | |
| pinmux_P1_30_gpio_pu_pin { | |
| pinctrl-single,pins = <0x174 0x37>; | |
| phandle = <0x99>; | |
| }; | |
| pinmux_P1_30_gpio_pd_pin { | |
| pinctrl-single,pins = <0x174 0x27>; | |
| phandle = <0x9a>; | |
| }; | |
| pinmux_P1_30_gpio_input_pin { | |
| pinctrl-single,pins = <0x174 0x2f>; | |
| phandle = <0x9b>; | |
| }; | |
| pinmux_P1_30_uart_pin { | |
| pinctrl-single,pins = <0x174 0x30>; | |
| phandle = <0x9d>; | |
| }; | |
| pinmux_P1_30_spi_cs_pin { | |
| pinctrl-single,pins = <0x174 0x31>; | |
| phandle = <0x9c>; | |
| }; | |
| pinmux_P1_30_can_pin { | |
| pinctrl-single,pins = <0x174 0x32>; | |
| phandle = <0x9e>; | |
| }; | |
| pinmux_P1_30_i2c_pin { | |
| pinctrl-single,pins = <0x174 0x33>; | |
| phandle = <0x9f>; | |
| }; | |
| pinmux_P1_30_pruout_pin { | |
| pinctrl-single,pins = <0x174 0x25>; | |
| phandle = <0xa0>; | |
| }; | |
| pinmux_P1_30_pruin_pin { | |
| pinctrl-single,pins = <0x174 0x2e>; | |
| phandle = <0xa1>; | |
| }; | |
| pinmux_P1_31_default_pin { | |
| pinctrl-single,pins = <0x1a0 0x2e>; | |
| phandle = <0xa2>; | |
| }; | |
| pinmux_P1_31_gpio_pin { | |
| pinctrl-single,pins = <0x1a0 0x2f>; | |
| phandle = <0xa3>; | |
| }; | |
| pinmux_P1_31_gpio_pu_pin { | |
| pinctrl-single,pins = <0x1a0 0x37>; | |
| phandle = <0xa4>; | |
| }; | |
| pinmux_P1_31_gpio_pd_pin { | |
| pinctrl-single,pins = <0x1a0 0x27>; | |
| phandle = <0xa5>; | |
| }; | |
| pinmux_P1_31_gpio_input_pin { | |
| pinctrl-single,pins = <0x1a0 0x2f>; | |
| phandle = <0xa6>; | |
| }; | |
| pinmux_P1_31_qep_pin { | |
| pinctrl-single,pins = <0x1a0 0x31>; | |
| phandle = <0xa7>; | |
| }; | |
| pinmux_P1_31_pruout_pin { | |
| pinctrl-single,pins = <0x1a0 0x25>; | |
| phandle = <0xa8>; | |
| }; | |
| pinmux_P1_31_pruin_pin { | |
| pinctrl-single,pins = <0x1a0 0x2e>; | |
| phandle = <0xa9>; | |
| }; | |
| pinmux_P1_32_default_pin { | |
| pinctrl-single,pins = <0x170 0x30>; | |
| phandle = <0xaa>; | |
| }; | |
| pinmux_P1_32_gpio_pin { | |
| pinctrl-single,pins = <0x170 0x2f>; | |
| phandle = <0xab>; | |
| }; | |
| pinmux_P1_32_gpio_pu_pin { | |
| pinctrl-single,pins = <0x170 0x37>; | |
| phandle = <0xac>; | |
| }; | |
| pinmux_P1_32_gpio_pd_pin { | |
| pinctrl-single,pins = <0x170 0x27>; | |
| phandle = <0xad>; | |
| }; | |
| pinmux_P1_32_gpio_input_pin { | |
| pinctrl-single,pins = <0x170 0x2f>; | |
| phandle = <0xae>; | |
| }; | |
| pinmux_P1_32_uart_pin { | |
| pinctrl-single,pins = <0x170 0x30>; | |
| phandle = <0xb0>; | |
| }; | |
| pinmux_P1_32_spi_cs_pin { | |
| pinctrl-single,pins = <0x170 0x31>; | |
| phandle = <0xaf>; | |
| }; | |
| pinmux_P1_32_can_pin { | |
| pinctrl-single,pins = <0x170 0x12>; | |
| phandle = <0xb1>; | |
| }; | |
| pinmux_P1_32_i2c_pin { | |
| pinctrl-single,pins = <0x170 0x33>; | |
| phandle = <0xb2>; | |
| }; | |
| pinmux_P1_32_pruout_pin { | |
| pinctrl-single,pins = <0x170 0x25>; | |
| phandle = <0xb3>; | |
| }; | |
| pinmux_P1_32_pruin_pin { | |
| pinctrl-single,pins = <0x170 0x2e>; | |
| phandle = <0xb4>; | |
| }; | |
| pinmux_P1_33_default_pin { | |
| pinctrl-single,pins = <0x194 0x2e>; | |
| phandle = <0xb5>; | |
| }; | |
| pinmux_P1_33_gpio_pin { | |
| pinctrl-single,pins = <0x194 0x2f>; | |
| phandle = <0xb6>; | |
| }; | |
| pinmux_P1_33_gpio_pu_pin { | |
| pinctrl-single,pins = <0x194 0x37>; | |
| phandle = <0xb7>; | |
| }; | |
| pinmux_P1_33_gpio_pd_pin { | |
| pinctrl-single,pins = <0x194 0x27>; | |
| phandle = <0xb8>; | |
| }; | |
| pinmux_P1_33_gpio_input_pin { | |
| pinctrl-single,pins = <0x194 0x2f>; | |
| phandle = <0xb9>; | |
| }; | |
| pinmux_P1_33_pwm_pin { | |
| pinctrl-single,pins = <0x194 0x21>; | |
| phandle = <0xbb>; | |
| }; | |
| pinmux_P1_33_spi_pin { | |
| pinctrl-single,pins = <0x194 0x33>; | |
| phandle = <0xba>; | |
| }; | |
| pinmux_P1_33_pruout_pin { | |
| pinctrl-single,pins = <0x194 0x25>; | |
| phandle = <0xbc>; | |
| }; | |
| pinmux_P1_33_pruin_pin { | |
| pinctrl-single,pins = <0x194 0x2e>; | |
| phandle = <0xbd>; | |
| }; | |
| pinmux_P1_34_default_pin { | |
| pinctrl-single,pins = <0x28 0x27>; | |
| phandle = <0xbe>; | |
| }; | |
| pinmux_P1_34_gpio_pin { | |
| pinctrl-single,pins = <0x28 0x2f>; | |
| phandle = <0xbf>; | |
| }; | |
| pinmux_P1_34_gpio_pu_pin { | |
| pinctrl-single,pins = <0x28 0x37>; | |
| phandle = <0xc0>; | |
| }; | |
| pinmux_P1_34_gpio_pd_pin { | |
| pinctrl-single,pins = <0x28 0x27>; | |
| phandle = <0xc1>; | |
| }; | |
| pinmux_P1_34_gpio_input_pin { | |
| pinctrl-single,pins = <0x28 0x2f>; | |
| phandle = <0xc2>; | |
| }; | |
| pinmux_P1_34_pwm_pin { | |
| pinctrl-single,pins = <0x28 0x24>; | |
| phandle = <0xc3>; | |
| }; | |
| pinmux_P1_35_default_pin { | |
| pinctrl-single,pins = <0xe8 0x2e>; | |
| phandle = <0xc4>; | |
| }; | |
| pinmux_P1_35_gpio_pin { | |
| pinctrl-single,pins = <0xe8 0x2f>; | |
| phandle = <0xc5>; | |
| }; | |
| pinmux_P1_35_gpio_pu_pin { | |
| pinctrl-single,pins = <0xe8 0x37>; | |
| phandle = <0xc6>; | |
| }; | |
| pinmux_P1_35_gpio_pd_pin { | |
| pinctrl-single,pins = <0xe8 0x27>; | |
| phandle = <0xc7>; | |
| }; | |
| pinmux_P1_35_gpio_input_pin { | |
| pinctrl-single,pins = <0xe8 0x2f>; | |
| phandle = <0xc8>; | |
| }; | |
| pinmux_P1_35_pruout_pin { | |
| pinctrl-single,pins = <0xe8 0x25>; | |
| phandle = <0xc9>; | |
| }; | |
| pinmux_P1_35_pruin_pin { | |
| pinctrl-single,pins = <0xe8 0x2e>; | |
| phandle = <0xca>; | |
| }; | |
| pinmux_P1_36_default_pin { | |
| pinctrl-single,pins = <0x190 0x21>; | |
| phandle = <0xcb>; | |
| }; | |
| pinmux_P1_36_gpio_pin { | |
| pinctrl-single,pins = <0x190 0x2f>; | |
| phandle = <0xcc>; | |
| }; | |
| pinmux_P1_36_gpio_pu_pin { | |
| pinctrl-single,pins = <0x190 0x37>; | |
| phandle = <0xcd>; | |
| }; | |
| pinmux_P1_36_gpio_pd_pin { | |
| pinctrl-single,pins = <0x190 0x27>; | |
| phandle = <0xce>; | |
| }; | |
| pinmux_P1_36_gpio_input_pin { | |
| pinctrl-single,pins = <0x190 0x2f>; | |
| phandle = <0xcf>; | |
| }; | |
| pinmux_P1_36_pwm_pin { | |
| pinctrl-single,pins = <0x190 0x21>; | |
| phandle = <0xd1>; | |
| }; | |
| pinmux_P1_36_spi_sclk_pin { | |
| pinctrl-single,pins = <0x190 0x33>; | |
| phandle = <0xd0>; | |
| }; | |
| pinmux_P1_36_pruout_pin { | |
| pinctrl-single,pins = <0x190 0x25>; | |
| phandle = <0xd2>; | |
| }; | |
| pinmux_P1_36_pruin_pin { | |
| pinctrl-single,pins = <0x190 0x2e>; | |
| phandle = <0xd3>; | |
| }; | |
| pinmux_P2_01_default_pin { | |
| pinctrl-single,pins = <0x48 0x26>; | |
| phandle = <0xd4>; | |
| }; | |
| pinmux_P2_01_gpio_pin { | |
| pinctrl-single,pins = <0x48 0x2f>; | |
| phandle = <0xd5>; | |
| }; | |
| pinmux_P2_01_gpio_pu_pin { | |
| pinctrl-single,pins = <0x48 0x37>; | |
| phandle = <0xd6>; | |
| }; | |
| pinmux_P2_01_gpio_pd_pin { | |
| pinctrl-single,pins = <0x48 0x27>; | |
| phandle = <0xd7>; | |
| }; | |
| pinmux_P2_01_gpio_input_pin { | |
| pinctrl-single,pins = <0x48 0x2f>; | |
| phandle = <0xd8>; | |
| }; | |
| pinmux_P2_01_pwm_pin { | |
| pinctrl-single,pins = <0x48 0x26>; | |
| phandle = <0xd9>; | |
| }; | |
| pinmux_P2_02_default_pin { | |
| pinctrl-single,pins = <0x6c 0x27>; | |
| phandle = <0xda>; | |
| }; | |
| pinmux_P2_02_gpio_pin { | |
| pinctrl-single,pins = <0x6c 0x2f>; | |
| phandle = <0xdb>; | |
| }; | |
| pinmux_P2_02_gpio_pu_pin { | |
| pinctrl-single,pins = <0x6c 0x37>; | |
| phandle = <0xdc>; | |
| }; | |
| pinmux_P2_02_gpio_pd_pin { | |
| pinctrl-single,pins = <0x6c 0x27>; | |
| phandle = <0xdd>; | |
| }; | |
| pinmux_P2_02_gpio_input_pin { | |
| pinctrl-single,pins = <0x6c 0x2f>; | |
| phandle = <0xde>; | |
| }; | |
| pinmux_P2_03_default_pin { | |
| pinctrl-single,pins = <0x24 0x27>; | |
| phandle = <0xdf>; | |
| }; | |
| pinmux_P2_03_gpio_pin { | |
| pinctrl-single,pins = <0x24 0x2f>; | |
| phandle = <0xe0>; | |
| }; | |
| pinmux_P2_03_gpio_pu_pin { | |
| pinctrl-single,pins = <0x24 0x37>; | |
| phandle = <0xe1>; | |
| }; | |
| pinmux_P2_03_gpio_pd_pin { | |
| pinctrl-single,pins = <0x24 0x27>; | |
| phandle = <0xe2>; | |
| }; | |
| pinmux_P2_03_gpio_input_pin { | |
| pinctrl-single,pins = <0x24 0x2f>; | |
| phandle = <0xe3>; | |
| }; | |
| pinmux_P2_03_pwm_pin { | |
| pinctrl-single,pins = <0x24 0x24>; | |
| phandle = <0xe4>; | |
| }; | |
| pinmux_P2_04_default_pin { | |
| pinctrl-single,pins = <0x68 0x27>; | |
| phandle = <0xe5>; | |
| }; | |
| pinmux_P2_04_gpio_pin { | |
| pinctrl-single,pins = <0x68 0x2f>; | |
| phandle = <0xe6>; | |
| }; | |
| pinmux_P2_04_gpio_pu_pin { | |
| pinctrl-single,pins = <0x68 0x37>; | |
| phandle = <0xe7>; | |
| }; | |
| pinmux_P2_04_gpio_pd_pin { | |
| pinctrl-single,pins = <0x68 0x27>; | |
| phandle = <0xe8>; | |
| }; | |
| pinmux_P2_04_gpio_input_pin { | |
| pinctrl-single,pins = <0x68 0x2f>; | |
| phandle = <0xe9>; | |
| }; | |
| pinmux_P2_05_default_pin { | |
| pinctrl-single,pins = <0x70 0x36>; | |
| phandle = <0xea>; | |
| }; | |
| pinmux_P2_05_gpio_pin { | |
| pinctrl-single,pins = <0x70 0x2f>; | |
| phandle = <0xeb>; | |
| }; | |
| pinmux_P2_05_gpio_pu_pin { | |
| pinctrl-single,pins = <0x70 0x37>; | |
| phandle = <0xec>; | |
| }; | |
| pinmux_P2_05_gpio_pd_pin { | |
| pinctrl-single,pins = <0x70 0x27>; | |
| phandle = <0xed>; | |
| }; | |
| pinmux_P2_05_gpio_input_pin { | |
| pinctrl-single,pins = <0x70 0x2f>; | |
| phandle = <0xee>; | |
| }; | |
| pinmux_P2_05_uart_pin { | |
| pinctrl-single,pins = <0x70 0x36>; | |
| phandle = <0xef>; | |
| }; | |
| pinmux_P2_06_default_pin { | |
| pinctrl-single,pins = <0x64 0x27>; | |
| phandle = <0xf0>; | |
| }; | |
| pinmux_P2_06_gpio_pin { | |
| pinctrl-single,pins = <0x64 0x2f>; | |
| phandle = <0xf1>; | |
| }; | |
| pinmux_P2_06_gpio_pu_pin { | |
| pinctrl-single,pins = <0x64 0x37>; | |
| phandle = <0xf2>; | |
| }; | |
| pinmux_P2_06_gpio_pd_pin { | |
| pinctrl-single,pins = <0x64 0x27>; | |
| phandle = <0xf3>; | |
| }; | |
| pinmux_P2_06_gpio_input_pin { | |
| pinctrl-single,pins = <0x64 0x2f>; | |
| phandle = <0xf4>; | |
| }; | |
| pinmux_P2_07_default_pin { | |
| pinctrl-single,pins = <0x74 0x36>; | |
| phandle = <0xf5>; | |
| }; | |
| pinmux_P2_07_gpio_pin { | |
| pinctrl-single,pins = <0x74 0x2f>; | |
| phandle = <0xf6>; | |
| }; | |
| pinmux_P2_07_gpio_pu_pin { | |
| pinctrl-single,pins = <0x74 0x37>; | |
| phandle = <0xf7>; | |
| }; | |
| pinmux_P2_07_gpio_pd_pin { | |
| pinctrl-single,pins = <0x74 0x27>; | |
| phandle = <0xf8>; | |
| }; | |
| pinmux_P2_07_gpio_input_pin { | |
| pinctrl-single,pins = <0x74 0x2f>; | |
| phandle = <0xf9>; | |
| }; | |
| pinmux_P2_07_uart_pin { | |
| pinctrl-single,pins = <0x74 0x36>; | |
| phandle = <0xfa>; | |
| }; | |
| pinmux_P2_08_default_pin { | |
| pinctrl-single,pins = <0x78 0x27>; | |
| phandle = <0xfb>; | |
| }; | |
| pinmux_P2_08_gpio_pin { | |
| pinctrl-single,pins = <0x78 0x2f>; | |
| phandle = <0xfc>; | |
| }; | |
| pinmux_P2_08_gpio_pu_pin { | |
| pinctrl-single,pins = <0x78 0x37>; | |
| phandle = <0xfd>; | |
| }; | |
| pinmux_P2_08_gpio_pd_pin { | |
| pinctrl-single,pins = <0x78 0x27>; | |
| phandle = <0xfe>; | |
| }; | |
| pinmux_P2_08_gpio_input_pin { | |
| pinctrl-single,pins = <0x78 0x2f>; | |
| phandle = <0xff>; | |
| }; | |
| pinmux_P2_09_default_pin { | |
| pinctrl-single,pins = <0x184 0x33>; | |
| phandle = <0x100>; | |
| }; | |
| pinmux_P2_09_gpio_pin { | |
| pinctrl-single,pins = <0x184 0x2f>; | |
| phandle = <0x101>; | |
| }; | |
| pinmux_P2_09_gpio_pu_pin { | |
| pinctrl-single,pins = <0x184 0x37>; | |
| phandle = <0x102>; | |
| }; | |
| pinmux_P2_09_gpio_pd_pin { | |
| pinctrl-single,pins = <0x184 0x27>; | |
| phandle = <0x103>; | |
| }; | |
| pinmux_P2_09_gpio_input_pin { | |
| pinctrl-single,pins = <0x184 0x2f>; | |
| phandle = <0x104>; | |
| }; | |
| pinmux_P2_09_uart_pin { | |
| pinctrl-single,pins = <0x184 0x30>; | |
| phandle = <0x105>; | |
| }; | |
| pinmux_P2_09_can_pin { | |
| pinctrl-single,pins = <0x184 0x32>; | |
| phandle = <0x106>; | |
| }; | |
| pinmux_P2_09_i2c_pin { | |
| pinctrl-single,pins = <0x184 0x33>; | |
| phandle = <0x107>; | |
| }; | |
| pinmux_P2_09_pru_uart_pin { | |
| pinctrl-single,pins = <0x184 0x35>; | |
| phandle = <0x108>; | |
| }; | |
| pinmux_P2_09_pruin_pin { | |
| pinctrl-single,pins = <0x184 0x2e>; | |
| phandle = <0x109>; | |
| }; | |
| pinmux_P2_10_default_pin { | |
| pinctrl-single,pins = <0x50 0x27>; | |
| phandle = <0x10a>; | |
| }; | |
| pinmux_P2_10_gpio_pin { | |
| pinctrl-single,pins = <0x50 0x2f>; | |
| phandle = <0x10b>; | |
| }; | |
| pinmux_P2_10_gpio_pu_pin { | |
| pinctrl-single,pins = <0x50 0x37>; | |
| phandle = <0x10c>; | |
| }; | |
| pinmux_P2_10_gpio_pd_pin { | |
| pinctrl-single,pins = <0x50 0x27>; | |
| phandle = <0x10d>; | |
| }; | |
| pinmux_P2_10_gpio_input_pin { | |
| pinctrl-single,pins = <0x50 0x2f>; | |
| phandle = <0x10e>; | |
| }; | |
| pinmux_P2_10_qep_pin { | |
| pinctrl-single,pins = <0x50 0x36>; | |
| phandle = <0x10f>; | |
| }; | |
| pinmux_P2_11_default_pin { | |
| pinctrl-single,pins = <0x180 0x33>; | |
| phandle = <0x110>; | |
| }; | |
| pinmux_P2_11_gpio_pin { | |
| pinctrl-single,pins = <0x180 0x2f>; | |
| phandle = <0x111>; | |
| }; | |
| pinmux_P2_11_gpio_pu_pin { | |
| pinctrl-single,pins = <0x180 0x37>; | |
| phandle = <0x112>; | |
| }; | |
| pinmux_P2_11_gpio_pd_pin { | |
| pinctrl-single,pins = <0x180 0x27>; | |
| phandle = <0x113>; | |
| }; | |
| pinmux_P2_11_gpio_input_pin { | |
| pinctrl-single,pins = <0x180 0x2f>; | |
| phandle = <0x114>; | |
| }; | |
| pinmux_P2_11_uart_pin { | |
| pinctrl-single,pins = <0x180 0x30>; | |
| phandle = <0x115>; | |
| }; | |
| pinmux_P2_11_can_pin { | |
| pinctrl-single,pins = <0x180 0x12>; | |
| phandle = <0x116>; | |
| }; | |
| pinmux_P2_11_i2c_pin { | |
| pinctrl-single,pins = <0x180 0x33>; | |
| phandle = <0x117>; | |
| }; | |
| pinmux_P2_11_pru_uart_pin { | |
| pinctrl-single,pins = <0x180 0x35>; | |
| phandle = <0x118>; | |
| }; | |
| pinmux_P2_11_pruin_pin { | |
| pinctrl-single,pins = <0x180 0x2e>; | |
| phandle = <0x119>; | |
| }; | |
| pinmux_P2_17_default_pin { | |
| pinctrl-single,pins = <0x8c 0x27>; | |
| phandle = <0x11a>; | |
| }; | |
| pinmux_P2_17_gpio_pin { | |
| pinctrl-single,pins = <0x8c 0x2f>; | |
| phandle = <0x11b>; | |
| }; | |
| pinmux_P2_17_gpio_pu_pin { | |
| pinctrl-single,pins = <0x8c 0x37>; | |
| phandle = <0x11c>; | |
| }; | |
| pinmux_P2_17_gpio_pd_pin { | |
| pinctrl-single,pins = <0x8c 0x27>; | |
| phandle = <0x11d>; | |
| }; | |
| pinmux_P2_17_gpio_input_pin { | |
| pinctrl-single,pins = <0x8c 0x2f>; | |
| phandle = <0x11e>; | |
| }; | |
| pinmux_P2_18_default_pin { | |
| pinctrl-single,pins = <0x3c 0x27>; | |
| phandle = <0x11f>; | |
| }; | |
| pinmux_P2_18_gpio_pin { | |
| pinctrl-single,pins = <0x3c 0x2f>; | |
| phandle = <0x120>; | |
| }; | |
| pinmux_P2_18_gpio_pu_pin { | |
| pinctrl-single,pins = <0x3c 0x37>; | |
| phandle = <0x121>; | |
| }; | |
| pinmux_P2_18_gpio_pd_pin { | |
| pinctrl-single,pins = <0x3c 0x27>; | |
| phandle = <0x122>; | |
| }; | |
| pinmux_P2_18_gpio_input_pin { | |
| pinctrl-single,pins = <0x3c 0x2f>; | |
| phandle = <0x123>; | |
| }; | |
| pinmux_P2_18_qep_pin { | |
| pinctrl-single,pins = <0x3c 0x34>; | |
| phandle = <0x124>; | |
| }; | |
| pinmux_P2_18_pru_ecap_pin { | |
| pinctrl-single,pins = <0x3c 0x25>; | |
| phandle = <0x125>; | |
| }; | |
| pinmux_P2_18_pruin_pin { | |
| pinctrl-single,pins = <0x3c 0x2e>; | |
| phandle = <0x126>; | |
| }; | |
| pinmux_P2_19_default_pin { | |
| pinctrl-single,pins = <0x2c 0x27>; | |
| phandle = <0x127>; | |
| }; | |
| pinmux_P2_19_gpio_pin { | |
| pinctrl-single,pins = <0x2c 0x2f>; | |
| phandle = <0x128>; | |
| }; | |
| pinmux_P2_19_gpio_pu_pin { | |
| pinctrl-single,pins = <0x2c 0x37>; | |
| phandle = <0x129>; | |
| }; | |
| pinmux_P2_19_gpio_pd_pin { | |
| pinctrl-single,pins = <0x2c 0x27>; | |
| phandle = <0x12a>; | |
| }; | |
| pinmux_P2_19_gpio_input_pin { | |
| pinctrl-single,pins = <0x2c 0x2f>; | |
| phandle = <0x12b>; | |
| }; | |
| pinmux_P2_19_pwm_pin { | |
| pinctrl-single,pins = <0x2c 0x24>; | |
| phandle = <0x12c>; | |
| }; | |
| pinmux_P2_20_default_pin { | |
| pinctrl-single,pins = <0x88 0x27>; | |
| phandle = <0x12d>; | |
| }; | |
| pinmux_P2_20_gpio_pin { | |
| pinctrl-single,pins = <0x88 0x2f>; | |
| phandle = <0x12e>; | |
| }; | |
| pinmux_P2_20_gpio_pu_pin { | |
| pinctrl-single,pins = <0x88 0x37>; | |
| phandle = <0x12f>; | |
| }; | |
| pinmux_P2_20_gpio_pd_pin { | |
| pinctrl-single,pins = <0x88 0x27>; | |
| phandle = <0x130>; | |
| }; | |
| pinmux_P2_20_gpio_input_pin { | |
| pinctrl-single,pins = <0x88 0x2f>; | |
| phandle = <0x131>; | |
| }; | |
| pinmux_P2_22_default_pin { | |
| pinctrl-single,pins = <0x38 0x27>; | |
| phandle = <0x132>; | |
| }; | |
| pinmux_P2_22_gpio_pin { | |
| pinctrl-single,pins = <0x38 0x2f>; | |
| phandle = <0x133>; | |
| }; | |
| pinmux_P2_22_gpio_pu_pin { | |
| pinctrl-single,pins = <0x38 0x37>; | |
| phandle = <0x134>; | |
| }; | |
| pinmux_P2_22_gpio_pd_pin { | |
| pinctrl-single,pins = <0x38 0x27>; | |
| phandle = <0x135>; | |
| }; | |
| pinmux_P2_22_gpio_input_pin { | |
| pinctrl-single,pins = <0x38 0x2f>; | |
| phandle = <0x136>; | |
| }; | |
| pinmux_P2_22_qep_pin { | |
| pinctrl-single,pins = <0x38 0x34>; | |
| phandle = <0x137>; | |
| }; | |
| pinmux_P2_22_pruin_pin { | |
| pinctrl-single,pins = <0x38 0x2e>; | |
| phandle = <0x138>; | |
| }; | |
| pinmux_P2_24_default_pin { | |
| pinctrl-single,pins = <0x30 0x27>; | |
| phandle = <0x139>; | |
| }; | |
| pinmux_P2_24_gpio_pin { | |
| pinctrl-single,pins = <0x30 0x2f>; | |
| phandle = <0x13a>; | |
| }; | |
| pinmux_P2_24_gpio_pu_pin { | |
| pinctrl-single,pins = <0x30 0x37>; | |
| phandle = <0x13b>; | |
| }; | |
| pinmux_P2_24_gpio_pd_pin { | |
| pinctrl-single,pins = <0x30 0x27>; | |
| phandle = <0x13c>; | |
| }; | |
| pinmux_P2_24_gpio_input_pin { | |
| pinctrl-single,pins = <0x30 0x2f>; | |
| phandle = <0x13d>; | |
| }; | |
| pinmux_P2_24_qep_pin { | |
| pinctrl-single,pins = <0x30 0x34>; | |
| phandle = <0x13e>; | |
| }; | |
| pinmux_P2_24_pruout_pin { | |
| pinctrl-single,pins = <0x30 0x26>; | |
| phandle = <0x13f>; | |
| }; | |
| pinmux_P2_25_default_pin { | |
| pinctrl-single,pins = <0x16c 0x34>; | |
| phandle = <0x140>; | |
| }; | |
| pinmux_P2_25_gpio_pin { | |
| pinctrl-single,pins = <0x16c 0x2f>; | |
| phandle = <0x141>; | |
| }; | |
| pinmux_P2_25_gpio_pu_pin { | |
| pinctrl-single,pins = <0x16c 0x37>; | |
| phandle = <0x142>; | |
| }; | |
| pinmux_P2_25_gpio_pd_pin { | |
| pinctrl-single,pins = <0x16c 0x27>; | |
| phandle = <0x143>; | |
| }; | |
| pinmux_P2_25_gpio_input_pin { | |
| pinctrl-single,pins = <0x16c 0x2f>; | |
| phandle = <0x144>; | |
| }; | |
| pinmux_P2_25_uart_pin { | |
| pinctrl-single,pins = <0x16c 0x31>; | |
| phandle = <0x147>; | |
| }; | |
| pinmux_P2_25_can_pin { | |
| pinctrl-single,pins = <0x16c 0x32>; | |
| phandle = <0x148>; | |
| }; | |
| pinmux_P2_25_i2c_pin { | |
| pinctrl-single,pins = <0x16c 0x33>; | |
| phandle = <0x149>; | |
| }; | |
| pinmux_P2_25_spi_pin { | |
| pinctrl-single,pins = <0x16c 0x34>; | |
| phandle = <0x145>; | |
| }; | |
| pinmux_P2_25_spi_cs_pin { | |
| pinctrl-single,pins = <0x16c 0x35>; | |
| phandle = <0x146>; | |
| }; | |
| pinmux_P2_27_default_pin { | |
| pinctrl-single,pins = <0x168 0x34>; | |
| phandle = <0x14a>; | |
| }; | |
| pinmux_P2_27_gpio_pin { | |
| pinctrl-single,pins = <0x168 0x2f>; | |
| phandle = <0x14b>; | |
| }; | |
| pinmux_P2_27_gpio_pu_pin { | |
| pinctrl-single,pins = <0x168 0x37>; | |
| phandle = <0x14c>; | |
| }; | |
| pinmux_P2_27_gpio_pd_pin { | |
| pinctrl-single,pins = <0x168 0x27>; | |
| phandle = <0x14d>; | |
| }; | |
| pinmux_P2_27_gpio_input_pin { | |
| pinctrl-single,pins = <0x168 0x2f>; | |
| phandle = <0x14e>; | |
| }; | |
| pinmux_P2_27_uart_pin { | |
| pinctrl-single,pins = <0x168 0x31>; | |
| phandle = <0x150>; | |
| }; | |
| pinmux_P2_27_can_pin { | |
| pinctrl-single,pins = <0x168 0x12>; | |
| phandle = <0x151>; | |
| }; | |
| pinmux_P2_27_i2c_pin { | |
| pinctrl-single,pins = <0x168 0x33>; | |
| phandle = <0x152>; | |
| }; | |
| pinmux_P2_27_spi_pin { | |
| pinctrl-single,pins = <0x168 0x34>; | |
| phandle = <0x14f>; | |
| }; | |
| pinmux_P2_28_default_pin { | |
| pinctrl-single,pins = <0x1a8 0x2e>; | |
| phandle = <0x153>; | |
| }; | |
| pinmux_P2_28_gpio_pin { | |
| pinctrl-single,pins = <0x1a8 0x2f>; | |
| phandle = <0x154>; | |
| }; | |
| pinmux_P2_28_gpio_pu_pin { | |
| pinctrl-single,pins = <0x1a8 0x37>; | |
| phandle = <0x155>; | |
| }; | |
| pinmux_P2_28_gpio_pd_pin { | |
| pinctrl-single,pins = <0x1a8 0x27>; | |
| phandle = <0x156>; | |
| }; | |
| pinmux_P2_28_gpio_input_pin { | |
| pinctrl-single,pins = <0x1a8 0x2f>; | |
| phandle = <0x157>; | |
| }; | |
| pinmux_P2_28_qep_pin { | |
| pinctrl-single,pins = <0x1a8 0x31>; | |
| phandle = <0x158>; | |
| }; | |
| pinmux_P2_28_pruout_pin { | |
| pinctrl-single,pins = <0x1a8 0x25>; | |
| phandle = <0x159>; | |
| }; | |
| pinmux_P2_28_pruin_pin { | |
| pinctrl-single,pins = <0x1a8 0x2e>; | |
| phandle = <0x15a>; | |
| }; | |
| pinmux_P2_29_default_pin { | |
| pinctrl-single,pins = <0x164 0x34>; | |
| phandle = <0x15b>; | |
| }; | |
| pinmux_P2_29_gpio_pin { | |
| pinctrl-single,pins = <0x164 0x2f>; | |
| phandle = <0x15c>; | |
| }; | |
| pinmux_P2_29_gpio_pu_pin { | |
| pinctrl-single,pins = <0x164 0x37>; | |
| phandle = <0x15d>; | |
| }; | |
| pinmux_P2_29_gpio_pd_pin { | |
| pinctrl-single,pins = <0x164 0x27>; | |
| phandle = <0x15e>; | |
| }; | |
| pinmux_P2_29_gpio_input_pin { | |
| pinctrl-single,pins = <0x164 0x2f>; | |
| phandle = <0x15f>; | |
| }; | |
| pinmux_P2_29_pwm_pin { | |
| pinctrl-single,pins = <0x164 0x20>; | |
| phandle = <0x163>; | |
| }; | |
| pinmux_P2_29_uart_pin { | |
| pinctrl-single,pins = <0x164 0x31>; | |
| phandle = <0x162>; | |
| }; | |
| pinmux_P2_29_spi_cs_pin { | |
| pinctrl-single,pins = <0x164 0x32>; | |
| phandle = <0x160>; | |
| }; | |
| pinmux_P2_29_pru_ecap_pin { | |
| pinctrl-single,pins = <0x164 0x23>; | |
| phandle = <0x164>; | |
| }; | |
| pinmux_P2_29_spi_sclk_pin { | |
| pinctrl-single,pins = <0x164 0x34>; | |
| phandle = <0x161>; | |
| }; | |
| pinmux_P2_30_default_pin { | |
| pinctrl-single,pins = <0x19c 0x2e>; | |
| phandle = <0x165>; | |
| }; | |
| pinmux_P2_30_gpio_pin { | |
| pinctrl-single,pins = <0x19c 0x2f>; | |
| phandle = <0x166>; | |
| }; | |
| pinmux_P2_30_gpio_pu_pin { | |
| pinctrl-single,pins = <0x19c 0x37>; | |
| phandle = <0x167>; | |
| }; | |
| pinmux_P2_30_gpio_pd_pin { | |
| pinctrl-single,pins = <0x19c 0x27>; | |
| phandle = <0x168>; | |
| }; | |
| pinmux_P2_30_gpio_input_pin { | |
| pinctrl-single,pins = <0x19c 0x2f>; | |
| phandle = <0x169>; | |
| }; | |
| pinmux_P2_30_pwm_pin { | |
| pinctrl-single,pins = <0x19c 0x21>; | |
| phandle = <0x16b>; | |
| }; | |
| pinmux_P2_30_spi_cs_pin { | |
| pinctrl-single,pins = <0x19c 0x33>; | |
| phandle = <0x16a>; | |
| }; | |
| pinmux_P2_30_pruout_pin { | |
| pinctrl-single,pins = <0x19c 0x25>; | |
| phandle = <0x16c>; | |
| }; | |
| pinmux_P2_30_pruin_pin { | |
| pinctrl-single,pins = <0x19c 0x2e>; | |
| phandle = <0x16d>; | |
| }; | |
| pinmux_P2_31_default_pin { | |
| pinctrl-single,pins = <0x1b0 0x34>; | |
| phandle = <0x16e>; | |
| }; | |
| pinmux_P2_31_gpio_pin { | |
| pinctrl-single,pins = <0x1b0 0x2f>; | |
| phandle = <0x16f>; | |
| }; | |
| pinmux_P2_31_gpio_pu_pin { | |
| pinctrl-single,pins = <0x1b0 0x37>; | |
| phandle = <0x170>; | |
| }; | |
| pinmux_P2_31_gpio_pd_pin { | |
| pinctrl-single,pins = <0x1b0 0x27>; | |
| phandle = <0x171>; | |
| }; | |
| pinmux_P2_31_gpio_input_pin { | |
| pinctrl-single,pins = <0x1b0 0x2f>; | |
| phandle = <0x172>; | |
| }; | |
| pinmux_P2_31_spi_cs_pin { | |
| pinctrl-single,pins = <0x1b0 0x34>; | |
| phandle = <0x173>; | |
| }; | |
| pinmux_P2_31_pruin_pin { | |
| pinctrl-single,pins = <0x1b0 0x2d>; | |
| phandle = <0x174>; | |
| }; | |
| pinmux_P2_32_default_pin { | |
| pinctrl-single,pins = <0x198 0x2e>; | |
| phandle = <0x175>; | |
| }; | |
| pinmux_P2_32_gpio_pin { | |
| pinctrl-single,pins = <0x198 0x2f>; | |
| phandle = <0x176>; | |
| }; | |
| pinmux_P2_32_gpio_pu_pin { | |
| pinctrl-single,pins = <0x198 0x37>; | |
| phandle = <0x177>; | |
| }; | |
| pinmux_P2_32_gpio_pd_pin { | |
| pinctrl-single,pins = <0x198 0x27>; | |
| phandle = <0x178>; | |
| }; | |
| pinmux_P2_32_gpio_input_pin { | |
| pinctrl-single,pins = <0x198 0x2f>; | |
| phandle = <0x179>; | |
| }; | |
| pinmux_P2_32_pwm_pin { | |
| pinctrl-single,pins = <0x198 0x21>; | |
| phandle = <0x17b>; | |
| }; | |
| pinmux_P2_32_spi_pin { | |
| pinctrl-single,pins = <0x198 0x33>; | |
| phandle = <0x17a>; | |
| }; | |
| pinmux_P2_32_pruout_pin { | |
| pinctrl-single,pins = <0x198 0x25>; | |
| phandle = <0x17c>; | |
| }; | |
| pinmux_P2_32_pruin_pin { | |
| pinctrl-single,pins = <0x198 0x2e>; | |
| phandle = <0x17d>; | |
| }; | |
| pinmux_P2_33_default_pin { | |
| pinctrl-single,pins = <0x34 0x27>; | |
| phandle = <0x17e>; | |
| }; | |
| pinmux_P2_33_gpio_pin { | |
| pinctrl-single,pins = <0x34 0x2f>; | |
| phandle = <0x17f>; | |
| }; | |
| pinmux_P2_33_gpio_pu_pin { | |
| pinctrl-single,pins = <0x34 0x37>; | |
| phandle = <0x180>; | |
| }; | |
| pinmux_P2_33_gpio_pd_pin { | |
| pinctrl-single,pins = <0x34 0x27>; | |
| phandle = <0x181>; | |
| }; | |
| pinmux_P2_33_gpio_input_pin { | |
| pinctrl-single,pins = <0x34 0x2f>; | |
| phandle = <0x182>; | |
| }; | |
| pinmux_P2_33_qep_pin { | |
| pinctrl-single,pins = <0x34 0x34>; | |
| phandle = <0x183>; | |
| }; | |
| pinmux_P2_33_pruout_pin { | |
| pinctrl-single,pins = <0x34 0x26>; | |
| phandle = <0x184>; | |
| }; | |
| pinmux_P2_34_default_pin { | |
| pinctrl-single,pins = <0x1a4 0x2e>; | |
| phandle = <0x185>; | |
| }; | |
| pinmux_P2_34_gpio_pin { | |
| pinctrl-single,pins = <0x1a4 0x2f>; | |
| phandle = <0x186>; | |
| }; | |
| pinmux_P2_34_gpio_pu_pin { | |
| pinctrl-single,pins = <0x1a4 0x37>; | |
| phandle = <0x187>; | |
| }; | |
| pinmux_P2_34_gpio_pd_pin { | |
| pinctrl-single,pins = <0x1a4 0x27>; | |
| phandle = <0x188>; | |
| }; | |
| pinmux_P2_34_gpio_input_pin { | |
| pinctrl-single,pins = <0x1a4 0x2f>; | |
| phandle = <0x189>; | |
| }; | |
| pinmux_P2_34_qep_pin { | |
| pinctrl-single,pins = <0x1a4 0x31>; | |
| phandle = <0x18a>; | |
| }; | |
| pinmux_P2_34_pruout_pin { | |
| pinctrl-single,pins = <0x1a4 0x25>; | |
| phandle = <0x18b>; | |
| }; | |
| pinmux_P2_34_pruin_pin { | |
| pinctrl-single,pins = <0x1a4 0x2e>; | |
| phandle = <0x18c>; | |
| }; | |
| pinmux_P2_35_default_pin { | |
| pinctrl-single,pins = <0xe0 0x2f>; | |
| phandle = <0x18d>; | |
| }; | |
| pinmux_P2_35_gpio_pin { | |
| pinctrl-single,pins = <0xe0 0x2f>; | |
| phandle = <0x18e>; | |
| }; | |
| pinmux_P2_35_gpio_pu_pin { | |
| pinctrl-single,pins = <0xe0 0x37>; | |
| phandle = <0x18f>; | |
| }; | |
| pinmux_P2_35_gpio_pd_pin { | |
| pinctrl-single,pins = <0xe0 0x27>; | |
| phandle = <0x190>; | |
| }; | |
| pinmux_P2_35_gpio_input_pin { | |
| pinctrl-single,pins = <0xe0 0x2f>; | |
| phandle = <0x191>; | |
| }; | |
| pinmux_P2_35_pruout_pin { | |
| pinctrl-single,pins = <0xe0 0x25>; | |
| phandle = <0x192>; | |
| }; | |
| pinmux_P2_35_pruin_pin { | |
| pinctrl-single,pins = <0xe0 0x2e>; | |
| phandle = <0x193>; | |
| }; | |
| }; | |
| scm_conf@0 { | |
| compatible = "syscon", "simple-bus"; | |
| reg = <0x0 0x800>; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x1>; | |
| ranges = <0x0 0x0 0x800>; | |
| phandle = <0x6>; | |
| clocks { | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| phandle = <0x1c1>; | |
| sys_clkin_ck@40 { | |
| #clock-cells = <0x0>; | |
| compatible = "ti,mux-clock"; | |
| clocks = <0x25 0x26 0x27 0x28>; | |
| ti,bit-shift = <0x16>; | |
| reg = <0x40>; | |
| phandle = <0x9>; | |
| }; | |
| adc_tsc_fck { | |
| #clock-cells = <0x0>; | |
| compatible = "fixed-factor-clock"; | |
| clocks = <0x9>; | |
| clock-mult = <0x1>; | |
| clock-div = <0x1>; | |
| phandle = <0x1c2>; | |
| }; | |
| dcan0_fck { | |
| #clock-cells = <0x0>; | |
| compatible = "fixed-factor-clock"; | |
| clocks = <0x9>; | |
| clock-mult = <0x1>; | |
| clock-div = <0x1>; | |
| phandle = <0x36>; | |
| }; | |
| dcan1_fck { | |
| #clock-cells = <0x0>; | |
| compatible = "fixed-factor-clock"; | |
| clocks = <0x9>; | |
| clock-mult = <0x1>; | |
| clock-div = <0x1>; | |
| phandle = <0x37>; | |
| }; | |
| mcasp0_fck { | |
| #clock-cells = <0x0>; | |
| compatible = "fixed-factor-clock"; | |
| clocks = <0x9>; | |
| clock-mult = <0x1>; | |
| clock-div = <0x1>; | |
| phandle = <0x1c3>; | |
| }; | |
| mcasp1_fck { | |
| #clock-cells = <0x0>; | |
| compatible = "fixed-factor-clock"; | |
| clocks = <0x9>; | |
| clock-mult = <0x1>; | |
| clock-div = <0x1>; | |
| phandle = <0x1c4>; | |
| }; | |
| smartreflex0_fck { | |
| #clock-cells = <0x0>; | |
| compatible = "fixed-factor-clock"; | |
| clocks = <0x9>; | |
| clock-mult = <0x1>; | |
| clock-div = <0x1>; | |
| phandle = <0x1c5>; | |
| }; | |
| smartreflex1_fck { | |
| #clock-cells = <0x0>; | |
| compatible = "fixed-factor-clock"; | |
| clocks = <0x9>; | |
| clock-mult = <0x1>; | |
| clock-div = <0x1>; | |
| phandle = <0x1c6>; | |
| }; | |
| sha0_fck { | |
| #clock-cells = <0x0>; | |
| compatible = "fixed-factor-clock"; | |
| clocks = <0x9>; | |
| clock-mult = <0x1>; | |
| clock-div = <0x1>; | |
| phandle = <0x1c7>; | |
| }; | |
| aes0_fck { | |
| #clock-cells = <0x0>; | |
| compatible = "fixed-factor-clock"; | |
| clocks = <0x9>; | |
| clock-mult = <0x1>; | |
| clock-div = <0x1>; | |
| phandle = <0x1c8>; | |
| }; | |
| rng_fck { | |
| #clock-cells = <0x0>; | |
| compatible = "fixed-factor-clock"; | |
| clocks = <0x9>; | |
| clock-mult = <0x1>; | |
| clock-div = <0x1>; | |
| phandle = <0x1c9>; | |
| }; | |
| ehrpwm0_tbclk@44e10664 { | |
| #clock-cells = <0x0>; | |
| compatible = "ti,gate-clock"; | |
| clocks = <0x29>; | |
| ti,bit-shift = <0x0>; | |
| reg = <0x664>; | |
| phandle = <0x3c>; | |
| }; | |
| ehrpwm1_tbclk@44e10664 { | |
| #clock-cells = <0x0>; | |
| compatible = "ti,gate-clock"; | |
| clocks = <0x29>; | |
| ti,bit-shift = <0x1>; | |
| reg = <0x664>; | |
| phandle = <0x3d>; | |
| }; | |
| ehrpwm2_tbclk@44e10664 { | |
| #clock-cells = <0x0>; | |
| compatible = "ti,gate-clock"; | |
| clocks = <0x29>; | |
| ti,bit-shift = <0x2>; | |
| reg = <0x664>; | |
| phandle = <0x3e>; | |
| }; | |
| }; | |
| }; | |
| wkup_m3_ipc@1324 { | |
| compatible = "ti,am3352-wkup-m3-ipc"; | |
| reg = <0x1324 0x24>; | |
| interrupts = <0x4e>; | |
| ti,rproc = <0x2a>; | |
| mboxes = <0x2b 0x2c>; | |
| phandle = <0x1ca>; | |
| }; | |
| dma-router@f90 { | |
| compatible = "ti,am335x-edma-crossbar"; | |
| reg = <0xf90 0x40>; | |
| #dma-cells = <0x3>; | |
| dma-requests = <0x20>; | |
| dma-masters = <0x2d>; | |
| phandle = <0x32>; | |
| }; | |
| clockdomains { | |
| phandle = <0x1cb>; | |
| }; | |
| }; | |
| }; | |
| interrupt-controller@48200000 { | |
| compatible = "ti,am33xx-intc"; | |
| interrupt-controller; | |
| #interrupt-cells = <0x1>; | |
| reg = <0x48200000 0x1000>; | |
| phandle = <0x1>; | |
| }; | |
| edma@49000000 { | |
| compatible = "ti,edma3-tpcc"; | |
| ti,hwmods = "tpcc"; | |
| reg = <0x49000000 0x10000>; | |
| reg-names = "edma3_cc"; | |
| interrupts = <0xc 0xd 0xe>; | |
| interrupt-names = "edma3_ccint", "edma3_mperr", "edma3_ccerrint"; | |
| dma-requests = <0x40>; | |
| #dma-cells = <0x2>; | |
| ti,tptcs = <0x2e 0x7 0x2f 0x5 0x30 0x0>; | |
| ti,edma-memcpy-channels = <0x14 0x15>; | |
| phandle = <0x2d>; | |
| }; | |
| tptc@49800000 { | |
| compatible = "ti,edma3-tptc"; | |
| ti,hwmods = "tptc0"; | |
| reg = <0x49800000 0x100000>; | |
| interrupts = <0x70>; | |
| interrupt-names = "edma3_tcerrint"; | |
| phandle = <0x2e>; | |
| }; | |
| tptc@49900000 { | |
| compatible = "ti,edma3-tptc"; | |
| ti,hwmods = "tptc1"; | |
| reg = <0x49900000 0x100000>; | |
| interrupts = <0x71>; | |
| interrupt-names = "edma3_tcerrint"; | |
| phandle = <0x2f>; | |
| }; | |
| tptc@49a00000 { | |
| compatible = "ti,edma3-tptc"; | |
| ti,hwmods = "tptc2"; | |
| reg = <0x49a00000 0x100000>; | |
| interrupts = <0x72>; | |
| interrupt-names = "edma3_tcerrint"; | |
| phandle = <0x30>; | |
| }; | |
| emif@4c000000 { | |
| compatible = "ti,emif-am3352"; | |
| reg = <0x4c000000 0x1000>; | |
| sram = <0x7 0x8>; | |
| phandle = <0x1cc>; | |
| }; | |
| gpio@44e07000 { | |
| compatible = "ti,omap4-gpio"; | |
| ti,hwmods = "gpio1"; | |
| gpio-controller; | |
| #gpio-cells = <0x2>; | |
| interrupt-controller; | |
| #interrupt-cells = <0x2>; | |
| reg = <0x44e07000 0x1000>; | |
| interrupts = <0x60>; | |
| gpio-line-names = "MDIO_DATA", "MDIO_CLK", "SPI0_SCLK", "SPI0_D0", "SPI0_D1", "SPI0_CS0", "SPI0_CS1", "ECAP0_IN_PWM0_OUT", "LCD_DATA12", "LCD_DATA13", "LCD_DATA14", "LCD_DATA15", "UART1_CTSN", "UART1_RTSN", "UART1_RXD", "UART1_TXD", "GMII1_TXD3", "GMII1_TXD2", "USB0_DRVVBUS", "XDMA_EVENT_INTR0", "XDMA_EVENT_INTR1", "GMII1_TXD1", "GPMC_AD8", "GPMC_AD9", "NC", "NC", "GPMC_AD10", "GPMC_AD11", "GMII1_TXD0", "RMII1_REFCLK", "GPMC_WAIT0", "GPMC_WPN"; | |
| phandle = <0x35>; | |
| }; | |
| gpio@4804c000 { | |
| compatible = "ti,omap4-gpio"; | |
| ti,hwmods = "gpio2"; | |
| gpio-controller; | |
| #gpio-cells = <0x2>; | |
| interrupt-controller; | |
| #interrupt-cells = <0x2>; | |
| reg = <0x4804c000 0x1000>; | |
| interrupts = <0x62>; | |
| gpio-line-names = "GPMC_AD0", "GPMC_AD1", "GPMC_AD2", "GPMC_AD3", "GPMC_AD4", "GPMC_AD5", "GPMC_AD6", "GPMC_AD7", "UART0_CTSN", "UART0_RTSN", "UART0_RXD", "UART0_TXD", "GPMC_AD12", "GPMC_AD13", "GPMC_AD14", "GPMC_AD15", "GPMC_A0", "GPMC_A1", "GPMC_A2", "GPMC_A3", "GPMC_A4", "GPMC_A5", "GPMC_A6", "GPMC_A7", "GPMC_A8", "GPMC_A9", "GPMC_A10", "GPMC_A11", "GPMC_BE1N", "GPMC_CSN0", "GPMC_CSN1", "GPMC_CSN2"; | |
| phandle = <0x196>; | |
| }; | |
| gpio@481ac000 { | |
| compatible = "ti,omap4-gpio"; | |
| ti,hwmods = "gpio3"; | |
| gpio-controller; | |
| #gpio-cells = <0x2>; | |
| interrupt-controller; | |
| #interrupt-cells = <0x2>; | |
| reg = <0x481ac000 0x1000>; | |
| interrupts = <0x20>; | |
| gpio-line-names = "GPMC_CSN3", "GPMC_CLK", "GPMC_ADVN_ALE", "GPMC_OEN_REN", "GPMC_WEN", "GPMC_BE0N_CLE", "LCD_DATA0", "LCD_DATA1", "LCD_DATA2", "LCD_DATA3", "LCD_DATA4", "LCD_DATA5", "LCD_DATA6", "LCD_DATA7", "LCD_DATA8", "LCD_DATA9", "LCD_DATA10", "LCD_DATA11", "GMII1_RXD3", "GMII1_RXD2", "GMII1_RXD1", "GMII1_RXD0", "LCD_VSYNC", "LCD_HSYNC", "LCD_PCLK", "LCD_AC_BIAS_EN", "MMC0_DAT3", "MMC0_DAT2", "MMC0_DAT1", "MMC0_DAT0", "MMC0_CLK", "MMC0_CMD"; | |
| phandle = <0x194>; | |
| }; | |
| gpio@481ae000 { | |
| compatible = "ti,omap4-gpio"; | |
| ti,hwmods = "gpio4"; | |
| gpio-controller; | |
| #gpio-cells = <0x2>; | |
| interrupt-controller; | |
| #interrupt-cells = <0x2>; | |
| reg = <0x481ae000 0x1000>; | |
| interrupts = <0x3e>; | |
| gpio-line-names = "GMII1_COL", "GMII1_CRS", "GMII1_RXER", "GMII1_TXEN", "GMII1_RXDV", "I2C0_SDA", "I2C0_SCL", "EMU0", "EMU1", "GMII1_TXCLK", "GMII1_RXCLK", "NC", "NC", "USB1_DRVVBUS", "MCASP0_ACLKX", "MCASP0_FSX", "MCASP0_AXR0", "MCASP0_AHCLKR", "MCASP0_ACLKR", "MCASP0_FSR", "MCASP0_AXR1", "MCASP0_AHCLKX", "NC", "NC", "NC", "NC", "NC", "NC", "NC", "NC", "NC", "NC"; | |
| phandle = <0x195>; | |
| }; | |
| serial@44e09000 { | |
| compatible = "ti,am3352-uart", "ti,omap3-uart"; | |
| ti,hwmods = "uart1"; | |
| clock-frequency = <0x2dc6c00>; | |
| reg = <0x44e09000 0x2000>; | |
| interrupts = <0x48>; | |
| status = "okay"; | |
| dmas = <0x2d 0x1a 0x0 0x2d 0x1b 0x0>; | |
| dma-names = "tx", "rx"; | |
| pinctrl-names = "default"; | |
| pinctrl-0; | |
| phandle = <0x1cd>; | |
| }; | |
| serial@48022000 { | |
| compatible = "ti,am3352-uart", "ti,omap3-uart"; | |
| ti,hwmods = "uart2"; | |
| clock-frequency = <0x2dc6c00>; | |
| reg = <0x48022000 0x2000>; | |
| interrupts = <0x49>; | |
| status = "okay"; | |
| dmas = <0x2d 0x1c 0x0 0x2d 0x1d 0x0>; | |
| dma-names = "tx", "rx"; | |
| pinctrl-names = "default"; | |
| pinctrl-0; | |
| phandle = <0x1ce>; | |
| }; | |
| serial@48024000 { | |
| compatible = "ti,am3352-uart", "ti,omap3-uart"; | |
| ti,hwmods = "uart3"; | |
| clock-frequency = <0x2dc6c00>; | |
| reg = <0x48024000 0x2000>; | |
| interrupts = <0x4a>; | |
| status = "okay"; | |
| dmas = <0x2d 0x1e 0x0 0x2d 0x1f 0x0>; | |
| dma-names = "tx", "rx"; | |
| pinctrl-names = "default"; | |
| pinctrl-0; | |
| phandle = <0x1cf>; | |
| }; | |
| serial@481a6000 { | |
| compatible = "ti,am3352-uart", "ti,omap3-uart"; | |
| ti,hwmods = "uart4"; | |
| clock-frequency = <0x2dc6c00>; | |
| reg = <0x481a6000 0x2000>; | |
| interrupts = <0x2c>; | |
| status = "disabled"; | |
| phandle = <0x1d0>; | |
| }; | |
| serial@481a8000 { | |
| compatible = "ti,am3352-uart", "ti,omap3-uart"; | |
| ti,hwmods = "uart5"; | |
| clock-frequency = <0x2dc6c00>; | |
| reg = <0x481a8000 0x2000>; | |
| interrupts = <0x2d>; | |
| status = "okay"; | |
| pinctrl-names = "default"; | |
| pinctrl-0; | |
| phandle = <0x1d1>; | |
| }; | |
| serial@481aa000 { | |
| compatible = "ti,am3352-uart", "ti,omap3-uart"; | |
| ti,hwmods = "uart6"; | |
| clock-frequency = <0x2dc6c00>; | |
| reg = <0x481aa000 0x2000>; | |
| interrupts = <0x2e>; | |
| status = "disabled"; | |
| phandle = <0x1d2>; | |
| }; | |
| i2c@44e0b000 { | |
| compatible = "ti,omap4-i2c"; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| ti,hwmods = "i2c1"; | |
| reg = <0x44e0b000 0x1000>; | |
| interrupts = <0x46>; | |
| status = "okay"; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x31>; | |
| clock-frequency = <0x61a80>; | |
| phandle = <0x1d3>; | |
| tps@24 { | |
| reg = <0x24>; | |
| compatible = "ti,tps65217"; | |
| interrupt-controller; | |
| #interrupt-cells = <0x1>; | |
| interrupts = <0x7>; | |
| interrupt-parent = <0x1>; | |
| ti,pmic-shutdown-controller; | |
| phandle = <0x1d4>; | |
| charger { | |
| compatible = "ti,tps65217-charger"; | |
| interrupts = <0x0 0x1>; | |
| interrupt-names = "USB", "AC"; | |
| status = "okay"; | |
| }; | |
| pwrbutton { | |
| compatible = "ti,tps65217-pwrbutton"; | |
| interrupts = <0x2>; | |
| status = "okay"; | |
| }; | |
| regulators { | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| regulator@0 { | |
| reg = <0x0>; | |
| regulator-compatible = "dcdc1"; | |
| regulator-name = "vdds_dpr"; | |
| regulator-always-on; | |
| phandle = <0x1d5>; | |
| }; | |
| regulator@1 { | |
| reg = <0x1>; | |
| regulator-compatible = "dcdc2"; | |
| regulator-name = "vdd_mpu"; | |
| regulator-min-microvolt = <0xe1d48>; | |
| regulator-max-microvolt = <0x149f4c>; | |
| regulator-boot-on; | |
| regulator-always-on; | |
| phandle = <0x5>; | |
| }; | |
| regulator@2 { | |
| reg = <0x2>; | |
| regulator-compatible = "dcdc3"; | |
| regulator-name = "vdd_core"; | |
| regulator-min-microvolt = <0xe1d48>; | |
| regulator-max-microvolt = <0x118c30>; | |
| regulator-boot-on; | |
| regulator-always-on; | |
| phandle = <0x1d6>; | |
| }; | |
| regulator@3 { | |
| reg = <0x3>; | |
| regulator-compatible = "ldo1"; | |
| regulator-name = "vio,vrtc,vdds"; | |
| regulator-always-on; | |
| phandle = <0x1d7>; | |
| }; | |
| regulator@4 { | |
| reg = <0x4>; | |
| regulator-compatible = "ldo2"; | |
| regulator-name = "vdd_3v3aux"; | |
| regulator-always-on; | |
| phandle = <0x1d8>; | |
| }; | |
| regulator@5 { | |
| reg = <0x5>; | |
| regulator-compatible = "ldo3"; | |
| regulator-name = "vdd_1v8"; | |
| regulator-min-microvolt = <0x1b7740>; | |
| regulator-max-microvolt = <0x1b7740>; | |
| regulator-always-on; | |
| phandle = <0x1d9>; | |
| }; | |
| regulator@6 { | |
| reg = <0x6>; | |
| regulator-compatible = "ldo4"; | |
| regulator-name = "vdd_3v3a"; | |
| regulator-always-on; | |
| phandle = <0x1da>; | |
| }; | |
| }; | |
| }; | |
| baseboard_eeprom@50 { | |
| compatible = "atmel,24c256"; | |
| reg = <0x50>; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x1>; | |
| phandle = <0x1db>; | |
| baseboard_data@0 { | |
| reg = <0x0 0x100>; | |
| phandle = <0x1dc>; | |
| }; | |
| }; | |
| }; | |
| i2c@4802a000 { | |
| compatible = "ti,omap4-i2c"; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| ti,hwmods = "i2c2"; | |
| reg = <0x4802a000 0x1000>; | |
| interrupts = <0x47>; | |
| status = "okay"; | |
| clock-frequency = <0x61a80>; | |
| phandle = <0x1dd>; | |
| }; | |
| i2c@4819c000 { | |
| compatible = "ti,omap4-i2c"; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| ti,hwmods = "i2c3"; | |
| reg = <0x4819c000 0x1000>; | |
| interrupts = <0x1e>; | |
| status = "okay"; | |
| clock-frequency = <0x61a80>; | |
| phandle = <0x1de>; | |
| }; | |
| mmc@48060000 { | |
| compatible = "ti,omap4-hsmmc"; | |
| ti,hwmods = "mmc1"; | |
| ti,dual-volt; | |
| ti,needs-special-reset; | |
| ti,needs-special-hs-handling; | |
| dmas = <0x32 0x18 0x0 0x0 0x32 0x19 0x0 0x0>; | |
| dma-names = "tx", "rx"; | |
| interrupts = <0x40>; | |
| reg = <0x48060000 0x1000>; | |
| status = "okay"; | |
| vmmc-supply = <0x33>; | |
| bus-width = <0x4>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x34>; | |
| cd-gpios = <0x35 0x6 0x1>; | |
| phandle = <0x1df>; | |
| }; | |
| mmc@481d8000 { | |
| compatible = "ti,omap4-hsmmc"; | |
| ti,hwmods = "mmc2"; | |
| ti,needs-special-reset; | |
| dmas = <0x2d 0x2 0x0 0x2d 0x3 0x0>; | |
| dma-names = "tx", "rx"; | |
| interrupts = <0x1c>; | |
| reg = <0x481d8000 0x1000>; | |
| status = "disabled"; | |
| phandle = <0x1e0>; | |
| }; | |
| mmc@47810000 { | |
| compatible = "ti,omap4-hsmmc"; | |
| ti,hwmods = "mmc3"; | |
| ti,needs-special-reset; | |
| interrupts = <0x1d>; | |
| reg = <0x47810000 0x1000>; | |
| status = "disabled"; | |
| phandle = <0x1e1>; | |
| }; | |
| spinlock@480ca000 { | |
| compatible = "ti,omap4-hwspinlock"; | |
| reg = <0x480ca000 0x1000>; | |
| ti,hwmods = "spinlock"; | |
| #hwlock-cells = <0x1>; | |
| phandle = <0x1e2>; | |
| }; | |
| wdt@44e35000 { | |
| compatible = "ti,omap3-wdt"; | |
| ti,hwmods = "wd_timer2"; | |
| reg = <0x44e35000 0x1000>; | |
| interrupts = <0x5b>; | |
| phandle = <0x1e3>; | |
| }; | |
| can@481cc000 { | |
| compatible = "ti,am3352-d_can"; | |
| ti,hwmods = "d_can0"; | |
| reg = <0x481cc000 0x2000>; | |
| clocks = <0x36>; | |
| clock-names = "fck"; | |
| syscon-raminit = <0x6 0x644 0x0>; | |
| interrupts = <0x34>; | |
| status = "okay"; | |
| pinctrl-names = "default"; | |
| pinctrl-0; | |
| phandle = <0x1e4>; | |
| }; | |
| can@481d0000 { | |
| compatible = "ti,am3352-d_can"; | |
| ti,hwmods = "d_can1"; | |
| reg = <0x481d0000 0x2000>; | |
| clocks = <0x37>; | |
| clock-names = "fck"; | |
| syscon-raminit = <0x6 0x644 0x1>; | |
| interrupts = <0x37>; | |
| status = "okay"; | |
| pinctrl-names = "default"; | |
| pinctrl-0; | |
| phandle = <0x1e5>; | |
| }; | |
| mailbox@480C8000 { | |
| compatible = "ti,omap4-mailbox"; | |
| reg = <0x480c8000 0x200>; | |
| interrupts = <0x4d>; | |
| ti,hwmods = "mailbox"; | |
| #mbox-cells = <0x1>; | |
| ti,mbox-num-users = <0x4>; | |
| ti,mbox-num-fifos = <0x8>; | |
| phandle = <0x2b>; | |
| wkup_m3 { | |
| ti,mbox-send-noirq; | |
| ti,mbox-tx = <0x0 0x0 0x0>; | |
| ti,mbox-rx = <0x0 0x0 0x3>; | |
| phandle = <0x2c>; | |
| }; | |
| }; | |
| timer@44e31000 { | |
| compatible = "ti,am335x-timer-1ms"; | |
| reg = <0x44e31000 0x400>; | |
| interrupts = <0x43>; | |
| ti,hwmods = "timer1"; | |
| ti,timer-alwon; | |
| phandle = <0x1e6>; | |
| }; | |
| timer@48040000 { | |
| compatible = "ti,am335x-timer"; | |
| reg = <0x48040000 0x400>; | |
| interrupts = <0x44>; | |
| ti,hwmods = "timer2"; | |
| phandle = <0x1e7>; | |
| }; | |
| timer@48042000 { | |
| compatible = "ti,am335x-timer"; | |
| reg = <0x48042000 0x400>; | |
| interrupts = <0x45>; | |
| ti,hwmods = "timer3"; | |
| phandle = <0x1e8>; | |
| }; | |
| timer@48044000 { | |
| compatible = "ti,am335x-timer"; | |
| reg = <0x48044000 0x400>; | |
| interrupts = <0x5c>; | |
| ti,hwmods = "timer4"; | |
| ti,timer-pwm; | |
| phandle = <0x1e9>; | |
| }; | |
| timer@48046000 { | |
| compatible = "ti,am335x-timer"; | |
| reg = <0x48046000 0x400>; | |
| interrupts = <0x5d>; | |
| ti,hwmods = "timer5"; | |
| ti,timer-pwm; | |
| phandle = <0x1ea>; | |
| }; | |
| timer@48048000 { | |
| compatible = "ti,am335x-timer"; | |
| reg = <0x48048000 0x400>; | |
| interrupts = <0x5e>; | |
| ti,hwmods = "timer6"; | |
| ti,timer-pwm; | |
| phandle = <0x1eb>; | |
| }; | |
| timer@4804a000 { | |
| compatible = "ti,am335x-timer"; | |
| reg = <0x4804a000 0x400>; | |
| interrupts = <0x5f>; | |
| ti,hwmods = "timer7"; | |
| ti,timer-pwm; | |
| phandle = <0x1ec>; | |
| }; | |
| rtc@44e3e000 { | |
| compatible = "ti,am3352-rtc", "ti,da830-rtc"; | |
| reg = <0x44e3e000 0x1000>; | |
| interrupts = <0x4b 0x4c>; | |
| ti,hwmods = "rtc"; | |
| clocks = <0x16>; | |
| clock-names = "int-clk"; | |
| system-power-controller; | |
| phandle = <0x1ed>; | |
| }; | |
| spi@48030000 { | |
| compatible = "ti,omap4-mcspi"; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| reg = <0x48030000 0x400>; | |
| interrupts = <0x41>; | |
| ti,spi-num-cs = <0x2>; | |
| ti,hwmods = "spi0"; | |
| dmas = <0x2d 0x10 0x0 0x2d 0x11 0x0 0x2d 0x12 0x0 0x2d 0x13 0x0>; | |
| dma-names = "tx0", "rx0", "tx1", "rx1"; | |
| status = "okay"; | |
| phandle = <0x1ee>; | |
| channel@0 { | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| compatible = "spidev"; | |
| reg = <0x0>; | |
| spi-max-frequency = <0x16e3600>; | |
| }; | |
| channel@1 { | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| compatible = "spidev"; | |
| reg = <0x1>; | |
| spi-max-frequency = <0x16e3600>; | |
| status = "disabled"; | |
| }; | |
| }; | |
| spi@481a0000 { | |
| compatible = "ti,omap4-mcspi"; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| reg = <0x481a0000 0x400>; | |
| interrupts = <0x7d>; | |
| ti,spi-num-cs = <0x2>; | |
| ti,hwmods = "spi1"; | |
| dmas = <0x2d 0x2a 0x0 0x2d 0x2b 0x0 0x2d 0x2c 0x0 0x2d 0x2d 0x0>; | |
| dma-names = "tx0", "rx0", "tx1", "rx1"; | |
| status = "okay"; | |
| phandle = <0x1ef>; | |
| channel@0 { | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| compatible = "spidev"; | |
| reg = <0x0>; | |
| spi-max-frequency = <0x16e3600>; | |
| }; | |
| channel@1 { | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| compatible = "spidev"; | |
| reg = <0x1>; | |
| spi-max-frequency = <0x16e3600>; | |
| }; | |
| }; | |
| usb@47400000 { | |
| compatible = "ti,am33xx-usb"; | |
| reg = <0x47400000 0x1000>; | |
| ranges; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x1>; | |
| ti,hwmods = "usb_otg_hs"; | |
| status = "okay"; | |
| phandle = <0x1f0>; | |
| control@44e10620 { | |
| compatible = "ti,am335x-usb-ctrl-module"; | |
| reg = <0x44e10620 0x10 0x44e10648 0x4>; | |
| reg-names = "phy_ctrl", "wakeup"; | |
| status = "okay"; | |
| phandle = <0x38>; | |
| }; | |
| usb-phy@47401300 { | |
| compatible = "ti,am335x-usb-phy"; | |
| reg = <0x47401300 0x100>; | |
| reg-names = "phy"; | |
| status = "okay"; | |
| ti,ctrl_mod = <0x38>; | |
| phandle = <0x39>; | |
| }; | |
| usb@47401000 { | |
| compatible = "ti,musb-am33xx"; | |
| status = "okay"; | |
| reg = <0x47401400 0x400 0x47401000 0x200>; | |
| reg-names = "mc", "control"; | |
| interrupts = <0x12>; | |
| interrupt-names = "mc"; | |
| dr_mode = "otg"; | |
| mentor,multipoint = <0x1>; | |
| mentor,num-eps = <0x10>; | |
| mentor,ram-bits = <0xc>; | |
| mentor,power = <0x1f4>; | |
| phys = <0x39>; | |
| dmas = <0x3a 0x0 0x0 0x3a 0x1 0x0 0x3a 0x2 0x0 0x3a 0x3 0x0 0x3a 0x4 0x0 0x3a 0x5 0x0 0x3a 0x6 0x0 0x3a 0x7 0x0 0x3a 0x8 0x0 0x3a 0x9 0x0 0x3a 0xa 0x0 0x3a 0xb 0x0 0x3a 0xc 0x0 0x3a 0xd 0x0 0x3a 0xe 0x0 0x3a 0x0 0x1 0x3a 0x1 0x1 0x3a 0x2 0x1 0x3a 0x3 0x1 0x3a 0x4 0x1 0x3a 0x5 0x1 0x3a 0x6 0x1 0x3a 0x7 0x1 0x3a 0x8 0x1 0x3a 0x9 0x1 0x3a 0xa 0x1 0x3a 0xb 0x1 0x3a 0xc 0x1 0x3a 0xd 0x1 0x3a 0xe 0x1>; | |
| dma-names = "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7", "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", "rx14", "rx15", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", "tx8", "tx9", "tx10", "tx11", "tx12", "tx13", "tx14", "tx15"; | |
| phandle = <0x1f1>; | |
| }; | |
| usb-phy@47401b00 { | |
| compatible = "ti,am335x-usb-phy"; | |
| reg = <0x47401b00 0x100>; | |
| reg-names = "phy"; | |
| status = "okay"; | |
| ti,ctrl_mod = <0x38>; | |
| phandle = <0x3b>; | |
| }; | |
| usb@47401800 { | |
| compatible = "ti,musb-am33xx"; | |
| status = "okay"; | |
| reg = <0x47401c00 0x400 0x47401800 0x200>; | |
| reg-names = "mc", "control"; | |
| interrupts = <0x13>; | |
| interrupt-names = "mc"; | |
| dr_mode = "host"; | |
| mentor,multipoint = <0x1>; | |
| mentor,num-eps = <0x10>; | |
| mentor,ram-bits = <0xc>; | |
| mentor,power = <0x1f4>; | |
| phys = <0x3b>; | |
| dmas = <0x3a 0xf 0x0 0x3a 0x10 0x0 0x3a 0x11 0x0 0x3a 0x12 0x0 0x3a 0x13 0x0 0x3a 0x14 0x0 0x3a 0x15 0x0 0x3a 0x16 0x0 0x3a 0x17 0x0 0x3a 0x18 0x0 0x3a 0x19 0x0 0x3a 0x1a 0x0 0x3a 0x1b 0x0 0x3a 0x1c 0x0 0x3a 0x1d 0x0 0x3a 0xf 0x1 0x3a 0x10 0x1 0x3a 0x11 0x1 0x3a 0x12 0x1 0x3a 0x13 0x1 0x3a 0x14 0x1 0x3a 0x15 0x1 0x3a 0x16 0x1 0x3a 0x17 0x1 0x3a 0x18 0x1 0x3a 0x19 0x1 0x3a 0x1a 0x1 0x3a 0x1b 0x1 0x3a 0x1c 0x1 0x3a 0x1d 0x1>; | |
| dma-names = "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7", "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", "rx14", "rx15", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", "tx8", "tx9", "tx10", "tx11", "tx12", "tx13", "tx14", "tx15"; | |
| phandle = <0x1f2>; | |
| }; | |
| dma-controller@47402000 { | |
| compatible = "ti,am3359-cppi41"; | |
| reg = <0x47400000 0x1000 0x47402000 0x1000 0x47403000 0x1000 0x47404000 0x4000>; | |
| reg-names = "glue", "controller", "scheduler", "queuemgr"; | |
| interrupts = <0x11>; | |
| interrupt-names = "glue"; | |
| #dma-cells = <0x2>; | |
| #dma-channels = <0x1e>; | |
| #dma-requests = <0x100>; | |
| status = "okay"; | |
| phandle = <0x3a>; | |
| }; | |
| }; | |
| epwmss@48300000 { | |
| compatible = "ti,am33xx-pwmss"; | |
| reg = <0x48300000 0x10>; | |
| ti,hwmods = "epwmss0"; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x1>; | |
| status = "okay"; | |
| ranges = <0x48300100 0x48300100 0x80 0x48300180 0x48300180 0x80 0x48300200 0x48300200 0x80>; | |
| phandle = <0x1f3>; | |
| ecap@48300100 { | |
| compatible = "ti,am3352-ecap", "ti,am33xx-ecap"; | |
| #pwm-cells = <0x3>; | |
| reg = <0x48300100 0x80>; | |
| clocks = <0x29>; | |
| clock-names = "fck"; | |
| interrupts = <0x1f>; | |
| interrupt-names = "ecap0"; | |
| status = "disabled"; | |
| phandle = <0x1f4>; | |
| }; | |
| eqep@0x48300180 { | |
| compatible = "ti,am33xx-eqep"; | |
| reg = <0x48300180 0x80>; | |
| clocks = <0x29>; | |
| clock-names = "fck"; | |
| interrupt-parent = <0x1>; | |
| interrupts = <0x4f>; | |
| status = "disabled"; | |
| phandle = <0x1f5>; | |
| }; | |
| pwm@48300200 { | |
| compatible = "ti,am3352-ehrpwm", "ti,am33xx-ehrpwm"; | |
| #pwm-cells = <0x3>; | |
| reg = <0x48300200 0x80>; | |
| clocks = <0x3c 0x29>; | |
| clock-names = "tbclk", "fck"; | |
| status = "okay"; | |
| pinctrl-names = "default"; | |
| pinctrl-0; | |
| phandle = <0x1f6>; | |
| }; | |
| }; | |
| epwmss@48302000 { | |
| compatible = "ti,am33xx-pwmss"; | |
| reg = <0x48302000 0x10>; | |
| ti,hwmods = "epwmss1"; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x1>; | |
| status = "okay"; | |
| ranges = <0x48302100 0x48302100 0x80 0x48302180 0x48302180 0x80 0x48302200 0x48302200 0x80>; | |
| phandle = <0x1f7>; | |
| ecap@48302100 { | |
| compatible = "ti,am3352-ecap", "ti,am33xx-ecap"; | |
| #pwm-cells = <0x3>; | |
| reg = <0x48302100 0x80>; | |
| clocks = <0x29>; | |
| clock-names = "fck"; | |
| interrupts = <0x2f>; | |
| interrupt-names = "ecap1"; | |
| status = "disabled"; | |
| phandle = <0x1f8>; | |
| }; | |
| eqep@0x48302180 { | |
| compatible = "ti,am33xx-eqep"; | |
| reg = <0x48302180 0x80>; | |
| clocks = <0x29>; | |
| clock-names = "fck"; | |
| interrupt-parent = <0x1>; | |
| interrupts = <0x58>; | |
| status = "disabled"; | |
| phandle = <0x1f9>; | |
| }; | |
| pwm@48302200 { | |
| compatible = "ti,am3352-ehrpwm", "ti,am33xx-ehrpwm"; | |
| #pwm-cells = <0x3>; | |
| reg = <0x48302200 0x80>; | |
| clocks = <0x3d 0x29>; | |
| clock-names = "tbclk", "fck"; | |
| status = "okay"; | |
| pinctrl-names = "default"; | |
| pinctrl-0; | |
| phandle = <0x1fa>; | |
| }; | |
| }; | |
| epwmss@48304000 { | |
| compatible = "ti,am33xx-pwmss"; | |
| reg = <0x48304000 0x10>; | |
| ti,hwmods = "epwmss2"; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x1>; | |
| status = "okay"; | |
| ranges = <0x48304100 0x48304100 0x80 0x48304180 0x48304180 0x80 0x48304200 0x48304200 0x80>; | |
| phandle = <0x1fb>; | |
| ecap@48304100 { | |
| compatible = "ti,am3352-ecap", "ti,am33xx-ecap"; | |
| #pwm-cells = <0x3>; | |
| reg = <0x48304100 0x80>; | |
| clocks = <0x29>; | |
| clock-names = "fck"; | |
| interrupts = <0x3d>; | |
| interrupt-names = "ecap2"; | |
| status = "disabled"; | |
| phandle = <0x1fc>; | |
| }; | |
| eqep@0x48304180 { | |
| compatible = "ti,am33xx-eqep"; | |
| reg = <0x48304180 0x80>; | |
| clocks = <0x29>; | |
| clock-names = "fck"; | |
| interrupt-parent = <0x1>; | |
| interrupts = <0x59>; | |
| status = "disabled"; | |
| phandle = <0x1fd>; | |
| }; | |
| pwm@48304200 { | |
| compatible = "ti,am3352-ehrpwm", "ti,am33xx-ehrpwm"; | |
| #pwm-cells = <0x3>; | |
| reg = <0x48304200 0x80>; | |
| clocks = <0x3e 0x29>; | |
| clock-names = "tbclk", "fck"; | |
| status = "okay"; | |
| pinctrl-names = "default"; | |
| pinctrl-0; | |
| phandle = <0x1fe>; | |
| }; | |
| }; | |
| ethernet@4a100000 { | |
| compatible = "ti,am335x-cpsw", "ti,cpsw"; | |
| ti,hwmods = "cpgmac0"; | |
| clocks = <0x3f 0x40>; | |
| clock-names = "fck", "cpts"; | |
| cpdma_channels = <0x8>; | |
| ale_entries = <0x400>; | |
| bd_ram_size = <0x2000>; | |
| mac_control = <0x20>; | |
| slaves = <0x2>; | |
| active_slave = <0x0>; | |
| cpts_clock_mult = <0x80000000>; | |
| cpts_clock_shift = <0x1d>; | |
| reg = <0x4a100000 0x800 0x4a101200 0x100>; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x1>; | |
| interrupts = <0x28 0x29 0x2a 0x2b>; | |
| ranges; | |
| syscon = <0x6>; | |
| status = "disabled"; | |
| phandle = <0x1ff>; | |
| mdio@4a101000 { | |
| compatible = "ti,cpsw-mdio", "ti,davinci_mdio"; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| ti,hwmods = "davinci_mdio"; | |
| bus_freq = <0xf4240>; | |
| reg = <0x4a101000 0x100>; | |
| status = "disabled"; | |
| phandle = <0x200>; | |
| }; | |
| slave@4a100200 { | |
| local-mac-address = [98 5d ad 56 96 ca]; | |
| mac-address = [98 5d ad 56 96 ca]; | |
| phandle = <0x201>; | |
| }; | |
| slave@4a100300 { | |
| local-mac-address = [98 5d ad 56 96 cc]; | |
| mac-address = [98 5d ad 56 96 cc]; | |
| phandle = <0x202>; | |
| }; | |
| cpsw-phy-sel@44e10650 { | |
| compatible = "ti,am3352-cpsw-phy-sel"; | |
| reg = <0x44e10650 0x4>; | |
| reg-names = "gmii-sel"; | |
| phandle = <0x203>; | |
| }; | |
| }; | |
| ocmcram@40300000 { | |
| compatible = "mmio-sram"; | |
| reg = <0x40300000 0x10000>; | |
| ranges = <0x0 0x40300000 0x10000>; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x1>; | |
| phandle = <0x204>; | |
| pm-sram-code@0 { | |
| compatible = "ti,sram"; | |
| reg = <0x0 0x1000>; | |
| protect-exec; | |
| phandle = <0x7>; | |
| }; | |
| pm-sram-data@1000 { | |
| compatible = "ti,sram"; | |
| reg = <0x1000 0x1000>; | |
| pool; | |
| phandle = <0x8>; | |
| }; | |
| }; | |
| pruss_soc_bus@4a326004 { | |
| linux,phandle = <0x21a>; | |
| compatible = "ti,am3356-pruss-soc-bus"; | |
| reg = <0x4a326004 0x4>; | |
| ti,hwmods = "pruss"; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x1>; | |
| ranges = <0x0 0x4a300000 0x80000>; | |
| status = "okay"; | |
| phandle = <0x21a>; | |
| pruss@0 { | |
| linux,phandle = <0x21b>; | |
| compatible = "ti,am3356-pruss"; | |
| reg = <0x0 0x80000>; | |
| interrupts = <0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b>; | |
| interrupt-names = "host2", "host3", "host4", "host5", "host6", "host7", "host8", "host9"; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x1>; | |
| ranges; | |
| status = "okay"; | |
| phandle = <0x21b>; | |
| memories@0 { | |
| linux,phandle = <0x21c>; | |
| reg = <0x0 0x2000 0x2000 0x2000 0x10000 0x3000>; | |
| reg-names = "dram0", "dram1", "shrdram2"; | |
| phandle = <0x21c>; | |
| }; | |
| cfg@26000 { | |
| linux,phandle = <0x21d>; | |
| compatible = "syscon"; | |
| reg = <0x26000 0x2000>; | |
| phandle = <0x21d>; | |
| }; | |
| iep@2e000 { | |
| linux,phandle = <0x21e>; | |
| compatible = "syscon"; | |
| reg = <0x2e000 0x31c>; | |
| phandle = <0x21e>; | |
| }; | |
| mii_rt@32000 { | |
| linux,phandle = <0x21f>; | |
| compatible = "syscon"; | |
| reg = <0x32000 0x58>; | |
| phandle = <0x21f>; | |
| }; | |
| intc@20000 { | |
| linux,phandle = <0x219>; | |
| compatible = "ti,am3356-pruss-intc"; | |
| reg = <0x20000 0x2000>; | |
| reg-names = "intc"; | |
| interrupt-controller; | |
| #interrupt-cells = <0x1>; | |
| phandle = <0x219>; | |
| }; | |
| pru@34000 { | |
| linux,phandle = <0x220>; | |
| compatible = "ti,am3356-pru"; | |
| reg = <0x34000 0x2000 0x22000 0x400 0x22400 0x100>; | |
| reg-names = "iram", "control", "debug"; | |
| firmware-name = "am335x-pru0-fw"; | |
| interrupt-parent = <0x219>; | |
| interrupts = <0x10 0x11>; | |
| interrupt-names = "vring", "kick"; | |
| phandle = <0x220>; | |
| }; | |
| pru@38000 { | |
| linux,phandle = <0x221>; | |
| compatible = "ti,am3356-pru"; | |
| reg = <0x38000 0x2000 0x24000 0x400 0x24400 0x100>; | |
| reg-names = "iram", "control", "debug"; | |
| firmware-name = "am335x-pru1-fw"; | |
| interrupt-parent = <0x219>; | |
| interrupts = <0x12 0x13>; | |
| interrupt-names = "vring", "kick"; | |
| phandle = <0x221>; | |
| }; | |
| mdio@32400 { | |
| linux,phandle = <0x222>; | |
| compatible = "ti,davinci_mdio"; | |
| reg = <0x32400 0x90>; | |
| clocks = <0x13>; | |
| clock-names = "fck"; | |
| bus_freq = <0xf4240>; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| status = "disabled"; | |
| phandle = <0x222>; | |
| }; | |
| }; | |
| }; | |
| elm@48080000 { | |
| compatible = "ti,am3352-elm"; | |
| reg = <0x48080000 0x2000>; | |
| interrupts = <0x4>; | |
| ti,hwmods = "elm"; | |
| status = "disabled"; | |
| phandle = <0x20e>; | |
| }; | |
| lcdc@4830e000 { | |
| compatible = "ti,am33xx-tilcdc"; | |
| reg = <0x4830e000 0x1000>; | |
| interrupts = <0x24>; | |
| ti,hwmods = "lcdc"; | |
| status = "disabled"; | |
| phandle = <0x20f>; | |
| }; | |
| tscadc@44e0d000 { | |
| compatible = "ti,am3359-tscadc"; | |
| reg = <0x44e0d000 0x1000>; | |
| interrupts = <0x10>; | |
| ti,hwmods = "adc_tsc"; | |
| status = "okay"; | |
| dmas = <0x2d 0x35 0x0 0x2d 0x39 0x0>; | |
| dma-names = "fifo0", "fifo1"; | |
| phandle = <0x210>; | |
| tsc { | |
| compatible = "ti,am3359-tsc"; | |
| }; | |
| adc { | |
| #io-channel-cells = <0x1>; | |
| compatible = "ti,am3359-adc"; | |
| ti,adc-channels = <0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7>; | |
| ti,chan-step-avg = <0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16>; | |
| ti,chan-step-opendelay = <0x98 0x98 0x98 0x98 0x98 0x98 0x98 0x98>; | |
| ti,chan-step-sampledelay = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; | |
| phandle = <0x211>; | |
| }; | |
| }; | |
| gpmc@50000000 { | |
| compatible = "ti,am3352-gpmc"; | |
| ti,hwmods = "gpmc"; | |
| ti,no-idle-on-init; | |
| reg = <0x50000000 0x2000>; | |
| interrupts = <0x64>; | |
| dmas = <0x2d 0x34 0x0>; | |
| dma-names = "rxtx"; | |
| gpmc,num-cs = <0x7>; | |
| gpmc,num-waitpins = <0x2>; | |
| #address-cells = <0x2>; | |
| #size-cells = <0x1>; | |
| interrupt-controller; | |
| #interrupt-cells = <0x2>; | |
| gpio-controller; | |
| #gpio-cells = <0x2>; | |
| status = "disabled"; | |
| phandle = <0x212>; | |
| }; | |
| sham@53100000 { | |
| compatible = "ti,omap4-sham"; | |
| ti,hwmods = "sham"; | |
| reg = <0x53100000 0x200>; | |
| interrupts = <0x6d>; | |
| dmas = <0x2d 0x24 0x0>; | |
| dma-names = "rx"; | |
| status = "okay"; | |
| phandle = <0x213>; | |
| }; | |
| aes@53500000 { | |
| compatible = "ti,omap4-aes"; | |
| ti,hwmods = "aes"; | |
| reg = <0x53500000 0xa0>; | |
| interrupts = <0x67>; | |
| dmas = <0x2d 0x6 0x0 0x2d 0x5 0x0>; | |
| dma-names = "tx", "rx"; | |
| status = "okay"; | |
| phandle = <0x214>; | |
| }; | |
| mcasp@48038000 { | |
| compatible = "ti,am33xx-mcasp-audio"; | |
| ti,hwmods = "mcasp0"; | |
| reg = <0x48038000 0x2000 0x46000000 0x400000>; | |
| reg-names = "mpu", "dat"; | |
| interrupts = <0x50 0x51>; | |
| interrupt-names = "tx", "rx"; | |
| status = "disabled"; | |
| dmas = <0x2d 0x8 0x2 0x2d 0x9 0x2>; | |
| dma-names = "tx", "rx"; | |
| phandle = <0x215>; | |
| }; | |
| mcasp@4803C000 { | |
| compatible = "ti,am33xx-mcasp-audio"; | |
| ti,hwmods = "mcasp1"; | |
| reg = <0x4803c000 0x2000 0x46400000 0x400000>; | |
| reg-names = "mpu", "dat"; | |
| interrupts = <0x52 0x53>; | |
| interrupt-names = "tx", "rx"; | |
| status = "disabled"; | |
| dmas = <0x2d 0xa 0x2 0x2d 0xb 0x2>; | |
| dma-names = "tx", "rx"; | |
| phandle = <0x216>; | |
| }; | |
| rng@48310000 { | |
| compatible = "ti,omap4-rng"; | |
| ti,hwmods = "rng"; | |
| reg = <0x48310000 0x2000>; | |
| interrupts = <0x6f>; | |
| phandle = <0x217>; | |
| }; | |
| sgx@56000000 { | |
| compatible = "ti,am3352-sgx530", "img,sgx530"; | |
| ti,hwmods = "gfx"; | |
| reg = <0x56000000 0x10000>; | |
| interrupts = <0x25>; | |
| clocks = <0x42>; | |
| clock-names = "fclk"; | |
| status = "okay"; | |
| phandle = <0x218>; | |
| }; | |
| P1_02_pinmux { | |
| compatible = "bone-pinmux-helper"; | |
| status = "okay"; | |
| pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "pruout", "pruin"; | |
| pinctrl-0 = <0x43>; | |
| pinctrl-1 = <0x44>; | |
| pinctrl-2 = <0x45>; | |
| pinctrl-3 = <0x46>; | |
| pinctrl-4 = <0x47>; | |
| pinctrl-5 = <0x48>; | |
| pinctrl-6 = <0x49>; | |
| }; | |
| P1_04_pinmux { | |
| compatible = "bone-pinmux-helper"; | |
| status = "okay"; | |
| pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "pruout", "pruin"; | |
| pinctrl-0 = <0x4a>; | |
| pinctrl-1 = <0x4b>; | |
| pinctrl-2 = <0x4c>; | |
| pinctrl-3 = <0x4d>; | |
| pinctrl-4 = <0x4e>; | |
| pinctrl-5 = <0x4f>; | |
| pinctrl-6 = <0x50>; | |
| }; | |
| P1_06_pinmux { | |
| compatible = "bone-pinmux-helper"; | |
| status = "okay"; | |
| pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "spi_cs", "i2c", "pwm", "pru_uart"; | |
| pinctrl-0 = <0x51>; | |
| pinctrl-1 = <0x52>; | |
| pinctrl-2 = <0x53>; | |
| pinctrl-3 = <0x54>; | |
| pinctrl-4 = <0x55>; | |
| pinctrl-5 = <0x56>; | |
| pinctrl-6 = <0x57>; | |
| pinctrl-7 = <0x58>; | |
| pinctrl-8 = <0x59>; | |
| }; | |
| P1_08_pinmux { | |
| compatible = "bone-pinmux-helper"; | |
| status = "okay"; | |
| pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "spi_sclk", "uart", "i2c", "pwm", "pru_uart"; | |
| pinctrl-0 = <0x5a>; | |
| pinctrl-1 = <0x5b>; | |
| pinctrl-2 = <0x5c>; | |
| pinctrl-3 = <0x5d>; | |
| pinctrl-4 = <0x5e>; | |
| pinctrl-5 = <0x5f>; | |
| pinctrl-6 = <0x60>; | |
| pinctrl-7 = <0x61>; | |
| pinctrl-8 = <0x62>; | |
| pinctrl-9 = <0x63>; | |
| }; | |
| P1_10_pinmux { | |
| compatible = "bone-pinmux-helper"; | |
| status = "okay"; | |
| pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "spi", "uart", "i2c", "pwm", "pru_uart"; | |
| pinctrl-0 = <0x64>; | |
| pinctrl-1 = <0x65>; | |
| pinctrl-2 = <0x66>; | |
| pinctrl-3 = <0x67>; | |
| pinctrl-4 = <0x68>; | |
| pinctrl-5 = <0x69>; | |
| pinctrl-6 = <0x6a>; | |
| pinctrl-7 = <0x6b>; | |
| pinctrl-8 = <0x6c>; | |
| pinctrl-9 = <0x6d>; | |
| }; | |
| P1_12_pinmux { | |
| compatible = "bone-pinmux-helper"; | |
| status = "okay"; | |
| pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "spi", "i2c", "pwm", "pru_uart"; | |
| pinctrl-0 = <0x6e>; | |
| pinctrl-1 = <0x6f>; | |
| pinctrl-2 = <0x70>; | |
| pinctrl-3 = <0x71>; | |
| pinctrl-4 = <0x72>; | |
| pinctrl-5 = <0x73>; | |
| pinctrl-6 = <0x74>; | |
| pinctrl-7 = <0x75>; | |
| pinctrl-8 = <0x76>; | |
| }; | |
| P1_20_pinmux { | |
| compatible = "bone-pinmux-helper"; | |
| status = "okay"; | |
| pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "pruin"; | |
| pinctrl-0 = <0x77>; | |
| pinctrl-1 = <0x78>; | |
| pinctrl-2 = <0x79>; | |
| pinctrl-3 = <0x7a>; | |
| pinctrl-4 = <0x7b>; | |
| pinctrl-5 = <0x7c>; | |
| }; | |
| P1_26_pinmux { | |
| compatible = "bone-pinmux-helper"; | |
| status = "okay"; | |
| pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "spi_cs", "can", "i2c", "pru_uart"; | |
| pinctrl-0 = <0x7d>; | |
| pinctrl-1 = <0x7e>; | |
| pinctrl-2 = <0x7f>; | |
| pinctrl-3 = <0x80>; | |
| pinctrl-4 = <0x81>; | |
| pinctrl-5 = <0x82>; | |
| pinctrl-6 = <0x83>; | |
| pinctrl-7 = <0x84>; | |
| pinctrl-8 = <0x85>; | |
| }; | |
| P1_28_pinmux { | |
| compatible = "bone-pinmux-helper"; | |
| status = "okay"; | |
| pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "spi_cs", "can", "i2c", "pru_uart"; | |
| pinctrl-0 = <0x86>; | |
| pinctrl-1 = <0x87>; | |
| pinctrl-2 = <0x88>; | |
| pinctrl-3 = <0x89>; | |
| pinctrl-4 = <0x8a>; | |
| pinctrl-5 = <0x8b>; | |
| pinctrl-6 = <0x8c>; | |
| pinctrl-7 = <0x8d>; | |
| pinctrl-8 = <0x8e>; | |
| }; | |
| P1_29_pinmux { | |
| compatible = "bone-pinmux-helper"; | |
| status = "okay"; | |
| pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "qep", "pruout", "pruin"; | |
| pinctrl-0 = <0x8f>; | |
| pinctrl-1 = <0x90>; | |
| pinctrl-2 = <0x91>; | |
| pinctrl-3 = <0x92>; | |
| pinctrl-4 = <0x93>; | |
| pinctrl-5 = <0x94>; | |
| pinctrl-6 = <0x95>; | |
| pinctrl-7 = <0x96>; | |
| }; | |
| P1_30_pinmux { | |
| compatible = "bone-pinmux-helper"; | |
| status = "okay"; | |
| pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "spi_cs", "uart", "can", "i2c", "pruout", "pruin"; | |
| pinctrl-0 = <0x97>; | |
| pinctrl-1 = <0x98>; | |
| pinctrl-2 = <0x99>; | |
| pinctrl-3 = <0x9a>; | |
| pinctrl-4 = <0x9b>; | |
| pinctrl-5 = <0x9c>; | |
| pinctrl-6 = <0x9d>; | |
| pinctrl-7 = <0x9e>; | |
| pinctrl-8 = <0x9f>; | |
| pinctrl-9 = <0xa0>; | |
| pinctrl-10 = <0xa1>; | |
| }; | |
| P1_31_pinmux { | |
| compatible = "bone-pinmux-helper"; | |
| status = "okay"; | |
| pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "qep", "pruout", "pruin"; | |
| pinctrl-0 = <0xa2>; | |
| pinctrl-1 = <0xa3>; | |
| pinctrl-2 = <0xa4>; | |
| pinctrl-3 = <0xa5>; | |
| pinctrl-4 = <0xa6>; | |
| pinctrl-5 = <0xa7>; | |
| pinctrl-6 = <0xa8>; | |
| pinctrl-7 = <0xa9>; | |
| }; | |
| P1_32_pinmux { | |
| compatible = "bone-pinmux-helper"; | |
| status = "okay"; | |
| pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "spi_cs", "uart", "can", "i2c", "pruout", "pruin"; | |
| pinctrl-0 = <0xaa>; | |
| pinctrl-1 = <0xab>; | |
| pinctrl-2 = <0xac>; | |
| pinctrl-3 = <0xad>; | |
| pinctrl-4 = <0xae>; | |
| pinctrl-5 = <0xaf>; | |
| pinctrl-6 = <0xb0>; | |
| pinctrl-7 = <0xb1>; | |
| pinctrl-8 = <0xb2>; | |
| pinctrl-9 = <0xb3>; | |
| pinctrl-10 = <0xb4>; | |
| }; | |
| P1_33_pinmux { | |
| compatible = "bone-pinmux-helper"; | |
| status = "okay"; | |
| pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "spi", "pwm", "pruout", "pruin"; | |
| pinctrl-0 = <0xb5>; | |
| pinctrl-1 = <0xb6>; | |
| pinctrl-2 = <0xb7>; | |
| pinctrl-3 = <0xb8>; | |
| pinctrl-4 = <0xb9>; | |
| pinctrl-5 = <0xba>; | |
| pinctrl-6 = <0xbb>; | |
| pinctrl-7 = <0xbc>; | |
| pinctrl-8 = <0xbd>; | |
| }; | |
| P1_34_pinmux { | |
| compatible = "bone-pinmux-helper"; | |
| status = "okay"; | |
| pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "pwm"; | |
| pinctrl-0 = <0xbe>; | |
| pinctrl-1 = <0xbf>; | |
| pinctrl-2 = <0xc0>; | |
| pinctrl-3 = <0xc1>; | |
| pinctrl-4 = <0xc2>; | |
| pinctrl-5 = <0xc3>; | |
| }; | |
| P1_35_pinmux { | |
| compatible = "bone-pinmux-helper"; | |
| status = "okay"; | |
| pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "pruout", "pruin"; | |
| pinctrl-0 = <0xc4>; | |
| pinctrl-1 = <0xc5>; | |
| pinctrl-2 = <0xc6>; | |
| pinctrl-3 = <0xc7>; | |
| pinctrl-4 = <0xc8>; | |
| pinctrl-5 = <0xc9>; | |
| pinctrl-6 = <0xca>; | |
| }; | |
| P1_36_pinmux { | |
| compatible = "bone-pinmux-helper"; | |
| status = "okay"; | |
| pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "spi_sclk", "pwm", "pruout", "pruin"; | |
| pinctrl-0 = <0xcb>; | |
| pinctrl-1 = <0xcc>; | |
| pinctrl-2 = <0xcd>; | |
| pinctrl-3 = <0xce>; | |
| pinctrl-4 = <0xcf>; | |
| pinctrl-5 = <0xd0>; | |
| pinctrl-6 = <0xd1>; | |
| pinctrl-7 = <0xd2>; | |
| pinctrl-8 = <0xd3>; | |
| }; | |
| P2_01_pinmux { | |
| compatible = "bone-pinmux-helper"; | |
| status = "okay"; | |
| pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "pwm"; | |
| pinctrl-0 = <0xd4>; | |
| pinctrl-1 = <0xd5>; | |
| pinctrl-2 = <0xd6>; | |
| pinctrl-3 = <0xd7>; | |
| pinctrl-4 = <0xd8>; | |
| pinctrl-5 = <0xd9>; | |
| }; | |
| P2_02_pinmux { | |
| compatible = "bone-pinmux-helper"; | |
| status = "okay"; | |
| pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input"; | |
| pinctrl-0 = <0xda>; | |
| pinctrl-1 = <0xdb>; | |
| pinctrl-2 = <0xdc>; | |
| pinctrl-3 = <0xdd>; | |
| pinctrl-4 = <0xde>; | |
| }; | |
| P2_03_pinmux { | |
| compatible = "bone-pinmux-helper"; | |
| status = "okay"; | |
| pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "pwm"; | |
| pinctrl-0 = <0xdf>; | |
| pinctrl-1 = <0xe0>; | |
| pinctrl-2 = <0xe1>; | |
| pinctrl-3 = <0xe2>; | |
| pinctrl-4 = <0xe3>; | |
| pinctrl-5 = <0xe4>; | |
| }; | |
| P2_04_pinmux { | |
| compatible = "bone-pinmux-helper"; | |
| status = "okay"; | |
| pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input"; | |
| pinctrl-0 = <0xe5>; | |
| pinctrl-1 = <0xe6>; | |
| pinctrl-2 = <0xe7>; | |
| pinctrl-3 = <0xe8>; | |
| pinctrl-4 = <0xe9>; | |
| }; | |
| P2_05_pinmux { | |
| compatible = "bone-pinmux-helper"; | |
| status = "okay"; | |
| pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "uart"; | |
| pinctrl-0 = <0xea>; | |
| pinctrl-1 = <0xeb>; | |
| pinctrl-2 = <0xec>; | |
| pinctrl-3 = <0xed>; | |
| pinctrl-4 = <0xee>; | |
| pinctrl-5 = <0xef>; | |
| }; | |
| P2_06_pinmux { | |
| compatible = "bone-pinmux-helper"; | |
| status = "okay"; | |
| pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input"; | |
| pinctrl-0 = <0xf0>; | |
| pinctrl-1 = <0xf1>; | |
| pinctrl-2 = <0xf2>; | |
| pinctrl-3 = <0xf3>; | |
| pinctrl-4 = <0xf4>; | |
| }; | |
| P2_07_pinmux { | |
| compatible = "bone-pinmux-helper"; | |
| status = "okay"; | |
| pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "uart"; | |
| pinctrl-0 = <0xf5>; | |
| pinctrl-1 = <0xf6>; | |
| pinctrl-2 = <0xf7>; | |
| pinctrl-3 = <0xf8>; | |
| pinctrl-4 = <0xf9>; | |
| pinctrl-5 = <0xfa>; | |
| }; | |
| P2_08_pinmux { | |
| compatible = "bone-pinmux-helper"; | |
| status = "okay"; | |
| pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input"; | |
| pinctrl-0 = <0xfb>; | |
| pinctrl-1 = <0xfc>; | |
| pinctrl-2 = <0xfd>; | |
| pinctrl-3 = <0xfe>; | |
| pinctrl-4 = <0xff>; | |
| }; | |
| P2_09_pinmux { | |
| compatible = "bone-pinmux-helper"; | |
| status = "okay"; | |
| pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "uart", "can", "i2c", "pru_uart", "pruin"; | |
| pinctrl-0 = <0x100>; | |
| pinctrl-1 = <0x101>; | |
| pinctrl-2 = <0x102>; | |
| pinctrl-3 = <0x103>; | |
| pinctrl-4 = <0x104>; | |
| pinctrl-5 = <0x105>; | |
| pinctrl-6 = <0x106>; | |
| pinctrl-7 = <0x107>; | |
| pinctrl-8 = <0x108>; | |
| pinctrl-9 = <0x109>; | |
| }; | |
| P2_10_pinmux { | |
| compatible = "bone-pinmux-helper"; | |
| status = "okay"; | |
| pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "qep"; | |
| pinctrl-0 = <0x10a>; | |
| pinctrl-1 = <0x10b>; | |
| pinctrl-2 = <0x10c>; | |
| pinctrl-3 = <0x10d>; | |
| pinctrl-4 = <0x10e>; | |
| pinctrl-5 = <0x10f>; | |
| }; | |
| P2_11_pinmux { | |
| compatible = "bone-pinmux-helper"; | |
| status = "okay"; | |
| pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "uart", "can", "i2c", "pru_uart", "pruin"; | |
| pinctrl-0 = <0x110>; | |
| pinctrl-1 = <0x111>; | |
| pinctrl-2 = <0x112>; | |
| pinctrl-3 = <0x113>; | |
| pinctrl-4 = <0x114>; | |
| pinctrl-5 = <0x115>; | |
| pinctrl-6 = <0x116>; | |
| pinctrl-7 = <0x117>; | |
| pinctrl-8 = <0x118>; | |
| pinctrl-9 = <0x119>; | |
| }; | |
| P2_17_pinmux { | |
| compatible = "bone-pinmux-helper"; | |
| status = "okay"; | |
| pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input"; | |
| pinctrl-0 = <0x11a>; | |
| pinctrl-1 = <0x11b>; | |
| pinctrl-2 = <0x11c>; | |
| pinctrl-3 = <0x11d>; | |
| pinctrl-4 = <0x11e>; | |
| }; | |
| P2_18_pinmux { | |
| compatible = "bone-pinmux-helper"; | |
| status = "okay"; | |
| pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "qep", "pru_ecap", "pruin"; | |
| pinctrl-0 = <0x11f>; | |
| pinctrl-1 = <0x120>; | |
| pinctrl-2 = <0x121>; | |
| pinctrl-3 = <0x122>; | |
| pinctrl-4 = <0x123>; | |
| pinctrl-5 = <0x124>; | |
| pinctrl-6 = <0x125>; | |
| pinctrl-7 = <0x126>; | |
| }; | |
| P2_19_pinmux { | |
| compatible = "bone-pinmux-helper"; | |
| status = "okay"; | |
| pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "pwm"; | |
| pinctrl-0 = <0x127>; | |
| pinctrl-1 = <0x128>; | |
| pinctrl-2 = <0x129>; | |
| pinctrl-3 = <0x12a>; | |
| pinctrl-4 = <0x12b>; | |
| pinctrl-5 = <0x12c>; | |
| }; | |
| P2_20_pinmux { | |
| compatible = "bone-pinmux-helper"; | |
| status = "okay"; | |
| pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input"; | |
| pinctrl-0 = <0x12d>; | |
| pinctrl-1 = <0x12e>; | |
| pinctrl-2 = <0x12f>; | |
| pinctrl-3 = <0x130>; | |
| pinctrl-4 = <0x131>; | |
| }; | |
| P2_22_pinmux { | |
| compatible = "bone-pinmux-helper"; | |
| status = "okay"; | |
| pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "qep", "pruin"; | |
| pinctrl-0 = <0x132>; | |
| pinctrl-1 = <0x133>; | |
| pinctrl-2 = <0x134>; | |
| pinctrl-3 = <0x135>; | |
| pinctrl-4 = <0x136>; | |
| pinctrl-5 = <0x137>; | |
| pinctrl-6 = <0x138>; | |
| }; | |
| P2_24_pinmux { | |
| compatible = "bone-pinmux-helper"; | |
| status = "okay"; | |
| pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "qep", "pruout"; | |
| pinctrl-0 = <0x139>; | |
| pinctrl-1 = <0x13a>; | |
| pinctrl-2 = <0x13b>; | |
| pinctrl-3 = <0x13c>; | |
| pinctrl-4 = <0x13d>; | |
| pinctrl-5 = <0x13e>; | |
| pinctrl-6 = <0x13f>; | |
| }; | |
| P2_25_pinmux { | |
| compatible = "bone-pinmux-helper"; | |
| status = "okay"; | |
| pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "spi", "spi_cs", "uart", "can", "i2c"; | |
| pinctrl-0 = <0x140>; | |
| pinctrl-1 = <0x141>; | |
| pinctrl-2 = <0x142>; | |
| pinctrl-3 = <0x143>; | |
| pinctrl-4 = <0x144>; | |
| pinctrl-5 = <0x145>; | |
| pinctrl-6 = <0x146>; | |
| pinctrl-7 = <0x147>; | |
| pinctrl-8 = <0x148>; | |
| pinctrl-9 = <0x149>; | |
| }; | |
| P2_27_pinmux { | |
| compatible = "bone-pinmux-helper"; | |
| status = "okay"; | |
| pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "spi", "uart", "can", "i2c"; | |
| pinctrl-0 = <0x14a>; | |
| pinctrl-1 = <0x14b>; | |
| pinctrl-2 = <0x14c>; | |
| pinctrl-3 = <0x14d>; | |
| pinctrl-4 = <0x14e>; | |
| pinctrl-5 = <0x14f>; | |
| pinctrl-6 = <0x150>; | |
| pinctrl-7 = <0x151>; | |
| pinctrl-8 = <0x152>; | |
| }; | |
| P2_28_pinmux { | |
| compatible = "bone-pinmux-helper"; | |
| status = "okay"; | |
| pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "qep", "pruout", "pruin"; | |
| pinctrl-0 = <0x153>; | |
| pinctrl-1 = <0x154>; | |
| pinctrl-2 = <0x155>; | |
| pinctrl-3 = <0x156>; | |
| pinctrl-4 = <0x157>; | |
| pinctrl-5 = <0x158>; | |
| pinctrl-6 = <0x159>; | |
| pinctrl-7 = <0x15a>; | |
| }; | |
| P2_29_pinmux { | |
| compatible = "bone-pinmux-helper"; | |
| status = "okay"; | |
| pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "spi_cs", "spi_sclk", "uart", "pwm", "pru_ecap"; | |
| pinctrl-0 = <0x15b>; | |
| pinctrl-1 = <0x15c>; | |
| pinctrl-2 = <0x15d>; | |
| pinctrl-3 = <0x15e>; | |
| pinctrl-4 = <0x15f>; | |
| pinctrl-5 = <0x160>; | |
| pinctrl-6 = <0x161>; | |
| pinctrl-7 = <0x162>; | |
| pinctrl-8 = <0x163>; | |
| pinctrl-9 = <0x164>; | |
| }; | |
| P2_30_pinmux { | |
| compatible = "bone-pinmux-helper"; | |
| status = "okay"; | |
| pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "spi_cs", "pwm", "pruout", "pruin"; | |
| pinctrl-0 = <0x165>; | |
| pinctrl-1 = <0x166>; | |
| pinctrl-2 = <0x167>; | |
| pinctrl-3 = <0x168>; | |
| pinctrl-4 = <0x169>; | |
| pinctrl-5 = <0x16a>; | |
| pinctrl-6 = <0x16b>; | |
| pinctrl-7 = <0x16c>; | |
| pinctrl-8 = <0x16d>; | |
| }; | |
| P2_31_pinmux { | |
| compatible = "bone-pinmux-helper"; | |
| status = "okay"; | |
| pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "spi_cs", "pruin"; | |
| pinctrl-0 = <0x16e>; | |
| pinctrl-1 = <0x16f>; | |
| pinctrl-2 = <0x170>; | |
| pinctrl-3 = <0x171>; | |
| pinctrl-4 = <0x172>; | |
| pinctrl-5 = <0x173>; | |
| pinctrl-6 = <0x174>; | |
| }; | |
| P2_32_pinmux { | |
| compatible = "bone-pinmux-helper"; | |
| status = "okay"; | |
| pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "spi", "pwm", "pruout", "pruin"; | |
| pinctrl-0 = <0x175>; | |
| pinctrl-1 = <0x176>; | |
| pinctrl-2 = <0x177>; | |
| pinctrl-3 = <0x178>; | |
| pinctrl-4 = <0x179>; | |
| pinctrl-5 = <0x17a>; | |
| pinctrl-6 = <0x17b>; | |
| pinctrl-7 = <0x17c>; | |
| pinctrl-8 = <0x17d>; | |
| }; | |
| P2_33_pinmux { | |
| compatible = "bone-pinmux-helper"; | |
| status = "okay"; | |
| pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "qep", "pruout"; | |
| pinctrl-0 = <0x17e>; | |
| pinctrl-1 = <0x17f>; | |
| pinctrl-2 = <0x180>; | |
| pinctrl-3 = <0x181>; | |
| pinctrl-4 = <0x182>; | |
| pinctrl-5 = <0x183>; | |
| pinctrl-6 = <0x184>; | |
| }; | |
| P2_34_pinmux { | |
| compatible = "bone-pinmux-helper"; | |
| status = "okay"; | |
| pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "qep", "pruout", "pruin"; | |
| pinctrl-0 = <0x185>; | |
| pinctrl-1 = <0x186>; | |
| pinctrl-2 = <0x187>; | |
| pinctrl-3 = <0x188>; | |
| pinctrl-4 = <0x189>; | |
| pinctrl-5 = <0x18a>; | |
| pinctrl-6 = <0x18b>; | |
| pinctrl-7 = <0x18c>; | |
| }; | |
| P2_35_pinmux { | |
| compatible = "bone-pinmux-helper"; | |
| status = "okay"; | |
| pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "pruout", "pruin"; | |
| pinctrl-0 = <0x18d>; | |
| pinctrl-1 = <0x18e>; | |
| pinctrl-2 = <0x18f>; | |
| pinctrl-3 = <0x190>; | |
| pinctrl-4 = <0x191>; | |
| pinctrl-5 = <0x192>; | |
| pinctrl-6 = <0x193>; | |
| }; | |
| cape-universal { | |
| compatible = "gpio-of-helper"; | |
| status = "okay"; | |
| pinctrl-names = "default"; | |
| pinctrl-0; | |
| P1_02 { | |
| gpio-name = "P1_02"; | |
| gpio = <0x194 0x17 0x0>; | |
| input; | |
| dir-changeable; | |
| }; | |
| P1_04 { | |
| gpio-name = "P1_04"; | |
| gpio = <0x194 0x19 0x0>; | |
| input; | |
| dir-changeable; | |
| }; | |
| P1_06 { | |
| gpio-name = "P1_06"; | |
| gpio = <0x35 0x5 0x0>; | |
| input; | |
| dir-changeable; | |
| }; | |
| P1_08 { | |
| gpio-name = "P1_08"; | |
| gpio = <0x35 0x2 0x0>; | |
| input; | |
| dir-changeable; | |
| }; | |
| P1_10 { | |
| gpio-name = "P1_10"; | |
| gpio = <0x35 0x3 0x0>; | |
| input; | |
| dir-changeable; | |
| }; | |
| P1_12 { | |
| gpio-name = "P1_12"; | |
| gpio = <0x35 0x4 0x0>; | |
| input; | |
| dir-changeable; | |
| }; | |
| P1_20 { | |
| gpio-name = "P1_20"; | |
| gpio = <0x35 0x14 0x0>; | |
| input; | |
| dir-changeable; | |
| }; | |
| P1_26 { | |
| gpio-name = "P1_26"; | |
| gpio = <0x35 0xc 0x0>; | |
| input; | |
| dir-changeable; | |
| }; | |
| P1_28 { | |
| gpio-name = "P1_28"; | |
| gpio = <0x35 0xd 0x0>; | |
| input; | |
| dir-changeable; | |
| }; | |
| P1_29 { | |
| gpio-name = "P1_29"; | |
| gpio = <0x195 0x15 0x0>; | |
| input; | |
| dir-changeable; | |
| }; | |
| P1_30 { | |
| gpio-name = "P1_30"; | |
| gpio = <0x196 0xb 0x0>; | |
| input; | |
| dir-changeable; | |
| }; | |
| P1_31 { | |
| gpio-name = "P1_31"; | |
| gpio = <0x195 0x12 0x0>; | |
| input; | |
| dir-changeable; | |
| }; | |
| P1_32 { | |
| gpio-name = "P1_32"; | |
| gpio = <0x196 0xa 0x0>; | |
| input; | |
| dir-changeable; | |
| }; | |
| P1_33 { | |
| gpio-name = "P1_33"; | |
| gpio = <0x195 0xf 0x0>; | |
| input; | |
| dir-changeable; | |
| }; | |
| P1_34 { | |
| gpio-name = "P1_34"; | |
| gpio = <0x35 0x1a 0x0>; | |
| input; | |
| dir-changeable; | |
| }; | |
| P1_35 { | |
| gpio-name = "P1_35"; | |
| gpio = <0x194 0x18 0x0>; | |
| input; | |
| dir-changeable; | |
| }; | |
| P1_36 { | |
| gpio-name = "P1_36"; | |
| gpio = <0x195 0xe 0x0>; | |
| input; | |
| dir-changeable; | |
| }; | |
| P2_01 { | |
| gpio-name = "P2_01"; | |
| gpio = <0x196 0x12 0x0>; | |
| input; | |
| dir-changeable; | |
| }; | |
| P2_02 { | |
| gpio-name = "P2_02"; | |
| gpio = <0x196 0x1b 0x0>; | |
| input; | |
| dir-changeable; | |
| }; | |
| P2_03 { | |
| gpio-name = "P2_03"; | |
| gpio = <0x35 0x17 0x0>; | |
| input; | |
| dir-changeable; | |
| }; | |
| P2_04 { | |
| gpio-name = "P2_04"; | |
| gpio = <0x196 0x1a 0x0>; | |
| input; | |
| dir-changeable; | |
| }; | |
| P2_05 { | |
| gpio-name = "P2_05"; | |
| gpio = <0x35 0x1e 0x0>; | |
| input; | |
| dir-changeable; | |
| }; | |
| P2_06 { | |
| gpio-name = "P2_06"; | |
| gpio = <0x196 0x19 0x0>; | |
| input; | |
| dir-changeable; | |
| }; | |
| P2_07 { | |
| gpio-name = "P2_07"; | |
| gpio = <0x35 0x1f 0x0>; | |
| input; | |
| dir-changeable; | |
| }; | |
| P2_08 { | |
| gpio-name = "P2_08"; | |
| gpio = <0x196 0x1c 0x0>; | |
| input; | |
| dir-changeable; | |
| }; | |
| P2_09 { | |
| gpio-name = "P2_09"; | |
| gpio = <0x35 0xf 0x0>; | |
| input; | |
| dir-changeable; | |
| }; | |
| P2_10 { | |
| gpio-name = "P2_10"; | |
| gpio = <0x196 0x14 0x0>; | |
| input; | |
| dir-changeable; | |
| }; | |
| P2_11 { | |
| gpio-name = "P2_11"; | |
| gpio = <0x35 0xe 0x0>; | |
| input; | |
| dir-changeable; | |
| }; | |
| P2_17 { | |
| gpio-name = "P2_17"; | |
| gpio = <0x194 0x1 0x0>; | |
| input; | |
| dir-changeable; | |
| }; | |
| P2_18 { | |
| gpio-name = "P2_18"; | |
| gpio = <0x196 0xf 0x0>; | |
| input; | |
| dir-changeable; | |
| }; | |
| P2_19 { | |
| gpio-name = "P2_19"; | |
| gpio = <0x35 0x1b 0x0>; | |
| input; | |
| dir-changeable; | |
| }; | |
| P2_20 { | |
| gpio-name = "P2_20"; | |
| gpio = <0x194 0x0 0x0>; | |
| input; | |
| dir-changeable; | |
| }; | |
| P2_22 { | |
| gpio-name = "P2_22"; | |
| gpio = <0x196 0xe 0x0>; | |
| input; | |
| dir-changeable; | |
| }; | |
| P2_24 { | |
| gpio-name = "P2_24"; | |
| gpio = <0x196 0xc 0x0>; | |
| input; | |
| dir-changeable; | |
| }; | |
| P2_25 { | |
| gpio-name = "P2_25"; | |
| gpio = <0x196 0x9 0x0>; | |
| input; | |
| dir-changeable; | |
| }; | |
| P2_27 { | |
| gpio-name = "P2_27"; | |
| gpio = <0x196 0x8 0x0>; | |
| input; | |
| dir-changeable; | |
| }; | |
| P2_28 { | |
| gpio-name = "P2_28"; | |
| gpio = <0x195 0x14 0x0>; | |
| input; | |
| dir-changeable; | |
| }; | |
| P2_29 { | |
| gpio-name = "P2_29"; | |
| gpio = <0x35 0x7 0x0>; | |
| input; | |
| dir-changeable; | |
| }; | |
| P2_30 { | |
| gpio-name = "P2_30"; | |
| gpio = <0x195 0x11 0x0>; | |
| input; | |
| dir-changeable; | |
| }; | |
| P2_31 { | |
| gpio-name = "P2_31"; | |
| gpio = <0x35 0x13 0x0>; | |
| input; | |
| dir-changeable; | |
| }; | |
| P2_32 { | |
| gpio-name = "P2_32"; | |
| gpio = <0x195 0x10 0x0>; | |
| input; | |
| dir-changeable; | |
| }; | |
| P2_33 { | |
| gpio-name = "P2_33"; | |
| gpio = <0x196 0xd 0x0>; | |
| input; | |
| dir-changeable; | |
| }; | |
| P2_34 { | |
| gpio-name = "P2_34"; | |
| gpio = <0x195 0x13 0x0>; | |
| input; | |
| dir-changeable; | |
| }; | |
| P2_35 { | |
| gpio-name = "P2_35"; | |
| gpio = <0x194 0x16 0x0>; | |
| input; | |
| dir-changeable; | |
| }; | |
| }; | |
| }; | |
| memory@80000000 { | |
| device_type = "memory"; | |
| reg = <0x80000000 0x20000000>; | |
| }; | |
| leds { | |
| pinctrl-names = "default", "sleep"; | |
| pinctrl-0 = <0x197>; | |
| pinctrl-1 = <0x198>; | |
| compatible = "gpio-leds"; | |
| led@2 { | |
| label = "beaglebone:green:usr0"; | |
| gpios = <0x196 0x15 0x0>; | |
| linux,default-trigger = "heartbeat"; | |
| default-state = "off"; | |
| }; | |
| led@3 { | |
| label = "beaglebone:green:usr1"; | |
| gpios = <0x196 0x16 0x0>; | |
| linux,default-trigger = "mmc0"; | |
| default-state = "off"; | |
| }; | |
| led@4 { | |
| label = "beaglebone:green:usr2"; | |
| gpios = <0x196 0x17 0x0>; | |
| linux,default-trigger = "cpu0"; | |
| default-state = "off"; | |
| }; | |
| led@5 { | |
| label = "beaglebone:green:usr3"; | |
| gpios = <0x196 0x18 0x0>; | |
| linux,default-trigger = "mmc1"; | |
| default-state = "off"; | |
| }; | |
| }; | |
| fixedregulator0 { | |
| compatible = "regulator-fixed"; | |
| regulator-name = "vmmcsd_fixed"; | |
| regulator-min-microvolt = <0x325aa0>; | |
| regulator-max-microvolt = <0x325aa0>; | |
| phandle = <0x33>; | |
| }; | |
| __symbols__ { | |
| aliases = "/aliases"; | |
| mpu_gate = "/cpus/idle-states/mpu_gate"; | |
| cpu0_opp_table = "/opp-table"; | |
| ocp = "/ocp"; | |
| l4_wkup = "/ocp/l4_wkup@44c00000"; | |
| wkup_m3 = "/ocp/l4_wkup@44c00000/wkup_m3@100000"; | |
| prcm = "/ocp/l4_wkup@44c00000/prcm@200000"; | |
| prcm_clocks = "/ocp/l4_wkup@44c00000/prcm@200000/clocks"; | |
| clk_32768_ck = "/ocp/l4_wkup@44c00000/prcm@200000/clocks/clk_32768_ck"; | |
| clk_rc32k_ck = "/ocp/l4_wkup@44c00000/prcm@200000/clocks/clk_rc32k_ck"; | |
| virt_19200000_ck = "/ocp/l4_wkup@44c00000/prcm@200000/clocks/virt_19200000_ck"; | |
| virt_24000000_ck = "/ocp/l4_wkup@44c00000/prcm@200000/clocks/virt_24000000_ck"; | |
| virt_25000000_ck = "/ocp/l4_wkup@44c00000/prcm@200000/clocks/virt_25000000_ck"; | |
| virt_26000000_ck = "/ocp/l4_wkup@44c00000/prcm@200000/clocks/virt_26000000_ck"; | |
| tclkin_ck = "/ocp/l4_wkup@44c00000/prcm@200000/clocks/tclkin_ck"; | |
| dpll_core_ck = "/ocp/l4_wkup@44c00000/prcm@200000/clocks/dpll_core_ck@490"; | |
| dpll_core_x2_ck = "/ocp/l4_wkup@44c00000/prcm@200000/clocks/dpll_core_x2_ck"; | |
| dpll_core_m4_ck = "/ocp/l4_wkup@44c00000/prcm@200000/clocks/dpll_core_m4_ck@480"; | |
| dpll_core_m5_ck = "/ocp/l4_wkup@44c00000/prcm@200000/clocks/dpll_core_m5_ck@484"; | |
| dpll_core_m6_ck = "/ocp/l4_wkup@44c00000/prcm@200000/clocks/dpll_core_m6_ck@4d8"; | |
| dpll_mpu_ck = "/ocp/l4_wkup@44c00000/prcm@200000/clocks/dpll_mpu_ck@488"; | |
| dpll_mpu_m2_ck = "/ocp/l4_wkup@44c00000/prcm@200000/clocks/dpll_mpu_m2_ck@4a8"; | |
| dpll_ddr_ck = "/ocp/l4_wkup@44c00000/prcm@200000/clocks/dpll_ddr_ck@494"; | |
| dpll_ddr_m2_ck = "/ocp/l4_wkup@44c00000/prcm@200000/clocks/dpll_ddr_m2_ck@4a0"; | |
| dpll_ddr_m2_div2_ck = "/ocp/l4_wkup@44c00000/prcm@200000/clocks/dpll_ddr_m2_div2_ck"; | |
| dpll_disp_ck = "/ocp/l4_wkup@44c00000/prcm@200000/clocks/dpll_disp_ck@498"; | |
| dpll_disp_m2_ck = "/ocp/l4_wkup@44c00000/prcm@200000/clocks/dpll_disp_m2_ck@4a4"; | |
| dpll_per_ck = "/ocp/l4_wkup@44c00000/prcm@200000/clocks/dpll_per_ck@48c"; | |
| dpll_per_m2_ck = "/ocp/l4_wkup@44c00000/prcm@200000/clocks/dpll_per_m2_ck@4ac"; | |
| dpll_per_m2_div4_wkupdm_ck = "/ocp/l4_wkup@44c00000/prcm@200000/clocks/dpll_per_m2_div4_wkupdm_ck"; | |
| dpll_per_m2_div4_ck = "/ocp/l4_wkup@44c00000/prcm@200000/clocks/dpll_per_m2_div4_ck"; | |
| cefuse_fck = "/ocp/l4_wkup@44c00000/prcm@200000/clocks/cefuse_fck@a20"; | |
| clk_24mhz = "/ocp/l4_wkup@44c00000/prcm@200000/clocks/clk_24mhz"; | |
| clkdiv32k_ck = "/ocp/l4_wkup@44c00000/prcm@200000/clocks/clkdiv32k_ck"; | |
| clkdiv32k_ick = "/ocp/l4_wkup@44c00000/prcm@200000/clocks/clkdiv32k_ick@14c"; | |
| l3_gclk = "/ocp/l4_wkup@44c00000/prcm@200000/clocks/l3_gclk"; | |
| pruss_ocp_gclk = "/ocp/l4_wkup@44c00000/prcm@200000/clocks/pruss_ocp_gclk@530"; | |
| mmu_fck = "/ocp/l4_wkup@44c00000/prcm@200000/clocks/mmu_fck@914"; | |
| timer1_fck = "/ocp/l4_wkup@44c00000/prcm@200000/clocks/timer1_fck@528"; | |
| timer2_fck = "/ocp/l4_wkup@44c00000/prcm@200000/clocks/timer2_fck@508"; | |
| timer3_fck = "/ocp/l4_wkup@44c00000/prcm@200000/clocks/timer3_fck@50c"; | |
| timer4_fck = "/ocp/l4_wkup@44c00000/prcm@200000/clocks/timer4_fck@510"; | |
| timer5_fck = "/ocp/l4_wkup@44c00000/prcm@200000/clocks/timer5_fck@518"; | |
| timer6_fck = "/ocp/l4_wkup@44c00000/prcm@200000/clocks/timer6_fck@51c"; | |
| timer7_fck = "/ocp/l4_wkup@44c00000/prcm@200000/clocks/timer7_fck@504"; | |
| usbotg_fck = "/ocp/l4_wkup@44c00000/prcm@200000/clocks/usbotg_fck@47c"; | |
| dpll_core_m4_div2_ck = "/ocp/l4_wkup@44c00000/prcm@200000/clocks/dpll_core_m4_div2_ck"; | |
| ieee5000_fck = "/ocp/l4_wkup@44c00000/prcm@200000/clocks/ieee5000_fck@e4"; | |
| wdt1_fck = "/ocp/l4_wkup@44c00000/prcm@200000/clocks/wdt1_fck@538"; | |
| l4_rtc_gclk = "/ocp/l4_wkup@44c00000/prcm@200000/clocks/l4_rtc_gclk"; | |
| l4hs_gclk = "/ocp/l4_wkup@44c00000/prcm@200000/clocks/l4hs_gclk"; | |
| l3s_gclk = "/ocp/l4_wkup@44c00000/prcm@200000/clocks/l3s_gclk"; | |
| l4fw_gclk = "/ocp/l4_wkup@44c00000/prcm@200000/clocks/l4fw_gclk"; | |
| l4ls_gclk = "/ocp/l4_wkup@44c00000/prcm@200000/clocks/l4ls_gclk"; | |
| sysclk_div_ck = "/ocp/l4_wkup@44c00000/prcm@200000/clocks/sysclk_div_ck"; | |
| cpsw_125mhz_gclk = "/ocp/l4_wkup@44c00000/prcm@200000/clocks/cpsw_125mhz_gclk"; | |
| cpsw_cpts_rft_clk = "/ocp/l4_wkup@44c00000/prcm@200000/clocks/cpsw_cpts_rft_clk@520"; | |
| gpio0_dbclk_mux_ck = "/ocp/l4_wkup@44c00000/prcm@200000/clocks/gpio0_dbclk_mux_ck@53c"; | |
| gpio0_dbclk = "/ocp/l4_wkup@44c00000/prcm@200000/clocks/gpio0_dbclk@408"; | |
| gpio1_dbclk = "/ocp/l4_wkup@44c00000/prcm@200000/clocks/gpio1_dbclk@ac"; | |
| gpio2_dbclk = "/ocp/l4_wkup@44c00000/prcm@200000/clocks/gpio2_dbclk@b0"; | |
| gpio3_dbclk = "/ocp/l4_wkup@44c00000/prcm@200000/clocks/gpio3_dbclk@b4"; | |
| lcd_gclk = "/ocp/l4_wkup@44c00000/prcm@200000/clocks/lcd_gclk@534"; | |
| mmc_clk = "/ocp/l4_wkup@44c00000/prcm@200000/clocks/mmc_clk"; | |
| gfx_fclk_clksel_ck = "/ocp/l4_wkup@44c00000/prcm@200000/clocks/gfx_fclk_clksel_ck@52c"; | |
| gfx_fck_div_ck = "/ocp/l4_wkup@44c00000/prcm@200000/clocks/gfx_fck_div_ck@52c"; | |
| sysclkout_pre_ck = "/ocp/l4_wkup@44c00000/prcm@200000/clocks/sysclkout_pre_ck@700"; | |
| clkout2_div_ck = "/ocp/l4_wkup@44c00000/prcm@200000/clocks/clkout2_div_ck@700"; | |
| dbg_sysclk_ck = "/ocp/l4_wkup@44c00000/prcm@200000/clocks/dbg_sysclk_ck@414"; | |
| dbg_clka_ck = "/ocp/l4_wkup@44c00000/prcm@200000/clocks/dbg_clka_ck@414"; | |
| stm_pmd_clock_mux_ck = "/ocp/l4_wkup@44c00000/prcm@200000/clocks/stm_pmd_clock_mux_ck@414"; | |
| trace_pmd_clk_mux_ck = "/ocp/l4_wkup@44c00000/prcm@200000/clocks/trace_pmd_clk_mux_ck@414"; | |
| stm_clk_div_ck = "/ocp/l4_wkup@44c00000/prcm@200000/clocks/stm_clk_div_ck@414"; | |
| trace_clk_div_ck = "/ocp/l4_wkup@44c00000/prcm@200000/clocks/trace_clk_div_ck@414"; | |
| clkout2_ck = "/ocp/l4_wkup@44c00000/prcm@200000/clocks/clkout2_ck@700"; | |
| prcm_clockdomains = "/ocp/l4_wkup@44c00000/prcm@200000/clockdomains"; | |
| clk_24mhz_clkdm = "/ocp/l4_wkup@44c00000/prcm@200000/clockdomains/clk_24mhz_clkdm"; | |
| scm = "/ocp/l4_wkup@44c00000/scm@210000"; | |
| am33xx_pinmux = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800"; | |
| user_leds_default = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/user_leds_default"; | |
| user_leds_sleep = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/user_leds_sleep"; | |
| i2c0_pins = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_i2c0_pins"; | |
| mmc0_pins = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_mmc0_pins"; | |
| P1_02_default_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_02_default_pin"; | |
| P1_02_gpio_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_02_gpio_pin"; | |
| P1_02_gpio_pu_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_02_gpio_pu_pin"; | |
| P1_02_gpio_pd_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_02_gpio_pd_pin"; | |
| P1_02_gpio_input_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_02_gpio_input_pin"; | |
| P1_02_pruout_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_02_pruout_pin"; | |
| P1_02_pruin_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_02_pruin_pin"; | |
| P1_04_default_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_04_default_pin"; | |
| P1_04_gpio_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_04_gpio_pin"; | |
| P1_04_gpio_pu_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_04_gpio_pu_pin"; | |
| P1_04_gpio_pd_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_04_gpio_pd_pin"; | |
| P1_04_gpio_input_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_04_gpio_input_pin"; | |
| P1_04_pruout_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_04_pruout_pin"; | |
| P1_04_pruin_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_04_pruin_pin"; | |
| P1_06_default_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_06_default_pin"; | |
| P1_06_gpio_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_06_gpio_pin"; | |
| P1_06_gpio_pu_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_06_gpio_pu_pin"; | |
| P1_06_gpio_pd_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_06_gpio_pd_pin"; | |
| P1_06_gpio_input_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_06_gpio_input_pin"; | |
| P1_06_spi_cs_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_06_spi_cs_pin"; | |
| P1_06_i2c_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_06_i2c_pin"; | |
| P1_06_pwm_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_06_pwm_pin"; | |
| P1_06_pru_uart_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_06_pru_uart_pin"; | |
| P1_08_default_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_08_default_pin"; | |
| P1_08_gpio_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_08_gpio_pin"; | |
| P1_08_gpio_pu_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_08_gpio_pu_pin"; | |
| P1_08_gpio_pd_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_08_gpio_pd_pin"; | |
| P1_08_gpio_input_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_08_gpio_input_pin"; | |
| P1_08_spi_sclk_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_08_spi_sclk_pin"; | |
| P1_08_uart_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_08_uart_pin"; | |
| P1_08_i2c_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_08_i2c_pin"; | |
| P1_08_pwm_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_08_pwm_pin"; | |
| P1_08_pru_uart_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_08_pru_uart_pin"; | |
| P1_10_default_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_10_default_pin"; | |
| P1_10_gpio_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_10_gpio_pin"; | |
| P1_10_gpio_pu_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_10_gpio_pu_pin"; | |
| P1_10_gpio_pd_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_10_gpio_pd_pin"; | |
| P1_10_gpio_input_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_10_gpio_input_pin"; | |
| P1_10_spi_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_10_spi_pin"; | |
| P1_10_uart_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_10_uart_pin"; | |
| P1_10_i2c_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_10_i2c_pin"; | |
| P1_10_pwm_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_10_pwm_pin"; | |
| P1_10_pru_uart_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_10_pru_uart_pin"; | |
| P1_12_default_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_12_default_pin"; | |
| P1_12_gpio_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_12_gpio_pin"; | |
| P1_12_gpio_pu_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_12_gpio_pu_pin"; | |
| P1_12_gpio_pd_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_12_gpio_pd_pin"; | |
| P1_12_gpio_input_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_12_gpio_input_pin"; | |
| P1_12_spi_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_12_spi_pin"; | |
| P1_12_i2c_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_12_i2c_pin"; | |
| P1_12_pwm_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_12_pwm_pin"; | |
| P1_12_pru_uart_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_12_pru_uart_pin"; | |
| P1_20_default_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_20_default_pin"; | |
| P1_20_gpio_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_20_gpio_pin"; | |
| P1_20_gpio_pu_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_20_gpio_pu_pin"; | |
| P1_20_gpio_pd_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_20_gpio_pd_pin"; | |
| P1_20_gpio_input_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_20_gpio_input_pin"; | |
| P1_20_pruin_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_20_pruin_pin"; | |
| P1_26_default_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_26_default_pin"; | |
| P1_26_gpio_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_26_gpio_pin"; | |
| P1_26_gpio_pu_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_26_gpio_pu_pin"; | |
| P1_26_gpio_pd_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_26_gpio_pd_pin"; | |
| P1_26_gpio_input_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_26_gpio_input_pin"; | |
| P1_26_can_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_26_can_pin"; | |
| P1_26_i2c_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_26_i2c_pin"; | |
| P1_26_spi_cs_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_26_spi_cs_pin"; | |
| P1_26_pru_uart_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_26_pru_uart_pin"; | |
| P1_28_default_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_28_default_pin"; | |
| P1_28_gpio_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_28_gpio_pin"; | |
| P1_28_gpio_pu_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_28_gpio_pu_pin"; | |
| P1_28_gpio_pd_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_28_gpio_pd_pin"; | |
| P1_28_gpio_input_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_28_gpio_input_pin"; | |
| P1_28_can_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_28_can_pin"; | |
| P1_28_i2c_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_28_i2c_pin"; | |
| P1_28_spi_cs_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_28_spi_cs_pin"; | |
| P1_28_pru_uart_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_28_pru_uart_pin"; | |
| P1_29_default_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_29_default_pin"; | |
| P1_29_gpio_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_29_gpio_pin"; | |
| P1_29_gpio_pu_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_29_gpio_pu_pin"; | |
| P1_29_gpio_pd_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_29_gpio_pd_pin"; | |
| P1_29_gpio_input_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_29_gpio_input_pin"; | |
| P1_29_qep_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_29_qep_pin"; | |
| P1_29_pruout_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_29_pruout_pin"; | |
| P1_29_pruin_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_29_pruin_pin"; | |
| P1_30_default_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_30_default_pin"; | |
| P1_30_gpio_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_30_gpio_pin"; | |
| P1_30_gpio_pu_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_30_gpio_pu_pin"; | |
| P1_30_gpio_pd_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_30_gpio_pd_pin"; | |
| P1_30_gpio_input_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_30_gpio_input_pin"; | |
| P1_30_uart_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_30_uart_pin"; | |
| P1_30_spi_cs_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_30_spi_cs_pin"; | |
| P1_30_can_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_30_can_pin"; | |
| P1_30_i2c_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_30_i2c_pin"; | |
| P1_30_pruout_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_30_pruout_pin"; | |
| P1_30_pruin_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_30_pruin_pin"; | |
| P1_31_default_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_31_default_pin"; | |
| P1_31_gpio_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_31_gpio_pin"; | |
| P1_31_gpio_pu_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_31_gpio_pu_pin"; | |
| P1_31_gpio_pd_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_31_gpio_pd_pin"; | |
| P1_31_gpio_input_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_31_gpio_input_pin"; | |
| P1_31_qep_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_31_qep_pin"; | |
| P1_31_pruout_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_31_pruout_pin"; | |
| P1_31_pruin_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_31_pruin_pin"; | |
| P1_32_default_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_32_default_pin"; | |
| P1_32_gpio_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_32_gpio_pin"; | |
| P1_32_gpio_pu_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_32_gpio_pu_pin"; | |
| P1_32_gpio_pd_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_32_gpio_pd_pin"; | |
| P1_32_gpio_input_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_32_gpio_input_pin"; | |
| P1_32_uart_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_32_uart_pin"; | |
| P1_32_spi_cs_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_32_spi_cs_pin"; | |
| P1_32_can_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_32_can_pin"; | |
| P1_32_i2c_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_32_i2c_pin"; | |
| P1_32_pruout_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_32_pruout_pin"; | |
| P1_32_pruin_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_32_pruin_pin"; | |
| P1_33_default_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_33_default_pin"; | |
| P1_33_gpio_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_33_gpio_pin"; | |
| P1_33_gpio_pu_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_33_gpio_pu_pin"; | |
| P1_33_gpio_pd_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_33_gpio_pd_pin"; | |
| P1_33_gpio_input_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_33_gpio_input_pin"; | |
| P1_33_pwm_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_33_pwm_pin"; | |
| P1_33_spi_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_33_spi_pin"; | |
| P1_33_pruout_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_33_pruout_pin"; | |
| P1_33_pruin_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_33_pruin_pin"; | |
| P1_34_default_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_34_default_pin"; | |
| P1_34_gpio_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_34_gpio_pin"; | |
| P1_34_gpio_pu_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_34_gpio_pu_pin"; | |
| P1_34_gpio_pd_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_34_gpio_pd_pin"; | |
| P1_34_gpio_input_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_34_gpio_input_pin"; | |
| P1_34_pwm_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_34_pwm_pin"; | |
| P1_35_default_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_35_default_pin"; | |
| P1_35_gpio_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_35_gpio_pin"; | |
| P1_35_gpio_pu_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_35_gpio_pu_pin"; | |
| P1_35_gpio_pd_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_35_gpio_pd_pin"; | |
| P1_35_gpio_input_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_35_gpio_input_pin"; | |
| P1_35_pruout_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_35_pruout_pin"; | |
| P1_35_pruin_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_35_pruin_pin"; | |
| P1_36_default_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_36_default_pin"; | |
| P1_36_gpio_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_36_gpio_pin"; | |
| P1_36_gpio_pu_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_36_gpio_pu_pin"; | |
| P1_36_gpio_pd_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_36_gpio_pd_pin"; | |
| P1_36_gpio_input_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_36_gpio_input_pin"; | |
| P1_36_pwm_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_36_pwm_pin"; | |
| P1_36_spi_sclk_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_36_spi_sclk_pin"; | |
| P1_36_pruout_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_36_pruout_pin"; | |
| P1_36_pruin_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P1_36_pruin_pin"; | |
| P2_01_default_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_01_default_pin"; | |
| P2_01_gpio_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_01_gpio_pin"; | |
| P2_01_gpio_pu_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_01_gpio_pu_pin"; | |
| P2_01_gpio_pd_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_01_gpio_pd_pin"; | |
| P2_01_gpio_input_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_01_gpio_input_pin"; | |
| P2_01_pwm_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_01_pwm_pin"; | |
| P2_02_default_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_02_default_pin"; | |
| P2_02_gpio_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_02_gpio_pin"; | |
| P2_02_gpio_pu_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_02_gpio_pu_pin"; | |
| P2_02_gpio_pd_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_02_gpio_pd_pin"; | |
| P2_02_gpio_input_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_02_gpio_input_pin"; | |
| P2_03_default_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_03_default_pin"; | |
| P2_03_gpio_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_03_gpio_pin"; | |
| P2_03_gpio_pu_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_03_gpio_pu_pin"; | |
| P2_03_gpio_pd_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_03_gpio_pd_pin"; | |
| P2_03_gpio_input_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_03_gpio_input_pin"; | |
| P2_03_pwm_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_03_pwm_pin"; | |
| P2_04_default_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_04_default_pin"; | |
| P2_04_gpio_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_04_gpio_pin"; | |
| P2_04_gpio_pu_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_04_gpio_pu_pin"; | |
| P2_04_gpio_pd_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_04_gpio_pd_pin"; | |
| P2_04_gpio_input_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_04_gpio_input_pin"; | |
| P2_05_default_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_05_default_pin"; | |
| P2_05_gpio_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_05_gpio_pin"; | |
| P2_05_gpio_pu_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_05_gpio_pu_pin"; | |
| P2_05_gpio_pd_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_05_gpio_pd_pin"; | |
| P2_05_gpio_input_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_05_gpio_input_pin"; | |
| P2_05_uart_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_05_uart_pin"; | |
| P2_06_default_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_06_default_pin"; | |
| P2_06_gpio_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_06_gpio_pin"; | |
| P2_06_gpio_pu_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_06_gpio_pu_pin"; | |
| P2_06_gpio_pd_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_06_gpio_pd_pin"; | |
| P2_06_gpio_input_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_06_gpio_input_pin"; | |
| P2_07_default_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_07_default_pin"; | |
| P2_07_gpio_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_07_gpio_pin"; | |
| P2_07_gpio_pu_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_07_gpio_pu_pin"; | |
| P2_07_gpio_pd_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_07_gpio_pd_pin"; | |
| P2_07_gpio_input_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_07_gpio_input_pin"; | |
| P2_07_uart_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_07_uart_pin"; | |
| P2_08_default_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_08_default_pin"; | |
| P2_08_gpio_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_08_gpio_pin"; | |
| P2_08_gpio_pu_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_08_gpio_pu_pin"; | |
| P2_08_gpio_pd_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_08_gpio_pd_pin"; | |
| P2_08_gpio_input_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_08_gpio_input_pin"; | |
| P2_09_default_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_09_default_pin"; | |
| P2_09_gpio_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_09_gpio_pin"; | |
| P2_09_gpio_pu_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_09_gpio_pu_pin"; | |
| P2_09_gpio_pd_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_09_gpio_pd_pin"; | |
| P2_09_gpio_input_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_09_gpio_input_pin"; | |
| P2_09_uart_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_09_uart_pin"; | |
| P2_09_can_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_09_can_pin"; | |
| P2_09_i2c_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_09_i2c_pin"; | |
| P2_09_pru_uart_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_09_pru_uart_pin"; | |
| P2_09_pruin_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_09_pruin_pin"; | |
| P2_10_default_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_10_default_pin"; | |
| P2_10_gpio_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_10_gpio_pin"; | |
| P2_10_gpio_pu_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_10_gpio_pu_pin"; | |
| P2_10_gpio_pd_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_10_gpio_pd_pin"; | |
| P2_10_gpio_input_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_10_gpio_input_pin"; | |
| P2_10_qep_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_10_qep_pin"; | |
| P2_11_default_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_11_default_pin"; | |
| P2_11_gpio_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_11_gpio_pin"; | |
| P2_11_gpio_pu_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_11_gpio_pu_pin"; | |
| P2_11_gpio_pd_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_11_gpio_pd_pin"; | |
| P2_11_gpio_input_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_11_gpio_input_pin"; | |
| P2_11_uart_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_11_uart_pin"; | |
| P2_11_can_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_11_can_pin"; | |
| P2_11_i2c_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_11_i2c_pin"; | |
| P2_11_pru_uart_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_11_pru_uart_pin"; | |
| P2_11_pruin_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_11_pruin_pin"; | |
| P2_17_default_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_17_default_pin"; | |
| P2_17_gpio_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_17_gpio_pin"; | |
| P2_17_gpio_pu_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_17_gpio_pu_pin"; | |
| P2_17_gpio_pd_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_17_gpio_pd_pin"; | |
| P2_17_gpio_input_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_17_gpio_input_pin"; | |
| P2_18_default_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_18_default_pin"; | |
| P2_18_gpio_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_18_gpio_pin"; | |
| P2_18_gpio_pu_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_18_gpio_pu_pin"; | |
| P2_18_gpio_pd_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_18_gpio_pd_pin"; | |
| P2_18_gpio_input_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_18_gpio_input_pin"; | |
| P2_18_qep_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_18_qep_pin"; | |
| P2_18_pru_ecap_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_18_pru_ecap_pin"; | |
| P2_18_pruin_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_18_pruin_pin"; | |
| P2_19_default_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_19_default_pin"; | |
| P2_19_gpio_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_19_gpio_pin"; | |
| P2_19_gpio_pu_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_19_gpio_pu_pin"; | |
| P2_19_gpio_pd_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_19_gpio_pd_pin"; | |
| P2_19_gpio_input_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_19_gpio_input_pin"; | |
| P2_19_pwm_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_19_pwm_pin"; | |
| P2_20_default_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_20_default_pin"; | |
| P2_20_gpio_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_20_gpio_pin"; | |
| P2_20_gpio_pu_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_20_gpio_pu_pin"; | |
| P2_20_gpio_pd_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_20_gpio_pd_pin"; | |
| P2_20_gpio_input_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_20_gpio_input_pin"; | |
| P2_22_default_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_22_default_pin"; | |
| P2_22_gpio_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_22_gpio_pin"; | |
| P2_22_gpio_pu_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_22_gpio_pu_pin"; | |
| P2_22_gpio_pd_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_22_gpio_pd_pin"; | |
| P2_22_gpio_input_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_22_gpio_input_pin"; | |
| P2_22_qep_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_22_qep_pin"; | |
| P2_22_pruin_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_22_pruin_pin"; | |
| P2_24_default_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_24_default_pin"; | |
| P2_24_gpio_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_24_gpio_pin"; | |
| P2_24_gpio_pu_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_24_gpio_pu_pin"; | |
| P2_24_gpio_pd_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_24_gpio_pd_pin"; | |
| P2_24_gpio_input_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_24_gpio_input_pin"; | |
| P2_24_qep_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_24_qep_pin"; | |
| P2_24_pruout_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_24_pruout_pin"; | |
| P2_25_default_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_25_default_pin"; | |
| P2_25_gpio_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_25_gpio_pin"; | |
| P2_25_gpio_pu_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_25_gpio_pu_pin"; | |
| P2_25_gpio_pd_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_25_gpio_pd_pin"; | |
| P2_25_gpio_input_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_25_gpio_input_pin"; | |
| P2_25_uart_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_25_uart_pin"; | |
| P2_25_can_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_25_can_pin"; | |
| P2_25_i2c_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_25_i2c_pin"; | |
| P2_25_spi_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_25_spi_pin"; | |
| P2_25_spi_cs_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_25_spi_cs_pin"; | |
| P2_27_default_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_27_default_pin"; | |
| P2_27_gpio_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_27_gpio_pin"; | |
| P2_27_gpio_pu_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_27_gpio_pu_pin"; | |
| P2_27_gpio_pd_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_27_gpio_pd_pin"; | |
| P2_27_gpio_input_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_27_gpio_input_pin"; | |
| P2_27_uart_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_27_uart_pin"; | |
| P2_27_can_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_27_can_pin"; | |
| P2_27_i2c_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_27_i2c_pin"; | |
| P2_27_spi_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_27_spi_pin"; | |
| P2_28_default_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_28_default_pin"; | |
| P2_28_gpio_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_28_gpio_pin"; | |
| P2_28_gpio_pu_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_28_gpio_pu_pin"; | |
| P2_28_gpio_pd_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_28_gpio_pd_pin"; | |
| P2_28_gpio_input_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_28_gpio_input_pin"; | |
| P2_28_qep_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_28_qep_pin"; | |
| P2_28_pruout_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_28_pruout_pin"; | |
| P2_28_pruin_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_28_pruin_pin"; | |
| P2_29_default_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_29_default_pin"; | |
| P2_29_gpio_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_29_gpio_pin"; | |
| P2_29_gpio_pu_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_29_gpio_pu_pin"; | |
| P2_29_gpio_pd_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_29_gpio_pd_pin"; | |
| P2_29_gpio_input_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_29_gpio_input_pin"; | |
| P2_29_pwm_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_29_pwm_pin"; | |
| P2_29_uart_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_29_uart_pin"; | |
| P2_29_spi_cs_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_29_spi_cs_pin"; | |
| P2_29_pru_ecap_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_29_pru_ecap_pin"; | |
| P2_29_spi_sclk_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_29_spi_sclk_pin"; | |
| P2_30_default_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_30_default_pin"; | |
| P2_30_gpio_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_30_gpio_pin"; | |
| P2_30_gpio_pu_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_30_gpio_pu_pin"; | |
| P2_30_gpio_pd_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_30_gpio_pd_pin"; | |
| P2_30_gpio_input_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_30_gpio_input_pin"; | |
| P2_30_pwm_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_30_pwm_pin"; | |
| P2_30_spi_cs_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_30_spi_cs_pin"; | |
| P2_30_pruout_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_30_pruout_pin"; | |
| P2_30_pruin_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_30_pruin_pin"; | |
| P2_31_default_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_31_default_pin"; | |
| P2_31_gpio_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_31_gpio_pin"; | |
| P2_31_gpio_pu_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_31_gpio_pu_pin"; | |
| P2_31_gpio_pd_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_31_gpio_pd_pin"; | |
| P2_31_gpio_input_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_31_gpio_input_pin"; | |
| P2_31_spi_cs_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_31_spi_cs_pin"; | |
| P2_31_pruin_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_31_pruin_pin"; | |
| P2_32_default_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_32_default_pin"; | |
| P2_32_gpio_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_32_gpio_pin"; | |
| P2_32_gpio_pu_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_32_gpio_pu_pin"; | |
| P2_32_gpio_pd_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_32_gpio_pd_pin"; | |
| P2_32_gpio_input_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_32_gpio_input_pin"; | |
| P2_32_pwm_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_32_pwm_pin"; | |
| P2_32_spi_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_32_spi_pin"; | |
| P2_32_pruout_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_32_pruout_pin"; | |
| P2_32_pruin_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_32_pruin_pin"; | |
| P2_33_default_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_33_default_pin"; | |
| P2_33_gpio_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_33_gpio_pin"; | |
| P2_33_gpio_pu_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_33_gpio_pu_pin"; | |
| P2_33_gpio_pd_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_33_gpio_pd_pin"; | |
| P2_33_gpio_input_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_33_gpio_input_pin"; | |
| P2_33_qep_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_33_qep_pin"; | |
| P2_33_pruout_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_33_pruout_pin"; | |
| P2_34_default_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_34_default_pin"; | |
| P2_34_gpio_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_34_gpio_pin"; | |
| P2_34_gpio_pu_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_34_gpio_pu_pin"; | |
| P2_34_gpio_pd_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_34_gpio_pd_pin"; | |
| P2_34_gpio_input_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_34_gpio_input_pin"; | |
| P2_34_qep_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_34_qep_pin"; | |
| P2_34_pruout_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_34_pruout_pin"; | |
| P2_34_pruin_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_34_pruin_pin"; | |
| P2_35_default_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_35_default_pin"; | |
| P2_35_gpio_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_35_gpio_pin"; | |
| P2_35_gpio_pu_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_35_gpio_pu_pin"; | |
| P2_35_gpio_pd_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_35_gpio_pd_pin"; | |
| P2_35_gpio_input_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_35_gpio_input_pin"; | |
| P2_35_pruout_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_35_pruout_pin"; | |
| P2_35_pruin_pin = "/ocp/l4_wkup@44c00000/scm@210000/pinmux@800/pinmux_P2_35_pruin_pin"; | |
| scm_conf = "/ocp/l4_wkup@44c00000/scm@210000/scm_conf@0"; | |
| scm_clocks = "/ocp/l4_wkup@44c00000/scm@210000/scm_conf@0/clocks"; | |
| sys_clkin_ck = "/ocp/l4_wkup@44c00000/scm@210000/scm_conf@0/clocks/sys_clkin_ck@40"; | |
| adc_tsc_fck = "/ocp/l4_wkup@44c00000/scm@210000/scm_conf@0/clocks/adc_tsc_fck"; | |
| dcan0_fck = "/ocp/l4_wkup@44c00000/scm@210000/scm_conf@0/clocks/dcan0_fck"; | |
| dcan1_fck = "/ocp/l4_wkup@44c00000/scm@210000/scm_conf@0/clocks/dcan1_fck"; | |
| mcasp0_fck = "/ocp/l4_wkup@44c00000/scm@210000/scm_conf@0/clocks/mcasp0_fck"; | |
| mcasp1_fck = "/ocp/l4_wkup@44c00000/scm@210000/scm_conf@0/clocks/mcasp1_fck"; | |
| smartreflex0_fck = "/ocp/l4_wkup@44c00000/scm@210000/scm_conf@0/clocks/smartreflex0_fck"; | |
| smartreflex1_fck = "/ocp/l4_wkup@44c00000/scm@210000/scm_conf@0/clocks/smartreflex1_fck"; | |
| sha0_fck = "/ocp/l4_wkup@44c00000/scm@210000/scm_conf@0/clocks/sha0_fck"; | |
| aes0_fck = "/ocp/l4_wkup@44c00000/scm@210000/scm_conf@0/clocks/aes0_fck"; | |
| rng_fck = "/ocp/l4_wkup@44c00000/scm@210000/scm_conf@0/clocks/rng_fck"; | |
| ehrpwm0_tbclk = "/ocp/l4_wkup@44c00000/scm@210000/scm_conf@0/clocks/ehrpwm0_tbclk@44e10664"; | |
| ehrpwm1_tbclk = "/ocp/l4_wkup@44c00000/scm@210000/scm_conf@0/clocks/ehrpwm1_tbclk@44e10664"; | |
| ehrpwm2_tbclk = "/ocp/l4_wkup@44c00000/scm@210000/scm_conf@0/clocks/ehrpwm2_tbclk@44e10664"; | |
| wkup_m3_ipc = "/ocp/l4_wkup@44c00000/scm@210000/wkup_m3_ipc@1324"; | |
| edma_xbar = "/ocp/l4_wkup@44c00000/scm@210000/dma-router@f90"; | |
| scm_clockdomains = "/ocp/l4_wkup@44c00000/scm@210000/clockdomains"; | |
| intc = "/ocp/interrupt-controller@48200000"; | |
| edma = "/ocp/edma@49000000"; | |
| edma_tptc0 = "/ocp/tptc@49800000"; | |
| edma_tptc1 = "/ocp/tptc@49900000"; | |
| edma_tptc2 = "/ocp/tptc@49a00000"; | |
| emif = "/ocp/emif@4c000000"; | |
| gpio0 = "/ocp/gpio@44e07000"; | |
| gpio1 = "/ocp/gpio@4804c000"; | |
| gpio2 = "/ocp/gpio@481ac000"; | |
| gpio3 = "/ocp/gpio@481ae000"; | |
| uart0 = "/ocp/serial@44e09000"; | |
| uart1 = "/ocp/serial@48022000"; | |
| uart2 = "/ocp/serial@48024000"; | |
| uart3 = "/ocp/serial@481a6000"; | |
| uart4 = "/ocp/serial@481a8000"; | |
| uart5 = "/ocp/serial@481aa000"; | |
| i2c0 = "/ocp/i2c@44e0b000"; | |
| tps = "/ocp/i2c@44e0b000/tps@24"; | |
| dcdc1_reg = "/ocp/i2c@44e0b000/tps@24/regulators/regulator@0"; | |
| dcdc2_reg = "/ocp/i2c@44e0b000/tps@24/regulators/regulator@1"; | |
| dcdc3_reg = "/ocp/i2c@44e0b000/tps@24/regulators/regulator@2"; | |
| ldo1_reg = "/ocp/i2c@44e0b000/tps@24/regulators/regulator@3"; | |
| ldo2_reg = "/ocp/i2c@44e0b000/tps@24/regulators/regulator@4"; | |
| ldo3_reg = "/ocp/i2c@44e0b000/tps@24/regulators/regulator@5"; | |
| ldo4_reg = "/ocp/i2c@44e0b000/tps@24/regulators/regulator@6"; | |
| baseboard_eeprom = "/ocp/i2c@44e0b000/baseboard_eeprom@50"; | |
| baseboard_data = "/ocp/i2c@44e0b000/baseboard_eeprom@50/baseboard_data@0"; | |
| i2c1 = "/ocp/i2c@4802a000"; | |
| i2c2 = "/ocp/i2c@4819c000"; | |
| mmc1 = "/ocp/mmc@48060000"; | |
| mmc2 = "/ocp/mmc@481d8000"; | |
| mmc3 = "/ocp/mmc@47810000"; | |
| hwspinlock = "/ocp/spinlock@480ca000"; | |
| wdt2 = "/ocp/wdt@44e35000"; | |
| dcan0 = "/ocp/can@481cc000"; | |
| dcan1 = "/ocp/can@481d0000"; | |
| mailbox = "/ocp/mailbox@480C8000"; | |
| mbox_wkupm3 = "/ocp/mailbox@480C8000/wkup_m3"; | |
| timer1 = "/ocp/timer@44e31000"; | |
| timer2 = "/ocp/timer@48040000"; | |
| timer3 = "/ocp/timer@48042000"; | |
| timer4 = "/ocp/timer@48044000"; | |
| timer5 = "/ocp/timer@48046000"; | |
| timer6 = "/ocp/timer@48048000"; | |
| timer7 = "/ocp/timer@4804a000"; | |
| rtc = "/ocp/rtc@44e3e000"; | |
| spi0 = "/ocp/spi@48030000"; | |
| spi1 = "/ocp/spi@481a0000"; | |
| usb = "/ocp/usb@47400000"; | |
| usb_ctrl_mod = "/ocp/usb@47400000/control@44e10620"; | |
| usb0_phy = "/ocp/usb@47400000/usb-phy@47401300"; | |
| usb0 = "/ocp/usb@47400000/usb@47401000"; | |
| usb1_phy = "/ocp/usb@47400000/usb-phy@47401b00"; | |
| usb1 = "/ocp/usb@47400000/usb@47401800"; | |
| cppi41dma = "/ocp/usb@47400000/dma-controller@47402000"; | |
| epwmss0 = "/ocp/epwmss@48300000"; | |
| ecap0 = "/ocp/epwmss@48300000/ecap@48300100"; | |
| eqep0 = "/ocp/epwmss@48300000/eqep@0x48300180"; | |
| ehrpwm0 = "/ocp/epwmss@48300000/pwm@48300200"; | |
| epwmss1 = "/ocp/epwmss@48302000"; | |
| ecap1 = "/ocp/epwmss@48302000/ecap@48302100"; | |
| eqep1 = "/ocp/epwmss@48302000/eqep@0x48302180"; | |
| ehrpwm1 = "/ocp/epwmss@48302000/pwm@48302200"; | |
| epwmss2 = "/ocp/epwmss@48304000"; | |
| ecap2 = "/ocp/epwmss@48304000/ecap@48304100"; | |
| eqep2 = "/ocp/epwmss@48304000/eqep@0x48304180"; | |
| ehrpwm2 = "/ocp/epwmss@48304000/pwm@48304200"; | |
| mac = "/ocp/ethernet@4a100000"; | |
| davinci_mdio = "/ocp/ethernet@4a100000/mdio@4a101000"; | |
| cpsw_emac0 = "/ocp/ethernet@4a100000/slave@4a100200"; | |
| cpsw_emac1 = "/ocp/ethernet@4a100000/slave@4a100300"; | |
| phy_sel = "/ocp/ethernet@4a100000/cpsw-phy-sel@44e10650"; | |
| ocmcram = "/ocp/ocmcram@40300000"; | |
| pm_sram_code = "/ocp/ocmcram@40300000/pm-sram-code@0"; | |
| pm_sram_data = "/ocp/ocmcram@40300000/pm-sram-data@1000"; | |
| pruss_soc_bus = "/ocp/pruss_soc_bus@4a326004", ""; | |
| pruss = "/ocp/pruss_soc_bus@4a326004/pruss@0", ""; | |
| pruss_mem = "/ocp/pruss_soc_bus@4a326004/pruss@0/memories@0", ""; | |
| pruss_cfg = "/ocp/pruss_soc_bus@4a326004/pruss@0/cfg@26000", ""; | |
| pruss_iep = "/ocp/pruss_soc_bus@4a326004/pruss@0/iep@2e000", ""; | |
| pruss_mii_rt = "/ocp/pruss_soc_bus@4a326004/pruss@0/mii_rt@32000", ""; | |
| pruss_intc = "/ocp/pruss_soc_bus@4a326004/pruss@0/intc@20000", ""; | |
| pru0 = "/ocp/pruss_soc_bus@4a326004/pruss@0/pru@34000", ""; | |
| pru1 = "/ocp/pruss_soc_bus@4a326004/pruss@0/pru@38000", ""; | |
| pruss_mdio = "/ocp/pruss_soc_bus@4a326004/pruss@0/mdio@32400", ""; | |
| elm = "/ocp/elm@48080000"; | |
| lcdc = "/ocp/lcdc@4830e000"; | |
| tscadc = "/ocp/tscadc@44e0d000"; | |
| am335x_adc = "/ocp/tscadc@44e0d000/adc"; | |
| gpmc = "/ocp/gpmc@50000000"; | |
| sham = "/ocp/sham@53100000"; | |
| aes = "/ocp/aes@53500000"; | |
| mcasp0 = "/ocp/mcasp@48038000"; | |
| mcasp1 = "/ocp/mcasp@4803C000"; | |
| rng = "/ocp/rng@48310000"; | |
| sgx = "/ocp/sgx@56000000"; | |
| vmmcsd_fixed = "/fixedregulator0"; | |
| }; | |
| }; |
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