Last active
September 20, 2018 00:44
-
-
Save tnishinaga/ed7048587f236e9820c1c024e4ddaceb to your computer and use it in GitHub Desktop.
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| https://github.com/ntfreak/openocd/blob/master/tcl/target/hi6220.cfg |
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| [1] tnishinaga@tx230> openocd \ ~/projects/synquacer/synquacer_baremetal_jtag | |
| -f interface/ftdi/dp_busblaster_kt-link.cfg \ | |
| -f target/hi6220.cfg -c "adapter_khz 10" | |
| Open On-Chip Debugger 0.10.0+dev-00531-g2253a31fb (2018-09-12-01:37) | |
| Licensed under GNU GPL v2 | |
| For bug reports, read | |
| http://openocd.org/doc/doxygen/bugs.html | |
| Info : auto-selecting first available session transport "jtag". To override use 'transport select <transport>'. | |
| hi6220.cpu.a7 | |
| adapter speed: 10 kHz | |
| Info : Listening on port 6666 for tcl connections | |
| Info : Listening on port 4444 for telnet connections | |
| Info : clock speed 10 kHz | |
| Info : JTAG tap: hi6220.tap tap/device found: 0x5ba00477 (mfg: 0x23b (ARM Ltd.), part: 0xba00, ver: 0x5) | |
| Info : hi6220.cpu0: hardware has 6 breakpoints, 4 watchpoints | |
| Info : Listening on port 3333 for gdb connections | |
| Info : Listening on port 3334 for gdb connections | |
| Info : Listening on port 3335 for gdb connections | |
| Info : accepting 'telnet' connection on tcp/4444 | |
| TargetName Type Endian TapName State | |
| -- ------------------ ---------- ------ ------------------ ------------ | |
| 0 hi6220.cpu0 aarch64 little hi6220.tap running | |
| 1 hi6220.cpu1 aarch64 little hi6220.tap examine deferred | |
| 2 hi6220.cpu2 aarch64 little hi6220.tap examine deferred | |
| 3 hi6220.cpu3 aarch64 little hi6220.tap examine deferred | |
| 4 hi6220.cpu4 aarch64 little hi6220.tap examine deferred | |
| 5 hi6220.cpu5 aarch64 little hi6220.tap examine deferred | |
| 6 hi6220.cpu6 aarch64 little hi6220.tap examine deferred | |
| 7 hi6220.cpu7 aarch64 little hi6220.tap examine deferred | |
| 8 hi6220.cpu.m3 cortex_m little hi6220.tap examine deferred | |
| 9* hi6220.cpu.a7 cortex_a little hi6220.tap examine deferred | |
| adapter_khz [khz] | |
| adapter_name | |
| adapter_nsrst_assert_width [milliseconds] | |
| adapter_nsrst_delay [milliseconds] | |
| dap | |
| dap create name '-chain-position' name | |
| dap info [ap_num] | |
| dap init | |
| dap names | |
| hi6220.dap | |
| hi6220.dap apcsw [value [mask]] | |
| hi6220.dap apid [ap_num] | |
| hi6220.dap apreg ap_num reg [value] | |
| hi6220.dap apsel [ap_num] | |
| hi6220.dap baseaddr [ap_num] | |
| hi6220.dap dpreg reg [value] | |
| hi6220.dap info [ap_num] | |
| hi6220.dap memaccess [cycles] | |
| hi6220.dap ti_be_32_quirks [enable] | |
| interface driver_name | |
| interface_list | |
| jtag_rclk [fallback_speed_khz] | |
| reset_config [none|trst_only|srst_only|trst_and_srst] | |
| [srst_pulls_trst|trst_pulls_srst|combined|separate] | |
| [srst_gates_jtag|srst_nogate] [trst_push_pull|trst_open_drain] | |
| [srst_push_pull|srst_open_drain] | |
| [connect_deassert_srst|connect_assert_srst] | |
| dap : command requires more arguments | |
| in procedure 'dap' | |
| AP ID register 0x34770002 | |
| Type is MEM-AP APB | |
| MEM-AP BASE 0x80000000 | |
| ROM table in legacy format | |
| Component base address 0x80000000 | |
| Peripheral ID 0x06000e7000 | |
| Designer is 0x6e7, Zenverge, Inc. | |
| Part is 0x0, Unrecognized | |
| Component class is 0x1, ROM table | |
| MEMTYPE system memory not present: dedicated debug bus | |
| ROMTABLE[0x0] = 0x1003 | |
| Component base address 0x80001000 | |
| Peripheral ID 0x04002bb908 | |
| Designer is 0x4bb, ARM Ltd. | |
| Part is 0x908, CoreSight CSTF (Trace Funnel) | |
| Component class is 0x9, CoreSight component | |
| Type is 0x12, Trace Link, Funnel, router | |
| ROMTABLE[0x4] = 0x2003 | |
| Component base address 0x80002000 | |
| Peripheral ID 0x04001bb961 | |
| Designer is 0x4bb, ARM Ltd. | |
| Part is 0x961, CoreSight TMC (Trace Memory Controller) | |
| Component class is 0x9, CoreSight component | |
| Type is 0x32, Trace Link, FIFO, buffer | |
| ROMTABLE[0x8] = 0x3003 | |
| Component base address 0x80003000 | |
| Peripheral ID 0x04003bb906 | |
| Designer is 0x4bb, ARM Ltd. | |
| Part is 0x906, CoreSight CTI (Cross Trigger) | |
| Component class is 0x9, CoreSight component | |
| Type is 0x14, Debug Control, Trigger Matrix | |
| ROMTABLE[0xc] = 0x4003 | |
| Component base address 0x80004000 | |
| Peripheral ID 0x04001bb961 | |
| Designer is 0x4bb, ARM Ltd. | |
| Part is 0x961, CoreSight TMC (Trace Memory Controller) | |
| Component class is 0x9, CoreSight component | |
| Type is 0x21, Trace Sink, Buffer | |
| ROMTABLE[0x10] = 0x5003 | |
| Component base address 0x80005000 | |
| Peripheral ID 0x04004bb912 | |
| Designer is 0x4bb, ARM Ltd. | |
| Part is 0x912, CoreSight TPIU (Trace Port Interface Unit) | |
| Component class is 0x9, CoreSight component | |
| Type is 0x11, Trace Sink, Port | |
| ROMTABLE[0x14] = 0x100003 | |
| Component base address 0x80100000 | |
| Peripheral ID 0x0000080000 | |
| Designer is 0x080, <invalid> | |
| Part is 0x0, Unrecognized | |
| Component class is 0x1, ROM table | |
| MEMTYPE system memory not present: dedicated debug bus | |
| [L01] ROMTABLE[0x0] = 0x1003 | |
| Component base address 0x80101000 | |
| Invalid CID 0x00000000 | |
| [L01] ROMTABLE[0x4] = 0x4003 | |
| Component base address 0x80104000 | |
| Invalid CID 0x00000000 | |
| [L01] ROMTABLE[0x8] = 0x80003 | |
| Component base address 0x80180000 | |
| Peripheral ID 0x04003bb4a3 | |
| Designer is 0x4bb, ARM Ltd. | |
| Part is 0x4a3, Cortex-A53 ROM (v7 Memory Map ROM Table) | |
| Component class is 0x1, ROM table | |
| MEMTYPE system memory not present: dedicated debug bus | |
| [L02] ROMTABLE[0x0] = 0x10003 | |
| Component base address 0x80190000 | |
| Peripheral ID 0x04003bbd03 | |
| Designer is 0x4bb, ARM Ltd. | |
| Part is 0xd03, Cortex-A53 Debug (Debug Unit) | |
| Component class is 0x9, CoreSight component | |
| Type is 0x15, Debug Logic, Processor | |
| [L02] ROMTABLE[0x4] = 0x11003 | |
| Component base address 0x80191000 | |
| Peripheral ID 0x04003bb9d3 | |
| Designer is 0x4bb, ARM Ltd. | |
| Part is 0x9d3, Cortex-A53 PMU (Performance Monitor Unit) | |
| Component class is 0x9, CoreSight component | |
| Type is 0x16, Perfomance Monitor, Processor | |
| [L02] ROMTABLE[0x8] = 0x12003 | |
| Component base address 0x80192000 | |
| Peripheral ID 0x04003bbd03 | |
| Designer is 0x4bb, ARM Ltd. | |
| Part is 0xd03, Cortex-A53 Debug (Debug Unit) | |
| Component class is 0x9, CoreSight component | |
| Type is 0x15, Debug Logic, Processor | |
| [L02] ROMTABLE[0xc] = 0x13003 | |
| Component base address 0x80193000 | |
| Peripheral ID 0x04003bb9d3 | |
| Designer is 0x4bb, ARM Ltd. | |
| Part is 0x9d3, Cortex-A53 PMU (Performance Monitor Unit) | |
| Component class is 0x9, CoreSight component | |
| Type is 0x16, Perfomance Monitor, Processor | |
| [L02] ROMTABLE[0x10] = 0x14003 | |
| Component base address 0x80194000 | |
| Peripheral ID 0x04003bbd03 | |
| Designer is 0x4bb, ARM Ltd. | |
| Part is 0xd03, Cortex-A53 Debug (Debug Unit) | |
| Component class is 0x9, CoreSight component | |
| Type is 0x15, Debug Logic, Processor | |
| [L02] ROMTABLE[0x14] = 0x15003 | |
| Component base address 0x80195000 | |
| Peripheral ID 0x04003bb9d3 | |
| Designer is 0x4bb, ARM Ltd. | |
| Part is 0x9d3, Cortex-A53 PMU (Performance Monitor Unit) | |
| Component class is 0x9, CoreSight component | |
| Type is 0x16, Perfomance Monitor, Processor | |
| [L02] ROMTABLE[0x18] = 0x16003 | |
| Component base address 0x80196000 | |
| Peripheral ID 0x04003bbd03 | |
| Designer is 0x4bb, ARM Ltd. | |
| Part is 0xd03, Cortex-A53 Debug (Debug Unit) | |
| Component class is 0x9, CoreSight component | |
| Type is 0x15, Debug Logic, Processor | |
| [L02] ROMTABLE[0x1c] = 0x17003 | |
| Component base address 0x80197000 | |
| Peripheral ID 0x04003bb9d3 | |
| Designer is 0x4bb, ARM Ltd. | |
| Part is 0x9d3, Cortex-A53 PMU (Performance Monitor Unit) | |
| Component class is 0x9, CoreSight component | |
| Type is 0x16, Perfomance Monitor, Processor | |
| [L02] ROMTABLE[0x20] = 0x18003 | |
| Component base address 0x80198000 | |
| Peripheral ID 0x04003bb9a8 | |
| Designer is 0x4bb, ARM Ltd. | |
| Part is 0x9a8, Cortex-A53 CTI (Cross Trigger) | |
| Component class is 0x9, CoreSight component | |
| Type is 0x14, Debug Control, Trigger Matrix | |
| [L02] ROMTABLE[0x24] = 0x19003 | |
| Component base address 0x80199000 | |
| Peripheral ID 0x04003bb9a8 | |
| Designer is 0x4bb, ARM Ltd. | |
| Part is 0x9a8, Cortex-A53 CTI (Cross Trigger) | |
| Component class is 0x9, CoreSight component | |
| Type is 0x14, Debug Control, Trigger Matrix | |
| [L02] ROMTABLE[0x28] = 0x1a003 | |
| Component base address 0x8019a000 | |
| Peripheral ID 0x04003bb9a8 | |
| Designer is 0x4bb, ARM Ltd. | |
| Part is 0x9a8, Cortex-A53 CTI (Cross Trigger) | |
| Component class is 0x9, CoreSight component | |
| Type is 0x14, Debug Control, Trigger Matrix | |
| [L02] ROMTABLE[0x2c] = 0x1b003 | |
| Component base address 0x8019b000 | |
| Peripheral ID 0x04003bb9a8 | |
| Designer is 0x4bb, ARM Ltd. | |
| Part is 0x9a8, Cortex-A53 CTI (Cross Trigger) | |
| Component class is 0x9, CoreSight component | |
| Type is 0x14, Debug Control, Trigger Matrix | |
| [L02] ROMTABLE[0x30] = 0x1c003 | |
| Component base address 0x8019c000 | |
| Peripheral ID 0x04003bb95d | |
| Designer is 0x4bb, ARM Ltd. | |
| Part is 0x95d, Cortex-A53 ETM (Embedded Trace) | |
| Component class is 0x9, CoreSight component | |
| Type is 0x13, Trace Source, Processor | |
| [L02] ROMTABLE[0x34] = 0x1d003 | |
| Component base address 0x8019d000 | |
| Peripheral ID 0x04003bb95d | |
| Designer is 0x4bb, ARM Ltd. | |
| Part is 0x95d, Cortex-A53 ETM (Embedded Trace) | |
| Component class is 0x9, CoreSight component | |
| Type is 0x13, Trace Source, Processor | |
| [L02] ROMTABLE[0x38] = 0x1e003 | |
| Component base address 0x8019e000 | |
| Peripheral ID 0x04003bb95d | |
| Designer is 0x4bb, ARM Ltd. | |
| Part is 0x95d, Cortex-A53 ETM (Embedded Trace) | |
| Component class is 0x9, CoreSight component | |
| Type is 0x13, Trace Source, Processor | |
| [L02] ROMTABLE[0x3c] = 0x1f003 | |
| Component base address 0x8019f000 | |
| Peripheral ID 0x04003bb95d | |
| Designer is 0x4bb, ARM Ltd. | |
| Part is 0x95d, Cortex-A53 ETM (Embedded Trace) | |
| Component class is 0x9, CoreSight component | |
| Type is 0x13, Trace Source, Processor | |
| [L02] ROMTABLE[0x40] = 0x0 | |
| [L02] End of ROM table | |
| [L01] ROMTABLE[0xc] = 0xc0003 | |
| Component base address 0x801c0000 | |
| Error: JTAG-DP STICKY ERROR | |
| Can't read component, the corresponding core might be turned off | |
| [L01] ROMTABLE[0x10] = 0x0 | |
| [L01] End of ROM table | |
| ROMTABLE[0x18] = 0x200003 | |
| Component base address 0x80200000 | |
| Error: JTAG-DP STICKY ERROR | |
| Can't read component, the corresponding core might be turned off | |
| ROMTABLE[0x1c] = 0x0 | |
| End of ROM table | |
| A | |
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment