VHDL Components Description

compareZero.vhd

library IEEE;
use ieee.std_logic_1164.all;
USE ieee.numeric_std.all;

entity compareZero is
	generic(n: integer := 4);
	port( data: in  unsigned(n-1 downto 0);
			zero: out std_logic -- 0: data <> 0;  1: data == 0
	);
end entity;

architecture comportamental of compareZero is
begin
	zero <= '1' when data=0 else '0';
end;

counter.vhd

library IEEE;
use ieee.std_logic_1164.all;
USE ieee.numeric_std.all;

entity counter is
	generic(	max: integer := 4;  -- valor máximo de contagem
				bits: integer := 2); -- quantidade de bits do contador
	port(	clock,
			reset,
			enable:	in  std_logic;  -- habilita ou para a contagem 
			count:	out unsigned(bits-1 downto 0)
	);
end entity;

architecture comportamental of counter is
signal icount: unsigned(bits-1 downto 0);
begin 
	count <= icount;
	process(reset, clock)
	begin
		if reset='1' then
			icount <= (others => '0');
		elsif clock'event and clock='1' then
			if enable='1' then
				if icount<max then
					icount <= icount + 1;
				else
					icount <= (others => '0');
				end if;
			end if;
		end if;
	end process;
end architecture;

SerialShifter.vhd

library IEEE;
use ieee.std_logic_1164.all;
USE ieee.numeric_std.all;

entity SerialShifter is 
	port(	clock, 
			reset,
			start: in std_logic;
			dataIn: in  std_logic_vector(7 downto 0);
			dataOut: out std_logic_vector(7 downto 0);
			done: out std_logic 
	);
end entity;

architecture comportamental of SerialShifter is

component shifterReg is
	generic(n: integer := 4);
	port(
		clock,
		reset,
		load:		in     std_logic; 
		leftIn,
		rightIn: in     std_logic;
		shift: in     std_logic_vector(1 downto 0);
		D: in     std_logic_vector(n-1 downto 0);
		Q: out std_logic_vector(n-1 downto 0);
		leftOut,
		rightOut:out std_logic
	);
end component;

component compareZero is
	generic(n: integer := 4);
	port(
		data: in  unsigned(n-1 downto 0);
		zero: out std_logic
	);
end component;

component counter is
	generic(max: integer := 4; bits: integer := 2);
	port(
		clock,
		reset,
		enable: in  std_logic;
		count: out unsigned(bits-1 downto 0)
	);
end component;

--usable signal
signal shift: std_logic_vector(1 downto 0);
signal zerotoshift: std_logic;
signal serialline: std_logic;
signal ortoenable: std_logic;
signal counttodata: unsigned(4-1 downto 0);

begin
	shift <= not '0' & zerotoshift; --0 é o mais significativo
	ortoenable <= start or not zerotoshift;
	done <= zerotoshift;

	ShifterReg1: shifterReg generic map (8) port map
	(
		clock, --clock
		reset, --reset
		'0', --load
		'0', --leftIN
		'0', --rightIN
		shift, --shift
		dataIn, --D
		open, --Q
		open, --leftOUT
		serialline --rightOUT
	);

	ShifterReg2: shifterReg generic map (8) port map
	(
		clock, --clock
		'0', --reset
		'0', --load
		serialline, --leftIN
		'0', --rightIN
		shift, --shift
		(others => '0'), --D
		dataOut, --Q
		open, --leftOUT
		open --rightOUT
	);

	Counter1: counter generic map (9,4) port map
	(
		clock, --clock
		reset, --reset
		ortoenable, --enable
		counttodata --count
	);


	Compare1: compareZero generic map (4) port map --generic map (4) default
	(
		counttodata, --data
		zerotoshift --zero
	);

end architecture;

shiftReg.vhd

library IEEE;
use ieee.std_logic_1164.all;

entity shifterReg is
	generic(n: integer := 4);
	port(	clock,
			reset,
			load:		in     std_logic; 
			leftIn,
			rightIn: in     std_logic;
			shift:	in     std_logic_vector(1 downto 0); --00: keep value; 01: shift right; 10: shift left; 11: impossible
			D:			in     std_logic_vector(n-1 downto 0);
			Q:			out std_logic_vector(n-1 downto 0);
			leftOut,
			rightOut:out std_logic
	);
end entity;

architecture comportamental of shifterReg is

signal iQ: std_logic_vector(n-1 downto 0);

begin
	Q <= iQ;
	process (reset, clock)
	begin
		if reset='1' then
			iQ <= (others => '0');
		elsif clock'event and clock='1' then
			if load='1' then
				iQ <= D;
			else
				rightOut <= iQ(0);
				leftOut <= iQ(n-1);
				if shift="01" then
					toRight: for i in 0 to n-2 loop
						iQ(i) <= iQ(i+1); --Q(i+1); não posso ler do sinal de saída
					end loop;
					iQ(n-1) <= leftIn;
				elsif shift="10" then
					toLeft: for i in n-1 downto 1 loop
						iQ(i) <= iQ(i-1);
					end loop;
					iQ(0) <= rightIn;
				end if;
			end if;
		end if;
	end process;
end architecture;

stm.do

force /clock  0 0ns, 1 10ns -r 20ns
force /reset  0 0ns, 1 5ns, 0 15ns
force /start  0 0ns, 1 25ns, 0 35ns
force /dataIn 00000000 0ns, 11001110 25ns, 00000000 35ns