deslocador n bits

deslocadornbit.vhdl

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity deslocadornbit is generic(tamanho: natural := 0); port(
  controle: in std_logic_vector(tamanho-1 downto 0);
  entrada: in std_logic_vector(tamanho-1 downto 0);
  saida: out std_logic_vector(tamanho-1 downto 0));
end entity;

architecture comportamento of deslocadornbit is

  type desloca is array(0 to tamanho-1) of std_logic_vector(tamanho-1 downto 0);
  signal conecta: desloca;

  begin
    p: for i in 0 to tamanho-1 generate
      q: for j in 0 to i-1 generate
        conecta(i)(j) <= entrada(j);
      end generate;
      r: for j in i to tamanho-i-2 generate
        conecta(i)(j+1) <= entrada(j);
      end generate;
    end generate;
    saida <= conecta(to_integer(unsigned(controle)));
end architecture;

+------------------------------------------------------------------------------------+
; Flow Summary ;
+------------------------------------+-----------------------------------------------+
; Flow Status ; Successful - Fri Apr 5 23:40:05 2013 ;
; Quartus II 32-bit Version ; 12.1 Build 243 01/31/2013 SP 1 SJ Web Edition ;
; Revision Name ; deslocador1bit ;
; Top-level Entity Name ; shift_reg ;
; Family ; Cyclone II ;
; Device ; EP2C35F672C6 ;
; Timing Models ; Final ;
; Total logic elements ; 3 / 33,216 ( < 1 % ) ;
; Total combinational functions ; 1 / 33,216 ( < 1 % ) ;
; Dedicated logic registers ; 3 / 33,216 ( < 1 % ) ;
; Total registers ; 3 ;
; Total pins ; 4 / 475 ( < 1 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 0 / 483,840 ( 0 % ) ;
; Embedded Multiplier 9-bit elements ; 0 / 70 ( 0 % ) ;
; Total PLLs ; 0 / 4 ( 0 % ) ;
+------------------------------------+-----------------------------------------------+