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Created May 7, 2013 16:24
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Quartus vhdl mesa de testes dando erro
Raw
modelsim_log
# do registrador_run_msim_gate_vhdl.do
# if {[file exists gate_work]} {
# vdel -lib gate_work -all
# }
# vlib gate_work
# vmap work gate_work
# Copying /home/oficinacriativa/altera/12.1/modelsim_ase/linuxaloem/../modelsim.ini to modelsim.ini
# Modifying modelsim.ini
# ** Warning: Copied /home/oficinacriativa/altera/12.1/modelsim_ase/linuxaloem/../modelsim.ini to modelsim.ini.
# Updated modelsim.ini.
#
# vcom -93 -work work {registrador.vho}
# Model Technology ModelSim ALTERA vcom 10.1b Compiler 2012.04 Apr 27 2012
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package VITAL_Timing
# -- Loading package VITAL_Primitives
# -- Loading package cycloneii_atom_pack
# -- Loading package cycloneii_components
# -- Compiling entity reg8
# -- Compiling architecture structure of reg8
#
# vcom -93 -work work {/home/oficinacriativa/ProjetosQuartus/registrador/test_tb.vhd}
# Model Technology ModelSim ALTERA vcom 10.1b Compiler 2012.04 Apr 27 2012
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package STD_LOGIC_UNSIGNED
# -- Compiling entity test_tb
# -- Compiling architecture bhv of test_tb
#
# vsim -t 1ps +transport_int_delays +transport_path_delays -sdftyp /test_tb=registrador_vhd.sdo -L cycloneii -L gate_work -L work -voptargs="+acc" test_tb
# vsim +transport_int_delays +transport_path_delays -L cycloneii -L gate_work -L work -voptargs=\"+acc\" -sdftyp /test_tb=registrador_vhd.sdo -t 1ps test_tb
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.std_logic_arith(body)
# Loading ieee.std_logic_unsigned(body)
# Loading work.test_tb(bhv)
# SDF 10.1b Compiler 2012.04 Apr 27 2012
# ** Warning: (vsim-3473) Component instance "uut : test" is not bound.
# Time: 0 ps Iteration: 0 Instance: /test_tb File: /home/oficinacriativa/ProjetosQuartus/registrador/test_tb.vhd
# Loading instances from registrador_vhd.sdo
# ** Error: (vsim-SDF-3250) registrador_vhd.sdo(39): Failed to find INSTANCE '\CLOCK~I\'.
# ** Error: (vsim-SDF-3250) registrador_vhd.sdo(39): Failed to find INSTANCE 'asynch_inst'.
# ** Error: (vsim-SDF-3250) registrador_vhd.sdo(48): Failed to find INSTANCE '\CLOCK~clkctrl\'.
# ** Error: (vsim-SDF-3250) registrador_vhd.sdo(57): Failed to find INSTANCE 'extena0_reg'.
# ** Error: (vsim-SDF-3250) registrador_vhd.sdo(72): Failed to find INSTANCE '\D[0]~I\'.
# ** Error: (vsim-SDF-3250) registrador_vhd.sdo(72): Failed to find INSTANCE 'asynch_inst'.
# ** Error: (vsim-SDF-3250) registrador_vhd.sdo(130): Failed to find INSTANCE '\D[1]~I\'.
# ** Error: (vsim-SDF-3250) registrador_vhd.sdo(130): Failed to find INSTANCE 'asynch_inst'.
# ** Error: (vsim-SDF-3250) registrador_vhd.sdo(155): Failed to find INSTANCE '\D[2]~I\'.
# ** Error: (vsim-SDF-3250) registrador_vhd.sdo(155): Failed to find INSTANCE 'asynch_inst'.
# ** Error: (vsim-SDF-3250) registrador_vhd.sdo(190): Failed to find INSTANCE '\D[3]~I\'.
# ** Error: (vsim-SDF-3250) registrador_vhd.sdo(190): Failed to find INSTANCE 'asynch_inst'.
# ** Error: (vsim-SDF-3250) registrador_vhd.sdo(225): Failed to find INSTANCE '\D[4]~I\'.
# ** Error: (vsim-SDF-3250) registrador_vhd.sdo(225): Failed to find INSTANCE 'asynch_inst'.
# ** Error: (vsim-SDF-3250) registrador_vhd.sdo(260): Failed to find INSTANCE '\D[5]~I\'.
# ** Error: (vsim-SDF-3250) registrador_vhd.sdo(260): Failed to find INSTANCE 'asynch_inst'.
# ** Error: (vsim-SDF-3250) registrador_vhd.sdo(285): Failed to find INSTANCE '\D[6]~I\'.
# ** Error: (vsim-SDF-3250) registrador_vhd.sdo(285): Failed to find INSTANCE 'asynch_inst'.
# ** Error: (vsim-SDF-3250) registrador_vhd.sdo(310): Failed to find INSTANCE '\D[7]~I\'.
# ** Error: (vsim-SDF-3250) registrador_vhd.sdo(310): Failed to find INSTANCE 'asynch_inst'.
# ** Error: (vsim-SDF-3250) registrador_vhd.sdo(335): Failed to find INSTANCE '\Q[0]~I\'.
# ** Error: (vsim-SDF-3250) registrador_vhd.sdo(335): Failed to find INSTANCE 'asynch_inst'.
# ** Error: (vsim-SDF-3250) registrador_vhd.sdo(114): Failed to find INSTANCE '\Q[0]~reg0\'.
# ** Error: (vsim-SDF-3250) registrador_vhd.sdo(345): Failed to find INSTANCE '\Q[1]~I\'.
# ** Error: (vsim-SDF-3250) registrador_vhd.sdo(345): Failed to find INSTANCE 'asynch_inst'.
# ** Error: (vsim-SDF-3250) registrador_vhd.sdo(139): Failed to find INSTANCE '\Q[1]~reg0\'.
# ** Error: (vsim-SDF-3250) registrador_vhd.sdo(355): Failed to find INSTANCE '\Q[2]~I\'.
# ** Error: (vsim-SDF-3250) registrador_vhd.sdo(355): Failed to find INSTANCE 'asynch_inst'.
# ** Error: (vsim-SDF-3250) registrador_vhd.sdo(174): Failed to find INSTANCE '\Q[2]~reg0\'.
# ** Error: (vsim-SDF-3250) registrador_vhd.sdo(164): Failed to find INSTANCE '\Q[2]~reg0feeder\'.
# ** Error: (vsim-SDF-3250) registrador_vhd.sdo(365): Failed to find INSTANCE '\Q[3]~I\'.
# ** Error: (vsim-SDF-3250) registrador_vhd.sdo(365): Failed to find INSTANCE 'asynch_inst'.
# ** Error: (vsim-SDF-3250) registrador_vhd.sdo(209): Failed to find INSTANCE '\Q[3]~reg0\'.
# ** Error: (vsim-SDF-3250) registrador_vhd.sdo(199): Failed to find INSTANCE '\Q[3]~reg0feeder\'.
# ** Error: (vsim-SDF-3250) registrador_vhd.sdo(375): Failed to find INSTANCE '\Q[4]~I\'.
# ** Error: (vsim-SDF-3250) registrador_vhd.sdo(375): Failed to find INSTANCE 'asynch_inst'.
# ** Error: (vsim-SDF-3250) registrador_vhd.sdo(244): Failed to find INSTANCE '\Q[4]~reg0\'.
# ** Error: (vsim-SDF-3250) registrador_vhd.sdo(234): Failed to find INSTANCE '\Q[4]~reg0feeder\'.
# ** Error: (vsim-SDF-3250) registrador_vhd.sdo(385): Failed to find INSTANCE '\Q[5]~I\'.
# ** Error: (vsim-SDF-3250) registrador_vhd.sdo(385): Failed to find INSTANCE 'asynch_inst'.
# ** Error: (vsim-SDF-3250) registrador_vhd.sdo(269): Failed to find INSTANCE '\Q[5]~reg0\'.
# ** Error: (vsim-SDF-3250) registrador_vhd.sdo(395): Failed to find INSTANCE '\Q[6]~I\'.
# ** Error: (vsim-SDF-3250) registrador_vhd.sdo(395): Failed to find INSTANCE 'asynch_inst'.
# ** Error: (vsim-SDF-3250) registrador_vhd.sdo(294): Failed to find INSTANCE '\Q[6]~reg0\'.
# ** Error: (vsim-SDF-3250) registrador_vhd.sdo(405): Failed to find INSTANCE '\Q[7]~I\'.
# ** Error: (vsim-SDF-3250) registrador_vhd.sdo(405): Failed to find INSTANCE 'asynch_inst'.
# ** Error: (vsim-SDF-3250) registrador_vhd.sdo(319): Failed to find INSTANCE '\Q[7]~reg0\'.
# ** Error: (vsim-SDF-3250) registrador_vhd.sdo(81): Failed to find INSTANCE '\RSTin~I\'.
# ** Error: (vsim-SDF-3250) registrador_vhd.sdo(81): Failed to find INSTANCE 'asynch_inst'.
# ** Error: (vsim-SDF-3250) registrador_vhd.sdo(90): Failed to find INSTANCE '\RSTin~clkctrl\'.
# ** Error: (vsim-SDF-3250) registrador_vhd.sdo(99): Failed to find INSTANCE 'extena0_reg'.
# ** Error: (vsim-SDF-3894) : Errors occured in reading and resolving instances from compiled SDF file(s).
# ** Fatal: SDF files require Altera primitive library
# Time: 0 ps Iteration: 0 Instance: /test_tb File: /home/oficinacriativa/ProjetosQuartus/registrador/test_tb.vhd Line: UNKNOWN
# FATAL ERROR while loading design
# Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO ./registrador_run_msim_gate_vhdl.do PAUSED at line 12
Raw
quartus_log
Info: *******************************************************************
Info: Running Quartus II 32-bit Analysis & Synthesis
Info: Version 12.1 Build 243 01/31/2013 Service Pack 1 SJ Web Edition
Info: Processing started: Tue May 7 13:20:48 2013
Info: Version 12.1 Build 243 01/31/2013 Service Pack 1 SJ Web Edition
Info: Processing started: Tue May 7 13:20:48 2013
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off registrador -c registrador
Warning (20028): Parallel compilation is not licensed and has been disabled
Info (12021): Found 2 design units, including 1 entities, in source file test_tb.vhd
Info (12022): Found design unit 1: test_tb-bhv
Info (12023): Found entity 1: test_tb
Info (12022): Found design unit 1: test_tb-bhv
Info (12023): Found entity 1: test_tb
Info (12021): Found 2 design units, including 1 entities, in source file reg8.vhd
Info (12022): Found design unit 1: reg8-bhv
Info (12023): Found entity 1: reg8
Info (12022): Found design unit 1: reg8-bhv
Info (12023): Found entity 1: reg8
Info (12127): Elaborating entity "reg8" for the top level hierarchy
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
Info (21057): Implemented 26 device resources after synthesis - the final resource count might be different
Info (21058): Implemented 10 input pins
Info (21059): Implemented 8 output pins
Info (21061): Implemented 8 logic cells
Info (21058): Implemented 10 input pins
Info (21059): Implemented 8 output pins
Info (21061): Implemented 8 logic cells
Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 1 warning
Info: Peak virtual memory: 351 megabytes
Info: Processing ended: Tue May 7 13:20:50 2013
Info: Elapsed time: 00:00:02
Info: Total CPU time (on all processors): 00:00:03
Info: Peak virtual memory: 351 megabytes
Info: Processing ended: Tue May 7 13:20:50 2013
Info: Elapsed time: 00:00:02
Info: Total CPU time (on all processors): 00:00:03
Info: *******************************************************************
Info: Running Quartus II 32-bit Fitter
Info: Version 12.1 Build 243 01/31/2013 Service Pack 1 SJ Web Edition
Info: Processing started: Tue May 7 13:20:53 2013
Info: Version 12.1 Build 243 01/31/2013 Service Pack 1 SJ Web Edition
Info: Processing started: Tue May 7 13:20:53 2013
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off registrador -c registrador
Warning (20028): Parallel compilation is not licensed and has been disabled
Info (119006): Selected device EP2C35F672C6 for design "registrador"
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
Info (176445): Device EP2C50F672C6 is compatible
Info (176445): Device EP2C70F672C6 is compatible
Info (176445): Device EP2C50F672C6 is compatible
Info (176445): Device EP2C70F672C6 is compatible
Info (169124): Fitter converted 3 user pins into dedicated programming pins
Info (169125): Pin ~ASDO~ is reserved at location E3
Info (169125): Pin ~nCSO~ is reserved at location D3
Info (169125): Pin ~LVDS150p/nCEO~ is reserved at location AE24
Info (169125): Pin ~ASDO~ is reserved at location E3
Info (169125): Pin ~nCSO~ is reserved at location D3
Info (169125): Pin ~LVDS150p/nCEO~ is reserved at location AE24
Critical Warning (169085): No exact pin location assignment(s) for 18 pins of 18 total pins
Info (169086): Pin Q[0] not assigned to an exact location on the device
Info (169086): Pin Q[1] not assigned to an exact location on the device
Info (169086): Pin Q[2] not assigned to an exact location on the device
Info (169086): Pin Q[3] not assigned to an exact location on the device
Info (169086): Pin Q[4] not assigned to an exact location on the device
Info (169086): Pin Q[5] not assigned to an exact location on the device
Info (169086): Pin Q[6] not assigned to an exact location on the device
Info (169086): Pin Q[7] not assigned to an exact location on the device
Info (169086): Pin D[0] not assigned to an exact location on the device
Info (169086): Pin CLOCK not assigned to an exact location on the device
Info (169086): Pin RSTin not assigned to an exact location on the device
Info (169086): Pin D[1] not assigned to an exact location on the device
Info (169086): Pin D[2] not assigned to an exact location on the device
Info (169086): Pin D[3] not assigned to an exact location on the device
Info (169086): Pin D[4] not assigned to an exact location on the device
Info (169086): Pin D[5] not assigned to an exact location on the device
Info (169086): Pin D[6] not assigned to an exact location on the device
Info (169086): Pin D[7] not assigned to an exact location on the device
Info (169086): Pin Q[0] not assigned to an exact location on the device
Info (169086): Pin Q[1] not assigned to an exact location on the device
Info (169086): Pin Q[2] not assigned to an exact location on the device
Info (169086): Pin Q[3] not assigned to an exact location on the device
Info (169086): Pin Q[4] not assigned to an exact location on the device
Info (169086): Pin Q[5] not assigned to an exact location on the device
Info (169086): Pin Q[6] not assigned to an exact location on the device
Info (169086): Pin Q[7] not assigned to an exact location on the device
Info (169086): Pin D[0] not assigned to an exact location on the device
Info (169086): Pin CLOCK not assigned to an exact location on the device
Info (169086): Pin RSTin not assigned to an exact location on the device
Info (169086): Pin D[1] not assigned to an exact location on the device
Info (169086): Pin D[2] not assigned to an exact location on the device
Info (169086): Pin D[3] not assigned to an exact location on the device
Info (169086): Pin D[4] not assigned to an exact location on the device
Info (169086): Pin D[5] not assigned to an exact location on the device
Info (169086): Pin D[6] not assigned to an exact location on the device
Info (169086): Pin D[7] not assigned to an exact location on the device
Critical Warning (332012): Synopsys Design Constraints File file not found: 'registrador.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Info (332144): No user constrained base clocks found in the design
Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
Info (176353): Automatically promoted node CLOCK (placed in PIN P2 (CLK2, LVDSCLK1p, Input))
Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3
Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3
Info (176353): Automatically promoted node RSTin (placed in PIN P1 (CLK3, LVDSCLK1n, Input))
Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G1
Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G1
Info (176233): Starting register packing
Info (176235): Finished register packing
Extra Info (176219): No registers were packed into other blocks
Extra Info (176219): No registers were packed into other blocks
Info (176214): Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
Info (176211): Number of I/O pins in group: 16 (unused VREF, 3.3V VCCIO, 8 input, 8 output, 0 bidirectional)
Info (176212): I/O standards used: 3.3-V LVTTL.
Info (176211): Number of I/O pins in group: 16 (unused VREF, 3.3V VCCIO, 8 input, 8 output, 0 bidirectional)
Info (176212): I/O standards used: 3.3-V LVTTL.
Info (176212): I/O standards used: 3.3-V LVTTL.
Info (176215): I/O bank details before I/O pin placement
Info (176214): Statistics of I/O banks
Info (176213): I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used -- 62 pins available
Info (176213): I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used -- 57 pins available
Info (176213): I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 56 pins available
Info (176213): I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 58 pins available
Info (176213): I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 65 pins available
Info (176213): I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 58 pins available
Info (176213): I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 58 pins available
Info (176213): I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 56 pins available
Info (176214): Statistics of I/O banks
Info (176213): I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used -- 62 pins available
Info (176213): I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used -- 57 pins available
Info (176213): I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 56 pins available
Info (176213): I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 58 pins available
Info (176213): I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 65 pins available
Info (176213): I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 58 pins available
Info (176213): I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 58 pins available
Info (176213): I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 56 pins available
Info (176213): I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used -- 62 pins available
Info (176213): I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used -- 57 pins available
Info (176213): I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 56 pins available
Info (176213): I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 58 pins available
Info (176213): I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 65 pins available
Info (176213): I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 58 pins available
Info (176213): I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 58 pins available
Info (176213): I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 56 pins available
Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00
Info (170189): Fitter placement preparation operations beginning
Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
Info (170191): Fitter placement operations beginning
Info (170137): Fitter placement was successful
Info (170192): Fitter placement operations ending: elapsed time is 00:00:00
Info (170193): Fitter routing operations beginning
Info (170195): Router estimated average interconnect usage is 0% of the available device resources
Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X33_Y0 to location X43_Y11
Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X33_Y0 to location X43_Y11
Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
Info (170201): Optimizations that may affect the design's routability were skipped
Info (170200): Optimizations that may affect the design's timing were skipped
Info (170201): Optimizations that may affect the design's routability were skipped
Info (170200): Optimizations that may affect the design's timing were skipped
Info (306004): Started post-fitting delay annotation
Warning (306006): Found 8 output pins without output pin load capacitance assignment
Info (306007): Pin "Q[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info (306007): Pin "Q[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info (306007): Pin "Q[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info (306007): Pin "Q[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info (306007): Pin "Q[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info (306007): Pin "Q[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info (306007): Pin "Q[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info (306007): Pin "Q[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info (306007): Pin "Q[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info (306007): Pin "Q[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info (306007): Pin "Q[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info (306007): Pin "Q[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info (306007): Pin "Q[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info (306007): Pin "Q[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info (306007): Pin "Q[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info (306007): Pin "Q[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info (306005): Delay annotation completed successfully
Info (306004): Started post-fitting delay annotation
Info (306005): Delay annotation completed successfully
Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:01
Warning (169174): The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info (144001): Generated suppressed messages file /home/oficinacriativa/ProjetosQuartus/registrador/output_files/registrador.fit.smsg
Info: Quartus II 32-bit Fitter was successful. 0 errors, 6 warnings
Info: Peak virtual memory: 435 megabytes
Info: Processing ended: Tue May 7 13:21:01 2013
Info: Elapsed time: 00:00:08
Info: Total CPU time (on all processors): 00:00:09
Info: Peak virtual memory: 435 megabytes
Info: Processing ended: Tue May 7 13:21:01 2013
Info: Elapsed time: 00:00:08
Info: Total CPU time (on all processors): 00:00:09
Info: *******************************************************************
Info: Running Quartus II 32-bit Assembler
Info: Version 12.1 Build 243 01/31/2013 Service Pack 1 SJ Web Edition
Info: Processing started: Tue May 7 13:21:04 2013
Info: Version 12.1 Build 243 01/31/2013 Service Pack 1 SJ Web Edition
Info: Processing started: Tue May 7 13:21:04 2013
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off registrador -c registrador
Info (115031): Writing out detailed assembly data for power analysis
Info (115030): Assembler is generating device programming files
Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 336 megabytes
Info: Processing ended: Tue May 7 13:21:07 2013
Info: Elapsed time: 00:00:03
Info: Total CPU time (on all processors): 00:00:03
Info: Peak virtual memory: 336 megabytes
Info: Processing ended: Tue May 7 13:21:07 2013
Info: Elapsed time: 00:00:03
Info: Total CPU time (on all processors): 00:00:03
Info (293026): Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER
Info: *******************************************************************
Info: Running Quartus II 32-bit TimeQuest Timing Analyzer
Info: Version 12.1 Build 243 01/31/2013 Service Pack 1 SJ Web Edition
Info: Processing started: Tue May 7 13:21:09 2013
Info: Version 12.1 Build 243 01/31/2013 Service Pack 1 SJ Web Edition
Info: Processing started: Tue May 7 13:21:09 2013
Info: Command: quartus_sta registrador -c registrador
Info: qsta_default_script.tcl version: #1
Warning (20028): Parallel compilation is not licensed and has been disabled
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Critical Warning (332012): Synopsys Design Constraints File file not found: 'registrador.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Info (332105): Deriving Clocks
Info (332105): create_clock -period 1.000 -name CLOCK CLOCK
Info (332105): create_clock -period 1.000 -name CLOCK CLOCK
Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Info: Analyzing Slow Model
Info (332140): No fmax paths to report
Info (332140): No Setup paths to report
Info (332140): No Hold paths to report
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Critical Warning (332148): Timing requirements not met
Info (332146): Worst-case minimum pulse width slack is -1.380
Info (332119): Slack End Point TNS Clock
Info (332119): ========= ============= =====================
Info (332119): -1.380 -9.380 CLOCK
Info (332119): Slack End Point TNS Clock
Info (332119): ========= ============= =====================
Info (332119): -1.380 -9.380 CLOCK
Info (332001): The selected device family is not supported by the report_metastability command.
Info: Analyzing Fast Model
Info (332140): No Setup paths to report
Info (332140): No Hold paths to report
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Critical Warning (332148): Timing requirements not met
Info (332146): Worst-case minimum pulse width slack is -1.380
Info (332119): Slack End Point TNS Clock
Info (332119): ========= ============= =====================
Info (332119): -1.380 -9.380 CLOCK
Info (332119): Slack End Point TNS Clock
Info (332119): ========= ============= =====================
Info (332119): -1.380 -9.380 CLOCK
Info (332001): The selected device family is not supported by the report_metastability command.
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings
Info: Peak virtual memory: 287 megabytes
Info: Processing ended: Tue May 7 13:21:10 2013
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01
Info: Peak virtual memory: 287 megabytes
Info: Processing ended: Tue May 7 13:21:10 2013
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01
Info: *******************************************************************
Info: Running Quartus II 32-bit EDA Netlist Writer
Info: Version 12.1 Build 243 01/31/2013 Service Pack 1 SJ Web Edition
Info: Processing started: Tue May 7 13:21:13 2013
Info: Version 12.1 Build 243 01/31/2013 Service Pack 1 SJ Web Edition
Info: Processing started: Tue May 7 13:21:13 2013
Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off registrador -c registrador
Info (204026): Generated files "registrador.vho", "registrador_fast.vho", "registrador_vhd.sdo" and "registrador_vhd_fast.sdo" in directory "/home/oficinacriativa/ProjetosQuartus/registrador/simulation/modelsim/" for EDA simulation tool
Info: Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 304 megabytes
Info: Processing ended: Tue May 7 13:21:13 2013
Info: Elapsed time: 00:00:00
Info: Total CPU time (on all processors): 00:00:01
Info: Peak virtual memory: 304 megabytes
Info: Processing ended: Tue May 7 13:21:13 2013
Info: Elapsed time: 00:00:00
Info: Total CPU time (on all processors): 00:00:01
Info: *******************************************************************
Info: Running Quartus II 32-bit Shell
Info: Version 12.1 Build 243 01/31/2013 Service Pack 1 SJ Web Edition
Info: Processing started: Tue May 7 13:21:14 2013
Info: Version 12.1 Build 243 01/31/2013 Service Pack 1 SJ Web Edition
Info: Processing started: Tue May 7 13:21:14 2013
Info: Command: quartus_sh -t /home/oficinacriativa/altera/12.1sp1/quartus/common/tcl/internal/nativelink/qnativesim.tcl --block_on_gui registrador registrador
Info: Quartus(args): --block_on_gui registrador registrador
Info: Info: Start Nativelink Simulation process
Info: Info: Starting NativeLink simulation with ModelSim-Altera software
Warning: Warning: File registrador_run_msim_gate_vhdl.do already exists - backing up current file as registrador_run_msim_gate_vhdl.do.bak3
Info: Info: Generated ModelSim-Altera script file /home/oficinacriativa/ProjetosQuartus/registrador/simulation/modelsim/registrador_run_msim_gate_vhdl.do
Info: Probing transcript
Info: ModelSim-Altera Info: # do registrador_run_msim_gate_vhdl.do
Info: ModelSim-Altera Info: # if {[file exists gate_work]} {
Info: ModelSim-Altera Info: # vdel -lib gate_work -all
Info: ModelSim-Altera Info: # }
Info: ModelSim-Altera Info: # vlib gate_work
Info: ModelSim-Altera Info: # vmap work gate_work
Info: ModelSim-Altera Info: # Copying /home/oficinacriativa/altera/12.1/modelsim_ase/linuxaloem/../modelsim.ini to modelsim.ini
Info: ModelSim-Altera Info: # Modifying modelsim.ini
Warning: ModelSim-Altera Warning: # ** Warning: Copied /home/oficinacriativa/altera/12.1/modelsim_ase/linuxaloem/../modelsim.ini to modelsim.ini.
Info: ModelSim-Altera Info: # Updated modelsim.ini.
Info: ModelSim-Altera Info: #
Info: ModelSim-Altera Info: # vcom -93 -work work {registrador.vho}
Info: ModelSim-Altera Info: # Model Technology ModelSim ALTERA vcom 10.1b Compiler 2012.04 Apr 27 2012
Info: ModelSim-Altera Info: # -- Loading package STANDARD
Info: ModelSim-Altera Info: # -- Loading package TEXTIO
Info: ModelSim-Altera Info: # -- Loading package std_logic_1164
Info: ModelSim-Altera Info: # -- Loading package VITAL_Timing
Info: ModelSim-Altera Info: # -- Loading package VITAL_Primitives
Info: ModelSim-Altera Info: # -- Loading package cycloneii_atom_pack
Info: ModelSim-Altera Info: # -- Loading package cycloneii_components
Info: ModelSim-Altera Info: # -- Compiling entity reg8
Info: ModelSim-Altera Info: # -- Compiling architecture structure of reg8
Info: ModelSim-Altera Info: #
Info: ModelSim-Altera Info: # vcom -93 -work work {/home/oficinacriativa/ProjetosQuartus/registrador/test_tb.vhd}
Info: ModelSim-Altera Info: # Model Technology ModelSim ALTERA vcom 10.1b Compiler 2012.04 Apr 27 2012
Info: ModelSim-Altera Info: # -- Loading package STANDARD
Info: ModelSim-Altera Info: # -- Loading package TEXTIO
Info: ModelSim-Altera Info: # -- Loading package std_logic_1164
Info: ModelSim-Altera Info: # -- Loading package std_logic_arith
Info: ModelSim-Altera Info: # -- Loading package STD_LOGIC_UNSIGNED
Info: ModelSim-Altera Info: # -- Compiling entity test_tb
Info: ModelSim-Altera Info: # -- Compiling architecture bhv of test_tb
Info: ModelSim-Altera Info: #
Info: ModelSim-Altera Info: # vsim -t 1ps +transport_int_delays +transport_path_delays -sdftyp /test_tb=registrador_vhd.sdo -L cycloneii -L gate_work -L work -voptargs="+acc" test_tb
Info: ModelSim-Altera Info: # vsim +transport_int_delays +transport_path_delays -L cycloneii -L gate_work -L work -voptargs=\"+acc\" -sdftyp /test_tb=registrador_vhd.sdo -t 1ps test_tb
Info: ModelSim-Altera Info: # Loading std.standard
Info: ModelSim-Altera Info: # Loading std.textio(body)
Info: ModelSim-Altera Info: # Loading ieee.std_logic_1164(body)
Info: ModelSim-Altera Info: # Loading ieee.std_logic_arith(body)
Info: ModelSim-Altera Info: # Loading ieee.std_logic_unsigned(body)
Info: ModelSim-Altera Info: # Loading work.test_tb(bhv)
Info: ModelSim-Altera Info: # SDF 10.1b Compiler 2012.04 Apr 27 2012
Warning: ModelSim-Altera Warning: # ** Warning: (vsim-3473) Component instance "uut : test" is not bound.
Info: ModelSim-Altera Info: # Time: 0 ps Iteration: 0 Instance: /test_tb File: /home/oficinacriativa/ProjetosQuartus/registrador/test_tb.vhd
Info: ModelSim-Altera Info: # Loading instances from registrador_vhd.sdo
Error: ModelSim-Altera Error: # ** Error: (vsim-SDF-3250) registrador_vhd.sdo(39): Failed to find INSTANCE '\CLOCK~I\'.
Error: ModelSim-Altera Error: # ** Error: (vsim-SDF-3250) registrador_vhd.sdo(39): Failed to find INSTANCE 'asynch_inst'.
Error: ModelSim-Altera Error: # ** Error: (vsim-SDF-3250) registrador_vhd.sdo(48): Failed to find INSTANCE '\CLOCK~clkctrl\'.
Error: ModelSim-Altera Error: # ** Error: (vsim-SDF-3250) registrador_vhd.sdo(57): Failed to find INSTANCE 'extena0_reg'.
Error: ModelSim-Altera Error: # ** Error: (vsim-SDF-3250) registrador_vhd.sdo(72): Failed to find INSTANCE '\D[0]~I\'.
Error: ModelSim-Altera Error: # ** Error: (vsim-SDF-3250) registrador_vhd.sdo(72): Failed to find INSTANCE 'asynch_inst'.
Error: ModelSim-Altera Error: # ** Error: (vsim-SDF-3250) registrador_vhd.sdo(130): Failed to find INSTANCE '\D[1]~I\'.
Error: ModelSim-Altera Error: # ** Error: (vsim-SDF-3250) registrador_vhd.sdo(130): Failed to find INSTANCE 'asynch_inst'.
Error: ModelSim-Altera Error: # ** Error: (vsim-SDF-3250) registrador_vhd.sdo(155): Failed to find INSTANCE '\D[2]~I\'.
Error: ModelSim-Altera Error: # ** Error: (vsim-SDF-3250) registrador_vhd.sdo(155): Failed to find INSTANCE 'asynch_inst'.
Error: ModelSim-Altera Error: # ** Error: (vsim-SDF-3250) registrador_vhd.sdo(190): Failed to find INSTANCE '\D[3]~I\'.
Error: ModelSim-Altera Error: # ** Error: (vsim-SDF-3250) registrador_vhd.sdo(190): Failed to find INSTANCE 'asynch_inst'.
Error: ModelSim-Altera Error: # ** Error: (vsim-SDF-3250) registrador_vhd.sdo(225): Failed to find INSTANCE '\D[4]~I\'.
Error: ModelSim-Altera Error: # ** Error: (vsim-SDF-3250) registrador_vhd.sdo(225): Failed to find INSTANCE 'asynch_inst'.
Error: ModelSim-Altera Error: # ** Error: (vsim-SDF-3250) registrador_vhd.sdo(260): Failed to find INSTANCE '\D[5]~I\'.
Error: ModelSim-Altera Error: # ** Error: (vsim-SDF-3250) registrador_vhd.sdo(260): Failed to find INSTANCE 'asynch_inst'.
Error: ModelSim-Altera Error: # ** Error: (vsim-SDF-3250) registrador_vhd.sdo(285): Failed to find INSTANCE '\D[6]~I\'.
Error: ModelSim-Altera Error: # ** Error: (vsim-SDF-3250) registrador_vhd.sdo(285): Failed to find INSTANCE 'asynch_inst'.
Error: ModelSim-Altera Error: # ** Error: (vsim-SDF-3250) registrador_vhd.sdo(310): Failed to find INSTANCE '\D[7]~I\'.
Error: ModelSim-Altera Error: # ** Error: (vsim-SDF-3250) registrador_vhd.sdo(310): Failed to find INSTANCE 'asynch_inst'.
Error: ModelSim-Altera Error: # ** Error: (vsim-SDF-3250) registrador_vhd.sdo(335): Failed to find INSTANCE '\Q[0]~I\'.
Error: ModelSim-Altera Error: # ** Error: (vsim-SDF-3250) registrador_vhd.sdo(335): Failed to find INSTANCE 'asynch_inst'.
Error: ModelSim-Altera Error: # ** Error: (vsim-SDF-3250) registrador_vhd.sdo(114): Failed to find INSTANCE '\Q[0]~reg0\'.
Error: ModelSim-Altera Error: # ** Error: (vsim-SDF-3250) registrador_vhd.sdo(345): Failed to find INSTANCE '\Q[1]~I\'.
Error: ModelSim-Altera Error: # ** Error: (vsim-SDF-3250) registrador_vhd.sdo(345): Failed to find INSTANCE 'asynch_inst'.
Error: ModelSim-Altera Error: # ** Error: (vsim-SDF-3250) registrador_vhd.sdo(139): Failed to find INSTANCE '\Q[1]~reg0\'.
Error: ModelSim-Altera Error: # ** Error: (vsim-SDF-3250) registrador_vhd.sdo(355): Failed to find INSTANCE '\Q[2]~I\'.
Error: ModelSim-Altera Error: # ** Error: (vsim-SDF-3250) registrador_vhd.sdo(355): Failed to find INSTANCE 'asynch_inst'.
Error: ModelSim-Altera Error: # ** Error: (vsim-SDF-3250) registrador_vhd.sdo(174): Failed to find INSTANCE '\Q[2]~reg0\'.
Error: ModelSim-Altera Error: # ** Error: (vsim-SDF-3250) registrador_vhd.sdo(164): Failed to find INSTANCE '\Q[2]~reg0feeder\'.
Error: ModelSim-Altera Error: # ** Error: (vsim-SDF-3250) registrador_vhd.sdo(365): Failed to find INSTANCE '\Q[3]~I\'.
Error: ModelSim-Altera Error: # ** Error: (vsim-SDF-3250) registrador_vhd.sdo(365): Failed to find INSTANCE 'asynch_inst'.
Error: ModelSim-Altera Error: # ** Error: (vsim-SDF-3250) registrador_vhd.sdo(209): Failed to find INSTANCE '\Q[3]~reg0\'.
Error: ModelSim-Altera Error: # ** Error: (vsim-SDF-3250) registrador_vhd.sdo(199): Failed to find INSTANCE '\Q[3]~reg0feeder\'.
Error: ModelSim-Altera Error: # ** Error: (vsim-SDF-3250) registrador_vhd.sdo(375): Failed to find INSTANCE '\Q[4]~I\'.
Error: ModelSim-Altera Error: # ** Error: (vsim-SDF-3250) registrador_vhd.sdo(375): Failed to find INSTANCE 'asynch_inst'.
Error: ModelSim-Altera Error: # ** Error: (vsim-SDF-3250) registrador_vhd.sdo(244): Failed to find INSTANCE '\Q[4]~reg0\'.
Error: ModelSim-Altera Error: # ** Error: (vsim-SDF-3250) registrador_vhd.sdo(234): Failed to find INSTANCE '\Q[4]~reg0feeder\'.
Error: ModelSim-Altera Error: # ** Error: (vsim-SDF-3250) registrador_vhd.sdo(385): Failed to find INSTANCE '\Q[5]~I\'.
Error: ModelSim-Altera Error: # ** Error: (vsim-SDF-3250) registrador_vhd.sdo(385): Failed to find INSTANCE 'asynch_inst'.
Error: ModelSim-Altera Error: # ** Error: (vsim-SDF-3250) registrador_vhd.sdo(269): Failed to find INSTANCE '\Q[5]~reg0\'.
Error: ModelSim-Altera Error: # ** Error: (vsim-SDF-3250) registrador_vhd.sdo(395): Failed to find INSTANCE '\Q[6]~I\'.
Error: ModelSim-Altera Error: # ** Error: (vsim-SDF-3250) registrador_vhd.sdo(395): Failed to find INSTANCE 'asynch_inst'.
Error: ModelSim-Altera Error: # ** Error: (vsim-SDF-3250) registrador_vhd.sdo(294): Failed to find INSTANCE '\Q[6]~reg0\'.
Error: ModelSim-Altera Error: # ** Error: (vsim-SDF-3250) registrador_vhd.sdo(405): Failed to find INSTANCE '\Q[7]~I\'.
Error: ModelSim-Altera Error: # ** Error: (vsim-SDF-3250) registrador_vhd.sdo(405): Failed to find INSTANCE 'asynch_inst'.
Error: ModelSim-Altera Error: # ** Error: (vsim-SDF-3250) registrador_vhd.sdo(319): Failed to find INSTANCE '\Q[7]~reg0\'.
Error: ModelSim-Altera Error: # ** Error: (vsim-SDF-3250) registrador_vhd.sdo(81): Failed to find INSTANCE '\RSTin~I\'.
Error: ModelSim-Altera Error: # ** Error: (vsim-SDF-3250) registrador_vhd.sdo(81): Failed to find INSTANCE 'asynch_inst'.
Error: ModelSim-Altera Error: # ** Error: (vsim-SDF-3250) registrador_vhd.sdo(90): Failed to find INSTANCE '\RSTin~clkctrl\'.
Error: ModelSim-Altera Error: # ** Error: (vsim-SDF-3250) registrador_vhd.sdo(99): Failed to find INSTANCE 'extena0_reg'.
Error: ModelSim-Altera Error: # ** Error: (vsim-SDF-3894) : Errors occured in reading and resolving instances from compiled SDF file(s).
Error: ModelSim-Altera Error: # ** Fatal: SDF files require Altera primitive library
Info: ModelSim-Altera Info: # Time: 0 ps Iteration: 0 Instance: /test_tb File: /home/oficinacriativa/ProjetosQuartus/registrador/test_tb.vhd Line: UNKNOWN
Info: ModelSim-Altera Info: # FATAL ERROR while loading design
Info: ModelSim-Altera Info: # Error loading design
Info: ModelSim-Altera Info: # Error: Error loading design
Info: ModelSim-Altera Info: # Pausing macro execution
Info: ModelSim-Altera Info: # MACRO ./registrador_run_msim_gate_vhdl.do PAUSED at line 12
Error: Errors encountered while running modelsim do file
Error: Error: NativeLink simulation flow was NOT successful
Info: Info: For messages from NativeLink scripts, check the file /home/oficinacriativa/ProjetosQuartus/registrador/registrador_nativelink_simulation.rpt
Error (293001): Quartus II Full Compilation was unsuccessful. 52 errors, 14 warnings
Raw
reg8.vhd
--construcao usando ff
--clear assincrono e enable
--registradores deslocamento
--carga paralela
--registrador deslocamento universal
--exemplo de uso em barramento
--conjunto de elementos de memoria (ffs) utilizados para armazenas n bits
--utilizam em comum os sinais de clock e de controle
library ieee;
use ieee.std_logic_1164.all;
entity reg8 is generic (nbits: natural := 8);
port (
D: in std_logic_vector(nbits - 1 downto 0);
RSTin, CLOCK: in std_logic;
Q: out std_logic_vector(nbits - 1 downto 0)
);
end reg8;
architecture bhv of reg8 is begin process (RSTin, CLOCK)
begin
if RSTin = '0' then
Q <= "00000000";
elsif CLOCK'event and CLOCK = '1' then
Q <= D;
end if;
end process;
end bhv;
Raw
test.tb.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity test_tb is end test_tb;
architecture bhv of test_tb is
component test
port(
D: in std_logic_vector(7 downto 0);
RSTin, CLOCK: in std_logic;
Q: out std_logic_vector(7 downto 0));
end component;
signal D : std_logic_vector(7 downto 0);
signal CLOCK : std_logic := '0';
signal RSTin : std_logic := '0';
signal Q : std_logic_vector(7 downto 0);
constant clk_period : time := 10 ns;
begin uut: test port map (
D => D,
CLOCK => CLOCK,
RSTin => RSTin);
clk_process : process
begin
CLOCK <= '0';
wait for clk_period/2;
CLOCK <= '1';
wait for clk_period/2;
end process;
stim_proc: process
begin
wait for 7 ns;
RSTin <='1';
wait for 3 ns;
RSTin <='0';
wait for 17 ns;
RSTin <= '1';
wait for 1 ns;
RSTin <= '0';
wait;
end process;
end bhv;
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