Subbloco para carregar a imagem

carrimag.vhd

library ieee;
use ieee.std_logic_1164.all;


entity carrimag is

	generic 
	(
		n : natural := 8
	);

	port 
	(
		imagemIN : in std_logic_vector(n-1 downto 0);
		escreve,carrega,reset,clk: in std_logic;
		imagemOUT : out std_logic_vector(n-1 downto 0);
		endereco	: in natural range 0 to 2**n -1;
		iPronta,iCarregada: out std_logic
	);

end entity;


architecture carrimg of carrimag is

	component single_port_ram is

		generic 
		(
			DATA_WIDTH : natural := 8;
			ADDR_WIDTH : natural := 6
		);

		port 
		(
			clk		: in std_logic;
			addr	: in natural range 0 to 2**ADDR_WIDTH - 1;
			data	: in std_logic_vector((DATA_WIDTH-1) downto 0);
			we		: in std_logic := '1';
			q		: out std_logic_vector((DATA_WIDTH -1) downto 0)
		);
	end component;


	signal img : std_logic_vector(n-1 downto 0);
	variable addr_reg : natural range 0 to n-1;
	variable contador_escreve : natural := 0;
	variable contador_carrega : natural := 0;
	begin

		process(clk,reset)
		begin
		if(reset = '1') then
				iPronta <= '0';
				contador_escreve := 0;
			
		elsif(rising_edge(clk)) then
			if(escreve = '1' AND carrega = '0') then
				if(contador_escreve = n) then
					iPronta <= '1';
					contador_escreve := 0;
				else
					img <= imagemIN;
					contador_escreve := contador_escreve + 1;
					addr_reg := contador_escreve;
					iPronta <= '0';
				end if;
			elsif(escreve = '0' AND carrega = '1') then
				addr_reg := endereco;
			end if;
		end if;
	end process;
		
		
memoriaRam: single_port_ram 
						GENERIC MAP (DATA_WIDTH => n, ADDR_WIDTH => n)
						PORT MAP (clk,addr_reg,img,escreve,imagemOUT);
end architecture;
		
		

ram.vhd

-- Quartus II VHDL Template
-- Single port RAM with single read/write address 

library ieee;
use ieee.std_logic_1164.all;

entity single_port_ram is

	generic 
	(
		DATA_WIDTH : natural := 8;
		ADDR_WIDTH : natural := 6
	);

	port 
	(
		clk	: in std_logic;
		addr	: in natural range 0 to 2**ADDR_WIDTH - 1;
		data	: in std_logic_vector((DATA_WIDTH-1) downto 0);
		we		: in std_logic := '1';
		q		: out std_logic_vector((DATA_WIDTH -1) downto 0)
	);

end entity;

architecture rtl of single_port_ram is

	-- Build a 2-D array type for the RAM
	subtype word_t is std_logic_vector((DATA_WIDTH-1) downto 0);
	type memory_t is array(2**ADDR_WIDTH-1 downto 0) of word_t;

	-- Declare the RAM signal.	
	signal ram : memory_t;

	-- Register to hold the address 
	signal addr_reg : natural range 0 to 2**ADDR_WIDTH-1;

begin

	process(clk)
	begin
	if(rising_edge(clk)) then
		if(we = '1') then
			ram(addr) <= data;
		end if;

		-- Register the address for reading
		addr_reg <= addr;
	end if;
	end process;

	q <= ram(addr_reg);

end rtl;