gistfile1.sh

/*
 * Board:   JZ-YKS (rev 1) "jz01"
 * 
 * CPU:     JZ4725B
 * SDRAM:   MT48LC32M16A2P-75
 * NAND:    K9GAG08U0M
 * 
 * CPU datasheet quotes:
 *  Operating frequency         360MHz (360000000Hz)        CPUSPEED, CFG_CPU_SPEED
 *  External oscillator         12MHz (12000000Hz)          EXTCLK, CFG_EXTAL
 * 
 * SDRAM datasheet quotes:
 *  The 512Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing
 *  536,870,912 bits. It is internally configured as a quad-bank DRAM with a synchronous
 *  interface (all signals are registered on the positive edge of the clock signal, CLK).
 *  Each of the x16’s 134,217,728-bit banks is organized as 8,192 rows by 1,024 columns by
 *  16 bits.
 *      Banks                   4                           SDRAM_BANKS, SDRAM_BANK4
 *      Rows                    8192 (2^13)                 SDRAM_ROWADDR, SDRAM_ROW
 *      Cols                    1024 (2^10)                 SDRAM_COLADDR, SDRAM_COL
 *      Bus Width               16 bits                     SDRAM_BUSWIDTH, SDRAM_BW16
 * 
 *  CL is the delay, in clock cycles, between the registration of a READ command and the
 *  availability of the first piece of output data. The latency can be set to two or three clocks.
 *      CAS Latency (CL)        2 or 3                      (?)SDRAM_CASL
 * 
 *  ACTIVE-to-PRECHARGE command     (tRAS)  min = 44 ns     SDRAM_TRAS
 *  ACTIVE-to-READ or WRITE delay   (tRCD)  min = 20 ns     SDRAM_RCD
 *  PRECHARGE command period        (tRP)   min = 20 ns     SDRAM_TPC
 *  WRITE recovery time             (tWR)   min = 15 ns     (?)SDRAM_TRWL
 *  Refresh period (8,192 rows)     (tREF)  max = 64 ms     (?)SDRAM_TREF
 *  [ 64ms, 8,192-cycle refresh ]
 * 
 * NAND datasheet quotes:
 *  8 Bit NAND Flash Memory                                 NAND_BUSWIDTH, BUS_WIDTH
 *  Memory Cell Array               (2G + 64M) x 8bit
 *  Data Register                   (4K + 128) x 8bit
 *  Page Program                    (4K + 128)Byte
 *  Block Erase                     (512K + 16K)Byte
 *  Page Size                       (4K + 128)Byte
 *  Memory Cell                     2bit / Memory Cell
 */

// jzboot configuration:
+ EXTCLK            12      # Define the external crystal in MHz
+ CPUSPEED          360     # Define the PLL output frequency
- PHMDIV            3       # Define the frequency divider ratio of PLL=CCLK:PCLK=HCLK=MCLK

  BAUDRATE          57600   # Define the uart baudrate
  USEUART           0       # UART number

+ SDRAM_BUSWIDTH    16      # The bus width of the SDRAM in bits (16|32)
+ SDRAM_BANKS       4       # The bank number (2|4)
+ SDRAM_ROWADDR     13      # Row address width in bits (11-13)
+ SDRAM_COLADDR     10      # Column address width in bits (8-12)
  SDRAM_ISMOBILE    0       # Define whether SDRAM is mobile SDRAM (only or Jz4750), 1: yes 0: no
  SDRAM_ISBUSSHARE  1       # Define whether SDRAM bus share with NAND 1:shared 0:unshared

+ NAND_BUSWIDTH     8       # The width of the NAND flash chip in bits (8|16|32)
  NAND_ROWCYCLES    3       # The row address cycles (2|3)
+ NAND_PAGESIZE     4096    # The page size of the NAND chip in bytes(512|2048|4096)
+ NAND_PAGEPERBLOCK 128     # The page number per block
  NAND_FORCEERASE   1       # The force to erase flag (0|1)
+ NAND_OOBSIZE      128     # OOB size in byte
  NAND_ECCPOS       12      # Specify the ECC offset inside the oob data (0-[oobsize-1])
  NAND_BADBLOCKPOS  0       # Specify the badblock flag offset inside the oob (0-[oobsize-1])
  NAND_BADBLOCKPAGE 127     # Specify the page number of badblock flag inside a block(0-[PAGEPERBLOCK-1])
  NAND_PLANENUM     1       # The planes number of target nand flash
  NAND_BCHBIT       8       # Specify the hardware BCH algorithm for 4750 (4|8)
  NAND_WPPIN        0       # Specify the write protect pin number
  NAND_BLOCKPERCHIP 0       # Specify the block number per chip,0 means

// UBIBoot configuration:
+ CFG_CPU_SPEED     360000000
+ CFG_EXTAL         12000000

  UART_BASE         UART0_BASE
  CONFIG_BAUDRATE   57600

? SDRAM_CASL        3       # CAS latency: 2 or 3 
+ SDRAM_TRAS        44      # RAS# Active Time (ns)
+ SDRAM_RCD         20      # RAS# to CAS# Delay (ns)
+ SDRAM_TPC         20      # RAS# Precharge Time (ns)
? SDRAM_TRWL        15      # Write Latency Time (ns)
? SDRAM_TREF        7812    # Refresh period (ns)
+ SDRAM_BW16        1
  SDRAM_BANK40      0
+ SDRAM_BANK4       1
  SDRAM_ROW0        11
+ SDRAM_ROW         13
  SDRAM_COL0        8
+ SDRAM_COL         10

  BUS_WIDTH         8
  ROW_CYCLE         3
  PAGE_SIZE         4096
  OOB_SIZE          (PAGE_SIZE/32)
  PAGE_PER_BLOCK    128
  BLOCK_SIZE        (PAGE_PER_BLOCK * PAGE_SIZE)
  BAD_BLOCK_POS     ((PAGE_SIZE==512) ? 5 : 0)
  BAD_BLOCK_PAGE    (PAGE_PER_BLOCK -1)
- ECC_BLOCK         512
- ECC_POS           12
- PAR_SIZE          9
- PAR_SIZE2         12

- UBI_MTD_EB_START  5
- UBI_MTD_NB_EB     127
- UBI_NB_VOLUMES    8
- UBI_KERNEL_VOLUME "kernel"