Created
September 25, 2022 12:45
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Output of core-to-core-latency on Windows-on-ARM
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Num cores: 8 | |
Num iterations per samples: 5000 | |
Num samples: 300 | |
1) CAS latency on a single shared cache line | |
0 1 2 3 4 5 6 7 | |
0 | |
1 73±0 | |
2 73±0 73±2 | |
3 73±0 70±0 70±0 | |
4 66±0 65±1 67±3 64±0 | |
5 69±2 64±0 64±0 64±0 62±4 | |
6 68±1 64±0 66±1 64±0 60±2 58±0 | |
7 67±1 64±0 64±0 64±0 58±1 58±0 58±0 | |
Min latency: 57.6ns ±0.2 cores: (7,5) | |
Max latency: 73.3ns ±0.4 cores: (1,0) | |
Mean latency: 65.4ns |
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