Litex include Riffa PCIE verilog

ac701.py

from migen import *
from migen.genlib.cdc import MultiReg

from litex.gen import *

from litex.soc.interconnect.csr import *
from litex.soc.integration.builder import *

from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform

from riffa_channel import Riffa_Channel
from chnl_tester import CHNL_Tester
_io = [
    ("clk200", 0,
        Subsignal("p", Pins("V4"), IOStandard("DIFF_SSTL15")),
        Subsignal("n", Pins("W4"), IOStandard("DIFF_SSTL15"))
    ),
    ("user_led",  0, Pins("F4"), IOStandard("LVCMOS33")),
    ("pcie_x4", 0,
        Subsignal("rst_n", Pins("M20"), IOStandard("LVCMOS33"), Misc("PULLUP=TRUE")),
        Subsignal("clk_p", Pins("F6")),
        Subsignal("clk_n", Pins("E6")),
        Subsignal("rx_p",  Pins("D9 B10 D11 B8")),
        Subsignal("rx_n",  Pins("C9 A10 C11 A8")),
        Subsignal("tx_p",  Pins("D7 B6 D5 B4")),
        Subsignal("tx_n",  Pins("C7 A6 C5 A4")),
    ),

]
class Platform(XilinxPlatform):
    default_clk_name   = "clk200"
    default_clk_period = 1e9/200e6

    def __init__(self):
        XilinxPlatform.__init__(self, "xc7a75t-fgg484-2", _io, toolchain="vivado")

class LiteFFA(LiteXModule):
    def __init__(self, platform):
        self.platform = platform

        C_NUM_CHNL = 2
        C_NUM_LANES = 4
        C_PCI_DATA_WIDTH  = 128
        #widths
        PCIE_BUS_ID_WIDTH = 8
        PCIE_DEVICE_ID_WIDTH = 5
        PCIE_FUNCTION_ID_WIDTH = 3
        PCIE_CONFIGURATION_REGISTER_WIDTH = 16

        #xilinx.vh
        SIG_XIL_RX_TUSER_W = 22
        SIG_XIL_TX_TUSER_W = 4
        SIG_BUSID_W = PCIE_BUS_ID_WIDTH
        SIG_DEVID_W = PCIE_DEVICE_ID_WIDTH
        SIG_FNID_W = PCIE_FUNCTION_ID_WIDTH
        SIG_CFGREG_W = PCIE_CONFIGURATION_REGISTER_WIDTH
        SIG_FC_CPLD_W = 12
        SIG_FC_CPLH_W = 8
        SIG_FC_SEL_W = 3

        #RIFFA
        SIG_CHNL_LENGTH_W = 32
        SIG_CHNL_OFFSET_W = 31

        self.RChannelS  = Riffa_Channel(C_NUM_CHNL, 
                                        SIG_CHNL_LENGTH_W, 
                                        SIG_CHNL_OFFSET_W,
                                        C_PCI_DATA_WIDTH).get_riffa()

        #pins
        pcie = platform.request("pcie_x4")

        self.riffa_params = dict()
        self.riffa_params.update(
            p_C_NUM_CHNL = C_NUM_CHNL,
            p_C_NUM_LANES = C_NUM_LANES,
            p_C_PCI_DATA_WIDTH = C_PCI_DATA_WIDTH,
            p_C_MAX_PAYLOAD_BYTES = 256,
            p_C_LOG_NUM_TAGS = 5,
        )
        #PCIE External Signal
        self.riffa_params.update(
            o_PCI_EXP_TXP = pcie.tx_p,
            o_PCI_EXP_TXN = pcie.tx_n,
            i_PCI_EXP_RXP = pcie.rx_p,
            i_PCI_EXP_RXN = pcie.rx_n,
            i_PCIE_REFCLK_P = pcie.clk_p,
            i_PCIE_REFCLK_N = pcie.clk_n,
            i_PCIE_RESET_N = pcie.rst_n
        )
        #FPGA Internal Signal
        self.riffa_params.update(
            i_CHNL_RX_CLK = self.RChannelS.CHNL_RX_CLK,
            o_CHNL_RX = self.RChannelS.CHNL_RX,
            i_CHNL_RX_ACK = self.RChannelS.CHNL_RX_ACK,
            o_CHNL_RX_LAST = self.RChannelS.CHNL_RX_LAST,
            o_CHNL_RX_LEN = self.RChannelS.CHNL_RX_LEN,
            o_CHNL_RX_OFF = self.RChannelS.CHNL_RX_OFF,
            o_CHNL_RX_DATA = self.RChannelS.CHNL_RX_DATA,
            o_CHNL_RX_DATA_VALID = self.RChannelS.CHNL_RX_DATA_VALID,
            i_CHNL_RX_DATA_REN = self.RChannelS.CHNL_RX_DATA_REN,
        )
        self.riffa_params.update(
            i_CHNL_TX_CLK = self.RChannelS.CHNL_TX_CLK,
            i_CHNL_TX = self.RChannelS.CHNL_TX,
            o_CHNL_TX_ACK = self.RChannelS.CHNL_TX_ACK,
            i_CHNL_TX_LAST = self.RChannelS.CHNL_TX_LAST,
            i_CHNL_TX_LEN = self.RChannelS.CHNL_TX_LEN,
            i_CHNL_TX_OFF = self.RChannelS.CHNL_TX_OFF,
            i_CHNL_TX_DATA = self.RChannelS.CHNL_TX_DATA,
            i_CHNL_TX_DATA_VALID = self.RChannelS.CHNL_TX_DATA_VALID,
            o_CHNL_TX_DATA_REN = self.RChannelS.CHNL_TX_DATA_REN,
        )
        self.riffa_params.update(
            o_PCIE_LINKUP = self.RChannelS.PCIE_LINKUP,
            o_PCIE_RDY = self.RChannelS.PCIE_RDY,
            o_CLK_O = self.RChannelS.CLK,
            o_RESET_O = self.RChannelS.RESET
        )
        riffa_dir = "./riffa_hdl"
        self.specials += Instance("AC701_Gen2x4If128", **self.riffa_params)

        self.platform.add_source("./riffa_ac7/AC701_Gen2x4If128.v")
        self.platform.add_source("./riffa_ac7/riffa_wrapper_ac701.v")
        self.platform.add_source_dir(riffa_dir)
        self.platform.add_verilog_include_path(riffa_dir)

        xci = "./ip/PCIeGen2x4If128.xci"
        self.platform.add_ip(xci)

        # Create clock domain
        self.clock_domains.cd_channel = ClockDomain()
        self.comb += self.cd_channel.clk.eq(self.RChannelS.CLK)

        cht1 = CHNL_Tester("channel")
        self.submodules.cht1 = cht1
        self.comb += Riffa_Channel.connect(self.RChannelS, cht1.DChannel, chn = 0)

        #cht2 = CHNL_Tester("channel")
        #self.submodules.cht2 = cht2
        #self.comb += Riffa_Channel.connect(self.RChannelS, cht2.DChannel, chn = 1)

#from migen.fhdl.verilog import convert
platform = Platform()
liteffa = LiteFFA(platform)
#convert(liteffa).write("liteffa.v")
        
platform.build(liteffa)