ICE40 IO Define

ice40_io.py

# iCE40 AsyncResetSynchronizer ---------------------------------------------------------------------

class LatticeiCE40AsyncResetSynchronizerImpl(Module):
    def __init__(self, cd, async_reset):
        rst1 = Signal()
        self.specials += [
            Instance("SB_DFFS",
                i_D = 0,
                i_S = async_reset,
                i_C = cd.clk,
                o_Q = rst1
            ),
            Instance("SB_DFFS",
                i_D = rst1,
                i_S = async_reset,
                i_C = cd.clk,
                o_Q = cd.rst
            )
        ]


class LatticeiCE40AsyncResetSynchronizer:
    @staticmethod
    def lower(dr):
        return LatticeiCE40AsyncResetSynchronizerImpl(dr.cd, dr.async_reset)

# iCE40 Tristate -----------------------------------------------------------------------------------

class LatticeiCE40TristateImpl(Module):
    def __init__(self, io, o, oe, i):
        nbits, sign = value_bits_sign(io)
        for bit in range(nbits):
            self.specials += Instance("SB_IO",
                p_PIN_TYPE      = C(0b101001, 6), # PIN_OUTPUT_TRISTATE + PIN_INPUT
                io_PACKAGE_PIN  = io[bit] if nbits > 1 else io,
                i_OUTPUT_ENABLE = oe,
                i_D_OUT_0       = o[bit]  if nbits > 1 else o,
                o_D_IN_0        = i[bit]  if nbits > 1 else i,
            )

class LatticeiCE40Tristate(Module):
    @staticmethod
    def lower(dr):
        return LatticeiCE40TristateImpl(dr.target, dr.o, dr.oe, dr.i)

# iCE40 Differential Output ------------------------------------------------------------------------

class LatticeiCE40DifferentialOutputImpl(Module):
    def __init__(self, i, o_p, o_n):
        self.specials += [
            Instance("SB_IO",
                p_PIN_TYPE     = C(0b011000, 6), # PIN_OUTPUT
                p_IO_STANDARD  = "SB_LVCMOS",
                io_PACKAGE_PIN = o_p,
                i_D_OUT_0      = i
            ),
            Instance("SB_IO",
                p_PIN_TYPE     = C(0b011000, 6), # PIN_OUTPUT
                p_IO_STANDARD  = "SB_LVCMOS",
                io_PACKAGE_PIN = o_n,
                i_D_OUT_0      = ~i
            )
        ]

class LatticeiCE40DifferentialOutput:
    @staticmethod
    def lower(dr):
        return LatticeiCE40DifferentialOutputImpl(dr.i, dr.o_p, dr.o_n)

# iCE40 DDR Output ---------------------------------------------------------------------------------

class LatticeiCE40DDROutputImpl(Module):
    def __init__(self, i1, i2, o, clk):
        self.specials += Instance("SB_IO",
            p_PIN_TYPE      = C(0b010000, 6), # PIN_OUTPUT_DDR
            p_IO_STANDARD   = "SB_LVCMOS",
            io_PACKAGE_PIN  = o,
            i_CLOCK_ENABLE  = 1,
            i_OUTPUT_CLK    = clk,
            i_OUTPUT_ENABLE = 1,
            i_D_OUT_0       = i1,
            i_D_OUT_1       = i2
        )


class LatticeiCE40DDROutput:
    @staticmethod
    def lower(dr):
        return LatticeiCE40DDROutputImpl(dr.i1, dr.i2, dr.o, dr.clk)

# iCE40 DDR Input ----------------------------------------------------------------------------------

class LatticeiCE40DDRInputImpl(Module):
    def __init__(self, i, o1, o2, clk):
        self.specials += Instance("SB_IO",
            p_PIN_TYPE      = C(0b000000, 6),  # PIN_INPUT_DDR
            p_IO_STANDARD   = "SB_LVCMOS",
            io_PACKAGE_PIN  = i,
            i_CLOCK_ENABLE  = 1,
            i_INPUT_CLK     = clk,
            o_D_IN_0        = o1,
            o_D_IN_1        = o2
        )


class LatticeiCE40DDRInput:
    @staticmethod
    def lower(dr):
        return LatticeiCE40DDRInputImpl(dr.i, dr.o1, dr.o2, dr.clk)

# iCE40 SDR Output ---------------------------------------------------------------------------------

class LatticeiCE40SDROutputImpl(Module):
    def __init__(self, i, o, clk):
        self.specials += Instance("SB_IO",
            # i_INPUT_CLK must match between two SB_IOs in the same tile.
            # In PIN_INPUT mode, this restriction is relaxed; an unconnected
            # i_INPUT_CLK also works.
            p_PIN_TYPE      = C(0b010101, 6), # PIN_OUTPUT_REGISTERED + PIN_INPUT
            p_IO_STANDARD   = "SB_LVCMOS",
            io_PACKAGE_PIN  = o,
            i_CLOCK_ENABLE  = 1,
            i_OUTPUT_CLK    = clk,
            i_OUTPUT_ENABLE = 1,
            i_D_OUT_0       = i
        )

class LatticeiCE40SDROutput:
    @staticmethod
    def lower(dr):
        return LatticeiCE40SDROutputImpl(dr.i, dr.o, dr.clk)

# iCE40 SDR Input ----------------------------------------------------------------------------------

class LatticeiCE40SDRInput:
    @staticmethod
    def lower(dr):
        return LatticeiCE40DDRInputImpl(dr.i, dr.o, Signal(), dr.clk)

# iCE40 SDR Tristate -------------------------------------------------------------------------------

class LatticeiCE40SDRTristateImpl(Module):
    def __init__(self, io, o, oe, i, clk):
        self.specials += Instance("SB_IO",
            p_PIN_TYPE      = C(0b110100, 6), # PIN_OUTPUT_REGISTERED_ENABLE_REGISTERED + PIN_INPUT_REGISTERED
            io_PACKAGE_PIN  = io,
            i_INPUT_CLK     = clk,
            i_OUTPUT_CLK    = clk,
            i_OUTPUT_ENABLE = oe,
            i_D_OUT_0       = o,
            o_D_IN_0        = i,
        )

class LatticeiCE40SDRTristate(Module):
    @staticmethod
    def lower(dr):
        return LatticeiCE40SDRTristateImpl(dr.io, dr.o, dr.oe, dr.i, dr.clk)

# iCE40 Trellis Special Overrides ------------------------------------------------------------------